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3f455d5236
- re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std
134 lines
3.9 KiB
VHDL
134 lines
3.9 KiB
VHDL
-- $Id: serport_uart_tx.vhd 417 2011-10-22 10:30:29Z mueller $
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: serport_uart_tx - syn
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-- Description: serial port UART - transmitter
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--
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-- Dependencies: -
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-- Test bench: tb/tb_serport_uart_rxtx
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-- Target Devices: generic
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-10-22 417 1.0.4 now numeric_std clean
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-- 2007-10-21 91 1.0.3 use 1 stop bits (redesigned _rx allows this)
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-- 2007-10-19 90 1.0.2 use 2 stop bits (allow CLKDIV=0 operation in sim)
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-06-30 62 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity serport_uart_tx is -- serial port uart: transmit part
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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TXSD : out slbit; -- transmit serial data (uart view)
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit -- transmit busy
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);
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end serport_uart_tx;
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architecture syn of serport_uart_tx is
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type regs_type is record
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ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
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bcnt : slv4; -- bit counter
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sreg : slv9; -- output shift register
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busy : slbit;
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end record regs_type;
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constant cntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
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constant regs_init : regs_type := (
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cntzero,
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(others=>'0'),
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(others=>'1'), -- sreg to all 1 !!
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'0'
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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R_REGS <= N_REGS;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, RESET, CLKDIV, TXDATA, TXENA)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable ld_ccnt : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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ld_ccnt := '0';
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if r.busy = '0' then
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ld_ccnt := '1';
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n.bcnt := (others=>'0');
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if TXENA = '1' then
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n.sreg := TXDATA & '0'; -- add start (0) bit
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n.busy := '1';
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end if;
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else
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if unsigned(r.ccnt) = 0 then
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ld_ccnt := '1';
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n.sreg := '1' & r.sreg(8 downto 1);
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n.bcnt := slv(unsigned(r.bcnt) + 1);
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if unsigned(r.bcnt) = 9 then -- if 10 bits send
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n.busy := '0'; -- declare all done
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end if;
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end if;
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end if;
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if RESET = '1' then
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ld_ccnt := '1';
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n.busy := '0';
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end if;
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if ld_ccnt = '1' then
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n.ccnt := CLKDIV;
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else
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n.ccnt := slv(unsigned(r.ccnt) - 1);
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end if;
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N_REGS <= n;
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TXBUSY <= r.busy;
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TXSD <= r.sreg(0);
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end process proc_next;
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end syn;
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