mirror of
https://github.com/wfjm/w11.git
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cbd8ce3468
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
47 lines
1.9 KiB
VHDL
47 lines
1.9 KiB
VHDL
-- $Id: simbus.vhd 444 2011-12-25 10:04:58Z mueller $
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--
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-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: simbus
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-- Description: Global signals for support control in test benches
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--
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-- Dependencies: -
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-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-12-23 444 2.0 remove global clock cycle signal
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-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
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-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
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-- 2007-08-27 76 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package simbus is
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signal SB_CLKSTOP : slbit := '0'; -- global clock stop
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signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
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signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
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signal SB_VAL : slbit := '0'; -- init bcast valid
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signal SB_ADDR : slv8 := (others=>'0'); -- init bcast address
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signal SB_DATA : slv16 := (others=>'0'); -- init bcast data
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-- Note: SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak ('L','H') and
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-- strong ('0','1') drivers. Therefore always remove strenght before
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-- using, e.g. with to_x01()
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end package simbus;
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