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3f455d5236
- re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std
120 lines
3.6 KiB
VHDL
120 lines
3.6 KiB
VHDL
-- $Id: dcm_sfs_gsim.vhd 426 2011-11-18 18:14:08Z mueller $
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--
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-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: dcm_sfs - sim
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-- Description: DCM for simple frequency synthesis
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-- simple vhdl model, without Xilinx UNISIM primitives
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan-3A,-3E
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-- Tool versions: xst 12.1, 13.1; ghdl 0.29
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-17 426 1.0.1 rename dcm_sp_sfs -> dcm_sfs
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-- 2010-11-12 338 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity dcm_sfs is -- DCM for simple frequency synthesis
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generic (
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CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
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CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
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CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
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port (
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CLKIN : in slbit; -- clock input
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CLKFX : out slbit; -- clock output (synthesized freq.)
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LOCKED : out slbit -- dcm locked
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);
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end dcm_sfs;
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architecture sim of dcm_sfs is
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signal CLK_DIVPULSE : slbit := '0';
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signal CLKOUT_PERIOD : time := 0 ns;
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signal R_CLKOUT : slbit := '0';
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signal R_LOCKED : slbit := '0';
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begin
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proc_clkin : process (CLKIN)
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variable t_lastclkin : time := 0 ns;
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variable t_lastperiod : time := 0 ns;
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variable t_period : time := 0 ns;
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variable nclkin : integer := 1;
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begin
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if CLKIN'event then
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if CLKIN = '1' then -- if CLKIN rising edge
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if t_lastclkin > 0 ns then
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t_lastperiod := t_period;
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t_period := now - t_lastclkin;
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CLKOUT_PERIOD <= (t_period * CLKFX_DIVIDE) / CLKFX_MULTIPLY;
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if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
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report "dcm_sp_sfs: CLKIN unstable" severity warning;
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end if;
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end if;
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t_lastclkin := now;
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if t_period > 0 ns then
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nclkin := nclkin - 1;
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if nclkin <= 0 then
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nclkin := CLKFX_DIVIDE;
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CLK_DIVPULSE <= '1';
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R_LOCKED <= '1';
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end if;
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end if;
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else -- if CLKIN falling edge
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CLK_DIVPULSE <= '0';
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end if;
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end if;
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end process proc_clkin;
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proc_clkout : process
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variable t_lastclkin : time := 0 ns;
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variable t_lastperiod : time := 0 ns;
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variable t_period : time := 0 ns;
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variable nclkin : integer := 1;
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begin
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loop
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wait until CLK_DIVPULSE = '1';
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for i in 1 to CLKFX_MULTIPLY loop
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R_CLKOUT <= '1';
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wait for CLKOUT_PERIOD/2;
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R_CLKOUT <= '0';
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if i /= CLKFX_MULTIPLY then
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wait for CLKOUT_PERIOD/2;
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end if;
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end loop; -- i
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end loop;
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end process proc_clkout;
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CLKFX <= R_CLKOUT;
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LOCKED <= R_LOCKED;
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end sim;
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