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2b5cfb7d96
- xsim support complete (but many issues to be resolved yet) - Added configurable w11a cache - Removed some never documented and now strategically obsolete designs
100 lines
3.5 KiB
VHDL
100 lines
3.5 KiB
VHDL
-- $Id: cdclib.vhd 774 2016-06-12 17:08:47Z mueller $
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--
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-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: cdclib
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-- Description: clock domain crossing components
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--
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-- Dependencies: -
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-- Tool versions: viv 2016.1-2016.2; ghdl 0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-06-11 774 1.0.1 add cdc_signal_s1_as; add INIT generic
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-- 2016-04-02 757 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package cdclib is
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component cdc_signal_s1 is -- cdc for signal (2 stage)
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generic (
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INIT : slbit := '0'); -- initial state
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port (
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CLKO : in slbit; -- O|output clock
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DI : in slbit; -- I|input data
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DO : out slbit -- O|output data
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);
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end component;
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component cdc_signal_s1_as is -- cdc for signal (2 stage), asyn input
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generic (
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INIT : slbit := '0'); -- initial state
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port (
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CLKO : in slbit; -- O|output clock
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DI : in slbit; -- I|input data
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DO : out slbit -- O|output data
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);
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end component;
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component cdc_vector_s0 is -- cdc for vector (1 stage)
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generic (
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DWIDTH : positive := 16); -- data port width
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port (
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CLKO : in slbit; -- O|output clock
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DI : in slv(DWIDTH-1 downto 0); -- I|input data
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DO : out slv(DWIDTH-1 downto 0) -- O|output data
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);
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end component;
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component cdc_vector_s1 is -- cdc for vector (2 stage)
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generic (
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DWIDTH : positive := 16); -- data port width
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port (
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CLKO : in slbit; -- O|output clock
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DI : in slv(DWIDTH-1 downto 0); -- I|input data
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DO : out slv(DWIDTH-1 downto 0) -- O|output data
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);
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end component;
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component cdc_pulse is -- clock domain crossing for a pulse
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generic (
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POUT_SINGLE : boolean := false; -- if true: single cycle pout
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BUSY_WACK : boolean := false; -- if true: busy waits for ack
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INIT : slbit := '0'); -- initial state
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port (
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CLKM : in slbit; -- M|clock master
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RESET : in slbit := '0'; -- M|reset
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CLKS : in slbit; -- S|clock slave
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PIN : in slbit; -- M|pulse in
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BUSY : out slbit; -- M|busy
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POUT : out slbit -- S|pulse out
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);
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end component;
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component cdc_value is -- cdc for value (slow change)
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generic (
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DWIDTH : positive := 16); -- data port width
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port (
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CLKO : in slbit; -- O|output clock
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DI : in slv(DWIDTH-1 downto 0); -- I|input data
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DO : out slv(DWIDTH-1 downto 0); -- O|output data
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DFIX : out slbit -- O|output data frozen
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);
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end component;
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end package cdclib;
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