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- Code base cleaned-up for vivado, fsm now inferred

Browse Source 
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
This commit is contained in:
Walter F.J. Mueller
2016-06-26 16:02:42 +00:00
parent e1479d4e5d
commit 2b5cfb7d96
343 changed files with 6071 additions and 4972 deletions
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22
Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 745 2016-03-18 22:10:34Z mueller $
# $Id: Makefile 772 2016-06-05 12:55:11Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@@ -6,6 +6,8 @@
#
# Revision History:
# Date Rev Version Comment
# 2016-06-05 772 1.2.4 add vmfsum,imfsum targets
# 2016-03-19 748 1.2.3 comment out legacy designs and tests
# 2016-02-19 732 1.2.1 remove dispunit syn and sim entries
# 2015-02-01 640 1.2 add vivado targets, separate from ise targets
# 2015-01-25 638 1.1 drop as type fx2 targets
@@ -30,18 +32,18 @@ SYN_ise += rtl/sys_gen/tst_snhumanio/s3board
SYN_ise += rtl/sys_gen/w11a/s3board
# Nexys2 -------------------------------------
SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic
SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic3
#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic
#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic3
SYN_ise += rtl/sys_gen/tst_rlink/nexys2
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
#SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
SYN_ise += rtl/sys_gen/tst_serloop/nexys2
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2
SYN_ise += rtl/sys_gen/w11a/nexys2
# Nexys3 -------------------------------------
SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic
SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic3
#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic
#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic3
SYN_ise += rtl/sys_gen/tst_rlink/nexys3
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
SYN_ise += rtl/sys_gen/tst_serloop/nexys3
@@ -111,6 +113,7 @@ SIM_viv += rtl/sys_gen/w11a/arty_bram/tb
.PHONY : default
.PHONY : all all_ise all_viv
.PHONY : all_sim_ise all_syn_ise all_syn_viv
.PHONY : vmfsum imfsum
.PHONY : clean
.PHONY : clean_sim_ise clean_sim_ise_tmp
.PHONY : clean_sym_ise clean_sim_viv clean_sym_ise_tmp clean_sym_viv_tmp
@@ -129,6 +132,8 @@ default :
@echo " make -j `nproc` all_syn_ise"
@echo " make -j `nproc` all_sim_viv"
@echo " make -j 1 all_syn_viv"
@echo " make vmfsum"
@echo " make imfsum"
@echo " make clean"
@echo " make clean_sim_ise"
@echo " make clean_syn_ise"
@@ -206,6 +211,11 @@ $(SIM_viv):
$(SYN_viv):
$(MAKE) -j 1 -C $@
#
vmfsum :
@xviv_msg_summary
imfsum :
@xise_msg_summary
#
all_lib :
$(MAKE) -C tools/src
clean_lib :

211
doc/README.txt
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@@ -1,4 +1,4 @@
$Id: README.txt 746 2016-03-19 13:08:36Z mueller $
$Id: README.txt 779 2016-06-26 15:37:16Z mueller $
Release notes for w11a
@@ -22,6 +22,213 @@ Release notes for w11a
2. Change Log ----------------------------------------------------------------
- trunk (2016-06-26: svn rev 36(oc) 779(wfjm); untagged w11a_V0.73) +++++++++
- Preface
- the 'basic vivado support' added with V0.64 was a minimal effort port of
the code base used under ISE, leading to sub-optimal results under vivado.
- the FSM inference under vivado is quirky and has several issues. The
most essential one prevented re-coding with 'one_hot' encoding, which
lead to high logic depth and low clock rates. Proper work-arounds were
applied to almost all FSMs, now vivado infers all (but one) properly
and re-codes them as 'one_hot'. That is especially important for the
pdp11_sequencer, which has 113 states. The sys_w11a_n4 system can now
run with up to 90 MHz (was 75-80 MHz before).
- due to a remaining synthesis issue the dmscnt and dmcmon debug units
are currently disabled for Artix based systems (see issue V0.73-3).
- memory inference is now used for all distributed and block rams under
vivado. The memory generators in memlib are still used under ISE
Note: they were initially setup to work around ISE synthesis issues.
- vivado synthesis and implementation use now 'explore' type flows for
optimal timing performance.
- the two clock dram based fifo was re-written (as fifo_2c_dram2) to allow
proper usage of vivado constraints (e.g. scoped xdc).
- vivado is now the prime platform for all further development
- the component test benches run now by default under Vivado with an
Artix-7 as default target. The makefiles for ISE with a Spartan-6 target
are available as 'Makefile.ise' and via the 'makeise' command.
- a message filter (xviv_msg_filter) has been developed which lists only
the unexpected message of a synthesis or implementation run. Filter
rule sets (.vmfset files) are available for all designs.
- full support for the vivado simuator 'xsim' has been added, there are
make targets to build a behavioral simulation as well as post-synthesis,
post-optimize, and post-routing functional and timing models. All these
models are now created in separate sub-directories and can now co-exist.
However see issues V.073-1 and 0.73-2 for severe caveats on xsim.
- vivado write_vhdl generates code which violates a vhdl language rule.
Attributes of port signals are declared in the wrong place. xsim and
other simulators accept this, but ghdl doesn't. As a work-around the
generated code is cleaned up by a filter (see xviv_sim_vhdl_cleanup).
- additional rlink devices
- the XADC block, available on all 7Series FPGAs, is now accessible via
rlink on all Arty, Basys3 and Nexys4 designs. Especially useful on the
Arty board because on this board also the currents are monitored.
- the USR_ACCESS register, available on all 7Series FPGAs, is now readable
via rlink on all Arty, Basys3 and Nexys4 designs. The vivado build flow
initializes this register with the build timestamp. This allows to
verify the build time of a design at run time.
- the cache used by the w11a (pdp11_cache) was initialy developed with the
tight block ram resources of the early Spartan-3 systems in mind. It had
8 kByte and used 5 BRAMs of size 18 kBit. With very little changes the
implenenation is now parametrized, and can generate also 16,32, 64 and
even 128 kByte caches which also use the 36 kBit BRAMs on the Artix.
There is a trade-off between cache sizes and clock rate due to routing
delays to the BRAM blocks. The w11a on the nexys4 runs with 16 kByte
cache and 90 MHz clock or with 64 kByte cache and 80 MHz. For practical
work loads, like a kernel compile, the 64 kByte configuration is better
and thus the default.
- resolved known issue V0.64-7: was caused by a combination of issues
and is now resolved by a combination of measures: add portsel logic for
arty tb, proper portsel setup, configurable timeout, and finally proper
timeout setting.
- resolved known issue V0.64-3: So far the arty, basys3 and nexys4 serial
port, based on a FTDI FT2232, was often operated at 10 MBaud. This rate
is in fact not supported by FTDI, the chip will use 8 instead of 10 MBaud.
Due to auto-bauding, which simly adapts to the actual baud rate, this went
undetected for some time. Now all designs use a serport block clocked with
120 MHz and can be operated with 12 MBaud.
- Summary
- new reference system: switched to Vivado 2016.2 (from 2015.4)
- code base cleaned-up for vivado, fsm now inferred
- xsim support complete (but many issues to be resolved yet)
- added configurable w11a cache
- removed some never documented and now strategically obsolete designs:
- sys_tst_fx2loop (for nexys2 and nexys3)
- sys_tst_rlink_cuff_ic3 (a three channel variant of the fx2 interface)
- New features
- new modules
- rtl/vlib
- generic_clk_100mhz.xdc - generic 100 MHz on CLK constraint (for tbs)
- rtl/vlib/cdclib - new directory for clock domain crossing
- cdc_pulse.vhd - cdc for a pulse (moved in from genlib)
- cdc_signal_s1.vhd - cdc for a signal, 2 stage
- cdc_vector_s0.vhd - cdc for a vector, 1 stage
- rtl/vlib/memlib
- fifo_2c_dram2.vhd - re-write of fifo_2c_dram to allow
proper usage of vivado constraints
- rtl/vlib/rbus
- rb_sres_or_6.vhd - rbus result or, 6 input
- rbd_usracc.vhd - return usr_access register
- rtl/vlib/rlink
- rlink_sp2c.vhd - rlink_core8 + serport_2clock2 combo
- rtl/vlib/serport
- serport_2clock2.vhd - like serport_2clock, use fifo_2c_dram2
- rtl/vlib/xlib
- usr_access_unisim.vhd - Wrapper for USR_ACCESS* entities
- new files
- tools/bin
- xise_msg_summary - list all filtered ISE messages
- xviv_msg_filter - message filter for vivado
- xviv_msg_summary - list all filtered vivado messages
- xviv_sim_vhdl_cleanup - cleanup vivado generated vhdl for ghdl
- makeise - wrapper for make -f Makefile.ise
- tools/tcl/rbtest
- test_flow.tcl - test back pressure and flow control
- Changes
- rtl/bplib/*/*_pins.xdc - add BITSTREAM.CONFIG.USR_ACCESS setup
- rtl/bplib/*/tb/tb_*.vbom - use -UUT attribute
- rtl/sys_gen/*/*/tb/tb_*.vbom - use -UUT attribute
- rtl/make_ise
- generic_ghdl.mk - use ghdl.?sim as workdir for ghdl
- generic_xflow.mk - use .imfset for ISE message rules
- rtl/make_viv
- generic_ghdl.mk - use ghdl.?sim as workdir for ghdl
- generic_vivado.mk - add [sorep]sim.v and %.vivado targets
- vmfset support, use xviv_sim_vhdl_cleanup
- generic_xsim.mk - [rep]sim models; use xsim.?sim as workdir
- viv_tools_build.tcl - use explore flows; prj,opt,pla modes
- viv_tools_config.tcl - add USR_ACCESS readback
- viv_tools_model.tcl - add [sor]sim_vhdl [sorepd]sim_veri modes
- rtl/sys_gen/*/* (all rlink based designs)
- sys_*.vhd - define rlink SYSID
- rtl/sys_gen/*/* (all rlink and 7series based designs)
- sys_*.vhd - add rbd_usracc, use serport_2clock2
- sys_conf.vhd - use PLL for clkser_gentype
- rtl/sys_gen/w11a/*
- sys_conf.vhd - add sys_conf_cache_twidth
- rtl/sys_gen/tst_serloop/nexys4
- sys_tst_serloop1_n4.vhd - clock now from cmt and configurable
- rtl/sys_gen/tst_serloop/tb
- tb_tst_serloop.vhd - use serport_(uart_rxtx|xontx)_tb
- rtl/vlib/*/tb/tb_*.vbom - use -UUT attribute
- rtl/vlib/*/tb/tbd_*.vbom - use generic_clk_100mhz.xdc
- rtl/vlib/comlib/comlib.vhd - leave return type unconstraint
- rtl/vlib/simlib/simlib.vhd - add writetimens()
- rtl/w11a
- pdp11_bram_memctl.vhd - use memory inference now
- pdp11_cache.vhd - now configurable size (8,16,32,64,128 kB)
- pdp11_sequencer.vhd - proc_snum conditional (vivado fsm fix)
- rtl/*/*.vbom - use memory inference for vivado
- rtl/*/*.vhd - workarounds and fixes to many FSMs
- tools/bin
- tbrun_tbw - use _bsim.log for behavioral sim log
- tbrun_tbwrri - use _bsim.log for behavioral sim log
use 120 sec timeout for simulation
- tbw - add '-norun', -run now default
- ti_rri - add --tout option
use 120 sec timeout for simulation
- vbomconv - add file properties (-UUT,-SCOPE_REF)
full xsim support now in -vsim_prj
- tools/src/librlink
- RlinkConnect - add USR_ACCESS register support
- tools/src/librlinktpp
- RtclRlinkConnect - add USR_ACCESS, timeout access
- tools/tcl/rbtest
- test_data.tcl - add dinc register tests
- tools/tcl/rlink
- util.tcl - add USR_ACCESS register support
- removed designs
- rtl/sys_gen/tst_fx2loop/nexys*/*/sys_tst_fx2loop_*_n*
- rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2
- renames
- *.mfset -> *.imfset - to be complementary to new .vmfset
- Makefile -> Makefile.ise - old ISE makefiles in component areas
- Bug fixes
- rtl/bplib/arty/tb
- tb_arty.vhd: - add portsel logic
- rtl/bplib/sysmon
- sysmon_rbus_core.vhd - use s_init (and not s_idle) after RESET
- rtl/vlib/xlib
- s7_cmt_sfs_*.vhd - correct mmcm range check boundaries
- tools/bin
- ti_w11: - proper portsel oob for -fx
- tbrun_tbwrri: - proper portsel oob for -hxon
- Known issues
- all issues: see README_known_issues.txt
- resolved issues:
- V0.72-1: since vivado 2016.1 xelab builds models which use DPI in a
mixed vhdl-verilog language environment.
- V0.72-2: now full support to build behavioral as well as functional and
timing simulations with xsim. See V.073-1 and 0.73-2 for caveats.
- V0.64-7: flow control issues with simulation models resolved
- V0.64-3: basys3, nexys4 and arty designs support now 12 MBaud.
- new issues:
- V0.73-1: as of vivado 2016.2 xelab shows sometimes extremely long build
times, especially for generated post-synthesis vhdl models. But also
building a behavioral simulation for a w11a design can take 25 min.
Even though post-synthesis or post-routing models are now generated
in verilog working with xsim is cumbersome and time consuming.
- V0.73-2: Many post-synthesis functional and especially post-routing
timing simulations currently fail due to startup and initialization
problems. Cause is MMCM/PLL startup, which is not properly reflected
in the test bench. Will be resolved in an upcoming release.
- V0.73-3: The 'state number generator' code in pdp11_sequencer causes
in vivado 2016.1 (and .2) that the main FSM isn't re-coded anymore,
which has high impact on achievable clock rate. The two optional
debug units depending on the state number, dmscnt and dmcmon, are
therefore currently deactivated in all Artix based systems (but are
available on all Spartan based systems).
- trunk (2016-03-19: svn rev 35(oc) 746(wfjm); untagged w11a_V0.72) +++++++++
- Preface
- The new low-cost Digilent Arty board is a very attractive platform.
@@ -70,7 +277,7 @@ Release notes for w11a
- serport_uart_*_tb - added copies for tb usage
- rtl/vlib/xlib/tb
- s7_cmt_sfs_tb - added copy for tb usage
-
- new files
- doc/man/man1
- tbrun_tbw.1 - man file for tbrun_tbw

18
doc/README_buildsystem_ISE.txt
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@@ -1,4 +1,4 @@
# $Id: README_buildsystem_ISE.txt 651 2015-02-26 21:32:15Z mueller $
# $Id: README_buildsystem_ISE.txt 779 2016-06-26 15:37:16Z mueller $
Guide to the Build System (Xilinx ISE Version)
@@ -114,13 +114,17 @@ Guide to the Build System (Xilinx ISE Version)
In many cases the test benches can also be compiled against the gate
level models derived after the xst, map or par step. To compile them
make ghdl_tmp_clean
make <tbench>_ssim # for post-xst
make <tbench>_fsim # for post-map
make <tbench>_tsim # for post-par
make <tbench>_ssim # for post-xst (using UNISIM)
make <tbench>_fsim # for post-map (using SIMPRIM)
make <tbench>_tsim # for post-par (using SIMPRIM)
The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
the compilation remains of earlier functional model compiles.
Individual working directories are used for the different models
ghdl.bsim for bahavioral model
ghdl.ssim for post-xst
ghdl.fsim for post-map
ghdl.tsim for post-par
and can co-exist. The 'make ghdl_tmp_clean' can be used to flush the ghdl
work areas, but in general this is not needed (since V0.73).
Notes:
- the post-xst simulation (_ssim targets) proved to be a valuable tool.

98
doc/README_buildsystem_Vivado.txt
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@@ -1,4 +1,4 @@
# $Id: README_buildsystem_Vivado.txt 745 2016-03-18 22:10:34Z mueller $
# $Id: README_buildsystem_Vivado.txt 779 2016-06-26 15:37:16Z mueller $
Guide to the Build System (Xilinx Vivado Version)
@@ -12,8 +12,9 @@ Guide to the Build System (Xilinx Vivado Version)
a. With ghdl
b. With Vivado xsim
4. Building systems
5. Configuring FPGAs (via make flow)
6. Note on ISE
5. Building vivado projects, creating gate level models
6. Configuring FPGAs (via make flow)
7. Note on ISE
1. Concept ----------------------------------------------------------------
@@ -102,8 +103,7 @@ Guide to the Build System (Xilinx Vivado Version)
3. Building test benches --------------------------------------------------
The build flows currently supports only ghdl.
Support for the Vivado simulator XSim will be added in a future release.
The build flows currently supports ghdl and the vivado simulator xsim.
3a. With ghdl --------------------------------------------------------
@@ -115,18 +115,29 @@ Guide to the Build System (Xilinx Vivado Version)
and generate the needed ghdl commands.
In some cases the test benches can also be compiled against the gate
level models derived after the synthesis or optimize step. To compile them
level models derived after the synthesis or optimize step.
Vivado only generated functional (UNISIM based) models in vhdl. Timing
(SIMPRIM based) models are only available on verilog. The combination
vivado + ghdl is therefore limited to functional model simulation.
To compile them
make ghdl_tmp_clean
make <tbench>_ssim # for post synthesis {see Notes}
make <tbench>_osim # for post optimize {see Notes}
make <tbench>_ssim # for post synthesis functional
make <tbench>_osim # for post optimize functional
make <tbench>_rsim # for post routing functional
The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
the compilation remains of earlier functional model compiles.
Individual working directories are used for the different models
ghdl.bsim for bahavioral model
ghdl.ssim for post synthesis
ghdl.osim for post optimize
ghdl.rsim for post routing
and can co-exist. The 'make ghdl_tmp_clean' can be used to flush the ghdl
work areas, but in general this is not needed (since V0.73).
Notes:
- post synthesis or optimize models currently very often fail to compile
in ghdl due to a bug in the ghdl code generator.
- Many post-synthesis functional currently fail due to startup and
initialization problems (see issue V0.73-2).
3b. With Vivado xsim -------------------------------------------------
@@ -139,16 +150,25 @@ Guide to the Build System (Xilinx Vivado Version)
In many cases the test benches can also be compiled against the gate
level models derived after the synthesis, optimize or routing step.
Vivado supports functional (UNISIM based) models in vhdl and in verilog,
and timing (SIMPRIM based) models only in verilog. Since practice showed
that verilog models compile and execute faster, verilog is used for both
functional and timing models.
make <tbench>_XSim_ssim # for post-synthesis
make <tbench>_XSim_osim # for post-optimize
make <tbench>_XSim_tsim # for post-routing
make <tbench>_XSim_ssim # for post-synthesis functional
make <tbench>_XSim_osim # for post-optimize functional
make <tbench>_XSim_rsim # for post-routing functional
make <tbench>_XSim_esim # for post-synthesis timing
make <tbench>_XSim_psim # for post-optimize timing
make <tbench>_XSim_tsim # for post-routing timing
Notes:
- xsim currently (as of Vivado 2015.4) crashes when DPI is used in a mixed
vhdl verilog context.
Since DPI is used in the rlink simulation all system test benches with
an rlink interface, thus most, will only run with ghdl and not with XSim.
- as of vivado 2016.2 xelab shows sometimes extremely long build times,
especially for generated post-synthesis vhdl models (see issue V0.73-1).
- Many post-synthesis functional and especially post-routing timing
simulations currently fail due to startup and initialization problems
(see issue V0.73-2).
4. Building systems -------------------------------------------------------
@@ -191,16 +211,48 @@ Guide to the Build System (Xilinx Vivado Version)
make <sys>_opt.dcp
make <sys>_rou.dcp
5. Configuring FPGAs ------------------------------------------------------
5. Building vivado projects, creating gate level models -------------------
Vivado is used in 'project mode', whenever one of the targets mentioned
above is build a vivado project is freshly created in the directory
project_mflow
with the project file
project_mflow/project_mflow.xpr
There are many make targets which
- just create the project
- start vivado in gui mode to inspect the most recent project
- create gate level models
Specifically
make <sys>.vivado # create vivado project from <sys>.vbom
make vivado # open project in project_mflow
make <sys>_ssim.vhd # post-synthesis functional model (vhdl)
make <sys>_osim.vhd # post-optimize functional model (vhdl)
make <sys>_rsim.vhd # post-routing functional model (vhdl)
make <sys>_ssim.v # post-synthesis functional model (verilog)
make <sys>_osim.v # post-optimize functional model (verilog)
make <sys>_rsim.v # post-routing functional model (verilog)
make <sys>_esim.v # post-synthesis timing model (verilog)
make <sys>_psim.v # post-optimize timing model (verilog)
make <sys>_tsim.v # post-routing timing model (verilog)
For timing model verilog file an associated sdf file is also generated.
6. Configuring FPGAs ------------------------------------------------------
The make flow supports also loading the bitstream into FPGAs via the
Vivado hardware server. Simply use
make <sys>.vconfig
Note: works with Basys3 and Nexys4, only one board must connected.
Note: works with Arty, Basys3, and Nexys4, only one board must connected.
6. Note on ISE ------------------------------------------------------------
7. Note on ISE ------------------------------------------------------------
The development for Nexys4 started with ISE, but has now fully moved to
Vivado. The make files for the ISE build flows have been kept for comparison
@@ -208,6 +260,8 @@ Guide to the Build System (Xilinx Vivado Version)
one can still start with a
make -f Makefile.ise <target>
or
makeise <target>
an ISE based build. To be used for tool comparisons, the ISE generated bit
files were never tested in an FPGA.

24
doc/README_known_issues.txt
View File

@@ -1,12 +1,22 @@
$Id: README_known_issues.txt 746 2016-03-19 13:08:36Z mueller $
$Id: README_known_issues.txt 779 2016-06-26 15:37:16Z mueller $
Known issues for this release.
The case id indicates the release when the issue was first recognized.
- V0.72-2: xsim simulations with timing annotation not yet available.
- V0.72-1: Vivado 2015.4 xelab crashes when DPI is used in a mxied vhdl-verilog
language environment. This prevents currently to build a xsim simulation
model for rlink based test benches.
- V0.73-1: as of vivado 2016.2 xelab shows sometimes extremely long build times,
especially for generated post-synthesis vhdl models. But also building a
behavioral simulation for a w11a design can take 25 min. Even though
post-synthesis or post-routing models are now generated in verilog working
with xsim is cumbersome and time consuming.
- V0.73-2: Many post-synthesis functional and especially post-routing timing
simulations currently fail due to startup and initialization problems.
Cause is MMCM/PLL startup, which is not properly reflected in the test
bench. Will be resolved in an upcoming release.
- V0.73-3: The 'state number generator' code in pdp11_sequencer causes in vivado
2016.1 (and .2) that the main FSM isn't re-coded anymore, which has high
impact on achievable clock rate. The two optional debug units depending on
the state number, dmscnt and dmcmon, are therefore currently deactivated in
all Artix based systems (but are available on all Spartan based systems).
- V0.66-1: the TM11 controller transfers data byte wise (all disk do it 16bit
word wise) and allows for odd byte length transfers. Odd length transfers
@@ -25,12 +35,8 @@ The case id indicates the release when the issue was first recognized.
- read or write 'with header' gives currently ILF
All this isn't used by any OS, so in practice not relevant.
- V0.64-7: ghdl simulated OS boots via ti_w11 (-n4 ect options) fail due to a
flow control issue (likely since V0.63).
- V0.64-6: IO delays still unconstraint in vivado. All critical IOs use
explicitly IOB flops, thus timing well defined.
- V0.64-3: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud is
not supported according to FTDI, but works. 12 MBaud in an upcoming release.
- V0.64-2: rlink throughput on basys3/nexys4 limited by serial port stack
round trip times. Will be overcome by libusb based custom driver.
- V0.64-1: The large default transfer size for disk accesses leads to bad

6
doc/man/man1/tbrun_tbw.1
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: tbrun_tbw.1 745 2016-03-18 22:10:34Z mueller $
.\" $Id: tbrun_tbw.1 774 2016-06-12 17:08:47Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -55,7 +55,7 @@ dry run, prints the commands but doesn't execute
.
.\" -- --lsuf ------------------------------------
.IP \fB\-\-lsuf\ \fIsuff\fR
use '_\fIsuff\fR.log' as suffix for log file. Default is '_dsim.log'
use '_\fIsuff\fR.log' as suffix for log file. Default is '_bsim.log'
.
.\" -- --stack -----------------------------------
.IP \fB\-\-stack\ \fInnn\fR
@@ -77,7 +77,7 @@ Simplest default case, will execute
make tb_serport_uart_rx
time tbw tb_serport_uart_rx 2>&1 |\\
ghdl_assert_filter |\\
tee tb_serport_uart_rx_dsim.log |\\
tee tb_serport_uart_rx_bsim.log |\\
egrep "(-[EFW]:|ERROR|FAIL|PASS|DONE)"
.EE

8
doc/man/man1/tbrun_tbwrri.1
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: tbrun_tbwrri.1 745 2016-03-18 22:10:34Z mueller $
.\" $Id: tbrun_tbwrri.1 774 2016-06-12 17:08:47Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -63,7 +63,7 @@ dry run, prints the commands but doesn't execute
.
.\" -- --lsuf ------------------------------------
.IP \fB\-\-lsuf\ \fIsuff\fR
use '_\fIsuff\fR.log' as suffix for log file. Default is '_dsim.log'
use '_\fIsuff\fR.log' as suffix for log file. Default is '_bsim.log'
.
.\" -- --stack -----------------------------------
.IP \fB\-\-stack\ \fInnn\fR
@@ -97,8 +97,8 @@ For s3board, nexys2, and nexys3 designs.
.
.\" -- --sxon ------------------------------------
.IP \fB\-\-sxon\fR
switched\ XON: enable XON flow control with SWI(1), will generate appropriate
'rlc oob' commands and ti_rri \-\-fifo options.
switched\ XON: enable XON flow control with SWI(1), will generate
appropriate 'rlc oob' commands and ti_rri \-\-fifo options.
For nexys4 designs.
.
.\" -- --hxon ------------------------------------

45
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@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: tbw.1 727 2016-02-07 13:58:47Z mueller $
.\" $Id: tbw.1 774 2016-06-12 17:08:47Z mueller $
.\"
.\" Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBW 1 2016-02-06 "Retro Project" "Retro Project Manual"
.TH TBW 1 2016-04-17 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbw \- wrapper script to start ghdl based VHDL test benches
@@ -52,9 +52,10 @@ or if defined to \fIFILEDEF\fP, and execute \fITBPROG\fP. In essence
.SS Using a \fItbw.dat\fP configuration file
When the generic file name or the stimulus file name does not follow the
simple default pattern or more than one input file is required a
configuration file can be used to define the setup. It has the fixed
name \fItbw.dat\fP and is searched the current working directory. The
format is described in section FILES.
configuration file can be used to define the setup. It has the fixed name
\fItbw.dat\fP and is searched the directory of the test bench program
\fITBPROG\fP.
The format is described in section FILES.
In this case the \fIFILEDEF\fP argument can be specified as 'tag=value'
pairs where tag refers to a generic name and value gives the concrete
@@ -68,15 +69,18 @@ defined via the \fItbw.dat\fP file, for details see section FILES.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
The options \fB\-run\fP, \fB\-fifo\fP and \fB\-verbose\fP are processed
by tbw itself. If more than one is given they must be in this order.
.IP \fB\-run\fR
Used for _ISim or _XSim tb's, ensures that simulation runs till end. Will
issue a 'run all' command for ISim and a '-R' option for XSim.
The options \fB\-fifo\fP, \fB\-verbose\fP and \fB\-norun\fP are processed
by tbw itself. They must be the first options after \fITBPROG\fP.
.IP \fB\-fifo\fR
Forces usage of rlink_cext fifo, will ignore tbw.dat
Forces usage of rlink_cext fifo in case no \fItbw.dat\fP is found or no section
matching \fITBPROG\fP is found in tbw.dat.
.IP \fB\-verbose\fR
show the used tag,value settings before execution
Show the used tag,value settings before execution
.IP \fB\-norun\fR
Start simulator in interactive mode.
Default for _XSim or _ISim tb's is to ensure that the simulation runs till
the end, as for ghdl. Therefore a '-R' option for XSim or a 'run all' command
for ISim is generated. The -norun option suppresses this.
.\" ------------------------------------------------------------------
.SH GHDL OPTIONS
@@ -111,9 +115,10 @@ display process name before each cycle.
.\" ------------------------------------------------------------------
.SH FILES
.IP "\fI./tbw.dat\fR" 4
This configuration file is searched for in the current working directory
and holds associations between generic file names and concrete file names
for one or more test bench executables. It contains sections of the format
This configuration file is searched for in the directory of the test bench
program \fITBPROG\fP and holds associations between generic file names and
concrete file names for one or more test bench executables. It contains
sections of the format
.EX
[\fITBPROG\fP]
@@ -179,6 +184,9 @@ produce a single \fIDONE\fP line
.PD
.RE
The convenience script \fBtbrun_tbw\fP(1) can be used in many cases to create
such a pipeline.
.SS Test benches controlled with \fBti_rri\fP
In these cases the test bench is started via \fBti_rri\fP using the
\fB\-\-run\fP and \fB\-\-fifo\fP options. Also here usually a pipe with
@@ -188,14 +196,19 @@ In these cases the test bench is started via \fBti_rri\fP using the
ti_rri \-\-run="tbw tb_tst_rlink_n3" \-\-fifo \-\-logl=3 \-\- \\
"package require tst_rlink" \\
"tst_rlink::setup" "tst_rlink::test_all" |\\
tee tb_tst_rlink_n3_dsim.log |\\
tee tb_tst_rlink_n3_bsim.log |\\
egrep "(\-[EFW]:|FAIL|PEND|DONE)"
.EE
The convenience script \fBtbrun_tbwrri\fP(1) can be used in many cases to
create these sometimes rather lengthy constructs.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR ti_rri (1),
.BR tbrun_tbw (1),
.BR tbrun_tbwrri (1),
.BR gtkwave (1),
.BR symlink (7),
.BR fifo (7)

12
doc/man/man1/ti_rri.1
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@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: ti_rri.1 742 2016-03-13 14:40:19Z mueller $
.\" $Id: ti_rri.1 776 2016-06-18 17:22:51Z mueller $
.\"
.\" Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TI_RRI 1 2016-03-13 "Retro Project" "Retro Project Manual"
.TH TI_RRI 1 2016-06-18 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
ti_rri \- \fBRlink\fP Backend Server
@@ -34,6 +34,8 @@ loads additional tcl packages when requested with \fB\-\-pack\fP
sets up logging and debug according to \fB\-\-log\fP, \fB\-\-logl\fP,
\fB\-\-dmpl\fP, and \fB\-\-tiol\fP
.IP "-"
sets up connection timeout according to \fB\-\-tout\fP
.IP "-"
starts an additional process if requested with \fB\-\-run\fP
.IP "-"
opens a connection when requested with \fB\-\-fifo\fP,
@@ -191,6 +193,12 @@ trace character activities
.PD
.RE
.
.\" -- --tout -----------------------------------
.IP \fB\-\-tout=\fIdt\fR
set connection timeout. Default is '1.'. Must be >0. . Should be set to a
larger value when slow simulators are connected, e.g. post-implentation
timing models.
.
.\" -- --int ------------------------------------
.IP \fB\-\-int\fP
enter interactive mode even when further tcl commands are given on the

15
doc/man/man1/ti_w11.1
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@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: ti_w11.1 745 2016-03-18 22:10:34Z mueller $
.\" $Id: ti_w11.1 748 2016-03-20 15:18:50Z mueller $
.\"
.\" Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -87,12 +87,21 @@ use 2nd serport with switched xon
.RE
.IP \fB-tmu\fP
activate trace and monitoring unit
.PD 0
.IP \fB-ghw\fP
activate ghw wave file writing
activate ghdl wave dump, will write a dump file with the name
\f<tb>.ghw\fR where <tb> is the filename of the test bench
.PD 0
.PD
.
.SS "common options"
.IP \fB-ll\fIn\fR
set rlink logging level to \fIn\fR (will issue a --logl=\fIn\fR).
.IP \fB-dl\fIn\fR
set rlink dump level to \fIn\fR (will issue a --dmpl=\fIn\fR).
.IP \fB-tl\fIn\fR
set rlink I/O trace level to \fIn\fR (will issue a --tiol=\fIn\fR).
.IP \fB-b\fR
batch mode
.IP \fB-e "\fR=\fIfile"\fR
load and execute \fIfile\fP. If the file type is '.mac' the file will
be on the fly compiled with \fBasm-11\fP(1), for all other file types

21
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@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: vbomconv.1 746 2016-03-19 13:08:36Z mueller $
.\" $Id: vbomconv.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -208,7 +208,7 @@ The first definition seen in the \fIvbom\fP
traversal is taken, all others are ignored. The filename in the usage clause
is the default used in case the logical name wasn't defined.
Last but not least are 5 directives defined in the \fBvbom\fP
Last but not least are 4 directives defined in the \fBvbom\fP
file format:
.
.IP "\fB@top\fP:\fIname\fP"
@@ -220,13 +220,6 @@ allows to specify additional system libraries. Currently used to indicate
that the \fIunisim\fP, \fIunimacro\fP or \fIsimprim\fP libraries are
needed by \fBghdl\fP.
.
.IP "\fB@uut\fP:\fIfile\fP"
signals that the \fIvbom\fP descibes a test bench and that \fIfile\fP is
the 'unit under test'. This allows to split the sources into a simulation
only test bench part and a synthesizable 'unit under test' part. \fIfile\fP
is typically a \fIvbom\fP in case of a functional simulation or the file
name of a generated post synthesis model.
.
.IP "\fB@xdc\fP:\fIfile\fP"
specifies that \fIfile\fP is a constraint file for Vivado synthesis and should
be included in the constraints fileset.
@@ -452,6 +445,15 @@ actions use \fBexec\fP(3) to execute the \fBghdl\fP command.
In these cases the caller will see the exit status of \fBghdl\fP.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP \fBVBOMCONV_XSIM_LANG\fP
Controls the language for the generated models used by xsim. Can be set to
\fIverilog\fP or to \fIvhdl\fP. If not defined \fIverilog\fP is used.
It affects \fB\-\-vsim_prj\fP but also \fB\-\-dep_vsim\fP.
Use \fBrm_dep\fP(1) to force regeneration of dependency files when this
environment variable is set, unset or changed.
.
.\" ------------------------------------------------------------------
.SH BUGS
.IP \(bu 2
Duplicate file elimination fails when one source file is refered to by
@@ -550,7 +552,6 @@ output like in
vbomconv --ghdl_a_cmd tb_w11a_n2.vbom | wc
vbomconv --isim_prj tb_w11a_n2.vbom | wc
.EP
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR vbom (5),

4
doc/man/man1/xise_ghdl_simprim.1
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: xise_ghdl_simprim.1 639 2015-01-30 18:12:19Z mueller $
.\" $Id: xise_ghdl_simprim.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -47,7 +47,7 @@ The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.SH ENVIRONMENT
.IP \fBXTWI_PATH\fP
points to the root of the currently active ISE/WebPack installation.
.

4
doc/man/man1/xise_ghdl_unisim.1
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: xise_ghdl_unisim.1 642 2015-02-06 18:53:12Z mueller $
.\" $Id: xise_ghdl_unisim.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -41,7 +41,7 @@ The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.SH ENVIRONMENT
.IP \fBXTWI_PATH\fP
points to the root of the currently active ISE installation.
.

19
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@@ -1,10 +1,10 @@
.\" -*- nroff -*-
.\" $Id: xise_msg_filter.1 640 2015-02-01 09:56:53Z mueller $
.\" $Id: xise_msg_filter.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.TH ISEMSG_FILTER 1 2015-01-30 "Retro Project" "Retro Project Manual"
.TH XISE_MSG_FILTER 1 2015-01-30 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xise_msg_filter \- message filter for Xilinx ISE tool chain log files
@@ -14,7 +14,7 @@ xise_msg_filter \- message filter for Xilinx ISE tool chain log files
.SY xise_msg_filter
.OP \-\-pack
.I TYPE
.I MFSET
.I IMFSET
.I LOGFILE
.
.SY xise_msg_filter
@@ -27,7 +27,7 @@ xise_msg_filter \- message filter for Xilinx ISE tool chain log files
Scans the log file \fILOGFILE\fP generated by Xilinx ISE tool specified
by \fITYPE\fP for informational, warning and error messages and compares
these messages against a set of message filter rules defined in the
\fIMFSET\fP file.
\fIIMFSET\fP file.
xise_msg_filter will print all no-matching messages.
All filter rules which do not match a message are also listed, these
messages are considered missing.
@@ -69,7 +69,7 @@ print full help.
.\" ------------------------------------------------------------------
.SH MESSAGE FILTER FILE FORMAT
.\" ----------------------------------------------
Simply a list of regular expression patters structured by section headers
Simply a list of regular expression patterns structured by section headers
of the form "[TYPE]".
Blank lines and lines starting with '#' will be ignored.
xise_msg_filter will extract the patters of the section matching the
@@ -86,22 +86,23 @@ xise_msg_filter will extract the patters of the section matching the
.EE
.\" ------------------------------------------------------------------
.SH EXIT STATUS
If \fITYPE\fP is invalid or the \fIMFSET\fP or \fILOGFILE\fP files
can't be opend an exit status 1 is returned.
If \fITYPE\fP is invalid or the \fIIMFSET\fP or \fILOGFILE\fP files
can't be opened an exit status 1 is returned.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBxise_msg_filter xst proj.mfset proj_xst.log\fR" 4
.IP "\fBxise_msg_filter xst proj.imfset proj_xst.log\fR" 4
Generate a short summary of a ISE xst log file.
.
.\" ------------------------------------------------------------------
.SH "BUGS"
The \fIMFSET\fP file is flat, no structuring possible, e.g. with includes.
The \fIIMFSET\fP file is flat, no structuring possible, e.g. with includes.
It be great to have for example default rules for each target device.
Since ISE is 'end-of-life' no further work on xise_msg_filter will be done.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xise_msg_summary (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR

34
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@@ -0,0 +1,34 @@
.\" -*- nroff -*-
.\" $Id: xise_msg_summary.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.TH XISE_MSG_SUMMARY 1 2016-06-05 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xise_msg_summary \- summarize all ISE tool chain log files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY xise_msg_summary
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
.\" ----------------------------------------------
Scans the current and all sub-directories for .imfset files and calls for
each message filter set
.EX
make \fIbasename\fP.mfsum
.EE
which in turn will use \fBxise_msg_filter\fP(1) to show unexpected messages
from all relevant log files and reports.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xise_msg_filter (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

4
doc/man/man1/xviv_ghdl_unisim.1
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@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: xviv_ghdl_unisim.1 642 2015-02-06 18:53:12Z mueller $
.\" $Id: xviv_ghdl_unisim.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -42,7 +42,7 @@ The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.SH ENVIRONMENT
.IP \fBXTWV_PATH\fP
points to the root of the currently active Vivado installation.
.

128
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@@ -0,0 +1,128 @@
.\" -*- nroff -*-
.\" $Id: xviv_msg_filter.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.TH XVIV_MSG_FILTER 1 2016-05-27 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xviv_msg_filter \- message filter for Xilinx Vivado tool chain log files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY xviv_msg_filter
.OP \-\-pack
.I TYPE
.I VMFSET
.I LOGFILE
.
.SY xviv_msg_filter
.B \-\-help
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
.\" ----------------------------------------------
Scans the log file \fILOGFILE\fP generated by Xilinx Vivado for messages and
compares these messages against a set of message filter rules defined in the
\fIVMFSET\fP file and selected by \fITYPE\fP.
xviv_msg_filter will print all no-matching messages.
All filter rules which do not match a message are also listed, these
messages are considered missing.
Matched messages are considered accepted.
In normal operation they will not create output.
xviv_msg_filter is useful for example in \fBmake\fP(1) based flows to
create a short summary from the log files.
The accepted values for \fITYPE\fP are:
.RS 3
.PD 0
.IP \fBsyn\fP 6
Vivado synthesis flow
.IP \fBimp\fP
Vivado implementation flow
.PD
.RE
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.\" ----------------------------------------------
.IP \fB\-\-pacc\fP
Print a summary of all accepted messages. The match count for each rule is
listed.
.
.\" ----------------------------------------------
.IP \fB\-\-help\fP
print full help.
.
.\" ------------------------------------------------------------------
.SH MESSAGE FILTER FILE FORMAT
.\" ----------------------------------------------
Simply a list of match rules structured by section headers
of the form "[TYPE]". '#' is interpreted as comment delimiter, everything
after a '#' in a line will be ignored.
xviv_msg_filter will extract the rules of the section matching the
\fITYPE\fP argument.
A line starting with '@' specifies a nested mfset file. This allows to
store the message filter sets in a structured way and factor out common
rule sets in separate files.
Each rule line has the format
.EX
<mode> [<name>] <pattern>
.EE
with
.IP \fBmode\fP 10
determines how the rule is applied
.RS
.PD 0
.IP \fBI\fP 4
matching messages are ignored
.IP \fBi\fP 4
matching messages are not printed, if no matching message is found a
notifivation is printed.
.IP \fBr\fP 4
signals that at least one matching message is required, if none seen, a
notifivation is printed.
.PD
.RE
.IP \fBname\fP
vivado message name, enclosed in [] brackets
.IP \fBpattern\fP
regular expression to match the message text. This field is optional, if
omitted all messages with th given name will match. '[' and ']' characters
are escaped to '\\[' and '\\]', because [] is very often part of signal
names. Character set matches are therefore not possible.
.SS Example message filter file
.EX
# -----------
[syn]
i [Designutils 20-1567] # false_path -hold and synth
# unused sequential element
i [Synth 8-3332] R_LREGS_reg[attn][\\d*]
i [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\\d*]
# -----------
[imp]
I [Vivado 12-2489] # multiple of 1 ps
.EE
.\" ------------------------------------------------------------------
.SH EXIT STATUS
If \fITYPE\fP is invalid or the \fIVMFSET\fP or \fILOGFILE\fP files
can't be opened an exit status 1 is returned.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBxviv_msg_filter syn proj.vmfset proj_syn.log\fR" 4
Generate a short summary of the vivado synthesis log file.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xviv_msg_summary (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

34
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@@ -0,0 +1,34 @@
.\" -*- nroff -*-
.\" $Id: xviv_msg_summary.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.TH XVIV_MSG_SUMMARY 1 2016-06-05 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xviv_msg_summary \- summarize all Vivado tool chain log files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY xviv_msg_summary
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
.\" ----------------------------------------------
Scans the current and all sub-directories for .vmfset files and calls for
each message filter set
.EX
make \fIbasename\fP.mfsum
.EE
which in turn will use \fBxviv_msg_filter\fP(1) to show unexpected messages
from all relevant log files and reports.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR xviv_msg_filter (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

37
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@@ -0,0 +1,37 @@
.\" -*- nroff -*-
.\" $Id: xviv_sim_vhdl_cleanup.1 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.TH XVIV_SIM_VHDL_CLEANUP 1 2016-06-05 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xviv_sim_vhdl_cleanup \- cleanup vivado generated vhdl for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY xviv_sim_vhdl_cleanup
.I file
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
.\" ----------------------------------------------
The vivado write_vhdl command generates code which violates a vhdl language
rule. Attributes of port signals are declared in the architecture, but should
be in the entiry declaration. xsim and other simulators accept this, but
\fBghdl\fP(1) doesn't. This script simply filters out lines like
.EX
attribute .... RTL_KEEP
.EE
Since attributes are ignored by \fBghdl\fP(1) anyway this avoids the
problem without any other side effects.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR ghdl (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

47
doc/man/man5/vbom.5
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: vbom.5 746 2016-03-19 13:08:36Z mueller $
.\" $Id: vbom.5 779 2016-06-26 15:37:16Z mueller $
.\"
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -34,7 +34,7 @@ Either source files or nested \fBvbom\fP's. The file names must be given
as relative path name from the directory the \fBvbom\fP file is located in.
Absolute path names are not allowed, nor is expansion of environment variables.
Currently three file types are accepted:
Currently the following file types are accepted:
.RS
.IP "\fB.vbom\fP" 6
refers to a nested \fBvbom\fP. Usually used for instantiated components.
@@ -58,6 +58,27 @@ via the \fIvhpi\fP mechanism. Supported only in conjunction with \fBghdl\fP.
.
.RE
.
.\" ----------------------------------------------
.IP "\fBFile attributes\fP"
File names can be followed by a list of attributes of the form
.EX
-\fIname\fP[:\fIvalue\fP] ...
.EE
Currently the following attributes are recognized
.RS
.IP "\fB-UUT\fP" 6
Signals that the \fIvbom\fP descibes a test bench and that file is
the 'unit under test'. This allows to split the sources into a simulation
only test bench part and a synthesizable 'unit under test' part. The file
is typically a \fIvbom\fP in case of a behavioural simulation or the file
name of a generated model for a functional or timing simulation.
.
.IP "\fB-SCOPE_REF[:\fIentity\fP]\fP" 6
Signals that the xdc file should be 'scoped to reference' to \fIentity\fP.
If \fIentity\fP is omitted the filename is taken as entity name.
In general used together with the \fB@xdc:\fP directive.
.
.RE
.
.\" ----------------------------------------------
.IP "\fBConditional file names\fP"
@@ -104,21 +125,22 @@ included in conjunction with simulation (ghdl,isim,vsim)
.IP "\fBLogical names\fP"
A logical name can be defined with
.EX
<lname> = <filename>
\fIlname\fP = \fIfilename\fP
.EE
The first definition of a logical name encountered in the traversal of the
\fBvbom\fP's by \fBvbomconv\fP(1) is taken, all later definitions are ignored.
A logical name can be used with
.EX
<lname> : <filename>
${\fIlname\fP}
${\fIlname\fP := \fIdefault\fP}
.EE
The filename in the usage clause is the default used in case the
logical name wasn't defined before it is used.
In the first form \fIlname\fP must have been defined before.
The second form allows to specify a \fIdefault\fP which is used when
\fIlname\fP hasn't been defined so far.
Again, the filenames, either of type \fI.vhd\fP or \fI.vbom\fP ,
must be given as relative path name from the directory the \fBvbom\fP
file is located in.
Again, the filenames must be given as relative path name from the directory
the \fBvbom\fP file is located in.
.\" ----------------------------------------------
.IP \fBDirectives\fP
@@ -134,13 +156,6 @@ Specifies an additional system library. Allowed values for \fIname\fP are
Currently used to generate the appropriate -L options for \fBghdl\fP commands,
e.g. generated by the \fBvbomconv\fP action \fB\-\-ghdl_m\fP.
.
.IP "\fB@uut\fP:\fIfile\fP"
Signals that the \fIvbom\fP descibes a test bench and that \fIfile\fP is
the 'unit under test'. This allows to split the sources into a simulation
only test bench part and a synthesizable 'unit under test' part. \fIfile\fP
is typically a \fIvbom\fP in case of a functional simulation or the file
name of a generated post synthesis model.
.
.IP "\fB@xdc\fP:\fIfile\fP"
Specifies that \fIfile\fP is a constraint file for Vivado synthesis and should
be included in the constraints fileset.

8
doc/w11a_os_guide.txt
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@@ -1,4 +1,4 @@
# $Id: w11a_os_guide.txt 745 2016-03-18 22:10:34Z mueller $
# $Id: w11a_os_guide.txt 779 2016-06-26 15:37:16Z mueller $
Guide to run operating system images on w11a systems
@@ -107,7 +107,7 @@ Guide to run operating system images on w11a systems
- for arty over serial
SWI = 0110 (gives console light emulation...)
ti_w11 -tu<dn>,10M,break,xon @<oskit-name>_boot.tcl
ti_w11 -tu<dn>,12M,break,xon @<oskit-name>_boot.tcl
NOTE: the arty w11a has currently only 176 kB memory (all from BRAMS!)
unix-v5 works fine. XXDP, RT11 and RSX-11M should work.
@@ -123,7 +123,7 @@ Guide to run operating system images on w11a systems
- for n4 over serial
SWI = 00000000 00101000 (gives console light display on LEDS)
ti_w11 -tu<dn>,10M,break,cts @<oskit-name>_boot.tcl
ti_w11 -tu<dn>,12M,break,cts @<oskit-name>_boot.tcl
- for n2,n3 over fx2
SWI = 00101100
@@ -164,7 +164,7 @@ Guide to run operating system images on w11a systems
4. simh simulator setup ---------------------------------------------------
Sometimes it is good to compare the w11a behaviour with the PDP-11 software
Sometimes it is good to compare the w11a behavior with the PDP-11 software
emulator from the simh project (see http://simh.trailing-edge.com/).
Under $RETROBASE/tools/simh two setup files are provided with configure

163
doc/w11a_tb_guide.txt
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@@ -1,9 +1,10 @@
# $Id: w11a_tb_guide.txt 745 2016-03-18 22:10:34Z mueller $
# $Id: w11a_tb_guide.txt 779 2016-06-26 15:37:16Z mueller $
Note: - Ghdl is used to all functional simulations
- Optionally Vivado xsim can be used (with some limitations)
- For post synthesis or post implementation simulations either
Ghdl or Vivado xsim (with some limitations) can be used.
Note: - Ghdl is used for all behavioral simulations
- Optionally Vivado xsim can be used
- For post synthesis or post implementation functionnal simulations
either Ghdl or Vivado xsim can be used.
- For timing simulations only Vivado xsim can be used.
- ISE isim is also available, but considered legacy support
Guide to running w11a test benches
@@ -47,27 +48,18 @@ Guide to running w11a test benches
produce a single DONE line
- Most tests can be run against
- the functional model
- the behavioral model
- post-synthesis functional
- post-optimization functional
- post-routing functional
- post-synthesis timing
- post-optimization timing
- post-routing timing
- gate level models at three stages (vivado flow)
- the post synthesis model (from *_syn.dcp)
- the post optimization model (from *_opt.dcp)
- the post routing model (from *_rou.dcp)
This is simply done using
make <testbench>_ssim for post-synthesis
make <testbench>_osim for post-optimization
make <testbench>_tsim for post-routing
Building the simulation models is handled by the build environment. See
README_buildsystem_Vivado.txt for details of the vivado flow and
README_buildsystem_ISE.txt for the ISE flow.
- gate level models at three stages (ISE flow)
- the post-xst model (produced by netgen from ngc xst output)
- the post-map model (produced by netgen from ncd ngdbuild output)
- the post-par model (produced by netgen from ncd par output)
This is simply done using
make <testbench>_ssim for post-xst
make <testbench>_fsim for post-map
make <testbench>_tsim for post-par
All the rest is handled by the build environment.
An example of a post-synthesis model is given for the w11a core test.
- for convenience a wrapper script 'tbrun_tbw' is used to generate the
@@ -85,69 +77,76 @@ Guide to running w11a test benches
cd $RETROBASE/rtl/vlib/serport/tb
tbrun_tbw tb_serport_uart_rx
-> 1269955.0 ns 63488: DONE
-> real 0m0.444s user 0m0.453s sys 0m0.007s
-> real 0m0.531s user 0m0.392s sys 0m0.014s
- serport receiver/transmitter test
tbrun_tbw tb_serport_uart_rxtx
-> 52335.0 ns 2607: DONE
-> real 0m0.074s user 0m0.077s sys 0m0.010s
-> real 0m0.120s user 0m0.065s sys 0m0.013s
- serport autobauder test
tbrun_tbw tb_serport_autobaud
-> 367475.0 ns 18364: DONE
-> real 0m0.247s user 0m0.258s sys 0m0.007s
-> real 0m0.343s user 0m0.316s sys 0m0.003s
- 9 bit comma,data to Byte stream converter test
cd $RETROBASE/rtl/vlib/comlib/tb
tbrun_tbw tb_cdata2byte
-> 7261.0 ns 354: DONE
-> real 0m0.042s user 0m0.042s sys 0m0.019s
-> real 0m0.088s user 0m0.057s sys 0m0.013s
- rlink core test
cd $RETROBASE/rtl/vlib/rlink/tb
tbrun_tbw tb_rlink_direct
-> 78975.0 ns 3939: DONE
-> real 0m0.225s user 0m0.226s sys 0m0.025s
-> real 0m0.270s user 0m0.222s sys 0m0.026s
- rlink core test via serial port interface
cd $RETROBASE/rtl/vlib/rlink/tb
tbrun_tbw --lsuf stim2_dsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat
tbrun_tbw --lsuf stim2_bsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat
-> 27595.0 ns 1370: DONE
-> real 0m0.098s user 0m0.111s sys 0m0.007s
-> real 0m0.184s user 0m0.145s sys 0m0.011s
tbrun_tbw --lsuf stim1_dsim tb_rlink_sp1c tb_rlink_stim.dat
tbrun_tbw --lsuf stim1_bsim tb_rlink_sp1c tb_rlink_stim.dat
-> 420295.0 ns 21005: DONE
-> real 0m0.942s user 0m0.947s sys 0m0.012s
-> real 0m0.939s user 0m0.945s sys 0m0.026s
- w11a core test (using behavioural model)
- w11a core test
- using behavioral model
cd $RETROBASE/rtl/w11a/tb
tbrun_tbw tb_pdp11core
-> 225355.0 ns 61258: DONE
-> real 0m6.280s user 0m6.284s sys 0m0.018s
cd $RETROBASE/rtl/w11a/tb
tbrun_tbw tb_pdp11core
-> 225355.0 ns 61258: DONE
-> real 0m6.446s user 0m6.387s sys 0m0.024s
- w11a core test (using Vivado post-synthesis model)
- using Vivado post-synthesis vhdl model and ghdl
tbrun_tbw tb_pdp11core_ssim
-> 225355.0 ns 61258: DONE
-> real 2m4.138s user 2m4.063s sys 0m0.050s
tbrun_tbw tb_pdp11core_ssim
-> 1225355.0 ns 61258: DONE
-> real 1m40.446s user 1m40.344s sys 0m0.075s
- using Vivado post-synthesis verilog model and xsim
tbrun_tbw tb_pdp11core_XSim_ssim
-> 1225355.0 ns 61258: DONE
-> real 1m14.835s user 1m13.997s sys 0m1.011s
- s3board sram controller test
cd $RETROBASE/rtl/bplib/s3board/tb
tbrun_tbw tb_s3_sram_memctl
-> 5015.0 ns 241: DONE
-> real 0m0.107s user 0m0.055s sys 0m0.020s
-> real 0m0.075s user 0m0.045s sys 0m0.022s
- nexys2/nexys3 cram controller test
cd $RETROBASE/rtl/bplib/nxcramlib/tb
tbrun_tbw tb_nx_cram_memctl_as
-> 24272.5 ns 1204: DONE
-> real 0m0.189s user 0m0.149s sys 0m0.055s
-> real 0m0.337s user 0m0.147s sys 0m0.146s
3. System tests benches ---------------------------------------------------
@@ -177,25 +176,25 @@ Guide to running w11a test benches
cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
tbrun_tbw tb_tst_serloop_s3
-> 301353.3 ns 18068: DONE
-> real 0m0.765s user 0m0.781s sys 0m0.013s
-> real 0m0.832s user 0m0.765s sys 0m0.036s
- sys_tst_serloop_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
tbrun_tbw tb_tst_serloop1_n2
-> 361560.0 ns 18068: DONE
-> real 0m0.994s user 0m0.991s sys 0m0.022s
-> real 0m0.799s user 0m0.758s sys 0m0.021s
tbrun_tbw tb_tst_serloop2_n2
-> 304353.3 ns 18248: DONE
-> real 0m1.543s user 0m1.561s sys 0m0.007s
-> real 0m1.274s user 0m1.236s sys 0m0.017s
- sys_tst_serloop_n3 test bench
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
tbrun_tbw tb_tst_serloop1_n3
-> 361560.0 ns 18068: DONE
-> real 0m0.740s user 0m0.755s sys 0m0.012s
-> real 0m0.841s user 0m0.820s sys 0m0.014s
4b. rlink tester -----------------------------------------------------
@@ -209,24 +208,24 @@ Guide to running w11a test benches
cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb
tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_arty \
"tst_rlink::setup" "tst_rlink::test_all"
-> 764400.0 ns 76419: DONE
-> real 0m9.323s user 0m9.233s sys 0m0.080s
-> 1028590.0 ns 102838: DONE
-> real 0m14.163s user 0m12.637s sys 0m0.152s
- sys_tst_rlink_b3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/basys3/tb
tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_b3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 763900.0 ns 76369: DONE
-> real 0m6.804s user 0m6.696s sys 0m0.085s
-> 1028820.0 ns 102861: DONE
-> real 0m9.275s user 0m9.041s sys 0m0.094s
- sys_tst_rlink_n4 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys4/tb
tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n4 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 758010.0 ns 75780: DONE
-> real 0m10.198s user 0m10.081s sys 0m0.104s
-> 1020240.0 ns 102003: DONE
-> real 0m9.751s user 0m9.544s sys 0m0.081s
- Spartan based systems
@@ -236,24 +235,24 @@ Guide to running w11a test benches
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 763770.0 ns 76356: DONE
-> real 0m5.955s user 0m5.834s sys 0m0.094s
-> 1024980.0 ns 102477: DONE
-> real 0m8.081s user 0m7.904s sys 0m0.106s
- sys_tst_rlink_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n2 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1526860.0 ns 76332: DONE
-> real 0m8.607s user 0m8.448s sys 0m0.150s
-> 2049320.0 ns 102455: DONE
-> real 0m7.934s user 0m7.748s sys 0m0.114s
- sys_tst_rlink_s3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_s3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1526540.0 ns 76317: DONE
-> real 0m5.650s user 0m5.571s sys 0m0.052s
-> 2049720.0 ns 102476: DONE
-> real 0m7.612s user 0m7.437s sys 0m0.075s
4c. rlink tester, Cypress FX2 based version --------------------------
@@ -266,16 +265,16 @@ Guide to running w11a test benches
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 440440.0 ns 44023: DONE
-> real 0m4.062s user 0m3.922s sys 0m0.111s
-> 558770.0 ns 55856: DONE
-> real 0m7.679s user 0m7.433s sys 0m0.185s
- sys_tst_rlink_cuff_ic_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n2 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 466940.0 ns 23336: DONE
-> real 0m2.831s user 0m2.696s sys 0m0.101s
-> 596300.0 ns 29804: DONE
-> real 0m3.741s user 0m3.542s sys 0m0.127s
4d. w11a systems -----------------------------------------------------
@@ -296,8 +295,8 @@ Guide to running w11a test benches
tbrun_tbwrri --pack rw11 tb_w11a_n4 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 6681310.0 ns 534488: DONE
-> real 1m26.253s user 1m26.139s sys 0m0.430s
-> 4812818.3 ns 577513: DONE
-> real 1m11.139s user 1m10.726s sys 0m0.545s
- Spartan based systems
- sys_w11a_n3 test bench
@@ -306,8 +305,8 @@ Guide to running w11a test benches
tbrun_tbwrri --cuff --pack rw11 tb_w11a_n3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 3614866.2 ns 231338: DONE
-> real 0m47.290s user 0m46.975s sys 0m0.537s
-> 3612428.7 ns 231182: DONE
-> real 0m47.454s user 0m47.241s sys 0m0.456s
- sys_w11a_n2 test bench
@@ -315,18 +314,18 @@ Guide to running w11a test benches
tbrun_tbwrri --cuff --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 4007500.0 ns 200364: DONE
-> real 0m43.803s user 0m43.698s sys 0m0.400s
-> 4009900.0 ns 200484: DONE
-> real 0m45.429s user 0m45.215s sys 0m0.480s
- sys_w11a_s3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
tbrun_tbwrri --fusp --pack rw11 tb_w11a_s3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 10526060.0 ns 526293: DONE
-> real 1m13.659s user 1m13.467s sys 0m0.431s
-> 10528880.0 ns 526434: DONE
-> real 1m13.706s user 1m13.483s sys 0m0.470s
A new, modular w11a test bench is under construction. So far it is very
incomplete. This very preliminary version can be executed with
@@ -334,13 +333,13 @@ Guide to running w11a test benches
- sys_w11a_n2 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11 tb_w11a_n2 \
tbrun_tbwrri --cuff --lsuf tbench_bsim --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
-> 3280220.0 ns 164000: DONE
-> real 0m30.190s user 0m30.843s sys 0m0.577s
-> 3268940.0 ns 163436: DONE
-> real 0m30.761s user 0m31.576s sys 0m0.502s
tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11 tb_w11a_n2 \
tbrun_tbwrri --cuff --lsuf tbench_bsim --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
-> 1387300.0 ns 69354: DONE
-> real 0m14.298s user 0m14.314s sys 0m0.240s
-> 1376360.0 ns 68807: DONE
-> real 0m16.991s user 0m17.049s sys 0m0.235s

14
rtl/bplib/arty/arty_pins.xdc
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@@ -1,15 +1,20 @@
# -*- tcl -*-
# $Id: arty_pins.xdc 740 2016-03-06 20:56:56Z mueller $
# $Id: arty_pins.xdc 758 2016-04-02 18:01:39Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Pin locks for Digilent Arty core functionality
# - USB UART
# - human I/O (switches, buttons, leds)
# Digilent Arty core functionality
# - Configuration setup
# - config voltage
# - enable bitstream timestamp
# - Pin Locks for
# - USB UART
# - human I/O (switches, buttons, leds)
#
# Revision History:
# Date Rev Version Comment
# 2016-04-02 758 1.2 add BITSTREAM.CONFIG.USR_ACCESS setup
# 2016-03-06 740 1.1 add A_VPWRP/N to baseline config
# 2016-01-31 726 1.0 Initial version
#
@@ -17,6 +22,7 @@
# config setup --------------------------------------------------------------
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
# clocks -- in bank 35 ------------------------------------------------------
set_property PACKAGE_PIN e3 [get_ports {I_CLK100}]

19
rtl/bplib/arty/tb/Makefile
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@@ -1,30 +1,41 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-06-18 776 1.1.1 add xsim_clean
# 2016-04-22 763 1.1 add include dep_vsim
# 2016-01-31 726 1.0 Initial version
#
EXE_all = tb_arty_dummy
#
include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk
#
.PHONY : all all_ssim clean
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
clean : viv_clean ghdl_clean
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
include $(wildcard *.o.dep_ghdl)
endif
#

2
rtl/bplib/arty/tb/tb_arty.vbom
View File

@@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_arty_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${arty_aif := arty_dummy.vbom}
${arty_aif := arty_dummy.vbom} -UUT
# design
tb_arty.vhd
@top:tb_arty

24
rtl/bplib/arty/tb/tb_arty.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_arty.vhd 740 2016-03-06 20:56:56Z mueller $
-- $Id: tb_arty.vhd 748 2016-03-20 15:18:50Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-20 748 1.2 BUGFIX: add PORTSEL_XON logic
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-02-20 734 1.0.2 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.0.1 direct instantiation of tbcore_rlink
@@ -81,6 +82,10 @@ architecture sim of tb_arty is
signal O_RGBLED2 : slv3 := (others=>'0');
signal O_RGBLED3 : slv3 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
@@ -152,7 +157,7 @@ begin
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => '0', -- FIXME: or 1 ???
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
@@ -183,4 +188,19 @@ begin
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most arty designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;

16
rtl/bplib/basys3/basys3_pins.xdc
View File

@@ -1,21 +1,27 @@
# -*- tcl -*-
# $Id: basys3_pins.xdc 726 2016-01-31 23:02:31Z mueller $
# $Id: basys3_pins.xdc 758 2016-04-02 18:01:39Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Pin locks for Digilent Basys 3 core functionality
# - USB UART
# - human I/O (switches, buttons, leds, display)
# Digilent Basys 3 core functionality
# - Configuration setup
# - config voltage
# - enable bitstream timestamp
# - Pin Locks for
# - USB UART
# - human I/O (switches, buttons, leds, display)
#
# Revision History:
# Date Rev Version Comment
# 2016-04-02 758 1.1 add BITSTREAM.CONFIG.USR_ACCESS setup
# 2015-01-30 640 1.0 Initial version
#
# config setup --------------------------------------------------------------
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
# clocks -- in bank 34 ------------------------------------------------------
set_property PACKAGE_PIN w5 [get_ports {I_CLK100}]

2
rtl/bplib/basys3/tb/tb_basys3.vbom
View File

@@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_basys3_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${basys3_aif := basys3_dummy.vbom}
${basys3_aif := basys3_dummy.vbom} -UUT
# design
tb_basys3.vhd
@top:tb_basys3

10
rtl/bplib/basys3/tb/tb_basys3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_basys3.vhd 734 2016-02-20 22:43:20Z mueller $
-- $Id: tb_basys3.vhd 748 2016-03-20 15:18:50Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,7 +26,7 @@
-- To test: generic, any basys3_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33
--
-- Revision History:
-- Date Rev Version Comment
@@ -182,6 +182,12 @@ begin
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most basys3 designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then

3
rtl/bplib/bpgen/Makefile → rtl/bplib/bpgen/Makefile.ise
View File

@@ -1,4 +1,5 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
# -*- makefile-gmake -*-
# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $
#
# Revision History:
# Date Rev Version Comment

4
rtl/bplib/bpgen/bp_swibtnled.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: bp_swibtnled.vhd 637 2015-01-25 18:36:40Z mueller $
-- $Id: bp_swibtnled.vhd 756 2016-03-29 21:49:46Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,7 +22,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
-- Tool versions: ise 11.4-14.7; viv 2014.4-2015.4; ghdl 0.26-0.33
--
-- Revision History:
-- Date Rev Version Comment

6
rtl/bplib/bpgen/sn_7segctl.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sn_7segctl.vhd 637 2015-01-25 18:36:40Z mueller $
-- $Id: sn_7segctl.vhd 750 2016-03-24 23:11:51Z mueller $
--
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -100,11 +100,11 @@ begin
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity FAILURE;
severity failure;
assert CDWIDTH >= 5
report "assert(CDWIDTH >= 5): CDWIDTH too small"
severity FAILURE;
severity failure;
proc_regs: process (CLK)
begin

2
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
View File

@@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${nexys2_fusp_aif := nexys2_fusp_dummy.vbom}
${nexys2_fusp_aif := nexys2_fusp_dummy.vbom} -UUT
# design
tb_nexys2_fusp.vhd
@top:tb_nexys2_fusp

2
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
tb_nexys2_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
@uut: ${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom}
${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom} -UUT
# design
tb_nexys2_fusp_cuff.vhd
@top:tb_nexys2_fusp_cuff

2
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom
View File

@@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${nexys3_fusp_aif := nexys3_fusp_dummy.vbom}
${nexys3_fusp_aif := nexys3_fusp_dummy.vbom} -UUT
# design
tb_nexys3_fusp.vhd
@top:tb_nexys3_fusp

2
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
tb_nexys3_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
@uut: ${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom}
${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom} -UUT
# design
tb_nexys3_fusp_cuff.vhd
@top:tb_nexys3_fusp_cuff

17
rtl/bplib/nexys4/nexys4_pins.xdc
View File

@@ -1,12 +1,20 @@
# -*- tcl -*-
# $Id: nexys4_pins.xdc 726 2016-01-31 23:02:31Z mueller $
# $Id: nexys4_pins.xdc 758 2016-04-02 18:01:39Z mueller $
#
# Pin locks for Nexys 4 core functionality
# - USB UART
# - human I/O (switches, buttons, leds, display)
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Nexys 4 core functionality
# - Configuration setup
# - config voltage
# - enable bitstream timestamp
# - Pin Locks for
# - USB UART
# - human I/O (switches, buttons, leds, display)
#
# Revision History:
# Date Rev Version Comment
# 2016-04-02 758 1.4 add BITSTREAM.CONFIG.USR_ACCESS setup
# 2015-02-06 643 1.3 factor out cram
# 2015-02-01 641 1.2 separate I_BTNRST_N
# 2015-01-31 640 1.1 fix RTS/CTS
@@ -16,6 +24,7 @@
# config setup --------------------------------------------------------------
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
# clocks -- in bank 35 ------------------------------------------------------
set_property PACKAGE_PIN e3 [get_ports {I_CLK100}]

19
rtl/bplib/nexys4/tb/Makefile
View File

@@ -1,30 +1,41 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-06-18 776 1.1.1 add xsim_clean
# 2016-04-22 763 1.1 add include dep_vsim
# 2016-01-03 724 1.0 Initial version
#
EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy
#
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk
#
.PHONY : all all_ssim clean
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
clean : viv_clean ghdl_clean
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
include $(wildcard *.o.dep_ghdl)
endif
#

2
rtl/bplib/nexys4/tb/tb_nexys4.vbom
View File

@@ -17,7 +17,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_nexys4_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${nexys4_aif := nexys4_dummy.vbom}
${nexys4_aif := nexys4_dummy.vbom} -UUT
# design
tb_nexys4.vhd
@top:tb_nexys4

2
rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
tb_nexys4_core.vbom
../../micron/mt45w8mw16b.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${nexys4_cram_aif := nexys4_cram_dummy.vbom}
${nexys4_cram_aif := nexys4_cram_dummy.vbom} -UUT
# design
tb_nexys4_cram.vhd
@top:tb_nexys4_cram

2
rtl/bplib/nxcramlib/Makefile → rtl/bplib/nxcramlib/Makefile.ise
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
# $Id: Makefile.ise 761 2016-04-17 08:53:48Z mueller $
#
# Revision History:
# Date Rev Version Comment

13
rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: nx_cram_memctl_as.vhd 718 2015-12-26 15:59:48Z mueller $
-- $Id: nx_cram_memctl_as.vhd 767 2016-05-26 07:47:51Z mueller $
--
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -13,7 +13,7 @@
--
------------------------------------------------------------------------------
-- Module Name: nx_cram_memctl_as - syn
-- Description: nexys2/3: CRAM driver - async and page mode
-- Description: nexys2/3/4: CRAM driver - async and page mode
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_o_gen
@@ -21,7 +21,7 @@
-- Test bench: tb/tb_nx_cram_memctl_as
-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.1; ghdl 0.26-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -31,6 +31,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.2.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-26 718 1.2.1 BUGFIX: do_dispatch(): always define imem_oe
-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
@@ -197,8 +198,8 @@ architecture syn of nx_cram_memctl_as is
(others=>'0') -- memdi
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal CLK_180 : slbit := '0';
signal MEM_CE_N : slbit := '1';

2
rtl/bplib/nxcramlib/tb/Makefile → rtl/bplib/nxcramlib/tb/Makefile.ise
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
# $Id: Makefile.ise 761 2016-04-17 08:53:48Z mueller $
#
# Revision History:
# Date Rev Version Comment

2
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom
View File

@@ -9,7 +9,7 @@
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../micron/mt45w8mw16b.vbom
@uut: ${uut := tbd_nx_cram_memctl_as.vbom}
${uut := tbd_nx_cram_memctl_as.vbom} -UUT
# design
tb_nx_cram_memctl.vhd
@top:tb_nx_cram_memctl

2
rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
View File

@@ -14,7 +14,7 @@
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
tb_s3board_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${s3board_fusp_aif := s3board_fusp_dummy.vbom}
${s3board_fusp_aif := s3board_fusp_dummy.vbom} -UUT
# design
tb_s3board_fusp.vhd
@top:tb_s3board_fusp

37
rtl/bplib/sysmon/Makefile Normal file
View File

@@ -0,0 +1,37 @@
# $Id: Makefile 761 2016-04-17 08:53:48Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-04-15 761 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#

1
rtl/bplib/sysmon/sysmon_rbus_core.vbom
View File

@@ -1,6 +1,7 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
sysmonrbuslib.vbom
# components
# design
sysmon_rbus_core.vhd

10
rtl/bplib/sysmon/sysmon_rbus_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sysmon_rbus_core.vhd 741 2016-03-12 23:49:03Z mueller $
-- $Id: sysmon_rbus_core.vhd 767 2016-05-26 07:47:51Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,10 +20,12 @@
-- Test bench: -
--
-- Target Devices: generic (all with SYSMON or XADC)
-- Tool versions: viv 2015.4; ghdl 0.33
-- Tool versions: viv 2015.4-2016.1; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-25 787 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- BUGFIX: use s_init in regs_init (was s_idle)
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
@@ -115,7 +117,7 @@ architecture syn of sysmon_rbus_core is
constant regs_init : regs_type := (
'0', -- rbsel
s_idle, -- state
s_init, -- state
(others=>'0'), -- eoscnt
'0','0','0','0', -- stat_ot, stat_j*
slv(to_unsigned(0,ALWIDTH)), -- almh
@@ -124,7 +126,7 @@ architecture syn of sysmon_rbus_core is
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
-- only internal regs have names, only 3 LSB in constant
constant rbaddr_cntl: slv3 := "000"; -- 0 -/-/f

11
rtl/bplib/sysmon/sysmonrbuslib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sysmonrbuslib.vhd 742 2016-03-13 14:40:19Z mueller $
-- $Id: sysmonrbuslib.vhd 770 2016-05-28 14:15:00Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,6 +19,7 @@
-- Tool versions: viv2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-28 770 1.0.1 ensure to_unsigned() has a type natural argument
-- 2016-03-13 742 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
@@ -195,17 +196,17 @@ package body sysmonrbuslib is
-- -------------------------------------
pure function xadc_temp2alim(temp : real) return bv16 is
variable ival : integer := 0;
variable ival : natural := 0;
begin
ival := integer(((temp + 273.14) * 16.0 * 4096.0) / 503.975);
ival := natural(((temp + 273.14) * 16.0 * 4096.0) / 503.975);
return to_bitvector(slv(to_unsigned(ival,16)));
end function xadc_temp2alim;
-- -------------------------------------
pure function xadc_svolt2alim (volt : real) return bv16 is
variable ival : integer := 0;
variable ival : natural := 0;
begin
ival := integer((volt * 16.0 * 4096.0) / 3.0);
ival := natural((volt * 16.0 * 4096.0) / 3.0);
return to_bitvector(slv(to_unsigned(ival,16)));
end function xadc_svolt2alim;

3
rtl/ibus/Makefile → rtl/ibus/Makefile.ise
View File

@@ -1,4 +1,5 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
# -*- makefile-gmake -*-
# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $
#
# Revision History:
# Date Rev Version Comment

3
rtl/ibus/ibd_ibmon.vbom
View File

@@ -4,6 +4,7 @@
iblib.vhd
# components
[sim]../vlib/memlib/ram_1swsr_wfirst_gen.vbom
[xst,vsyn]../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom
[xst]../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom
[vsyn]../vlib/memlib/ram_1swsr_wfirst_gen.vbom
# design
ibd_ibmon.vhd

9
rtl/ibus/ibd_iist.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibd_iist.vhd 641 2015-02-01 22:12:15Z mueller $
-- $Id: ibd_iist.vhd 767 2016-05-26 07:47:51Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2009-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -29,6 +29,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 0.8.2 don't init N_REGS (vivado fix for fsm inference)
-- 2011-11-18 427 0.8.1 now numeric_std clean
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im
@@ -218,7 +219,7 @@ architecture syn of ibd_iist is
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
begin

3
rtl/ibus/ibdr_rhrp.vbom
View File

@@ -4,6 +4,7 @@
iblib.vhd
# components
[sim]../vlib/memlib/ram_1swar_gen.vbom
[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom
[vsyn]../vlib/memlib/ram_1swar_gen.vbom
# design
ibdr_rhrp.vhd

9
rtl/ibus/ibdr_rhrp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_rhrp.vhd 692 2015-06-21 11:53:24Z mueller $
-- $Id: ibdr_rhrp.vhd 767 2016-05-26 07:47:51Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -28,6 +28,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2015-06-20 692 1.0.3 BUGFIX: fix func-go when drive/init busy checks
-- 2015-06-05 690 1.0.2 use 'not unit' for lsb of rpsn to avoid SI detect
-- BUGFIX: set rmr only for write to busy unit
@@ -401,7 +402,7 @@ architecture syn of ibdr_rhrp is
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';

3
rtl/ibus/ibdr_rk11.vbom
View File

@@ -4,6 +4,7 @@
iblib.vhd
# components
[sim]../vlib/memlib/ram_1swar_gen.vbom
[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom
[vsyn]../vlib/memlib/ram_1swar_gen.vbom
# design
ibdr_rk11.vhd

9
rtl/ibus/ibdr_rk11.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_rk11.vhd 672 2015-05-02 21:58:28Z mueller $
-- $Id: ibdr_rk11.vhd 767 2016-05-26 07:47:51Z mueller $
--
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -29,6 +29,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.3.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
@@ -168,7 +169,7 @@ architecture syn of ibdr_rk11 is
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';

3
rtl/ibus/ibdr_rl11.vbom
View File

@@ -4,6 +4,7 @@
iblib.vhd
# components
[sim]../vlib/memlib/ram_1swar_gen.vbom
[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom
[vsyn]../vlib/memlib/ram_1swar_gen.vbom
# design
ibdr_rl11.vhd

9
rtl/ibus/ibdr_rl11.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibdr_rl11.vhd 655 2015-03-04 20:35:21Z mueller $
-- $Id: ibdr_rl11.vhd 767 2016-05-26 07:47:51Z mueller $
--
-- Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,7 +18,7 @@
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -27,6 +27,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.0.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore
-- 2015-02-28 653 1.0 Initial verison
-- 2014-06-09 561 0.1 First draft
@@ -238,7 +239,7 @@ architecture syn of ibdr_rl11 is
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';

11
rtl/ibus/iblib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: iblib.vhd 672 2015-05-02 21:58:28Z mueller $
-- $Id: iblib.vhd 770 2016-05-28 14:15:00Z mueller $
--
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Definitions for ibus interface and bus entities
--
-- Dependencies: -
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type
-- 2015-04-24 668 2.1 add ibd_ibmon
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon
-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw
@@ -115,8 +116,8 @@ component ib_sres_or_gen is -- ibus result or, generic
end component;
type intmap_type is record -- interrupt map entry type
vec : integer; -- vector address
pri : integer; -- priority
vec : natural; -- vector address
pri : natural; -- priority
end record intmap_type;
constant intmap_init : intmap_type := (0,0);

10
rtl/make_ise/generic_ghdl.mk
View File

@@ -1,10 +1,11 @@
# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $
# $Id: generic_ghdl.mk 778 2016-06-25 15:18:01Z mueller $
#
# Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2016-06-24 778 1.1 use ghdl.?sim as workdir
# 2015-02-14 646 1.4 use --xlpath for vbomconv; drop cygwin support;
# 2014-07-26 575 1.3.2 use XTWI_PATH now (ise/vivado switch done later)
# 2013-01-27 477 1.3.1 use dontincdep.mk to suppress .dep include on clean
@@ -42,9 +43,8 @@ include ${RETROBASE}/rtl/make_ise/dontincdep.mk
ghdl_clean: ghdl_tmp_clean
rm -f $(EXE_all)
rm -f $(EXE_all:%=%_[sft]sim)
rm -f cext_*.o
#
ghdl_tmp_clean:
find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f
rm -f work-obj93.cf
rm -rf ghdl.[bsft]sim
rm -f cext_*.o e~*.o
#

49
rtl/make_ise/generic_xflow.mk
View File

@@ -1,10 +1,12 @@
# $Id: generic_xflow.mk 733 2016-02-20 12:24:13Z mueller $
# $Id: generic_xflow.mk 778 2016-06-25 15:18:01Z mueller $
#
# Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2016-06-25 778 1.11.2 mfset rule: add message if log not found
# 2016-05-27 769 1.11.1 rename mfset to imfset
# 2015-05-02 672 1.11 ucf_cpp handling: remove -C (gcc 4.8 stdc-predef.h)
# 2015-02-06 643 1.10 use make_ise; rename xise_msg_filter <- isemsg_filter
# drop --ise_path from vbomconv;
@@ -100,8 +102,8 @@ XFLOW = xflow -p ${ISE_PATH}
@ echo "==============================================================="
@ echo "* XST Diagnostic Summary *"
@ echo "==============================================================="
@ if [ -r $*.mfset ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi
@ if [ ! -r $*.mfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi
@ if [ -r $*.imfset ]; then xise_msg_filter xst $*.imfset $*_xst.log; fi
@ if [ ! -r $*.imfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi
@ echo "==============================================================="
#
# the following rule needed to generate an %_*sim.vhd in a ./tb sub-directory
@@ -122,8 +124,8 @@ XFLOW = xflow -p ${ISE_PATH}
@ echo "==============================================================="
@ echo "* XST Diagnostic Summary *"
@ echo "==============================================================="
@ if [ -r $*.mfset ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi
@ if [ ! -r $*.mfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi
@ if [ -r $*.imfset ]; then xise_msg_filter xst $*.imfset $*_xst.log; fi
@ if [ ! -r $*.imfset ]; then grep -i -A 1 ":.*:" $*_xst.log || true; fi
@ echo "==============================================================="
#
# Implement 1 (map+par)
@@ -155,19 +157,19 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ./ise/$*_pad.txt ]; then cp -p ./ise/$*_pad.txt ./$*_pad.log; fi
if [ -r ./ise/$*.twr ]; then cp -p ./ise/$*.twr ./$*_twr.log; fi
if [ -r ./ise/$*.tsi ]; then cp -p ./ise/$*.tsi ./$*_tsi.log; fi
@ if [ -r $*.mfset ]; then \
@ if [ -r $*.imfset ]; then \
echo "=============================================================";\
echo "* Translate Diagnostic Summary *";\
echo "=============================================================";\
xise_msg_filter tra $*.mfset $*_tra.log;\
xise_msg_filter tra $*.imfset $*_tra.log;\
echo "=============================================================";\
echo "* MAP Diagnostic Summary *";\
echo "=============================================================";\
xise_msg_filter map $*.mfset $*_map.log;\
xise_msg_filter map $*.imfset $*_map.log;\
echo "=============================================================";\
echo "* PAR Diagnostic Summary *";\
echo "=============================================================";\
xise_msg_filter par $*.mfset $*_par.log;\
xise_msg_filter par $*.imfset $*_par.log;\
echo "=============================================================";\
fi
#
@@ -185,11 +187,11 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ./ise/$*.bit ]; then cp -p ./ise/$*.bit .; fi
if [ -r ./ise/$*.msk ]; then cp -p ./ise/$*.msk .; fi
if [ -r ./ise/$*.bgn ]; then cp -p ./ise/$*.bgn ./$*_bgn.log; fi
@ if [ -r $*.mfset ]; then \
@ if [ -r $*.imfset ]; then \
echo "=============================================================";\
echo "* Bitgen Diagnostic Summary *";\
echo "=============================================================";\
xise_msg_filter bgn $*.mfset $*_bgn.log;\
xise_msg_filter bgn $*.imfset $*_bgn.log;\
echo "=============================================================";\
fi
#
@@ -225,18 +227,27 @@ endif
# Print log file summary
# input: %_*.log (not depended)
# output: .PHONY
%.mfsum: %.mfset
%.mfsum: %.imfset
@ echo "=== XST summary ============================================="
@ if [ -r $*_xst.log ]; then xise_msg_filter xst $*.mfset $*_xst.log; fi
@ if [ -r $*_xst.log ]; \
then xise_msg_filter xst $*.imfset $*_xst.log; \
else echo " !!! no $*_xst.log found"; fi
@ echo "=== Translate summary ======================================="
@ if [ -r $*_tra.log ]; then xise_msg_filter tra $*.mfset $*_tra.log; fi
@ if [ -r $*_tra.log ]; \
then xise_msg_filter tra $*.imfset $*_tra.log; \
else echo " !!! no $*_tra.log found"; fi
@ echo "=== MAP summary ============================================="
@ if [ -r $*_map.log ]; then xise_msg_filter map $*.mfset $*_map.log; fi
@ if [ -r $*_map.log ]; \
then xise_msg_filter map $*.imfset $*_map.log; \
else echo " !!! no $*_map.log found"; fi
@ echo "=== PAR summary ============================================="
@ if [ -r $*_par.log ]; then xise_msg_filter par $*.mfset $*_par.log; fi
@ if [ -r $*_par.log ]; \
then xise_msg_filter par $*.imfset $*_par.log; \
else echo " !!! no $*_par.log found"; fi
@ echo "=== Bitgen summary =========================================="
@ if [ -r $*_bgn.log ]; then xise_msg_filter bgn $*.mfset $*_bgn.log; fi
@ if [ -r $*_bgn.log ]; \
then xise_msg_filter bgn $*.imfset $*_bgn.log; \
else echo " !!! no $*_bgn.log found"; fi
#
#
#

18
rtl/make_viv/generic_ghdl.mk
View File

@@ -1,10 +1,11 @@
# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $
# $Id: generic_ghdl.mk 778 2016-06-25 15:18:01Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2016-06-24 778 1.1 add rsim model; use ghdl.?sim as workdir
# 2015-02-14 646 1.0 Initial version (cloned from make_ise)
#
GHDLIEEE = --ieee=synopsys
@@ -14,12 +15,16 @@ GHDLXLPATH = ${XTWV_PATH}/ghdl
vbomconv --ghdl_i $<
vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $<
#
# rules for _[o]sim to use 'virtual' [o]sim vbom's (derived from _ssim)
# rules for _[or]sim to use 'virtual' [or]sim vbom's (derived from _ssim)
#
%_osim : %_ssim.vbom
vbomconv --ghdl_i $*_osim.vbom
vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_osim.vbom
#
%_rsim : %_ssim.vbom
vbomconv --ghdl_i $*_rsim.vbom
vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_rsim.vbom
#
%.dep_ghdl: %.vbom
vbomconv --dep_ghdl $< > $@
#
@@ -29,10 +34,9 @@ include ${RETROBASE}/rtl/make_ise/dontincdep.mk
#
ghdl_clean: ghdl_tmp_clean
rm -f $(EXE_all)
rm -f $(EXE_all:%=%_[so]sim)
rm -f cext_*.o
rm -f $(EXE_all:%=%_[sor]sim)
#
ghdl_tmp_clean:
find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f
rm -f work-obj93.cf
rm -rf ghdl.[bsor]sim
rm -f cext_*.o e~*.o
#

134
rtl/make_viv/generic_vivado.mk
View File

@@ -1,10 +1,14 @@
# $Id: generic_vivado.mk 733 2016-02-20 12:24:13Z mueller $
# $Id: generic_vivado.mk 778 2016-06-25 15:18:01Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2016-06-24 778 1.3 add rsim.vhd and [sorep]sim.v targets
# 2016-06-11 774 1.2.1 call xviv_sim_vhdl_cleanup for %_[so]sim rules
# 2016-05-27 769 1.2 add xviv_msg_filter support
# 2016-03-26 752 1.1 new %.vivado; separate %_opt.dcp,%_pla.dcp,%_rou.dcp
# 2015-02-15 646 1.0 Initial version
# 2015-01-25 637 0.1 First draft
#---
@@ -37,6 +41,18 @@ endif
# when chaining, don't delete 'expensive' intermediate files:
.SECONDARY :
#
# Setup vivado project
# input: %.vbom vbom project description
# output: .PHONY
#
%.vivado : %.vbom
rm -rf project_mflow
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_BOARD_SETUP} \
-source ${VIV_BUILD_FLOW} \
-tclargs $* prj
#
# Synthesize + Implement -> generate bit file
# input: %.vbom vbom project description
# output: %.bit
@@ -48,6 +64,20 @@ endif
-source ${VIV_BOARD_SETUP} \
-source ${VIV_BUILD_FLOW} \
-tclargs $* bit
@ if [ -r $*.vmfset ]; then make $*.mfsum; fi
#
# Print log file summary
# input: %_*.log (not depended)
# output: .PHONY
%.mfsum: %.vmfset
@ echo "=== Synthesis flow summary =================================="
@ if [ -r $*_syn.log ]; \
then xviv_msg_filter syn $*.vmfset $*_syn.log; \
else echo " !!! no $*_syn.log found"; fi
@ echo "=== Implementation flow summary=============================="
@ if [ -r $*_imp.log ]; \
then xviv_msg_filter imp $*.vmfset $*_imp.log; \
else echo " !!! no $*_imp.log found"; fi
#
# Configure FPGA with vivado hardware server
# input: %.bit
@@ -62,6 +92,7 @@ endif
#
# Partial Synthesize + Implement -> generate dcp for model generation
#
# run synthesis only
%_syn.dcp : %.vbom
rm -rf project_mflow
xtwv vivado -mode batch \
@@ -69,7 +100,27 @@ endif
-source ${VIV_BOARD_SETUP} \
-source ${VIV_BUILD_FLOW} \
-tclargs $* syn
%_opt.dcp %_rou.dcp : %.vbom
#
# run synthesis + implementation up to step opt_design
%_opt.dcp : %.vbom
rm -rf project_mflow
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_BOARD_SETUP} \
-source ${VIV_BUILD_FLOW} \
-tclargs $* opt
#
# run synthesis + implementation up to step place_design
%_pla.dcp : %.vbom
rm -rf project_mflow
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_BOARD_SETUP} \
-source ${VIV_BUILD_FLOW} \
-tclargs $* pla
#
# run synthesis + implementation (but not bit file generation)
%_rou.dcp : %.vbom
rm -rf project_mflow
xtwv vivado -mode batch \
-source ${VIV_INIT} \
@@ -85,7 +136,8 @@ endif
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* ssim
-tclargs $* ssim_vhd
xviv_sim_vhdl_cleanup $@
#
# Post-optimization functional simulation model (Vhdl/Unisim)
# input: %_opt.dcp
@@ -95,7 +147,71 @@ endif
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* osim
-tclargs $* osim_vhd
xviv_sim_vhdl_cleanup $@
#
# Post-routing functional simulation model (Vhdl/Unisim)
# input: %_rou.dcp
# output: %_rsim.vhd
#
%_rsim.vhd : %_rou.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* rsim_vhd
xviv_sim_vhdl_cleanup $@
#
# Post-synthesis functional simulation model (Verilog/Unisim)
# input: %_syn.dcp
# output: %_ssim.v
#
%_ssim.v : %_syn.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* ssim_v
#
# Post-optimization functional simulation model (Verilog/Unisim)
# input: %_opt.dcp
# output: %_osim.v
#
%_osim.v : %_opt.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* osim_v
#
# Post-routing functional simulation model (Verilog/Unisim)
# input: %_rou.dcp
# output: %_rsim.v
#
%_rsim.v : %_rou.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* rsim_v
#
# Post-synthesis timing simulation model (Verilog/Simprim)
# input: %_syn.dcp
# output: %_esim.v
# %_esim.sdf
#
%_esim.v %_esim.sdf : %_syn.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* esim_v
#
# Post-optimization timing simulation model (Verilog/Simprim)
# input: %_opt.dcp
# output: %_psim.v
# %_psim.sdf
#
%_psim.v %_psim.sdf : %_opt.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* psim_v
#
# Post-routing timing simulation model (Verilog/Simprim)
# input: %_rou.dcp
@@ -106,7 +222,7 @@ endif
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* tsim
-tclargs $* tsim_v
#
# vivado project quick starter
#
@@ -133,9 +249,9 @@ viv_clean: viv_tmp_clean
rm -f *.jou
rm -f *.log
rm -f *.rpt
rm -f *_[so]sim.vhd
rm -f *_tsim.v
rm -f *_tsim.sdf
rm -f *_[sor]sim.vhd
rm -f *_[sorept]sim.v
rm -f *_[ept]sim.sdf
#
viv_tmp_clean:
rm -rf ./project_mflow

50
rtl/make_viv/generic_xsim.mk
View File

@@ -1,10 +1,11 @@
# $Id: generic_xsim.mk 733 2016-02-20 12:24:13Z mueller $
# $Id: generic_xsim.mk 778 2016-06-25 15:18:01Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2016-06-24 778 1.1 add [rep]sim models; use xsim.?sim as workdir
# 2016-02-06 727 1.0 Initial version
#
%_XSim : %.vbom
@@ -13,7 +14,7 @@
$*_vsim.sh
rm -rf $*_vsim.sh
#
# rule to build XSim ssim model from _ssim vbom
# rule to build XSim ssim model from _ssim vbom (post synth, functional)
#
%_XSim_ssim : %_ssim.vbom
vbomconv -vsim_prj $< > $*_vsim.sh
@@ -21,7 +22,7 @@
$*_vsim.sh
rm -rf $*_vsim.sh
#
# rule to build XSim osim model from _ssim vbom
# rule to build XSim osim model from _ssim vbom (post opt, functional)
#
%_XSim_osim : %_ssim.vbom
vbomconv -vsim_prj $*_osim.vbom > $*_vsim.sh
@@ -29,7 +30,31 @@
$*_vsim.sh
rm -rf $*_vsim.sh
#
# rule to build XSim tsim model from _ssim vbom
# rule to build XSim rsim model from _ssim vbom (post route, functional)
#
%_XSim_rsim : %_ssim.vbom
vbomconv -vsim_prj $*_rsim.vbom > $*_vsim.sh
chmod +x $*_vsim.sh
$*_vsim.sh
rm -rf $*_vsim.sh
#
# rule to build XSim esim model from _ssim vbom (post synth, timing)
#
%_XSim_esim : %_ssim.vbom
vbomconv -vsim_prj $*_esim.vbom > $*_vsim.sh
chmod +x $*_vsim.sh
$*_vsim.sh
rm -rf $*_vsim.sh
#
# rule to build XSim psim model from _ssim vbom (post opt, timing)
#
%_XSim_psim : %_ssim.vbom
vbomconv -vsim_prj $*_psim.vbom > $*_vsim.sh
chmod +x $*_vsim.sh
$*_vsim.sh
rm -rf $*_vsim.sh
#
# rule to build XSim tsim model from _ssim vbom (post rou, timing)
#
%_XSim_tsim : %_ssim.vbom
vbomconv -vsim_prj $*_tsim.vbom > $*_vsim.sh
@@ -48,13 +73,18 @@ xsim_clean: xsim_tmp_clean
rm -f $(EXE_all:%=%_XSim)
rm -f $(EXE_all:%=%_XSim_ssim)
rm -f $(EXE_all:%=%_XSim_osim)
rm -f $(EXE_all:%=%_XSim_rsim)
rm -f $(EXE_all:%=%_XSim_esim)
rm -f $(EXE_all:%=%_XSim_psim)
rm -f $(EXE_all:%=%_XSim_tsim)
rm -rf xsim.[bsorept]sim
#
xsim_tmp_clean:
rm -f isim.log isim.wdb
rm -f xsim.jou xsim.log
rm -f xsim_*.backup.jou xsim_*.backup.log
rm -f webtalk.jou webtalk.log
rm -f webtalk_*.backup.jou webtalk_*.backup.log
rm -rf xsim.dir
rm -f *.wdb
rm -f xsim.jou xsim_*.backup.jou
rm -f xsim.log xsim_*.backup.log
rm -f webtalk.jou webtalk_*.backup.jou
rm -f webtalk.log webtalk_*.backup.log
rm -rf xsim.[bsorept]sim/xsim.dir/xil_defaultlib
rm -f xsim.dir
#

225
rtl/make_viv/viv_tools_build.tcl
View File

@@ -1,11 +1,17 @@
# $Id: viv_tools_build.tcl 738 2016-03-06 13:02:53Z mueller $
# $Id: viv_tools_build.tcl 767 2016-05-26 07:47:51Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2016-02-28 649 1.1.1 add 2015.4 specific setups
# 2016-05-22 767 1.2 cleaner setup handling; use explore flows
# add 2016.1 specific setups
# 2016-04-02 758 1.1.5 remove USR_ACCESS setup, must be done in xdc
# 2016-03-26 752 1.1.4 more steps supported: prj,opt,pla
# 2016-03-25 751 1.1.3 suppress some messages
# 2016-03-19 748 1.1.2 set bitstream USR_ACCESS to TIMESTAMP
# 2016-02-28 738 1.1.1 add 2015.4 specific setups
# 2015-02-21 649 1.1 add 2014.4 specific setups
# 2015-02-14 646 1.0 Initial version
#
@@ -42,6 +48,13 @@ proc rvtb_mv_file {src dst} {
return ""
}
#
# --------------------------------------------------------------------
#
proc rvtb_rm_file {src} {
exec rm -f $src
}
#
# --------------------------------------------------------------------
#
@@ -58,50 +71,125 @@ proc rvtb_cp_file {src dst} {
# --------------------------------------------------------------------
#
proc rvtb_build_check {step} {
get_msg_config -rules
return ""
}
#
# --------------------------------------------------------------------
#
proc rvtb_version_is {val} {
set vers [version -short]
return [expr {$vers eq $val}]
}
#
# --------------------------------------------------------------------
#
proc rvtb_version_min {val} {
set vers [version -short]
return [expr {[string compare $vers $val] >= 0}]
}
#
# --------------------------------------------------------------------
#
proc rvtb_version_max {val} {
set vers [version -short]
return [expr {[string compare $vers $val] <= 0}]
}
#
# --------------------------------------------------------------------
#
proc rvtb_version_in {min max} {
set vers [version -short]
return [expr {[string compare $vers $min] >= 0 && \
[string compare $vers $max] <= 0}]
}
#
# --------------------------------------------------------------------
#
proc rvtb_default_build {stem step} {
# general setups
switch [version -short] {
"2014.4" {
# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
# set here to avoid messages during create_project
set_msg_config -suppress -id {Board 49-26}
}
"2015.4" {
# enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html
set_param synth.elaboration.rodinMoreOptions \
{rt::set_parameter ignoreVhdlAssertStmts false}
}
# supported step values
# prj setup project
# syn run synthesis
# opt run synthesis + implementation up to step opt_design
# pla run synthesis + implementation up to step place_design
# imp run synthesis + implementation (but not bit file generation)
# bit Synthesize + Implement + generate bit file
if {![regexp -- {^(prj|syn|opt|pla|imp|bit)$} $step]} {
error "bad step name $step"
}
# general setups (prior to project creation) ------------------
# version dependent setups
if {[rvtb_version_is "2014.4"]} {
# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
# set here to avoid messages during create_project
set_msg_config -suppress -id {Board 49-26}
}
# read setup
set setup_file [rvtb_locate_setup_file $stem]
if {$setup_file ne ""} {source -notrace $setup_file}
# Create project
# Create project ----------------------------------------------
rvtb_trace_cmd "create_project project_mflow ./project_mflow"
# Setup project properties
# Setup project properties -------------------------------
set obj [get_projects project_mflow]
set_property "default_lib" "xil_defaultlib" $obj
set_property "part" $::rvtb_part $obj
set_property "simulator_language" "Mixed" $obj
set_property "target_language" "VHDL" $obj
# version dependent setups
switch [version -short] {
"2014.4" {
# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
# repeated here because create_project apparently clears msg_config
set_msg_config -suppress -id {Board 49-26}
}
# general setups -----------------------------------------
# suppress message which don't convey useful information
set_msg_config -suppress -id {DRC 23-20}; # DSP48 output pilelining
set_msg_config -suppress -id {Project 1-120}; # WebTalk mandatory
set_msg_config -suppress -id {Common 17-186}; # WebTalk info send
# Setup list of extra synthesis options (for later rodinMoreOptions)
set synth_more_opts {}
# version independent setups -----------------------------
# setup synthesis and implementation strategies
set_property strategy Flow_PerfOptimized_high [get_runs synth_1]
set_property strategy Performance_Explore [get_runs impl_1]
# FSM recognition threshold (default is 5)
# see http://www.xilinx.com/support/answers/58574.html
lappend synth_more_opts {rt::set_parameter minFsmStates 3}
# version dependent setups -------------------------------
if {[rvtb_version_is "2014.4"]} {
# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
# repeated here because create_project apparently clears msg_config
set_msg_config -suppress -id {Board 49-26}
}
if {[rvtb_version_is "2015.4"]} {
# enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html
lappend synth_more_opts {rt::set_parameter ignoreVhdlAssertStmts false}
}
if {[rvtb_version_min "2016.1"]} {
# enable vhdl asserts via global option (after 2016.1)
set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
}
# now setup extra synthesis options
# see http://www.xilinx.com/support/answers/58248.html
# -> since used via 'set_param' it's a parameter
# -> only last definition counts
# -> use ';' separated list
# -> these options are **NOT** preserved in project file !!
if {[llength $synth_more_opts]} {
puts "# extra synthesis options:"
foreach opt $synth_more_opts { puts "# $opt"}
set_param synth.elaboration.rodinMoreOptions [join $synth_more_opts "; "]
}
# Setup filesets
@@ -109,61 +197,102 @@ proc rvtb_default_build {stem step} {
eval $vbom_prj
update_compile_order -fileset sources_1
if {$step eq "prj"} {
puts "rvtb_default_build-I: new project setup for ${stem}"
return ""
}
# some handy variables
set path_runs "project_mflow/project_mflow.runs"
set path_syn1 "${path_runs}/synth_1"
set path_imp1 "${path_runs}/impl_1"
# build: synthesize
# build: synthesize ------------------------------------------------
puts "# current rodinMoreOptions:"
puts [get_param synth.elaboration.rodinMoreOptions]
rvtb_trace_cmd "launch_runs synth_1"
rvtb_trace_cmd "wait_on_run synth_1"
rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log"
rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt"
rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp"
rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp"
if {$step eq "syn"} {return [rvtb_build_check $step]}
# build: implement
rvtb_trace_cmd "launch_runs impl_1"
# build: implement -------------------------------------------------
set launch_opt ""
if {$step eq "opt"} {set launch_opt "-to_step opt_design"}
if {$step eq "pla"} {set launch_opt "-to_step place_design"}
rvtb_trace_cmd "launch_runs ${launch_opt} impl_1"
rvtb_trace_cmd "wait_on_run impl_1"
rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log"
rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt"
rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt"
rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp"
rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt"
if {$step eq "opt"} {
rvtb_trace_cmd "open_checkpoint $path_imp1/${stem}_opt.dcp"
report_utilization -file "${stem}_opt_util.rpt"
report_utilization -hierarchical -file "${stem}_opt_util_h.rpt"
return [rvtb_build_check $step]
}
rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp"
rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt"
rvtb_cp_file "$path_imp1/${stem}_clock_utilization_placed.rpt" \
"${stem}_pla_clk.rpt"
rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \
"${stem}_rou_tim.rpt"
rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \
"${stem}_pla_util.rpt"
rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt"
rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \
"${stem}_pla_cset.rpt"
rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt"
"${stem}_pla_clk_set.rpt"
rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp"
rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp"
rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp"
if {$step eq "pla"} {
return [rvtb_build_check $step]
}
rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp"
rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt"
rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt"
rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \
"${stem}_rou_tim.rpt"
rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt"
rvtb_cp_file "$path_imp1/${stem}_clock_utilization_routed.rpt" \
"${stem}_rou_clk_util.rpt"
# additional reports
rvtb_trace_cmd "open_run impl_1"
report_utilization -file "${stem}_rou_util.rpt"
report_utilization -file "${stem}_rou_util.rpt"
report_utilization -hierarchical -file "${stem}_rou_util_h.rpt"
report_datasheet -file "${stem}_rou_ds.rpt"
report_datasheet -file "${stem}_rou_ds.rpt"
report_cdc -file "${stem}_rou_cdc.rpt"
report_clock_interaction -delay_type min_max -significant_digits 3 \
-file "${stem}_rou_clk_int.rpt"
if {[get_property SSN_REPORT [get_property PART [current_project]]]} {
report_ssn -format TXT -file "${stem}_rou_ssn.rpt"
}
if {$step eq "imp"} {return [rvtb_build_check $step]}
# build: bitstream
# build: bitstream -------------------------------------------------
# check for critical warnings, e.g.
# [Timing 38-282] The design failed to meet the timing requirements.
# in that case abort build
rvtb_rm_file "./${stem}.bit"
if {[get_msg_config -severity {critical warning} -count]} {
puts "rvtb_default_build-E: abort due to critical warnings seen before"
puts "rvtb_default_build-E: no bitfile generated"
return [rvtb_build_check $step]
}
rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream"
rvtb_trace_cmd "wait_on_run impl_1"
rvtb_mv_file "$path_imp1/${stem}.bit" "."
rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log"
rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log"
rvtb_mv_file "$path_imp1/${stem}.bit" "."
return [rvtb_build_check $step]
}

26
rtl/make_viv/viv_tools_config.tcl
View File

@@ -1,13 +1,27 @@
# $Id: viv_tools_config.tcl 646 2015-02-15 12:04:55Z mueller $
# $Id: viv_tools_config.tcl 758 2016-04-02 18:01:39Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2016-04-02 758 1.1 add USR_ACCESS readback
# 2015-02-14 646 1.0 Initial version
#
#
# --------------------------------------------------------------------
#
proc rvtb_format_usracc {usracc} {
set sec [expr { ($usracc >> 0) & 0x3f } ]; # 6 bit 05:00
set min [expr { ($usracc >> 6) & 0x3f } ]; # 6 bit 11:06
set hr [expr { ($usracc >> 12) & 0x1f } ]; # 5 bit 16:12
set yr [expr {(($usracc >> 17) & 0x3f)+2000} ]; # 6 bit 22:17
set mo [expr { ($usracc >> 23) & 0x0f } ]; # 4 bit 26:23
set day [expr { ($usracc >> 27) & 0x1f } ]; # 5 bit 31:27
return [format "%04d-%02d-%02d %02d:%02d:%02d" $yr $mo $day $hr $min $sec]
}
#
# --------------------------------------------------------------------
#
@@ -25,5 +39,13 @@ proc rvtb_default_config {stem} {
# and configure FPGA
program_hw_devices [lindex [get_hw_devices] 0]
# and check USR_ACCESS setting
set usracc_raw [get_property REGISTER.USR_ACCESS [lindex [get_hw_devices] 0] ]
set usracc_num "0x$usracc_raw"
set usracc_fmt [rvtb_format_usracc $usracc_num]
puts ""
puts "USR_ACCESS: 0x$usracc_raw $usracc_fmt"
puts ""
return "";
}

63
rtl/make_viv/viv_tools_model.tcl
View File

@@ -1,38 +1,59 @@
# $Id: viv_tools_model.tcl 646 2015-02-15 12:04:55Z mueller $
# $Id: viv_tools_model.tcl 778 2016-06-25 15:18:01Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2016-06-24 778 1.1 support mode [sor]sim_vhdl [sorepd]sim_veri
# 2016-06-19 777 1.0.1 use full absolute path name for sdf annotate
# 2015-02-14 646 1.0 Initial version
#
#
# --------------------------------------------------------------------
#
# supported modes
# base ----- func ----- timing
# vhdl veri veri
# post synth _syn.dcp ssim_vhd ssim_v esim_v
# post phys_opt _opt.dcp osim_vhd osim_v psim_v
# post route _rou.dcp rsim_vhd rsim_v tsim_v
#
proc rvtb_default_model {stem mode} {
switch $mode {
ssim {
open_checkpoint "${stem}_syn.dcp"
write_vhdl -mode funcsim -force "${stem}_ssim.vhd"
if {[regexp -- {^([sor])sim_(vhd|v)$} $mode matched type lang] ||
[regexp -- {^([ept])sim_(v)$} $mode matched type lang]} {
switch $type {
s -
e {open_checkpoint "${stem}_syn.dcp"}
o -
p {open_checkpoint "${stem}_opt.dcp"}
r -
t {open_checkpoint "${stem}_rou.dcp"}
}
osim {
open_checkpoint "${stem}_opt.dcp"
write_vhdl -mode funcsim -force "${stem}_osim.vhd"
if {$lang eq "vhd"} {
write_vhdl -mode funcsim -force "${stem}_${type}sim.vhd"
} else {
if {$type eq "s" || $type eq "o" || $type eq "r"} {
write_verilog -mode funcsim -force "${stem}_${type}sim.v"
} else {
# use full absolute path name for sdf annotate
# reason: the _tsim.v is sometimes generated in system path and
# used from the tb path. xelab doesn't find the sdf in that case
# Solution are absolute path (ugly) or symlink (ugly, who does setup..)
write_verilog -mode timesim -force \
-sdf_anno true \
-sdf_file "[pwd]/${stem}_${type}sim.sdf" \
"${stem}_${type}sim.v"
write_sdf -mode timesim -force \
-process_corner slow \
"${stem}_${type}sim.sdf"
}
}
tsim {
open_checkpoint "${stem}_rou.dcp"
write_verilog -mode timesim -force -sdf_anno true "${stem}_tsim.v"
write_sdf -mode timesim -force "${stem}_tsim.sdf"
}
default {
error "-E: bad mode: $mode";
}
} else {
error "rvtb_default_model-E: bad mode: $mode";
}
return "";
}

2
rtl/sys_gen/tst_fx2loop/.cvsignore
View File

@@ -1,2 +0,0 @@
tst_fx2loop
tst_fx2loop_si

41
rtl/sys_gen/tst_fx2loop/Makefile
View File

@@ -1,41 +0,0 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2014-11-08 602 1.3 rename realclean->distclean
# 2013-01-05 470 1.2 fix LDLIBS (must come after objs)
# 2012-02-26 458 1.1 add tst_fx2loop_si
# 2011-12-26 445 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk
#
.PHONY : all clean distclean
#
all : tst_fx2loop tst_fx2loop_si
#
clean : ise_clean
rm -f tst_fx2loop
rm -f tst_fx2loop_si
#
distclean :
rm -f tst_fx2loop tst_fx2loop_si
#
CFLAGS = -Wall -O2 -g
LDLIBS = -lusb-1.0
#
tst_fx2loop : tst_fx2loop.c
${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c ${LDLIBS}
tst_fx2loop_si : tst_fx2loop_si.c
${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c ${LDLIBS}
#
#----
#
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
endif
#

1
rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore
View File

@@ -1 +0,0 @@
sys_tst_fx2loop_ic_n2.ucf

30
rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile
View File

@@ -1,30 +0,0 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-01-15 453 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk
FX2_FILE = nexys2_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#

58
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd
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@@ -1,58 +0,0 @@
-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2;
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

63
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset
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@@ -1,63 +0,0 @@
# $Id: sys_tst_fx2loop_ic_n2.mfset 453 2012-01-15 17:51:18Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Node <TST/R_REGS.tx2data_\d*> of sequential type is unconnected
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS\..*_\d> of sequential type is unconnected
Node <TST/TX2W2B/R_REGS.datl_\d*> of sequential type is unconnected
Node <TST/TX2W2B/R_REGS.dath_\d*> of sequential type is unconnected
Signal <FX2_TX2DATA> is assigned but never used
Input <BTN> is never used
Input <SWI<4>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <I_MEM_WAIT> is never used
Signal <TXODD> is assigned but never used
Signal <TX2ODD> is assigned but never used
Signal <RXODD> is assigned but never used
#
# ----------------------------------------------------------------------------
[tra]
INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP
The Offset constraint .*, is specified without a duration
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
A clock IOB / clock component pair have been found that are not placed at
The Offset constraint .*, is specified without a duration
The signal I_MEM_WAIT_IBUF has no load
The signal I_BTN<1>_IBUF has no load
The signal I_BTN<2>_IBUF has no load
The signal I_BTN<3>_IBUF has no load
There are 4 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
To achieve optimal frequency synthesis performance .* consult
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete

15
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp
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@@ -1,15 +0,0 @@
## $Id: sys_tst_fx2loop_ic_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-12-26 445 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
#include "bplib/nexys2/nexys2_pins.ucf"
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"

8
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom
View File

@@ -1,8 +0,0 @@
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_fx2loop_n2.vbom
@ucf_cpp: sys_tst_fx2loop_ic_n2.ucf
@top: sys_tst_fx2loop_n2

1
rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore
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@@ -1 +0,0 @@
sys_tst_fx2loop_ic3_n2.ucf

30
rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile
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@@ -1,30 +0,0 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-01-15 453 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk
FX2_FILE = nexys2_jtag_3fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#

58
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd
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@@ -1,58 +0,0 @@
-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2;
constant sys_conf_fx2_type : string := "ic3";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

58
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset
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@@ -1,58 +0,0 @@
# $Id: sys_tst_fx2loop_ic3_n2.mfset 453 2012-01-15 17:51:18Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS\..*_\d> of sequential type is unconnected
Input <BTN> is never used
Input <SWI<4>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <I_MEM_WAIT> is never used
Signal <TXODD> is assigned but never used
Signal <TX2ODD> is assigned but never used
Signal <RXODD> is assigned but never used
#
# ----------------------------------------------------------------------------
[tra]
INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP
The Offset constraint .*, is specified without a duration
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
A clock IOB / clock component pair have been found that are not placed at
The Offset constraint .*, is specified without a duration
The signal I_MEM_WAIT_IBUF has no load
The signal I_BTN<1>_IBUF has no load
The signal I_BTN<2>_IBUF has no load
The signal I_BTN<3>_IBUF has no load
There are 4 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
To achieve optimal frequency synthesis performance .* consult
The signal <I_MEM_WAIT_IBUF> is incomplete
The signal <I_BTN<1>_IBUF> is incomplete
The signal <I_BTN<2>_IBUF> is incomplete
The signal <I_BTN<3>_IBUF> is incomplete

15
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp
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@@ -1,15 +0,0 @@
## $Id: sys_tst_fx2loop_ic3_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-12-26 445 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
#include "bplib/nexys2/nexys2_pins.ucf"
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"

8
rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom
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@@ -1,8 +0,0 @@
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_fx2loop_n2.vbom
@ucf_cpp: sys_tst_fx2loop_ic3_n2.ucf
@top: sys_tst_fx2loop_n2

28
rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom
View File

@@ -1,28 +0,0 @@
# this is the vbom for the 'generic' top level entity
# to be referenced in the vbom's of the specific systems
# ./ic/sys_tst_fx2loop_ic_n2
# ./ic3/sys_tst_fx2loop_ic3_n2
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../tst_fx2looplib.vbom
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_fx2loop_hiomap.vbom
../tst_fx2loop.vbom
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_fx2loop_n2.vhd
## no @ucf_cpp

316
rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd
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@@ -1,316 +0,0 @@
-- $Id: sys_tst_fx2loop_n2.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_fx2loop_n2 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
-- tst_fx2loop
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100
-- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-25 638 1.1.1 retire fx2_2fifoctl_as
-- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_fx2looplib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_fx2loop_n2 is -- top level
-- implements nexys2_aif + fx2 pins
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_fx2loop_n2;
architecture syn of sys_tst_fx2loop_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal LED_MAP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '1';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_fx2loop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
SWI => SWI,
BTN => BTN,
LED => LED_MAP,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
begin
if SWI(4) = '1' then
LED(7) <= '0';
LED(6) <= '0';
LED(5) <= FX2_TX2BUSY;
LED(4) <= FX2_TX2ENA;
LED(3) <= FX2_TXBUSY;
LED(2) <= FX2_TXENA;
LED(1) <= FX2_RXHOLD;
LED(0) <= FX2_RXVAL;
else
LED <= LED_MAP;
end if;
end process proc_led;
TST : tst_fx2loop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY
);
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
O_TXD <= I_RXD; -- loop-back in serial port...
end syn;

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rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore
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sys_tst_fx2loop_ic_n3.ucf

30
rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile
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@@ -1,30 +0,0 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-04-09 461 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk
FX2_FILE = nexys3_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#

63
rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd
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@@ -1,63 +0,0 @@
-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2012-04-24 510 1.1 use 3/2 clock-> 150 MHz sysclk
-- 2012-04-09 461 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 2;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

48
rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp
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@@ -1,48 +0,0 @@
## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 556 2014-05-29 19:01:39Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints
## 2012-04-09 461 1.0 Initial version
##
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;
## constrain async pad->pad delays
TIMEGRP TG_SLOW_INS = PADS(I_RXD);
TIMEGRP TG_SLOW_OUTS = PADS(O_TXD);
TIMESPEC TS_ASYNC_PADS=FROM TG_SLOW_INS TO TG_SLOW_OUTS 10 ns;
## FX2 controller specific constraints
## constrain cdc path in fifos and reset
TIMESPEC TS_CDC_FIFO =
FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*
*FIFO/R_REG?_rst?
*FIFO/R_REG?_rst?_s)
TO FFS(*FIFO/R_REG?_?addr_c*
*FIFO/R_REG?_rst?_c
*FIFO/R_REG?_rst?_sc)
5 ns DATAPATHONLY;
## constrain cdc path in monitor
TIMESPEC TS_CDC_FX2MONI = FROM FFS
TO FFS(FX2_CNTL*/R_MONI_C*) 5 ns DATAPATHONLY;
##
## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"
##
## FX2 interface
##
#include "bplib/nexys3/nexys3_pins_fx2.ucf"
#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"

8
rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom
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@@ -1,8 +0,0 @@
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_fx2loop_n3.vbom
@ucf_cpp: sys_tst_fx2loop_ic_n3.ucf
@top: sys_tst_fx2loop_n3

1
rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore
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@@ -1 +0,0 @@
sys_tst_fx2loop_ic3_n3.ucf

30
rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile
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@@ -1,30 +0,0 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-04-09 461 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk
FX2_FILE = nexys3_jtag_3fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#

63
rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd
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@@ -1,63 +0,0 @@
-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2012-04-25 510 1.1 use 3/2 clock-> 150 MHz sysclk
-- 2012-04-09 461 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 2;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_fx2_type : string := "ic3";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

20
rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp
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@@ -1,20 +0,0 @@
## $Id: sys_tst_fx2loop_ic3_n3.ucf_cpp 461 2012-04-09 21:17:54Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2012-04-09 461 1.0 Initial version
##
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"
##
## FX2 interface
##
#include "bplib/nexys3/nexys3_pins_fx2.ucf"
#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"

8
rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom
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@@ -1,8 +0,0 @@
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_fx2loop_n3.vbom
@ucf_cpp: sys_tst_fx2loop_ic3_n3.ucf
@top: sys_tst_fx2loop_n3

28
rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom
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@@ -1,28 +0,0 @@
# this is the vbom for the 'generic' top level entity
# to be referenced in the vbom's of the specific systems
# ./ic/sys_tst_fx2loop_ic_n3
# ./ic3/sys_tst_fx2loop_ic3_n3
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../tst_fx2looplib.vbom
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_fx2loop_hiomap.vbom
../tst_fx2loop.vbom
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_fx2loop_n3.vhd
## no @ucf_cpp

330
rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd
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@@ -1,330 +0,0 @@
-- $Id: sys_tst_fx2loop_n3.vhd 638 2015-01-25 22:01:38Z mueller $
--
-- Copyright 2012-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_fx2loop_n3 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
-- tst_fx2loop
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-04-25 510 14.5 P58f xc6slx16-2 416 516 68 199 p 5.3 ic3/150
-- 2013-04-24 510 13.3 O76d xc6slx16-2 417 674 68 228 p 5.3 ic3/175
-- 2012-04-09 461 13.3 O76d xc6slx16-2 429 620 48 232 p 7.2 ic3/100
--
-- 2013-04-25 510 14.5 P58f xc6slx16-2 349 427 48 163 p 5.4 ic2/150
-- 2013-04-24 510 13.3 O76d xc6slx16-2 355 569 48 208 p 5.4 ic2/175
-- 2012-04-09 461 13.3 O76d xc6slx16-2 347 499 32 175 p 7.9 ic2/100
--
-- 2013-04-24 510 13.3 O76d xc6slx16-2 299 486 32 175 p FAIL as2/100
-- 2012-04-09 461 13.3 O76d xc6slx16-2 299 460 32 164 p FAIL as2/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk
-- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_fx2looplib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_fx2loop_n3 is -- top level
-- implements nexys3_aif + fx2 pins
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_fx2loop_n3;
architecture syn of sys_tst_fx2loop_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal LED_MAP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '1';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 8, -- good for up to 255 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_fx2loop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED_MAP,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
begin
if SWI(4) = '1' then
LED(7) <= '0';
LED(6) <= '0';
LED(5) <= FX2_TX2BUSY;
LED(4) <= FX2_TX2ENA;
LED(3) <= FX2_TXBUSY;
LED(2) <= FX2_TXENA;
LED(1) <= FX2_RXHOLD;
LED(0) <= FX2_RXVAL;
else
LED <= LED_MAP;
end if;
end process proc_led;
TST : tst_fx2loop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY
);
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
O_TXD <= I_RXD; -- loop-back in serial port...
end syn;

1045
rtl/sys_gen/tst_fx2loop/tst_fx2loop.c
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rtl/sys_gen/tst_fx2loop/tst_fx2loop.vbom
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# libs
../../vlib/slvtypes.vhd
../../vlib/comlib/comlib.vhd
../../bplib/fx2lib/fx2lib.vhd
tst_fx2looplib.vhd
# components
../../vlib/comlib/byte2word.vbom
../../vlib/comlib/word2byte.vbom
# design
tst_fx2loop.vhd

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rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd
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-- $Id: tst_fx2loop.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop - syn
-- Description: simple stand-alone tester for fx2lib components
--
-- Dependencies: comlib/byte2word
-- comlib/word2byte
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-24 510 1.0.1 fix sensitivity list of proc_next
-- 2012-01-15 453 1.0 Initial version
-- 2011-12-26 445 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
-- ----------------------------------------------------------------------------
entity tst_fx2loop is -- tester for fx2lib components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit; -- transmit busy
TX2DATA : out slv8; -- transmit 2 data in
TX2ENA : out slbit; -- transmit 2 data enable
TX2BUSY : in slbit -- transmit 2 busy
);
end tst_fx2loop;
architecture syn of tst_fx2loop is
type regs_type is record
rxdata : slv16; -- next rx word
txdata : slv16; -- next tx word
tx2data : slv16; -- next tx2 word
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx word counter
txcnt : slv32; -- tx word counter
tx2cnt : slv32; -- tx2 word counter
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- tx2data
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- tx2cnt
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RXWDATA : slv16 := (others=>'0');
signal RXWVAL : slbit := '0';
signal RXWHOLD : slbit := '0';
signal RXODD : slbit := '0';
signal TXWDATA : slv16 := (others=>'0');
signal TXWENA : slbit := '0';
signal TXWBUSY : slbit := '0';
signal TXODD : slbit := '0';
signal TX2WDATA : slv16 := (others=>'0');
signal TX2WENA : slbit := '0';
signal TX2WBUSY : slbit := '0';
signal TX2ODD : slbit := '0';
signal RXHOLD_L : slbit := '0'; -- local copy of out port signal
signal TXENA_L : slbit := '0'; -- local copy of out port signal
signal TX2ENA_L : slbit := '0'; -- local copy of out port signal
signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal
begin
CNTL_RESET_L <= '0'; -- so far unused
RXB2W : byte2word
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => RXDATA,
ENA => RXVAL,
BUSY => RXHOLD_L,
DO => RXWDATA,
VAL => RXWVAL,
HOLD => RXWHOLD,
ODD => RXODD
);
TX1W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TXWDATA,
ENA => TXWENA,
BUSY => TXWBUSY,
DO => TXDATA,
VAL => TXENA_L,
HOLD => TXBUSY,
ODD => TXODD
);
TX2W2B : word2byte
port map (
CLK => CLK,
RESET => CNTL_RESET_L,
DI => TX2WDATA,
ENA => TX2WENA,
BUSY => TX2WBUSY,
DO => TX2DATA,
VAL => TX2ENA_L,
HOLD => TX2BUSY,
ODD => TX2ODD
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI,
RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY,
RXHOLD_L, TXBUSY, TX2BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxwhold : slbit := '1';
variable itxwena : slbit := '0';
variable itxwdata : slv16 := (others=>'0');
variable itx2wena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irxwhold := '1';
itxwena := '0';
itxwdata := RXWDATA;
itx2wena := '0';
if HIO_CNTL.throttle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXWVAL='1' and r.rxthrottle='0' then
irxwhold := '0';
if RXWDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := slv(unsigned(RXWDATA) + 1);
end if;
when c_mode_txblast =>
itxwdata := r.txdata;
if TXWBUSY = '0' then
itxwena := '1';
n.txdata := slv(unsigned(r.txdata) + 1);
end if;
irxwhold := '0';
when c_mode_loop =>
itxwdata := RXWDATA;
if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then
irxwhold := '0';
itxwena := '1';
end if;
when others => null;
end case;
if HIO_CNTL.tx2blast = '1' then
if TX2WBUSY = '0' then
itx2wena := '1';
n.tx2data := slv(unsigned(r.tx2data) + 1);
end if;
end if;
if RXWVAL='1' and irxwhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxwena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
if itx2wena = '1' then
n.tx2cnt := slv(unsigned(r.tx2cnt) + 1);
end if;
N_REGS <= n;
RXWHOLD <= irxwhold;
TXWENA <= itxwena;
TXWDATA <= itxwdata;
TX2WENA <= itx2wena;
TX2WDATA <= r.tx2data;
HIO_STAT.rxhold <= RXHOLD_L;
HIO_STAT.txbusy <= TXBUSY;
HIO_STAT.tx2busy <= TX2BUSY;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.tx2cnt <= r.tx2cnt;
end process proc_next;
RXHOLD <= RXHOLD_L;
TXENA <= TXENA_L;
TX2ENA <= TX2ENA_L;
end syn;

7
rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom
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@@ -1,7 +0,0 @@
# libs
../../vlib/slvtypes.vhd
../../bplib/fx2lib/fx2lib.vhd
tst_fx2looplib.vbom
# components
# design
tst_fx2loop_hiomap.vhd

194
rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd
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@@ -1,194 +0,0 @@
-- $Id: tst_fx2loop_hiomap.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_fx2loop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage
-- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout
-- 2011-12-26 445 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3) -- unused --
-- (2) -- unused --
-- (1) -- unused --
-- (0) reset state [!! decoded by top level design !!]
--
-- SWI(7:5) select display
-- (4) -- unused --
-- (3) throttle
-- (2) tx2blast
-- (1:0) mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
--
-- LED(7) MONI.fifo_ep4
-- (6) MONI.fifo_ep6
-- (5) MONI.fifo_ep8
-- (4) MONI.flag_ep4_empty
-- (3) MONI.flag_ep4_almost
-- (2) MONI.flag_ep6_full
-- (1) MONI.flag_ep6_almost
-- (0) rxsecnt > 0 (sequence error)
--
-- DSP data as selected by SWI(7:5)
-- 000 -> rxsecnt
-- 001 -> -- unused -- (display ffff)
-- 010 -> rxcnt.l
-- 011 -> rxcnt.h
-- 100 -> txcnt.l
-- 101 -> txcnt.h
-- 110 -> tx2cnt.l
-- 111 -> tx2cnt.h
--
-- DP(3) FX2_TXBUSY (shows tx back preasure)
-- (2) FX2_MONI.slwr (shows tx activity)
-- (1) FX2_RXHOLD (shows rx back preasure)
-- (0) FX2_MONI.slrd (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.fx2lib.all;
use work.tst_fx2looplib.all;
-- ----------------------------------------------------------------------------
entity tst_fx2loop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_fx2loop_hiomap;
architecture syn of tst_fx2loop_hiomap is
type regs_type is record
dspdat : slv16; -- display data
dummy : slbit; -- <remove when 2nd signal added...>
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- dspdat
'0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
-- setup tester controls
icntl.mode := SWI(1 downto 0);
icntl.tx2blast := SWI(2);
icntl.throttle := SWI(3);
-- setup leds
iled(7) := FX2_MONI.fifo_ep4;
iled(6) := FX2_MONI.fifo_ep6;
iled(5) := FX2_MONI.fifo_ep8;
iled(4) := FX2_MONI.flag_ep4_empty;
iled(3) := FX2_MONI.flag_ep4_almost;
iled(2) := FX2_MONI.flag_ep6_full;
iled(1) := FX2_MONI.flag_ep6_almost;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if;
-- setup display data
case SWI(7 downto 5) is
when "000" => idat := HIO_STAT.rxsecnt;
when "001" => idat := (others=>'1');
when "010" => idat := HIO_STAT.rxcnt(15 downto 0);
when "011" => idat := HIO_STAT.rxcnt(31 downto 16);
when "100" => idat := HIO_STAT.txcnt(15 downto 0);
when "101" => idat := HIO_STAT.txcnt(31 downto 16);
when "110" => idat := HIO_STAT.tx2cnt(15 downto 0);
when "111" => idat := HIO_STAT.tx2cnt(31 downto 16);
when others => null;
end case;
n.dspdat := idat;
-- setup display decimal points
idp(3) := HIO_STAT.txbusy; -- tx back preasure
idp(2) := FX2_MONI.slwr; -- tx activity
idp(1) := HIO_STAT.rxhold; -- rx back preasure
idp(0) := FX2_MONI.slrd; -- rx activity
N_REGS <= n;
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;

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