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279 lines
8.2 KiB
VHDL
279 lines
8.2 KiB
VHDL
-- $Id: tb_cdata2byte.vhd 790 2016-07-20 18:52:44Z mueller $
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--
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-- Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: tb_cdata2byte - sim
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-- Description: Test bench for cdata2byte and byte2cdata
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--
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-- Dependencies: simlib/simclk
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-- simlib/simclkcnt
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-- tbd_cdata2byte [UUT]
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--
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-- To test: cdata2byte
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-- byte2cdata
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--
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-- Target Devices: generic
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--
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-- Verified (with tb_cdata2byte_stim.dat):
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-- Date Rev Code ghdl ise Target Comment
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-- 2014-10-25 599 _ssim 0.31 17.1 sc6slx16 c: ok
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-- 2014-10-25 599 - 0.31 - c: ok
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2014-10-25 599 1.1.1 use wait_* to control stim and moni timing
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-- 2014-10-19 598 1.1 use simfifo with shared variables
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-- 2014-10-18 597 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.simlib.all;
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use work.comlib.all;
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entity tb_cdata2byte is
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end tb_cdata2byte;
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architecture sim of tb_cdata2byte is
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constant clk_dsc : clock_dsc := (20 ns, 1 ns, 1 ns);
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constant clk_offset : Delay_length := 200 ns;
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signal CLK : slbit := '0';
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signal RESET : slbit := '0';
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signal CLK_STOP : slbit := '0';
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signal CLK_CYCLE : integer := 0;
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signal C2B_ESCXON : slbit := '0';
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signal C2B_ESCFILL : slbit := '0';
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signal C2B_DI : slv9 := (others=>'0');
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signal C2B_ENA : slbit := '0';
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signal C2B_BUSY : slbit := '0';
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signal C2B_DO : slv8 := (others=>'0');
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signal C2B_VAL : slbit := '0';
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signal B2C_BUSY : slbit := '0';
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signal B2C_DO : slv9 := (others=>'0');
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signal B2C_VAL : slbit := '0';
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signal B2C_HOLD : slbit := '0';
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shared variable sv_sff_monc_cnt : natural := 0;
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shared variable sv_sff_monc_arr : simfifo_type(0 to 7, 7 downto 0);
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shared variable sv_sff_monb_cnt : natural := 0;
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shared variable sv_sff_monb_arr : simfifo_type(0 to 7, 8 downto 0);
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begin
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CLKGEN : simclk
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generic map (
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PERIOD => clk_dsc.period,
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OFFSET => clk_offset)
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port map (
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CLK => CLK,
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CLK_STOP => CLK_STOP
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);
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CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
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UUT : entity work.tbd_cdata2byte
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port map (
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CLK => CLK,
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RESET => RESET,
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C2B_ESCXON => C2B_ESCXON,
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C2B_ESCFILL => C2B_ESCFILL,
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C2B_DI => C2B_DI,
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C2B_ENA => C2B_ENA,
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C2B_BUSY => C2B_BUSY,
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C2B_DO => C2B_DO,
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C2B_VAL => C2B_VAL,
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B2C_BUSY => B2C_BUSY,
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B2C_DO => B2C_DO,
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B2C_VAL => B2C_VAL,
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B2C_HOLD => B2C_HOLD
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);
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proc_stim: process
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file fstim : text open read_mode is "tb_cdata2byte_stim";
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variable iline : line;
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variable oline : line;
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variable ok : boolean;
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variable dname : string(1 to 6) := (others=>' ');
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variable idel : natural := 0;
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variable ilen : natural := 0;
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variable nbusy : integer := 0;
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variable iesc : slbit := '0';
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variable itxdata9 : slbit := '0';
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variable itxdata : slv8 := (others=>'0');
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variable irxdata9 : slbit := '0';
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variable irxdata : slv8 := (others=>'0');
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variable dat9 : slv9 := (others=>'0');
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begin
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wait_nextstim(CLK, clk_dsc);
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file_loop: while not endfile(fstim) loop
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readline (fstim, iline);
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readcomment(iline, ok);
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next file_loop when ok;
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readword(iline, dname, ok);
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if ok then
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case dname is
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when ".reset" => -- .reset
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write(oline, string'(".reset"));
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writeline(output, oline);
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RESET <= '1';
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wait_nextstim(CLK, clk_dsc);
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RESET <= '0';
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wait_nextstim(CLK, clk_dsc);
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when ".wait " => -- .wait
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read_ea(iline, idel);
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wait_nextstim(CLK, clk_dsc, idel);
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when "escxon" => -- escxon
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read_ea(iline, iesc);
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C2B_ESCXON <= iesc;
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when "escfil" => -- escfil
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read_ea(iline, iesc);
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C2B_ESCFILL <= iesc;
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when "bhold " => -- bhold
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read_ea(iline, idel);
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read_ea(iline, ilen);
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B2C_HOLD <= '1' after idel*clk_dsc.period,
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'0' after (idel+ilen)*clk_dsc.period;
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when "data " => -- data
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read_ea(iline, itxdata9);
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readgen_ea(iline, itxdata);
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read_ea(iline, irxdata9);
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if irxdata9 = '0' then
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simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, itxdata);
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else
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readgen_ea(iline, irxdata);
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simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, c_cdata_escape);
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simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, irxdata);
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end if;
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dat9 := itxdata9 & itxdata;
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simfifo_put(sv_sff_monb_cnt, sv_sff_monb_arr, dat9);
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C2B_DI <= dat9;
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C2B_ENA <= '1';
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wait_stim2moni(CLK, clk_dsc);
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wait_untilsignal(CLK, clk_dsc, C2B_BUSY, '0', nbusy);
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writetimestamp(oline, CLK_CYCLE, ": stim ");
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write(oline, itxdata9, right, 2);
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write(oline, itxdata, right, 9);
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writeoptint(oline, " nbusy=", nbusy);
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writeline(output, oline);
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wait_nextstim(CLK, clk_dsc);
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C2B_ENA <= '0';
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when others => -- unknown command
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write(oline, string'("?? unknown command: "));
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write(oline, dname);
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writeline(output, oline);
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report "aborting" severity failure;
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end case;
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else
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report "failed to find command" severity failure;
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end if;
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testempty_ea(iline);
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end loop; -- file_loop:
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writetimestamp(oline, CLK_CYCLE, ": DONE ");
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writeline(output, oline);
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wait_nextstim(CLK, clk_dsc, 12);
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CLK_STOP <= '1';
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wait; -- suspend proc_stim forever
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-- clock is stopped, sim will end
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end process proc_stim;
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proc_monc: process
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variable oline : line;
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variable nhold : integer := 0;
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begin
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loop
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wait_nextmoni(CLK, clk_dsc);
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if C2B_VAL = '1' then
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if B2C_BUSY = '1' then -- c2b_hold = b2c_busy !
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nhold := nhold + 1;
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else
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writetimestamp(oline, CLK_CYCLE, ": monc ");
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write(oline, string'(" "));
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write(oline, C2B_DO, right, 9);
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writeoptint(oline, " nhold=", nhold);
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simfifo_writetest(oline, sv_sff_monc_cnt, sv_sff_monc_arr, C2B_DO);
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writeline(output, oline);
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nhold := 0;
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end if;
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end if;
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end loop;
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end process proc_monc;
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proc_monb: process
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variable oline : line;
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variable nhold : integer := 0;
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begin
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loop
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wait_nextmoni(CLK, clk_dsc);
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if B2C_VAL = '1' then
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if B2C_HOLD = '1' then
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nhold := nhold + 1;
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else
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writetimestamp(oline, CLK_CYCLE, ": monb ");
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write(oline, B2C_DO(8), right, 2);
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write(oline, B2C_DO(7 downto 0), right, 9);
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writeoptint(oline, " nhold=", nhold);
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simfifo_writetest(oline, sv_sff_monb_cnt, sv_sff_monb_arr, B2C_DO);
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writeline(output, oline);
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nhold := 0;
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end if;
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end if;
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end loop;
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end process proc_monb;
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end sim;
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