github.com/wfjm.w11
1
0
Fork 0
mirror of https://github.com/wfjm/w11.git synced 2026-04-19 02:17:23 +00:00
Code Issues Releases Wiki Activity

- upgraded CRAM controller, now with 'page mode' support

Browse Source 
- new test bench driver tbrun, give automatized test bench execution
This commit is contained in:
Walter F.J. Mueller
2016-10-15 07:42:21 +00:00
parent 2b5cfb7d96
commit 5983b0bb2a
402 changed files with 18795 additions and 1204 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 772 2016-06-05 12:55:11Z mueller $
# $Id: Makefile 810 2016-10-02 16:51:12Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@@ -6,8 +6,11 @@
#
# Revision History:
# Date Rev Version Comment
# 2016-10-01 810 1.2.6 move component tests to SIM_viv when vivado used
# 2016-07-10 785 1.2.5 re-enable rtl/sys_gen/tst_sram/nexys4 (ok in 2016.2)
# 2016-06-05 772 1.2.4 add vmfsum,imfsum targets
# 2016-03-19 748 1.2.3 comment out legacy designs and tests
# 2016-02-19 733 1.2.2 disable rtl/sys_gen/tst_sram/nexys4 (fails in 2015.4)
# 2016-02-19 732 1.2.1 remove dispunit syn and sim entries
# 2015-02-01 640 1.2 add vivado targets, separate from ise targets
# 2015-01-25 638 1.1 drop as type fx2 targets
@@ -29,6 +32,7 @@
SYN_ise += rtl/sys_gen/tst_rlink/s3board
SYN_ise += rtl/sys_gen/tst_serloop/s3board
SYN_ise += rtl/sys_gen/tst_snhumanio/s3board
SYN_ise += rtl/sys_gen/tst_sram/s3board
SYN_ise += rtl/sys_gen/w11a/s3board
# Nexys2 -------------------------------------
@@ -39,6 +43,7 @@ SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
#SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
SYN_ise += rtl/sys_gen/tst_serloop/nexys2
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2
SYN_ise += rtl/sys_gen/tst_sram/nexys2
SYN_ise += rtl/sys_gen/w11a/nexys2
# Nexys3 -------------------------------------
@@ -48,6 +53,7 @@ SYN_ise += rtl/sys_gen/tst_rlink/nexys3
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
SYN_ise += rtl/sys_gen/tst_serloop/nexys3
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3
SYN_ise += rtl/sys_gen/tst_sram/nexys3
SYN_ise += rtl/sys_gen/w11a/nexys3
# Vivado based targets, by board type --------------------
@@ -61,6 +67,7 @@ SYN_viv += rtl/sys_gen/w11a/basys3
SYN_viv += rtl/sys_gen/tst_rlink/nexys4
SYN_viv += rtl/sys_gen/tst_serloop/nexys4
SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4
SYN_viv += rtl/sys_gen/tst_sram/nexys4
SYN_viv += rtl/sys_gen/w11a/nexys4
# Arty ---------------------------------------
@@ -71,30 +78,38 @@ SYN_viv += rtl/sys_gen/w11a/arty_bram
# ISE flow -----------------------------------------------
# Component tests ----------------------------
SIM_ise += rtl/bplib/nxcramlib/tb
SIM_ise += rtl/vlib/comlib/tb
SIM_ise += rtl/vlib/rlink/tb
SIM_ise += rtl/vlib/serport/tb
SIM_ise += rtl/w11a/tb
# S3board ------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/s3board/tb
SIM_ise += rtl/sys_gen/tst_serloop/s3board/tb
SIM_ise += rtl/sys_gen/tst_sram/s3board/tb
SIM_ise += rtl/sys_gen/w11a/s3board/tb
# Nexys2 -------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/nexys2/tb
SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys2/tb
SIM_ise += rtl/sys_gen/tst_sram/nexys2/tb
SIM_ise += rtl/sys_gen/w11a/nexys2/tb
# Nexys3 -------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/nexys3/tb
SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb
SIM_ise += rtl/sys_gen/tst_sram/nexys3/tb
SIM_ise += rtl/sys_gen/w11a/nexys3/tb
# Vivado flow --------------------------------------------
# Component tests ----------------------------
SIM_viv += rtl/bplib/issi/tb
SIM_viv += rtl/bplib/micron/tb
SIM_viv += rtl/bplib/nxcramlib/tb
SIM_viv += rtl/vlib/comlib/tb
SIM_viv += rtl/vlib/rlink/tb
SIM_viv += rtl/vlib/serport/tb
SIM_viv += rtl/w11a/tb
# Basys3 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb
#SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb
@@ -103,6 +118,7 @@ SIM_viv += rtl/sys_gen/w11a/basys3/tb
# Nexys4 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/nexys4/tb
SIM_viv += rtl/sys_gen/tst_serloop/nexys4/tb
SIM_viv += rtl/sys_gen/tst_sram/nexys4/tb
SIM_viv += rtl/sys_gen/w11a/nexys4/tb
# Arty ---------------------------------------

154
doc/README.txt
View File

@@ -1,4 +1,4 @@
$Id: README.txt 779 2016-06-26 15:37:16Z mueller $
$Id: README.txt 811 2016-10-03 07:24:02Z mueller $
Release notes for w11a
@@ -22,6 +22,156 @@ Release notes for w11a
2. Change Log ----------------------------------------------------------------
- trunk (2016-10-02: svn rev 37(oc) 811(wfjm); untagged w11a_V0.74) +++++++++
- Preface
- the current version of the memory controller for the micron mt45w8mw16b
'cellular ram' used on nexys2, nexys3, and nexys4 uses the asynchronous
access mode. The device supports a 'page mode' to speed up read access to
subsequent addresses. Even though prepared in the controller logic this
feature was simply forgotten. This is now properly implemented and
results in a bit faster cache line load times. The overall performance
of a w11a design is measurably, but marginally better.
- many unit tests still used a ISE environment. All board independent
tests were converted now to a vivado environment, only tests which
really depend a FPGA not supported by vivado stay with ISE.
- a total of 82 unit or system tests are currently available. Many of them
can be executed by different simulation engines, ghdl or the ISE/vivado
build-in simulators, and for different stages of the implementation flow,
from initial behavioral simulation over post-synthesis functional to final
post-routing timing simulation. This results in a large number of possible
tests. All test benches are all self-checking, but the execution of them
was so far not sufficiently automatized.
This was addressed with 'tbrun', a test bench driver, which obtains a
list of all available test benches from configuration files, selects
a subset given by selection criteria, and executes them. It can handle
the parallel execution of tests so multi-core systems can be very
easily exploited. Running all tests is now a single shell command.
- a new tool 'tbfilt' simplifies the logic of self-checking test benches
and can also be used as a tool to analyze the full log files produced
by the test benches
- several test benches have been added to this release, most notably the
memory tester sys_tst_sram_* which was originally developed to verify
the s3board SRAM controller and later ported to verify the nexys* CRAM
controller.
- the system test benches with SRAM and CRAM now include the PCB trace
delay between FPGA and memory chip. The new entity simbididly models a
bi-directional bus delay.
- so far test benches ended by stopping the clock, all processes were
written such that they enter a permanent wait, which causes the simulation
to stop. Worked for fine behavioral simulations, but fails when Xilinx
MMCMs are involved in post-synthesis simulations. The UNISIM models
apparently have timed waits. The test benches were modified to stop via a
report with severity failure, the test environment detects this specific
assertion/report failure and accepts it as successful termination of
the simulation.
- the configuration of the board switches in system test benches was done
in a sub-optimal way which could lead to startup problems. tbrun_tbwrri
uses now a different mechanism which ensures that all board and test
bench configuration is done in the first ns of the simulation and has
thus completed well before all other activities.
- finally a caveat: post-synthesis simulations work fine with ISE, but
currently not with vivado, even in case of almost identical designs,
like sys_tst_rlink_n3 vs sys_tst_rlink_n4. Is under investigation.
- Summary
- upgraded CRAM controller, now with 'page mode' support
- new test bench driver tbrun, give automatized test bench execution
- New features
- new modules
- rtl/bplib/issi/tb/* - added unit test for is61lv25616al model
- rtl/bplib/micron/tb/* - added unit test for mt45w8mw16b model
- rtl/sys_gen/tst_serloop - add serloop2 (2 clock) designs for n3,n4
- nexys3/sys_tst_serloop2_n3.vhd
- nexys4/sys_tst_serloop2_n4.vhd
- rtl/sys_gen/tst_sram - add sram test design for
- nexys2/*
- nexys3/*
- nexys4/*
- s3board/*
- rtl/vlib/genlib/tb
- clkdivce_tb.vhd - copy for tb usage of clkdivce
- rtl/vlib/rlink/tb
- rlink_tba.vhd - rlink test bench adapter
- tb_rlink_tba.vhd - test bench for rbus devices
- tbd_tba_ttcombo.vhd - tba tester for ttcombo
- rtl/vlib/simlib
- simbididly.vhd - bi-di bus delay model
- rtl/vlib/xlib
- gsr_pulse.vhd - pulse GSR at startup
- gsr_pulse_dummy.vhd - no-action dummy (for bsim models)
- rtl/w11a/tb
- tb_rlink_tba_pdp11core.vhd - tba tester for w11a
- new files
- doc/man/man1 - added tbrun,tbfilt man pages
- */tbrun.yml - test bench descriptors for tbrun
- rtl/sys_gen/w11a/tb
- tb_w11a_mem70*.dat - stim files for additional tests
- rtl/w11a/tb
- tb_pdp11core_ubmap.dat - stim files for additional test
- tools/bin
- njobihtm - determine #jobs
- tbfilt - test bench output filter
- tbrun - test bench driver
- ticonv_rri - converts old 'mode rri' for ti_rri
- tools/tcl/tst_sram/*.tcl - support for sys_tst_sram
- Changes
- rtl/bplib
- arty/tb/tb_arty.vhd - add gsr_pulse (provisional....)
- */tb/tb_*.vhd - tbcore_rlink without CLK_STOP now
- fx2lib/tb/fx2_2fifo_core.vhd - proc_ifclk: remove clock stop
- nexys2/tb/tb_nexys2_core.vhd - use simbididly
- nexys3/tb/tb_nexys3_core.vhd - use simbididly
- nexys4/tb/tb_nexys4_cram.vhd - use simbididly
- nxcramlib
- nx_cram_memctl_as.vhd - add page mode support
- nxcramlib.vhd - add cram_*delay functions
- s3board
- s3_sram_memctl.vhd - drop "KEEP" for data (better for dbg)
- tb/tb_s3board_core.vhd - use simbididly
- rtl/make_ise
- generic_ghdl.mk - ghdl_clean: remove also gcov files
- rtl/make_viv
- generic_ghdl.mk - ghdl_clean: remove also gcov files
- generic_vivado.mk - viv_clean: rm only vivado logs
- generic_xsim.mk - xsim work dir now xsim.<mode>.<stem>
- rtl/sys_gen/tst_serloop
- */tb/tb_tst_serloop*.vhd - remove CLK_STOP logic
- tb/tb_tst_serloop.vhd - remove CLK_STOP logic
- rtl/sys_gen/w11a/nexys*
- sys_conf.vhd - use cram_*delay functions
- rtl/vlib/rlink
- rlink_core.vhd - remove 'assert false' from report stmts
- tb/tb_rlink.vhd - use clkdivce_tb
- tbcore/tbcore_rlink.vhd - conf: add .wait, CONF_DONE; drop CLK_STOP
- rtl/vlib/simlib
- simbus.vhd - rename SB_CLKSTOP > SB_SIMSTOP
- simclk.vhd - CLK_STOP now optional port
- rtl/vlib/xlib
- */s*_cmt_sfs_*.vhd - remove 'assert false' from report stmts
- tools/bin
- tbrun_tbwrri - add --r(l|b)mon,(b|s)wait; configure
now via _conf={...}
- tbw - use {} as delimiter for immediate mode
- vbomconv - add VBOMCONV_GHDL_OPTS and .._GHDL_GCOV
- xise_ghdl_* - add ghdlopts as 1st option; def is -O2
- removed files
- tools/bin/ghdl_assert_filter - obsolete (use tbfilt now)
- renames
- rtl/make_viv/viv_*.tcl -> tools/vivado - separate make and tools
- Bug fixes
- tools/bin
- tbw - xsim: append -R to ARGV (was prepended...)
- xtwi - add ":." to PATH even under BARE_PATH
- Known issues
- all issues: see README_known_issues.txt
- no resolved or new issues in this release
- trunk (2016-06-26: svn rev 36(oc) 779(wfjm); untagged w11a_V0.73) +++++++++
- Preface
- the 'basic vivado support' added with V0.64 was a minimal effort port of
@@ -120,7 +270,7 @@ Release notes for w11a
- serport_2clock2.vhd - like serport_2clock, use fifo_2c_dram2
- rtl/vlib/xlib
- usr_access_unisim.vhd - Wrapper for USR_ACCESS* entities
- new files
- new files
- tools/bin
- xise_msg_summary - list all filtered ISE messages
- xviv_msg_filter - message filter for vivado

75
doc/man/man1/njobihtm.1 Normal file
View File

@@ -0,0 +1,75 @@
.\" -*- nroff -*-
.\" $Id: njobihtm.1 810 2016-10-02 16:51:12Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH NJOBIHTM 1 2016-10-01 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
njobihtm \- number of jobs considering hyper-threading and memory
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY njobihtm
.OP -v
.OP -m nnn[MG]
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBnjobihtm\fP determines the number of CPU-intensive jobs based on the
number of CPU and memory resources. The 'ihtm' stands for 'intelligent
hyper-threading and memory'. The script
.RS 2
.PD 0
.IP "-" 2
determines the number of physical cores and the number of threads per core
.IP "-"
assumes that only a quarter of the additional hyper-threads are useful
.IP "-"
if \fB-m\fP is given. determines the memory size, assumes that at least
one GB should be available for general usage, and limits the number of
jobs accordingly.
.PD
.RE
.PP
The number of jobs is written to STDOUT, and can be used like `njobs`.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" -- --mem -------------------------------------
.IP \fB\-m\ \fIsize\fR
gives the required physical memory per job.
\fIsize\fP must be given as integer with either a 'M' or 'G', indicating MB
or GB.
.
.\" -- --verbose ---------------------------------
.IP \fB\-v\fP
if given the found system parameters and the reasoning is printed to STDERR.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBmake -j `njobihtm` all\fR" 4
Start \fBmake\fR(1) with a reasonable number of jobs.
.IP "\fBnjobihtm -v -m=2G\fR" 4
Determines the number of jobs with 2 GB memory per job. On a system with 4 cores
and hyper-threading and 8 GB installed memory one gets due to the '-v' the
output
.EX
#cpus: 8
#thread/cpu: 2
#cores: 4
mem(MB): 7961
#job (cpus): 5
#job (mem): 3
3
.EE
Note that the '-v' output goes to STDERR, only the answer '3' to STDOUT.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

307
doc/man/man1/tbfilt.1 Normal file
View File

@@ -0,0 +1,307 @@
.\" -*- nroff -*-
.\" $Id: tbfilt.1 803 2016-08-28 12:39:00Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBFILT 1 2016-08-27 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbfilt \- filter for and analysis of test bench log files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY tbfilt
.B \-\-tee
.I OFILE
.OP OPTIONS
.
.SY tbfilt
.OP OPTIONS
.RI [ FILES ]...
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
.SS Principle of Operation
\fBtbfilt\fP is the central tool to analyze the log files created by the test
benches. It scans the test bench output for messages which indicate a test
failure and based on this marks a test as \fBPASS\fPed or \fBFAIL\fPed.
It can be used in two modes:
.RS 2
.IP "-" 2
as filter during test bench execution, typically in a setup like
.EX
tbw <test_bench> 2>&1 | tbfilt --tee=<log_file>
.EE
tbfilt reads the output from the test bench via stdin and a pipe, filters
out the messages indicating a failure and shows them on stdout, and saves
the full test bench output to the file given in the \fB\-\-tee\fP option.
In this mode tbfilt works similar to a
.EX
tee ... | egrep ...
.EE
pipeline with a very involved egrep selection expression.
The exit status of tbfilt is 1 in case the test is considered as \fBFAIL\fPed.
.
.IP "-" 2
as log file analysis tool. In this case the test bench log files are either
specified explicitly as arguments or determined via the \fB\-\-find\fP or
\fB\-\-all\fP options.
If the \fB\-\-summary\fP option is specified a one line summary for each
test log file is displayed. The format of this summary is configurable via
the \fB\-\-format\fP, \fB\-\-wide\fP, and \fB\-\-compact\fP options and via
the \fB\TBFILT_FORMAT\fP environment variable.
The exit status of tbfilt is 1 in case any of the tests is considered as
\fBFAIL\fPed.
.
.RE
.PP
.
.SS Filter Criteria
A line which contains any of the following strings is considered as an
indication of a \fBFAIL\fPed test:
.RS 2
.PD 0
.IP "\fB-E:\fR"
.IP "\fB-F:\fR"
.IP "\fBERROR\fR"
.IP "\fBFAIL\fR"
.IP "\fB:(assertion warning):\fR"
.IP "\fB:(assertion error):\fR"
.IP "\fB:(assertion failure):\fR"
.PD
.RE
As excption to the general rules above the following assertion messages
are accepted:
Assertion warnings from IEEE libraries at startup (t=0) are ignored. They are
hard to avoid in complex models and in general don't indicate a real issue.
.RS 2
.PD 0
.IP "-" 2
assertion warnings from IEEE libraries at startup (t=0). They are hard to
avoid in complex models and in general don't indicate a real issue. Best
is to suppress them in \fBghdl\fP(1) with the
option '--ieee-asserts=disable-at-0'.
.IP "-" 2
assertion failure with the text 'Simulation Finished'. It is used to end
simulations in \fBghdl\fP(1) in some test benches.
.PD
.RE
tbfilt also expects a line in one of the formats
.EX
xxx ns: DONE -- tb'swithout clock
xxx.x ns xxx: DONE -- single clock tb's
xxx.x ns xxx: DONE-xxx -- multiclock tb's (max taken)
.EE
and considers a test \fBFAIL\fPed if it is missing.
In addition lines containing
.RS 4
.PD 0
.IP "\fB-W:\fR"
.IP "\fBPASS\fR"
.PD
.RE
will be displayed. If the \fB\-\-pcom\fP option is specified also all lines
starting with 'C'.
Finally, tbfilt checks for a line of the format
.EX
real xmx.xxxs user xmx.xxxs sys xmx.xxxs
.EE
and extracts the test bench execution times from this. It can be generated
by a \fBbash\fP(1) 'time' command when
.EX
export TIMEFORMAT=$'real %3lR user %3lU sys %3lS'
.EE
is set. The wrapper scripts \fB\tbrun_tbw\fP(1) or \fBtbrun_tbwrri\fP(1)
are in general used to set this up correctly.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" --------------------------------------------------------
.SS Filter Options
.
.\" -- --tee -------------------------------------
.IP "\fB\-\-tee=\fIofile\fR"
All log file input is written to \fIofile\fP. Typically used to save the
test bench output in a file when tbfilt is used in filter mode in a pipeline
and reads from stdin.
.
.\" -- --pcom ------------------------------------
.IP \fB\-\-pcom\fP
Enables that lines starting with "C" are also displayed.
.
.\" --------------------------------------------------------
.SS File Selection Options
.
.\" -- --find ------------------------------------
.IP "\fB\-\-find=\fIpatt\fR"
When given the input files are determined with a \fBfind\fP(1) command.
The selection pattern \fIpatt\fR is used with a find -regex in egrep mode.
This is functionally similar to a
.EX
find -regextype egrep -regex '\fIpatt\fR' | sort | tbfilt ....
.EE
pipeline.
When no '*' wildcard is found in \fIpatt\fR it is assumed to be a mode
specification and the pattern is prefixed by
.EX
.*/tb_.*_
.EE
and suffixed by
.EX
.*\\.log
.EE
to select all log files of a given mode (e.g. 'bsim').
.
.\" -- --all -------------------------------------
.IP \fB\-\-all\fP
When given uses as input files all test bench files which conform the
naming convention. Is equivalent to the option
.EX
--find '.*/tb_.*_[bfsorept]sim(_.*)?\\.log'
.EE
.
.\" --------------------------------------------------------
.SS Summary Options
.
.\" -- --summary----------------------------------
.IP \fB\-\-summary\fP
Selects summary mode. Only a single summary line per input file is written.
The format is configurable via the \fB\-\-format\fP, \fB\-\-wide\fP, and
\fB\-\-compact\fP options and via the \fBTBFILT_FORMAT\fP environment variable.
The precedence is (in increasing priority):
.RS
.PD 0
.IP " -" 4
build default ('%ec %pf %nf')
.IP " -"
\fBTBFILT_FORMAT\fP option
.IP " -"
\fB\-\-wide\fP option
.IP " -"
\fB\-\-compact\fP option
.IP " -"
\fB\-\-format\fP option
.PD
.RE
.
.\" -- --wide ------------------------------------
.IP \fB\-\-wide\fP
Selects a wide format for summary outputs, designed to give the most pertinent
information. Uses a format of "%fd %fs %tr %tc %sc %ec %pf %nf".
.
.\" -- --compact ---------------------------------
.IP \fB\-\-compact\fP
Selects a compact format for summary outputs, designed to give the key info
on a 80 character wide line. Uses a format of "%fa %tg %sg %ec %pf %ns".
.
.\" -- --nohead ----------------------------------
.IP \fB\-\-nohead\fP
Suppresses the head line of summary outputs. Useful of summary output is
piped into sort or other tools.
.
.\" -- --format ----------------------------------
.IP "\fB\-\-format=\fIfmt\fR"
Defined the format of the summary lines.
The format specification \fIfmt\fR string is a sequence of conversion
specifications of the form '%xx', which will be replaces by the respective
values and other characters which are simply copied (usually a blank as
delimiter).
The supported conversion specifications are:
.RS
.PD 0
.IP \fB%fd\fP 5
modification date of input file (as yyyy-mm-dd)
.IP \fB%ft\fP
modification time of input file (as hh:mm:ss)
.IP \fB%fs\fP
modification time of input file short format (as hh:mm)
.IP \fB%fa\fP
age of input file in seconds, minutes, hours or days
.IP \fB%tr\fP
real (wall clock) time of test bench run
.IP \fB%tu\fP
user time of test bench run
.IP \fB%ts\fP
system time of test bench run
.IP \fB%tc\fP
total cpu (user+system) time of test bench run
.IP \fB%tg\fP
show '%tc c' if cpu time significant, otherwise '%tr r'
.IP \fB%st\fP
simulation time in ns
.IP \fB%ss\fP
simulation time short format (in usec, msec, or sec)
.IP \fB%sc\fP
main system clock cycles till DONE
.IP \fB%sg\fP
use %sc, if available, otherwise %ss
.IP \fB%sp\fP
cpu time per simulation clock cycle (in usec or msec)
.IP \fB%sm\fP
estimate of system clock rate (in MHz)
.IP \fB%ec\fP
error count
.IP \fB%pf\fP
PASS or FAIL, derived from error count
.IP \fB%nf\fP
full file name (with path)
.IP \fB%ns\fP
short file name (without path)
.PD
.RE
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
In case the test bench is considered FAILed an exit status 1 is returned.
In case of an error at startup, e.g. no input files or invalid format
specification, an error message to stderr or printed and an exit status
of 2 is returned.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP "\fBTBFILT_FORMAT\fR" 4
Defines the default summary format and overwrites the build-in default of
"%ec %pf %nf".
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.SS As Filter
Usually used together with \fBtbw\fP(1) in pipelines like
.EX
tbw <test_bench> 2>&1 | tbfilt --tee=<log_file>
.EE
Since tbfilt expects also the output of a \fBbash\fP(1) 'time' command
in the input stream the setup of the pipeline is more involved.
In general the wrapper scripts \fB\tbrun_tbw\fP(1) or \fBtbrun_tbwrri\fP(1)
are used.
.
.SS As Analysis Tool
To generate a compact overview of all test bench outputs use
.EX
cd $RETROBASE
tbfilt -all -summary -compact
.EE
To generate a report indicating all \fBFAIL\fPed test use
.EX
cd $RETROBASE
tbfilt -all -summary -nohead | grep FAIL
.EE
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbw (1),
.BR tbrun_tbw (1),
.BR tbrun_tbwrri (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

239
doc/man/man1/tbrun.1 Normal file
View File

@@ -0,0 +1,239 @@
.\" -*- nroff -*-
.\" $Id: tbrun.1 812 2016-10-03 18:39:50Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBRUN 1 2016-10-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbrun \- test bench driver
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY tbrun
.OP OPTIONS
.OP DSCFILE
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBtbrun\fP organizes the execution of large sets of test benches. It will
.RS 2
.PD 0
.IP "-" 2
read the file \fIDSCFILE\fP, which describes the full set of test benches.
The top level \fIDSCFILE\fP typically includes other files which allows to
organize the description in a well structured manner. If no \fIDSCFILE\fP
is specified the file \fItbrun.yml\fP in the current working directory is
used.
.IP "-"
selects based on the given \fB\-\-tag\fP and \fB\-\-exclude\fP options the
tests to be executed in a given run.
.IP "-"
determines based on the \fB\-\-mode\fP option the simulation engine and
the simulation type, behavioral or post-synthesis or later. See section
MODES for details.
.IP "-"
executes the tests which as much parallelism as possible. The \fB\-\-jobs\fP
option specifies the maximal number of jobs, and a locking logic prevents that
more than one test is run in one working directory.
.PD
.RE
.PP
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" -- --tag -------------------------------------
.IP \fB\-\-tag=\fItlist\fR
specifies the tags a test must match to be selected for execution.
\fItlist\fR can be a comma separated list of tags, a test must match
all tags given in \fItlist\fR to be selected.
.br
\fB\-\-tag\fP can be specified multiple times, the selections are ored.
In effect, a test must match all tags in the \fItlist\fR of one of the
specified \fB\-\-tag\fP options.
.br
If no \fB\-\-tag\fP option is given an implicit \fI\-\-tag=default\fP is
assumed, so all tests with the tag 'default' are executed.
.
.\" -- --exclude ---------------------------------
.IP \fB\-\-exclude=\fItlist\fR
specifies the tags a test must not match. \fItlist\fR can again be a comma
separated list, a test which matches all the tags given is excluded.
.br
\fB\-\-exclude\fP can be specified multiple times, the rejections are ored.
In effect, a test is rejected if it matches all tags in the \fItlist\fR of
one of the specified \fB\-\-exclude\fP options.
.
.\" -- --mode ------------------------------------
.IP \fB\-\-mode=\fImlist\fR
determines the simulation engine and the type of simulation. Can be a
comma separated list, if several modes are specified all of them will
be executed.
.br
If no \fB\-\-mode\fP is given the default value 'bsim' is used.
Note that unlike \fB\-\-tag\fP and \fB\-\-exclude\fP only a single
\fB\-\-mode\fP option is processed, if multiple are present only the
last one will be used.
.RS
Each mode specification has the format '[\fIengine\fP]_[\fItype\fP]'
and follows the model name suffix rules of the build system.
If the \fIengine\fP part is omitted \fBghdl\fP(1) is assumed as default.
If the \fItype\fP part is omitted 'bsim' is assumed as default.
Other supported values for \fIengine\fP are
.RS 2
.PD 0
.IP \fBISim\fP 6
the Xilinx ISE build-in simulator
.IP \fBXSim\fP
the Xilinx vivado build-in simulator
.PD
.RE
The \fItype\fP part has the following supported values
.RS 2
.PD 0
.IP \fBbsim\fP 6
behavioral simulation
.IP \fBssim\fP
post-synthesis functional simulation
.IP \fBfsim\fP
post-map simulation (only ISE)
.IP \fBosim\fP
post-optimize functional simulation (only vivado)
.IP \fBrsim\fP
post-routing functional simulation (only vivado)
.IP \fBesim\fP
post-synthesis timing simulation (only vivado)
.IP \fBpsim\fP
post-optimize timing simulation (only vivado)
.IP \fBtsim\fP
post-routing timing simulation
.PD
.RE
.RE
.
.\" -- --jobs ------------------------------------
.IP \fB\-\-jobs=\fInjob\fR
.RS
specifies the maximal number of parallel jobs.
Without \fB\-\-jobs\fP option the tests are executed sequentially and
the test output is forwarded immediately to stdout.
With \fB\-\-jobs\fP option a task dispatcher is used which starts the jobs,
received and buffers the test output, and forwards it to stdout when the
job completes. The test outputs are always in the original selection order,
thus not affected by the completion order.
The task dispatcher displays also a progress line when stdout is a terminal
device of the format
.EX
#-I: t047: 5l 35.6s; t053: 5l 20.2s (26t,2w,31o)
.EE
where
.RS 2
.PD 0
.IP "t***:" 6
specifies the current task number
.IP "**l"
number of output lines collected for this task
.IP "*.*s"
run time (as real time) of the task (running since time)
.IP "**t"
number of tasks still waiting for execution
.IP "*w"
number of tasks currently running
.IP "*o"
number of tasks in pending output queue
.PD
.RE
Note that \fB\-\-jobs\fP enables the task dispatcher and thus output
buffering and progress line output even when \fInjob\fP is '1' !
.RE
.
.\" -- --tee -------------------------------------
.IP \fB\-\-tee=\fIoutfile\fR
if specified the all output send to stdout with the exception of the
progress line updates is also written in the file \fIoutfile\fR.
This is very convenient in conjunction with the \fB\-\-jobs\fP option
which generates progress line output only when stdout is a terminal
device.
Using shell pipes and \fBtee\fP(1) will therefore prevent progress lines,
use the \fB\-\-tee\fP instead to save the output into a file.
.
.\" -- --dry -------------------------------------
.IP \fB\-\-dry\fP
dry run, prints the generated commands, but doesn't execute.
When used without \f\-\-jobs\fP option a commented list of shell commands
is printed which describes the linear execution of the selected tests.
.br
When used together with \f\-\-jobs\fP this option mainly serves to debug
the task dispatcher. A random wait of 0.2 to 1.8 sec is generated for each
selected test.
.
\" -- --trace -----------------------------------
.IP \fB\-\-trace\fP
prints additional information on job control
.
.\" -- --nomake ----------------------------------
.IP \fB\-\-nomake\fP
don't execute make step of test bench.
Will be forwarded to \fBtbrun_tbw\fP(1) and \fBtbrun_tbwrri\fP(1)
based test benches.
.
\" -- --norun -----------------------------------
.IP \fB\-\-norun\fP
don't execute run step of test bench, useful to only execute make step.
Will be forwarded to \fBtbrun_tbw\fP(1) and \fBtbrun_tbwrri\fP(1)
based test benches.
.
\" -- --rlmon -----------------------------------
.IP \fB\-\-rlmon\fP
enable the rlink monitor, will be forwarded to \fBtbrun_tbwrri\fP(1)
based test benches.
.
\" -- --rbmon -----------------------------------
.IP \fB\-\-rbmon\fP
enable the rbus monitor, will be forwarded to \fBtbrun_tbwrri\fP(1)
based test benches
.
.\" -- --bwait ----------------------------------
.IP \fB\-\-bwait=\fItwait\fR
specifies startup wait for behavioral simulations.
\fItwait\fR must be an integer, time unit is 1 ns. Will be forwarded
to \fBtbrun_tbwrri\fP(1) based test benches.
.
.\" -- --swait ----------------------------------
.IP \fB\-\-swait=\fItwait\fR
specifies startup wait for post-synthesis and higher simulations.
\fItwait\fR must be an integer, time unit is 1 ns. Will be forwarded
to \fBtbrun_tbwrri\fP(1) based test benches.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBtbrun" 4
Simplest default case, will use the \fItbrun.yml\fP file in the current
working directory, assume \fI\-\-tag=default\fP and \fI\-\-mode=bsim\fP
and this select all tests tagged with 'default' and run the behavioral
simulation with \fBghdl\fP(1). Done in simple sequential mode.
.IP "\fBtbrun --jobs=2 --tag=viv,sys_w11a --mode=XSim" 4
Will select all tests which have a 'viv' and a 'sys_w11a' tag,
use XSim as simulation engine and run the behavioral simulation.
Will use the task dispatcher and will try to run 2 tests in parallel.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbrun_tbw (1),
.BR tbrun_tbwrri (1),
.BR tbfilt (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

37
doc/man/man1/tbrun_tbw.1
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: tbrun_tbw.1 774 2016-06-12 17:08:47Z mueller $
.\" $Id: tbrun_tbw.1 800 2016-08-21 22:02:49Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBRUN_TBW 1 2016-03-18 "Retro Project" "Retro Project Manual"
.TH TBRUN_TBW 1 2016-08-21 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbrun_tbw \- \fBtbw\fP based test bench starter
@@ -30,15 +30,8 @@ issue a \fBmake\fP(1) command to (re)-build \fITBENCH\fP.
.IP "-"
build a \fBtbw\fP(1) command, using \fISTIMFILE\fP if specified.
.IP "-"
create a shell pipe to which runs tbw and handles the output with
.IP " -" 4
\fBghdl_assert_filter\fP(1) to suppress irrelevant diagnostics
created by \fBghdl\fP(1) and it's IEEE libs
.IP " -"
\fBtee\fP(1) to save the output to a log file. The log file
name is build as "<TBENCH>_<lsuf>.log"
.IP " -"
\fBegrep\fP(1) to filter out only essential lines to stdout
create a shell pipe to which runs tbw and handles the test bench output with
\fBtbfilt\fP(1) to determine success of failure.
.PD
.RE
.PP
@@ -53,6 +46,14 @@ and not '--ghw=xxx' !
.IP \fB\-\-dry\fP
dry run, prints the commands but doesn't execute
.
.\" -- --nomake ----------------------------------
.IP \fB\-\-nomake\fP
don't execute make step (\fITBENCH\fP neither build nor updated)
.
\" -- --norun -----------------------------------
.IP \fB\-\-norun\fP
don't execute test bench (useful to only execute make step)
.
.\" -- --lsuf ------------------------------------
.IP \fB\-\-lsuf\ \fIsuff\fR
use '_\fIsuff\fR.log' as suffix for log file. Default is '_bsim.log'
@@ -68,23 +69,25 @@ write a ghw file with name '\fIfname\fP.ghw'
.\" -- --tbw opts --------------------------------
.IP \fB\-\-tbw\ \fIopts\fR
append \fIopts\fP to the \fBtbw\fP(1) command
.\" -- --pcom ------------------------------------
.IP \fB\-\-pcom\fR
enables that test bench comments are passed to stdout.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBtbrun_tbw tb_serport_uart_rx" 4
Simplest default case, will execute
Simplest default case, will execute in essence
.EX
make tb_serport_uart_rx
time tbw tb_serport_uart_rx 2>&1 |\\
ghdl_assert_filter |\\
tee tb_serport_uart_rx_bsim.log |\\
egrep "(-[EFW]:|ERROR|FAIL|PASS|DONE)"
tbw tb_serport_uart_rx 2>&1 | tbfilt
.EE
The issued command is more involved, defines TIMEFORMAT, adds a bash 'time',
and some redirects to ensure that the 'time' output ends up un the log file.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbw (1),
.BR ghdl_assert_filter (1),
.BR tbfilt (1),
.BR ghdl (1)
.\" ------------------------------------------------------------------

46
doc/man/man1/tbrun_tbwrri.1
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: tbrun_tbwrri.1 774 2016-06-12 17:08:47Z mueller $
.\" $Id: tbrun_tbwrri.1 808 2016-09-17 13:02:46Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBRUN_TBWRRI 1 2016-03-18 "Retro Project" "Retro Project Manual"
.TH TBRUN_TBWRRI 1 2016-09-17 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbrun_tbw \- \fBti_rri\fP plus \fBtbw\fP based test bench starter
@@ -38,15 +38,8 @@ setup commands resulting from \fB\-\-cuff\fP, \fB\-\-fusp\fP, ...
.IP " -"
all optional \fICOMMANDS\fP
.IP "-" 2
create shell pipes to filter the output with
.IP " -" 4
\fBghdl_assert_filter\fP(1) to suppress irrelevant diagnostics
created by \fBghdl\fP(1) and it's IEEE libs
.IP " -"
\fBtee\fP(1) to save the output to a log file. The log file
name is build as "<TBENCH>_<lsuf>.log"
.IP " -"
\fBegrep\fP(1) to filter out only essential lines to stdout
create shell pipe to filter the output with \fBtbfilt\fP(1) to determine
success of failure.
.PD
.RE
.PP
@@ -61,6 +54,14 @@ and not '--ghw=xxx' !
.IP \fB\-\-dry\fP
dry run, prints the commands but doesn't execute
.
.\" -- --nomake ----------------------------------
.IP \fB\-\-nomake\fP
don't execute make step (\fITBENCH\fP neither build nor updated)
.
.\" -- --norun -----------------------------------
.IP \fB\-\-norun\fP
don't execute test bench (useful to only execute make step)
.
.\" -- --lsuf ------------------------------------
.IP \fB\-\-lsuf\ \fIsuff\fR
use '_\fIsuff\fR.log' as suffix for log file. Default is '_bsim.log'
@@ -110,6 +111,27 @@ For basys3 and arty designs.
.IP \fB\-\-pcom\fR
enables that test bench comments are passed to stdout.
.
.\" -- --rlmon -----------------------------------
.IP \fB\-\-rlmon\fR
configures the test bench to enable rlmon (rlink communication monitor, logs
all characters read and send by the rlink core).
Done in UUT, thus useful only for behavioral simulations.
.
.\" -- --rbmon -----------------------------------
.IP \fB\-\-rbmon\fR
configures the test bench to enable rbmon (rbus monitor, logs all rbus
transactions).
Done in UUT, thus useful only for behavioral simulations.
.
.\" -- --bwait -----------------------------------
.IP \fB\-\-bwait\fR\ \fItime\fR
add additional \fItime\fR ns startup waiting time for behavioral models.
.
.\" -- --swait -----------------------------------
.IP \fB\-\-bwait\fR\ \fItime\fR
add additional \fItime\fR ns startup waiting time for post-synthesis and
later models.
.\" -- --help ------------------------------------
.IP \fB\-\-help\fR
print help message and quit.
@@ -118,7 +140,7 @@ print help message and quit.
.SH "SEE ALSO"
.BR tbw (1),
.BR ti_rri (1),
.BR ghdl_assert_filter (1),
.BR tbfilt (1),
.BR ghdl (1)
.\" ------------------------------------------------------------------

37
doc/man/man1/tbw.1
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: tbw.1 774 2016-06-12 17:08:47Z mueller $
.\" $Id: tbw.1 810 2016-10-02 16:51:12Z mueller $
.\"
.\" Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBW 1 2016-04-17 "Retro Project" "Retro Project Manual"
.TH TBW 1 2016-10-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbw \- wrapper script to start ghdl based VHDL test benches
@@ -113,6 +113,23 @@ display time as simulation advances.
display process name before each cycle.
.
.\" ------------------------------------------------------------------
.
.SH ENVIRONMENT
.IP \fBTBW_GHDL_OPTS\fP 4
Additional options which are passed to ghdl based simulations.
Of particular value are
.RS
.IP "\fB\-\-ieee\-asserts=disable\-at\-0\fP" 4
suppresses assertion warnings from the ieee libraries at startup time (t=0ns).
.IP "\fB\-\-unbuffered\fP"
sets output at all files (stdout, stderr, and files opened for write) to
unbuffered mode. This is very helpful to keep output from the ghdl
simulation and other programs in a co-simulation environment in synch.
Note: only available for ghdl 0.34dev after merge of Jonsba/master #100 on
2016-06-26.
.RE
.
.\" ------------------------------------------------------------------
.SH FILES
.IP "\fI./tbw.dat\fR" 4
This configuration file is searched for in the directory of the test bench
@@ -168,7 +185,7 @@ When the simulation stops a line with the word \fIDONE\fP is printed.
These test benches are usually run like
.EX
tbw <testbenchname> [stimfile] | tee <logfile> | egrep "(FAIL|DONE)"
tbw <testbenchname> [stimfile] | tbfilt --tee <logfile>
.EE
where
@@ -177,10 +194,8 @@ where
.IP "\-" 2
\fBtbw\fP sets up the stimulus file and runs the test bench executable
.IP "\-"
\fBtee\fP ensures that the full log is saved
.IP "\-"
\fBegrep\fP filters \fIFAIL\fP and \fIDONE\fP lines, a successful run will
produce a single \fIDONE\fP line
\fBtbfilt\fP ensures that the full log is saved and the PASS/FAIL criteria
are extracted
.PD
.RE
@@ -190,14 +205,13 @@ such a pipeline.
.SS Test benches controlled with \fBti_rri\fP
In these cases the test bench is started via \fBti_rri\fP using the
\fB\-\-run\fP and \fB\-\-fifo\fP options. Also here usually a pipe with
\fBtee\fP and \fBegrep\fP is used, a typical example is
\fBtbfilt\fP(1) is used, a typical example is
.EX
ti_rri \-\-run="tbw tb_tst_rlink_n3" \-\-fifo \-\-logl=3 \-\- \\
"package require tst_rlink" \\
"tst_rlink::setup" "tst_rlink::test_all" |\\
tee tb_tst_rlink_n3_bsim.log |\\
egrep "(\-[EFW]:|FAIL|PEND|DONE)"
tbfilt --tee=tb_tst_rlink_n3_bsim.log
.EE
The convenience script \fBtbrun_tbwrri\fP(1) can be used in many cases to
@@ -206,8 +220,9 @@ create these sometimes rather lengthy constructs.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR ti_rri (1),
.BR tbrun_tbw (1),
.BR tbfilt (1),
.BR ti_rri (1),
.BR tbrun_tbwrri (1),
.BR gtkwave (1),
.BR symlink (7),

26
doc/man/man1/vbomconv.1
View File

@@ -1,12 +1,12 @@
.\" -*- nroff -*-
.\" $Id: vbomconv.1 779 2016-06-26 15:37:16Z mueller $
.\" $Id: vbomconv.1 783 2016-07-03 21:14:57Z mueller $
.\"
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\"
.\" ------------------------------------------------------------------
.
.TH VBOMCONV 1 2016-03-19 "Retro Project" "Retro Project Manual"
.TH VBOMCONV 1 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbomconv \- generate files and actions from vbom manifest files
@@ -446,13 +446,33 @@ In these cases the caller will see the exit status of \fBghdl\fP.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP \fBVBOMCONV_XSIM_LANG\fP
.IP \fBVBOMCONV_XSIM_LANG\fP 4
Controls the language for the generated models used by xsim. Can be set to
\fIverilog\fP or to \fIvhdl\fP. If not defined \fIverilog\fP is used.
It affects \fB\-\-vsim_prj\fP but also \fB\-\-dep_vsim\fP.
Use \fBrm_dep\fP(1) to force regeneration of dependency files when this
environment variable is set, unset or changed.
.
.IP \fBVBOMCONV_GHDL_OPTS\fP
Extra options for the ghdl compile stage. If not specified "\fB-O2 -g\fP" is
taken to enable optimization (is not default for gcc backend!) and debug
symbols (needed for assertion failure backtrace).
.
.IP \fBVBOMCONV_GHDL_GCOV\fP
If defined and set to '1' \fBghdl\fP(1) models will be compiled with
\fBgcov\fP(1) coverage support. This option is only available when ghdl
was compiled with gcc backend, the llvm and mcode backend do not support
coverage analysis. The generated ghdl options will be appended after the
ones given by \fBVBOMCONV_GHDL_OPTS\fP. Note that no default options are
assume, so -Ox or -g options must be explicitly given via
\fBVBOMCONV_GHDL_OPTS\fP.
The additional ghdl options are
.EX
-Wc,-ftest-coverage
-Wc,-fprofile-arcs
-Wl,-lgcov
.EE
.
.\" ------------------------------------------------------------------
.SH BUGS
.IP \(bu 2

18
doc/man/man1/xise_ghdl_simprim.1
View File

@@ -1,18 +1,20 @@
.\" -*- nroff -*-
.\" $Id: xise_ghdl_simprim.1 779 2016-06-26 15:37:16Z mueller $
.\" $Id: xise_ghdl_simprim.1 782 2016-07-03 08:09:36Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XISE_GHDL_SIMPRIM 1 2015-01-29 "Retro Project" "Retro Project Manual"
.TH XISE_GHDL_SIMPRIM 1 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xise_ghdl_simprim \- compile Xilinx ISE SIMPRIM libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xise_ghdl_simprim
.SY xise_ghdl_simprim
.RI [ GHDL-OPTIONS ]...
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
@@ -45,6 +47,12 @@ self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
Options added after the xise_ghdl_simprim command are simply forwarded to
the 'ghdl -a' commands. In general used to specify the optimize level.
If no options given \fI-O2 -g\fP is used.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
@@ -64,7 +72,7 @@ directory must be writable for the script.
.SH "SEE ALSO"
.BR xtwi (1),
.BR ghdl (1),
.BR xilinx_ghdl_unisim (1)
.BR xise_ghdl_unisim (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR

16
doc/man/man1/xise_ghdl_unisim.1
View File

@@ -1,18 +1,20 @@
.\" -*- nroff -*-
.\" $Id: xise_ghdl_unisim.1 779 2016-06-26 15:37:16Z mueller $
.\" $Id: xise_ghdl_unisim.1 782 2016-07-03 08:09:36Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XISE_GHDL_UNISIM 1 2015-02-04 "Retro Project" "Retro Project Manual"
.TH XISE_GHDL_UNISIM 1 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xise_ghdl_unisim \- compile Xilinx ISE UNISIM and UNIMACRO libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xise_ghdl_unisim
.SY xise_ghdl_unisim
.RI [ GHDL-OPTIONS ]...
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
@@ -39,6 +41,12 @@ self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
Options added after the xise_ghdl_unisim command are simply forwarded to
the 'ghdl -a' commands. In general used to specify the optimize level.
If no options given \fI-O2 -g\fP is used.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT

18
doc/man/man1/xviv_ghdl_unisim.1
View File

@@ -1,18 +1,20 @@
.\" -*- nroff -*-
.\" $Id: xviv_ghdl_unisim.1 779 2016-06-26 15:37:16Z mueller $
.\" $Id: xviv_ghdl_unisim.1 782 2016-07-03 08:09:36Z mueller $
.\"
.\" Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XVIV_GHDL_UNISIM 1 2015-02-04 "Retro Project" "Retro Project Manual"
.TH XVIV_GHDL_UNISIM 1 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xviv_ghdl_unisim \- compile Xilinx Vivado UNISIM and UNIMACRO libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xviv_ghdl_unisim
.SY xviv_ghdl_unisim
.RI [ GHDL-OPTIONS ]...
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
@@ -40,7 +42,13 @@ self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
Options added after the xviv_ghdl_unisim command are simply forwarded to
the 'ghdl -a' commands. In general used to specify the optimize level.
If no options given \fI-O2 -g\fP is used.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP \fBXTWV_PATH\fP

12
doc/man/man5/vbom.5
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: vbom.5 779 2016-06-26 15:37:16Z mueller $
.\" $Id: vbom.5 782 2016-07-03 08:09:36Z mueller $
.\"
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH VBOM 2016-03-19 "Retro Project" "Retro Project Manual"
.TH VBOM 2016-07-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbom \- vhdl manifest file format - 'vhdl bill of material'
@@ -48,13 +48,15 @@ described by this \fBvbom\fP file.
.B "\fB.v\fP"
.TQ
.B "\fB.sv\fP"
refers to a verilog or system-verilog source file. Accepted by the vivado
refers to a verilog or system verilog source file. Accepted by the vivado
xsim simulator. Typically used for DPI wrappers or simprim based models
in vivado.
.
.IP "\fB.c\fP"
refers to the C source which implements a \fIvhdl\fP function or procedure
via the \fIvhpi\fP mechanism. Supported only in conjunction with \fBghdl\fP.
refers to the C sources which implement either a vhdl function or
procedure via the VHPI mechanism or a system verilog functions
via the DPI mechanism. Supported only in conjunction with ghdl
and vivado simulator.
.
.RE
.

387
doc/w11a_tb_guide.txt
View File

@@ -1,4 +1,4 @@
# $Id: w11a_tb_guide.txt 779 2016-06-26 15:37:16Z mueller $
# $Id: w11a_tb_guide.txt 810 2016-10-02 16:51:12Z mueller $
Note: - Ghdl is used for all behavioral simulations
- Optionally Vivado xsim can be used
@@ -7,22 +7,25 @@ Note: - Ghdl is used for all behavioral simulations
- For timing simulations only Vivado xsim can be used.
- ISE isim is also available, but considered legacy support
Guide to running w11a test benches
Guide to running test benches
Table of content:
1. Unit tests benches
2. Available unit tests benches
3. System tests benches
4. Available system tests benches
1. Tests bench environment
2. Unit test benches
3. System test benches
4. Test bench driver
5. Execute all available tests
6. Available unit tests benches
7. Available system tests benches
1. Unit tests benches -----------------------------------------------------
1. Tests bench environment ------------------------------------------------
All unit test benches have the same simple structure:
All test benches have the same simple structure:
- a stimulus process reads test patterns as well as the expected
responses from a stimulus file
- the test benches are 'self-checking'. For unit tests a stimulus process
reads test patterns as well as the expected responses from a stimulus file
- the responses are checked in very simple cases by the stimulus process,
in general by a monitoring process
@@ -35,120 +38,40 @@ Guide to running w11a test benches
- at the end a line with the word "DONE" is printed.
- the test bench is run like
tbw <testbenchname> [stimfile] | tee <logfile> | egrep "(FAIL|DONE)"
where
- 'tbw' is a small perl script setting up a symbolic link to the
stimulus file, the default extracted from the file tbw.dat, if
an optional file name is give this one will be used instead.
- 'tee' ensures that the full log is saved
- 'egrep' filters FAIL and DONE lines, a successful run will
produce a single DONE line
- Most tests can be run against
- the behavioral model
- post-synthesis functional
- post-optimization functional
- post-routing functional
- post-synthesis timing
- post-optimization timing
- post-routing timing
- Most tests can be run as
- bsim: the behavioral model
- ssim: post-synthesis functional
- osim: post-optimization functional
- rsim: post-routing functional
- esim: post-synthesis timing
- psim: post-optimization timing
- tsim: post-routing timing
Building the simulation models is handled by the build environment. See
README_buildsystem_Vivado.txt for details of the vivado flow and
README_buildsystem_ISE.txt for the ISE flow.
An example of a post-synthesis model is given for the w11a core test.
2. Unit test benches ------------------------------------------------------
All unit test are executed via 'tbw' (test bench warpper) script.
- the test bench is run like
tbw <testbenchname> [stimfile] | tbfilt --tee <logfile>
where
- tbw sets up the environment of the test bench and starts it.
It generates required symbolic links, e.g. to the stimulus file,
the defaults extracted from the file tbw.dat, if an optional file
name is give this one will be used instead.
- tbfilt saves the full test bench output to a logfile and filters
the output for PASS/FAIL criteria
- for convenience a wrapper script 'tbrun_tbw' is used to generate the
tbw|tee|egrep pipe. This script also checks with 'make' whether the
tbw|tbfilt pipe. This script also checks with 'make' whether the
test bench is up-to-date or must be (re)-compiled.
2. Available unit tests benches -------------------------------------------
In the following the available tests are listed with their tbrun_tbw which
- will call 'make' to build them
- and create the pipe setup to run them
and the expected output (the run time measured on a 3 GHz system)
- serport receiver test
cd $RETROBASE/rtl/vlib/serport/tb
tbrun_tbw tb_serport_uart_rx
-> 1269955.0 ns 63488: DONE
-> real 0m0.531s user 0m0.392s sys 0m0.014s
- serport receiver/transmitter test
tbrun_tbw tb_serport_uart_rxtx
-> 52335.0 ns 2607: DONE
-> real 0m0.120s user 0m0.065s sys 0m0.013s
- serport autobauder test
tbrun_tbw tb_serport_autobaud
-> 367475.0 ns 18364: DONE
-> real 0m0.343s user 0m0.316s sys 0m0.003s
- 9 bit comma,data to Byte stream converter test
cd $RETROBASE/rtl/vlib/comlib/tb
tbrun_tbw tb_cdata2byte
-> 7261.0 ns 354: DONE
-> real 0m0.088s user 0m0.057s sys 0m0.013s
- rlink core test
cd $RETROBASE/rtl/vlib/rlink/tb
tbrun_tbw tb_rlink_direct
-> 78975.0 ns 3939: DONE
-> real 0m0.270s user 0m0.222s sys 0m0.026s
- rlink core test via serial port interface
cd $RETROBASE/rtl/vlib/rlink/tb
tbrun_tbw --lsuf stim2_bsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat
-> 27595.0 ns 1370: DONE
-> real 0m0.184s user 0m0.145s sys 0m0.011s
tbrun_tbw --lsuf stim1_bsim tb_rlink_sp1c tb_rlink_stim.dat
-> 420295.0 ns 21005: DONE
-> real 0m0.939s user 0m0.945s sys 0m0.026s
- w11a core test
- using behavioral model
cd $RETROBASE/rtl/w11a/tb
tbrun_tbw tb_pdp11core
-> 225355.0 ns 61258: DONE
-> real 0m6.446s user 0m6.387s sys 0m0.024s
- using Vivado post-synthesis vhdl model and ghdl
tbrun_tbw tb_pdp11core_ssim
-> 1225355.0 ns 61258: DONE
-> real 1m40.446s user 1m40.344s sys 0m0.075s
- using Vivado post-synthesis verilog model and xsim
tbrun_tbw tb_pdp11core_XSim_ssim
-> 1225355.0 ns 61258: DONE
-> real 1m14.835s user 1m13.997s sys 0m1.011s
- s3board sram controller test
cd $RETROBASE/rtl/bplib/s3board/tb
tbrun_tbw tb_s3_sram_memctl
-> 5015.0 ns 241: DONE
-> real 0m0.075s user 0m0.045s sys 0m0.022s
- nexys2/nexys3 cram controller test
cd $RETROBASE/rtl/bplib/nxcramlib/tb
tbrun_tbw tb_nx_cram_memctl_as
-> 24272.5 ns 1204: DONE
-> real 0m0.337s user 0m0.147s sys 0m0.146s
3. System tests benches ---------------------------------------------------
3. System test benches ----------------------------------------------------
The system tests allow to verify to verify a full system design.
In this case vhdl test bench code contains
@@ -163,183 +86,93 @@ Guide to running w11a test benches
simulation, or via a serial port to a FPGA board. This way the same tests
can be executed in simulation and on real hardware.
4. Available system tests benches -----------------------------------------
In general the script 'tbrun_tbwrri' is used to generate the quite lengthy
ommand to properly setup the tbw|tbfilt pipe. This script also checks
with 'make' whether the test bench is up-to-date or must be (re)-compiled.
4a. serport tester ---------------------------------------------------
4. Test bench driver ------------------------------------------------------
The sys_tst_serloop design is a test target for validating the serial
link UART stack. Send and receive throughput as well as loop-back tests
are supported
All available tests (unit and system test benches) are described in a
set of descriptor files, usually called 'tbrun.yml'. The top level file
in $RETROBASE includes other descriptor files located in the source
directories of the tests.
- sys_tst_serloop_s3 test bench
The script 'tbrun' reads these descriptor files, selects tests based
on --tag and --exclude options, and executes the tests with the
simulation engine and simulation type given by the --mode option.
For full description of see 'man tbrun'.
cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
tbrun_tbw tb_tst_serloop_s3
-> 301353.3 ns 18068: DONE
-> real 0m0.832s user 0m0.765s sys 0m0.036s
The low level drivers 'tbrun_tbw' and 'tbrun_tbwrri' will automatically
build the model if it is not available or outdated. This is very convenient
when working with a single test bench during development.
- sys_tst_serloop_n2 test bench
When executing a large number of them it's in general better to separate
the model building (make phase) made model execution (run phase). Both
the low level drivers as well as 'tbrun' support this via the options
--nomake and --norun.
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
tbrun_tbw tb_tst_serloop1_n2
-> 361560.0 ns 18068: DONE
-> real 0m0.799s user 0m0.758s sys 0m0.021s
The individial test benches are simplest started via tbrun and a proper
selection via --tag. Very helpful is
tbrun_tbw tb_tst_serloop2_n2
-> 304353.3 ns 18248: DONE
-> real 0m1.274s user 0m1.236s sys 0m0.017s
cd $RETROBASE
tbrun --dry --tag=.*
- sys_tst_serloop_n3 test bench
which gives a listing of all available test. The tag list as well as
the shell commands to execute the test are shown.
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
tbrun_tbw tb_tst_serloop1_n3
-> 361560.0 ns 18068: DONE
-> real 0m0.841s user 0m0.820s sys 0m0.014s
5. Execute all available tests --------------------------------------------
4b. rlink tester -----------------------------------------------------
As stated above it is in general better to to separate the model building
(make phase) made model execution (run phase). The currently recommended
way to execute all test benches is given below.
The run time is measured on a 3 GHz dual core system.
The sys_tst_rlink design is a test target for validating the rlink and
rbus functionality at all levels.
cd $RETROBASE
# build all behavioral models
# first all with ISE work flow
time nice tbrun -j 2 -norun -tag=ise -tee=tbrun_make_ise_bsim.log
# --> real 3m41.732s user 6m3.381s sys 0m24.224s
- Artix based systems
# than all with vivado work flow
time nice tbrun -j 2 -norun -tag=viv -tee=tbrun_make_viv_bsim.log
# --> real 3m36.532s user 5m58.319s sys 0m25.235s
# than execute all behavioral models
time nice tbrun -j 2 -nomake -tag=ise -tee=tbrun_run_ise_bsim.log
# --> real 3m19.799s user 5m45.060s sys 0m6.625s
time nice tbrun -j 2 -nomake -tag=viv -tee=tbrun_run_viv_bsim.log
#--> real 3m49.193s user 5m44.063s sys 0m5.332s
- sys_tst_rlink_arty test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb
tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_arty \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1028590.0 ns 102838: DONE
-> real 0m14.163s user 0m12.637s sys 0m0.152s
All test create an individual logfile. 'tbfilt' can be used to scan
these logfiles and create a summary with
- sys_tst_rlink_b3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/basys3/tb
tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_b3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1028820.0 ns 102861: DONE
-> real 0m9.275s user 0m9.041s sys 0m0.094s
tbfilt -all -sum -comp
It should look like
76m 0m00.034s c 0.92u 0 PASS tb_is61lv25616al_bsim.log
76m 0m00.153s c 4.00u 0 PASS tb_mt45w8mw16b_bsim.log
76m 0m00.168s c 1146 0 PASS tb_nx_cram_memctl_as_bsim.log
...
...
76m 0m03.729s c 61258 0 PASS tb_pdp11core_bsim_base.log
76m 0m00.083s c 1121 0 PASS tb_pdp11core_bsim_ubmap.log
76m 0m00.068s c 1031 0 PASS tb_rlink_tba_pdp11core_bsim_ibdr.log
- sys_tst_rlink_n4 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys4/tb
tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n4 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1020240.0 ns 102003: DONE
-> real 0m9.751s user 0m9.544s sys 0m0.081s
6. Available unit tests benches -------------------------------------------
tbrun --tag=comlib # comlib unit tests
tbrun --tag=serport # serport unit tests
tbrun --tag=rlink # rlink unit tests
tbrun --tag=issi # SRAM model unit tests
tbrun --tag=micron # CRAM model unit tests
tbrun --tag=sram_memctl # SRAM controller unit tests
tbrun --tag=cram_memctl # CRAM controller unit tests
tbrun --tag=w11a # w11a unit tests
- Spartan based systems
- sys_tst_rlink_n3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1024980.0 ns 102477: DONE
-> real 0m8.081s user 0m7.904s sys 0m0.106s
- sys_tst_rlink_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n2 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 2049320.0 ns 102455: DONE
-> real 0m7.934s user 0m7.748s sys 0m0.114s
- sys_tst_rlink_s3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_s3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 2049720.0 ns 102476: DONE
-> real 0m7.612s user 0m7.437s sys 0m0.075s
4c. rlink tester, Cypress FX2 based version --------------------------
The sys_tst_rlink_cuff design is a test target for validating the rlink and
rbus functionality at all levels over the Cypress FX2 USB interface which
is provided by the Nexys2 abd Nexys3 boards.
- sys_tst_rlink_cuff_ic_n3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 558770.0 ns 55856: DONE
-> real 0m7.679s user 0m7.433s sys 0m0.185s
- sys_tst_rlink_cuff_ic_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n2 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 596300.0 ns 29804: DONE
-> real 0m3.741s user 0m3.542s sys 0m0.127s
4d. w11a systems -----------------------------------------------------
The stimulus file used in the w11a core test can be executed in the full
system context with the following commands. Note that the cycle number
printed in the DONE line can now vary slightly because the response time of
the rlink backend process and thus scheduling of backend vs. ghdl process
can affect the result.
For convenience a wrapper script 'tbrun_tbwrri' is used to generate the
required quite long ti_rri command. Like for 'tbrun_tbw' the script also
checks with 'make' whether the test bench is up-to-date or must be
(re)-compiled.
- Artix based systems
cd $RETROBASE/rtl/sys_gen/w11a/nexys4/tb
tbrun_tbwrri --pack rw11 tb_w11a_n4 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 4812818.3 ns 577513: DONE
-> real 1m11.139s user 1m10.726s sys 0m0.545s
- Spartan based systems
- sys_w11a_n3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
tbrun_tbwrri --cuff --pack rw11 tb_w11a_n3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 3612428.7 ns 231182: DONE
-> real 0m47.454s user 0m47.241s sys 0m0.456s
- sys_w11a_n2 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
tbrun_tbwrri --cuff --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 4009900.0 ns 200484: DONE
-> real 0m45.429s user 0m45.215s sys 0m0.480s
- sys_w11a_s3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
tbrun_tbwrri --fusp --pack rw11 tb_w11a_s3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 10528880.0 ns 526434: DONE
-> real 1m13.706s user 1m13.483s sys 0m0.470s
A new, modular w11a test bench is under construction. So far it is very
incomplete. This very preliminary version can be executed with
- sys_w11a_n2 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
tbrun_tbwrri --cuff --lsuf tbench_bsim --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
-> 3268940.0 ns 163436: DONE
-> real 0m30.761s user 0m31.576s sys 0m0.502s
tbrun_tbwrri --cuff --lsuf tbench_bsim --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
-> 1376360.0 ns 68807: DONE
-> real 0m16.991s user 0m17.049s sys 0m0.235s
7. Available system tests benches -----------------------------------------
tbrun --tag=sys_tst_serloop.* # all sys_tst_serloop designs
tbrun --tag=sys_tst_rlink # all sys_tst_rlink designs
tbrun --tag=sys_tst_rlink_cuff # all sys_tst_rlink_cuff designs
tbrun --tag=sys_tst_sram # all sys_tst_sram designs
tbrun --tag=sys_w11a # all w11a designs

54
rtl/bplib/arty/tb/sys_conf_sim.vhd Normal file
View File

@@ -0,0 +1,54 @@
-- $Id: sys_conf_sim.vhd 726 2016-01-31 23:02:31Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_arty_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;

1
rtl/bplib/arty/tb/tb_arty.vbom
View File

@@ -11,6 +11,7 @@
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
${gsr_pulse := ../../../vlib/xlib/gsr_pulse_dummy.vbom}
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom

17
rtl/bplib/arty/tb/tb_arty.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_arty.vhd 748 2016-03-20 15:18:50Z mueller $
-- $Id: tb_arty.vhd 809 2016-09-18 19:49:14Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,10 +26,12 @@
-- To test: generic, any arty_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-18 809 1.3 add gsr_pulse (provisional....)
-- 2016-09-02 805 1.2.1 tbcore_rlink without CLK_STOP now
-- 2016-03-20 748 1.2 BUGFIX: add PORTSEL_XON logic
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-02-20 734 1.0.2 use s7_cmt_sfs_tb to avoid xsim conflict
@@ -59,7 +61,6 @@ architecture sim of tb_arty is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -86,18 +87,19 @@ architecture sim of tb_arty is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
@@ -120,7 +122,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,

5
rtl/bplib/basys3/tb/basys3_dummy.vbom Normal file
View File

@@ -0,0 +1,5 @@
# libs
../../../vlib/slvtypes.vhd
# components
# design
basys3_dummy.vhd

59
rtl/bplib/basys3/tb/basys3_dummy.vhd Normal file
View File

@@ -0,0 +1,59 @@
-- $Id: basys3_dummy.vhd 726 2016-01-31 23:02:31Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: basys3_dummy - syn
-- Description: basys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_basys3
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0.1 fix typos
-- 2015-01-15 634 1.0 Initial version (derived from nexys4_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity basys3_dummy is -- BASYS 3 dummy (base; loopback)
-- implements basys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end basys3_dummy;
architecture syn of basys3_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;

54
rtl/bplib/basys3/tb/sys_conf_sim.vhd Normal file
View File

@@ -0,0 +1,54 @@
-- $Id: sys_conf_sim.vhd 810 2016-10-02 16:51:12Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_basys3_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-10-01 810 1.0 Initial version (cloned from nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;

14
rtl/bplib/basys3/tb/tb_basys3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_basys3.vhd 748 2016-03-20 15:18:50Z mueller $
-- $Id: tb_basys3.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,10 +26,11 @@
-- To test: generic, any basys3_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33
-- Tool versions: viv 2014.4-2016.2; ghdl 0.31-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.1.4 tbcore_rlink without CLK_STOP now
-- 2016-02-20 734 1.1.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.1.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.1.1 use serport/tb/serport_master_tb
@@ -59,7 +60,6 @@ architecture sim of tb_basys3 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -84,8 +84,8 @@ architecture sim of tb_basys3 is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
@@ -94,8 +94,7 @@ begin
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
@@ -118,7 +117,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,

37
rtl/bplib/bpgen/Makefile Normal file
View File

@@ -0,0 +1,37 @@
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#

20
rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: fx2_2fifo_core.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: fx2_2fifo_core.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,9 +18,10 @@
-- Dependencies: memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.0.1 proc_ifclk: remove clock stop (not needed anymore)
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
@@ -131,15 +132,15 @@ begin
);
proc_ifclk: process
constant offset : time := 200 ns;
constant halfperiod_7 : time := 16700 ps;
constant halfperiod_6 : time := 16600 ps;
constant offset : Delay_length := 200 ns;
constant halfperiod_7 : Delay_length := 16700 ps;
constant halfperiod_6 : Delay_length := 16600 ps;
begin
CLK30 <= '0';
wait for offset;
clk_loop: loop
loop
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
@@ -152,11 +153,8 @@ begin
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_6;
exit clk_loop when to_x01(SB_CLKSTOP) = '1';
end loop;
wait; -- endless wait, simulator will stop
end process proc_ifclk;
proc_state: process (CLK30)

26
rtl/bplib/issi/is61lv25616al.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: is61lv25616al.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: is61lv25616al.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -126,18 +126,18 @@ end is61lv25616al_bank;
architecture sim of is61lv25616al_bank is
constant T_rc : time := 10 ns; -- read cycle time (min)
constant T_aa : time := 10 ns; -- address access time (max)
constant T_oha : time := 2 ns; -- output hold time (min)
constant T_ace : time := 10 ns; -- ce access time (max)
constant T_doe : time := 4 ns; -- oe access time (max)
constant T_hzoe : time := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : time := 0 ns; -- oe to low-Z output (min)
constant T_hzce : time := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : time := 3 ns; -- ce to low-Z output (min)
constant T_ba : time := 4 ns; -- lb,ub access time (max)
constant T_hzb : time := 3 ns; -- lb,ub to high-Z output (min=0,max=3)
constant T_lzb : time := 0 ns; -- lb,ub low-Z output (min)
constant T_rc : Delay_length := 10 ns; -- read cycle time (min)
constant T_aa : Delay_length := 10 ns; -- address access time (max)
constant T_oha : Delay_length := 2 ns; -- output hold time (min)
constant T_ace : Delay_length := 10 ns; -- ce access time (max)
constant T_doe : Delay_length := 4 ns; -- oe access time (max)
constant T_hzoe : Delay_length := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : Delay_length := 0 ns; -- oe to low-Z output (min)
constant T_hzce : Delay_length := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : Delay_length := 3 ns; -- ce to low-Z output (min)
constant T_ba : Delay_length := 4 ns; -- lb,ub access time (max)
constant T_hzb : Delay_length := 3 ns; -- lb,ub to high-Z out (min=0,max=3)
constant T_lzb : Delay_length := 0 ns; -- lb,ub low-Z output (min)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');

2
rtl/bplib/issi/tb/.cvsignore Normal file
View File

@@ -0,0 +1,2 @@
tb_is61lv25616al
tb_is61lv25616al_stim

46
rtl/bplib/issi/tb/Makefile Normal file
View File

@@ -0,0 +1,46 @@
# $Id: Makefile 804 2016-08-28 17:33:50Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 804 1.3 remove ISim, add XSim support
# 2011-08-13 405 1.2 use includes from rtl/make
# 2009-11-21 252 1.1 add ISim support
# 2007-12-14 101 1.0 Initial version
#
EXE_all = tb_is61lv25616al
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
endif
#

7
rtl/bplib/issi/tb/tb_is61lv25616al.vbom Normal file
View File

@@ -0,0 +1,7 @@
#
# libs
../../../vlib/simlib/simlib.vhd
# components
../is61lv25616al.vbom
# design
tb_is61lv25616al.vhd

193
rtl/bplib/issi/tb/tb_is61lv25616al.vhd Normal file
View File

@@ -0,0 +1,193 @@
-- $Id: tb_is61lv25616al.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_is61lv25616al - sim
-- Description: Test bench for is61lv25616al memory model
--
-- Dependencies: is61lv25616al [UUT]
--
-- To test: is61lv25616al
--
-- Verified (with tb_is61lv25616al_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2010-05-16 291 - 0.26 - - c:ok
-- 2007-12-15 101 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-21 432 1.1.1 now numeric_std clean
-- 2010-05-16 291 1.1 initial values for all act.low signals now '1'
-- 2007-12-14 101 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_is61lv25616al is
end tb_is61lv25616al;
architecture sim of tb_is61lv25616al is
signal CE_N : slbit := '1';
signal OE_N : slbit := '1';
signal WE_N : slbit := '1';
signal UB_N : slbit := '1';
signal LB_N : slbit := '1';
signal ADDR : slv18 := (others=>'0');
signal DATA : slv16 := (others=>'0');
begin
UUT : entity work.is61lv25616al
port map (
CE_N => CE_N,
OE_N => OE_N,
WE_N => WE_N,
UB_N => UB_N,
LB_N => LB_N,
ADDR => ADDR,
DATA => DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_is61lv25616al_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idtime : Delay_length := 0 ns;
variable imatch : boolean := false;
variable ival : slbit := '0';
variable ival2 : slv2 := (others=>'0');
variable ival16 : slv16 := (others=>'0');
variable ival18 : slv18 := (others=>'0');
variable ice : slbit := '0';
variable ioe : slbit := '0';
variable iwe : slbit := '0';
variable ibe : slv2 := "00";
variable iaddr : slv18 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ide : slbit := '0';
variable idchk : slv16 := (others=>'0');
begin
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wdo " => -- wdo
read_ea(iline, idtime);
wait for idtime;
readtagval_ea(iline, "ce", imatch, ival);
if imatch then ice := ival; end if;
readtagval_ea(iline, "oe", imatch, ival);
if imatch then ioe := ival; end if;
readtagval_ea(iline, "we", imatch, ival);
if imatch then iwe := ival; end if;
readtagval_ea(iline, "be", imatch, ival2, 2);
if imatch then ibe := ival2; end if;
readtagval_ea(iline, "a", imatch, ival18, 16);
if imatch then iaddr := ival18; end if;
readtagval_ea(iline, "de", imatch, ival);
if imatch then ide := ival; end if;
readtagval_ea(iline, "d", imatch, ival16, 16);
if imatch then idata := ival16; end if;
CE_N <= not ice;
OE_N <= not ioe;
WE_N <= not iwe;
LB_N <= not ibe(0);
UB_N <= not ibe(1);
ADDR <= iaddr;
if ide = '1' then
DATA <= idata;
else
DATA <= (others=>'Z');
end if;
write(oline, now, right, 12);
write(oline, string'(": wdo "));
write(oline, string'(" ce="));
write(oline, ice);
write(oline, string'(" oe="));
write(oline, ioe);
write(oline, string'(" we="));
write(oline, iwe);
write(oline, string'(" be="));
write(oline, ibe, right, 2);
write(oline, string'(" a="));
writegen(oline, iaddr, right, 5, 16);
write(oline, string'(" de="));
write(oline, ide);
if ide = '1' then
write(oline, string'(" d="));
writegen(oline, idata, right, 4, 16);
end if;
readtagval_ea(iline, "D", imatch, idchk, 16);
if imatch then
write(oline, string'(" D="));
writegen(oline, DATA, right, 4, 16);
write(oline, string'(" CHECK"));
if DATA = idchk then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL exp="));
writegen(oline, idchk, right, 4, 16);
end if;
end if;
writeline(output, oline);
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop;
write(oline, now, right, 12);
write(oline, string'(": DONE"));
writeline(output, oline);
wait; -- suspend proc_stim forever
-- no clock, sim will end
end process proc_stim;
end sim;

92
rtl/bplib/issi/tb/tb_is61lv25616al_stim.dat Normal file
View File

@@ -0,0 +1,92 @@
# $Id: tb_is61lv25616al_stim.dat 146 2008-05-16 19:17:42Z mueller $
#
C Write first 8 cells, full words
#
wdo 0 ns ce=1 be=11 a=00000 de=1 d=1000
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00001 de=1 d=1101
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00002 de=1 d=1202
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00003 de=1 d=1303
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00004 de=1 d=1404
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00005 de=1 d=1505
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00006 de=1 d=1606
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00007 de=1 d=1707
wdo 10 ns we=1
wdo 20 ns we=0
#
wdo 10 ns be=11 de=0
wdo 20 ns
#
C Read first 8 cells
#
wdo 20 ns oe=1 a=00000
wdo 20 ns D=1000
wdo 0 ns oe=1 a=00001
wdo 20 ns D=1101
wdo 0 ns oe=1 a=00002
wdo 20 ns D=1202
wdo 0 ns oe=1 a=00003
wdo 20 ns D=1303
wdo 0 ns oe=1 a=00004
wdo 20 ns D=1404
wdo 0 ns oe=1 a=00005
wdo 20 ns D=1505
wdo 0 ns oe=1 a=00006
wdo 20 ns D=1606
wdo 0 ns oe=1 a=00007
wdo 20 ns D=1707
#
wdo 0 ns oe=0
wdo 20 ns
#
C Byte write in last 4 cells
wdo 0 ns ce=1 be=00 a=00004 de=1 d=3414 -- no write
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=01 a=00005 de=1 d=3515 -- low byte write
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=10 a=00006 de=1 d=3616 -- high byte write
wdo 10 ns we=1
wdo 20 ns we=0
wdo 10 ns ce=1 be=11 a=00007 de=1 d=3717 -- full word write
wdo 10 ns we=1
wdo 20 ns we=0
#
wdo 10 ns be=11 de=0
wdo 20 ns
#
C Read again first 8 cells
#
wdo 20 ns oe=1 a=00000
wdo 20 ns D=1000
wdo 0 ns oe=1 a=00001
wdo 20 ns D=1101
wdo 0 ns oe=1 a=00002
wdo 20 ns D=1202
wdo 0 ns oe=1 a=00003
wdo 20 ns D=1303
wdo 0 ns oe=1 a=00004
wdo 20 ns D=1404
wdo 0 ns oe=1 a=00005
wdo 20 ns D=1515
wdo 0 ns oe=1 a=00006
wdo 20 ns D=3606
wdo 0 ns oe=1 a=00007
wdo 20 ns D=3717
#
wdo 20 ns
#

13
rtl/bplib/issi/tb/tbrun.yml Normal file
View File

@@ -0,0 +1,13 @@
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-00-10 806 1.1 use nossim because no _ssim support available
# 2016-08-12 797 1.0 Initial version
#
- default:
mode: ${viv_modes_nossim}
#
- tag: [default, viv, bplib, issi]
test: |
tbrun_tbw tb_is61lv25616al${ms}

89
rtl/bplib/micron/mt45w8mw16b.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: mt45w8mw16b.vhd 718 2015-12-26 15:59:48Z mueller $
-- $Id: mt45w8mw16b.vhd 799 2016-08-21 09:20:19Z mueller $
--
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,16 +16,18 @@
-- Description: Micron MT45W8MW16B CellularRAM model
-- Currently a much simplified model
-- - only async accesses
-- - ignores CLK and CRE
-- - ignores CLK
-- - simple model for response of DATA lines, but no
-- check for timing violations of control lines
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-18 799 1.4.1 remove 'assert false' from report statements
-- 2016-07-10 786 1.4 add RCR handling; page mode by default now off !!
-- 2015-12-26 718 1.3.3 BUGFIX: initialize L_ADDR with all '1', see comment
-- 2011-11-19 427 1.3.2 now numeric_std clean
-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
@@ -82,19 +84,23 @@ end mt45w8mw16b;
architecture sim of mt45w8mw16b is
-- timing constants for -701 speed grade (70 ns; 104 MHz)
constant T_aa : time := 70 ns; -- address access time (max)
constant T_apa : time := 20 ns; -- page acess time (max)
constant T_oh : time := 5 ns; -- output hold from addr change (max)
constant T_oe : time := 20 ns; -- output enable to valid output (max)
constant T_ohz : time := 8 ns; -- output disable to high-z output (max)
constant T_olz : time := 3 ns; -- output enable to low-z output (min)
constant T_lz : time := 10 ns; -- chip enable to low-z output (min)
constant T_hz : time := 8 ns; -- chip disable to high-z output (max)
constant T_aa : Delay_length := 70 ns; -- address access time (max)
constant T_apa : Delay_length := 20 ns; -- page access time (max)
constant T_oh : Delay_length := 5 ns; -- output hold from addr change (max)
constant T_oe : Delay_length := 20 ns; -- output enable to valid output (max)
constant T_ohz : Delay_length := 8 ns; -- output disable to high-z out (max)
constant T_olz : Delay_length := 3 ns; -- output enable to low-z output (min)
constant T_lz : Delay_length := 10 ns; -- chip enable to low-z output (min)
constant T_hz : Delay_length := 8 ns; -- chip disable to high-z output (max)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
subtype xcr_f_sel is integer range 19 downto 18; -- cre register select
constant xcr_sel_rcr : slv2 := "00";
constant xcr_sel_bcr : slv2 := "10";
constant bcr_f_mode : integer := 15; -- operating mode
constant bcr_f_ilat : integer := 14; -- initial latency
subtype bcr_f_lc is integer range 13 downto 11; -- latency counter
@@ -103,6 +109,14 @@ architecture sim of mt45w8mw16b is
subtype bcr_f_drive is integer range 5 downto 4; -- drive strength
constant bcr_f_bw : integer := 3; -- burst wrap
subtype bcr_f_bl is integer range 2 downto 0; -- burst length
subtype rcr_f_res3 is integer range 22 downto 20; -- reserved - MBZ
subtype rcr_f_res2 is integer range 17 downto 8; -- reserved - MBZ
constant rcr_f_pmode : integer := 7; -- page mode (1=ena)
subtype rcr_f_res1 is integer range 6 downto 5; -- reserved - MBZ
constant rcr_f_dpd : integer := 4; -- dpd mode (1=dis)
constant rcr_f_res0 : integer := 3; -- reserved - MBZ
subtype rcr_f_par is integer range 2 downto 0; -- array conf (000=all)
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
@@ -115,6 +129,7 @@ architecture sim of mt45w8mw16b is
signal ADV : slbit := '0';
signal WE_L_EFF : slbit := '0';
signal WE_U_EFF : slbit := '0';
signal WE_C_EFF : slbit := '0';
signal R_BCR_MODE : slbit := '1'; -- mode: def: async
signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable
@@ -124,7 +139,12 @@ architecture sim of mt45w8mw16b is
signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
signal R_RCR_PMODE : slbit := '0'; -- pmode:def: disabled (ena=1 !)
signal R_RCR_DPD : slbit := '1'; -- dpd: def: disabled (ena=0 !)
signal R_RCR_PAR : slv3 := "000"; -- par: def: full array
signal R_T_APA_EFF : Delay_length := T_aa; -- page mode disabled by default
signal L_ADDR : slv23 := (others=>'1'); -- all '1' for propper 1st access
signal DOUT_VAL_EN : slbit := '0';
signal DOUT_VAL_AA : slbit := '0';
@@ -144,9 +164,11 @@ begin
BE_U <= not UB_N;
ADV <= not ADV_N;
WE_L_EFF <= CE and WE and BE_L;
WE_U_EFF <= CE and WE and BE_U;
WE_L_EFF <= CE and WE and BE_L and (not CRE);
WE_U_EFF <= CE and WE and BE_U and (not CRE);
WE_C_EFF <= CE and WE and CRE;
-- address valid logic, latch ADDR when ADV true
proc_adv: process (ADV, ADDR)
begin
@@ -174,7 +196,7 @@ begin
DOUT_VAL_EN <= '0', '1' after T_aa;
end if;
if L_ADDR'event then
DOUT_VAL_PA <= '0', '1' after T_apa;
DOUT_VAL_PA <= '0', '1' after R_T_APA_EFF;
if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then
DOUT_VAL_AA <= '0', '1' after T_aa;
end if;
@@ -207,7 +229,7 @@ begin
end if;
end process proc_dout_lz;
proc_cram: process (CE, OE, WE, WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
proc_cram: process (WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
@@ -224,6 +246,39 @@ begin
end process proc_cram;
proc_cr: process (WE_C_EFF, L_ADDR)
begin
if falling_edge(WE_C_EFF) then
case L_ADDR(xcr_f_sel) is
when xcr_sel_rcr =>
R_RCR_PMODE <= L_ADDR(rcr_f_pmode);
if L_ADDR(rcr_f_pmode) = '1' then
R_T_APA_EFF <= T_apa;
else
R_T_APA_EFF <= T_aa;
end if;
assert L_ADDR(rcr_f_res3) = "000"
report "bad rcr write: 22:20 not zero" severity error;
assert L_ADDR(rcr_f_res2) = "0000000000"
report "bad rcr write: 17: 8 not zero" severity error;
assert L_ADDR(rcr_f_res1) = "00"
report "bad rcr write: 6: 5 not zero" severity error;
assert L_ADDR(rcr_f_dpd) = '1'
report "bad rcr write: dpd not '1'" severity error;
assert L_ADDR(rcr_f_res0) = '0'
report "bad rcr write: 3: 3 not zero" severity error;
assert L_ADDR(rcr_f_par) = "000"
report "bad rcr write: par not '000'" severity error;
when xcr_sel_bcr =>
report "bcr written - not supported" severity error;
when others =>
report "bad select field" severity error;
end case;
end if;
end process proc_cr;
proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE,
DOUT_LZ_CE, DOUT_LZ_OE)
variable idout : slv16 := (others=>'0');

2
rtl/bplib/micron/tb/.cvsignore Normal file
View File

@@ -0,0 +1,2 @@
tb_mt45w8mw16b
tb_mt45w8mw16b_stim

46
rtl/bplib/micron/tb/Makefile Normal file
View File

@@ -0,0 +1,46 @@
# $Id: Makefile 804 2016-08-28 17:33:50Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-28 804 1.2 remove ISim, add XSim support
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-16 291 1.0 Initial version
#
EXE_all = tb_mt45w8mw16b
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
endif
#

8
rtl/bplib/micron/tb/tb_mt45w8mw16b.vbom Normal file
View File

@@ -0,0 +1,8 @@
#
# libs
../../../vlib/simlib/simlib.vhd
# components
../mt45w8mw16b.vbom
../../../vlib/simlib/simbididly.vbom
# design
tb_mt45w8mw16b.vhd

247
rtl/bplib/micron/tb/tb_mt45w8mw16b.vhd Normal file
View File

@@ -0,0 +1,247 @@
-- $Id: tb_mt45w8mw16b.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_mt45w8mw16b - sim
-- Description: Test bench for mt45w8mw16b memory model
--
-- Dependencies: mt45w8mw16b [UUT]
-- simlib/simbididly
--
-- To test: mt45w8mw16b
--
-- Verified (with tb_mt45w8mw16b_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2016-07-16 787 - 0.33 - - c:ok
-- 2010-05-16 291 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 787 1.2 test also CRE; use simbididly;
-- 2011-11-21 432 1.1.1 now numeric_std clean
-- 2010-05-16 291 1.0 Initial version (cloned from tb_is61lv25616al)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_mt45w8mw16b is
end tb_mt45w8mw16b;
architecture sim of tb_mt45w8mw16b is
constant pcb_delay : Delay_length := 1 ns;
signal MM_CE_N : slbit := '1';
signal MM_OE_N : slbit := '1';
signal MM_WE_N : slbit := '1';
signal MM_UB_N : slbit := '1';
signal MM_LB_N : slbit := '1';
signal MM_CRE : slbit := '0';
signal MM_MWAIT : slbit := '0';
signal MM_ADDR : slv23 := (others=>'0');
signal MM_DATA : slv16 := (others=>'Z');
signal TB_CE_N : slbit := '1';
signal TB_OE_N : slbit := '1';
signal TB_WE_N : slbit := '1';
signal TB_UB_N : slbit := '1';
signal TB_LB_N : slbit := '1';
signal TB_CRE : slbit := '0';
signal TB_MWAIT : slbit := '0';
signal TB_ADDR : slv23 := (others=>'0');
signal TB_DATA : slv16 := (others=>'Z');
begin
UUT : entity work.mt45w8mw16b
port map (
CLK => '0',
CE_N => MM_CE_N,
OE_N => MM_OE_N,
WE_N => MM_WE_N,
UB_N => MM_UB_N,
LB_N => MM_LB_N,
ADV_N => '0',
CRE => MM_CRE,
MWAIT => MM_MWAIT,
ADDR => MM_ADDR,
DATA => MM_DATA
);
MM_CE_N <= TB_CE_N after pcb_delay;
MM_OE_N <= TB_OE_N after pcb_delay;
MM_WE_N <= TB_WE_N after pcb_delay;
MM_UB_N <= TB_UB_N after pcb_delay;
MM_LB_N <= TB_LB_N after pcb_delay;
MM_CRE <= TB_CRE after pcb_delay;
MM_ADDR <= TB_ADDR after pcb_delay;
TB_MWAIT <= MM_MWAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => TB_DATA,
B => MM_DATA);
proc_stim: process
file fstim : text open read_mode is "tb_mt45w8mw16b_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idtime : Delay_length := 0 ns;
variable imatch : boolean := false;
variable ival : slbit := '0';
variable ival2 : slv2 := (others=>'0');
variable ival16 : slv16 := (others=>'0');
variable ival23 : slv23 := (others=>'0');
variable ice : slbit := '0';
variable ioe : slbit := '0';
variable iwe : slbit := '0';
variable ibe : slv2 := "00";
variable icre : slbit := '0';
variable iaddr : slv23 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ide : slbit := '0';
variable idchk : slv16 := (others=>'0');
begin
-- initial signal driver settings
TB_CE_N <= '1';
TB_OE_N <= '1';
TB_WE_N <= '1';
TB_UB_N <= '1';
TB_LB_N <= '1';
TB_CRE <= '0';
TB_ADDR <= (others=>'0');
TB_DATA <= (others=>'Z');
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wdo " => -- wdo
read_ea(iline, idtime);
wait for idtime;
readtagval_ea(iline, "ce", imatch, ival);
if imatch then ice := ival; end if;
readtagval_ea(iline, "cre", imatch, ival);
if imatch then icre := ival; end if;
readtagval_ea(iline, "oe", imatch, ival);
if imatch then ioe := ival; end if;
readtagval_ea(iline, "we", imatch, ival);
if imatch then iwe := ival; end if;
readtagval_ea(iline, "be", imatch, ival2, 2);
if imatch then ibe := ival2; end if;
readtagval_ea(iline, "a", imatch, ival23, 16);
if imatch then iaddr := ival23; end if;
readtagval_ea(iline, "de", imatch, ival);
if imatch then ide := ival; end if;
readtagval_ea(iline, "d", imatch, ival16, 16);
if imatch then idata := ival16; end if;
TB_CE_N <= not ice;
TB_OE_N <= not ioe;
TB_WE_N <= not iwe;
TB_LB_N <= not ibe(0);
TB_UB_N <= not ibe(1);
TB_CRE <= icre;
TB_ADDR <= iaddr;
if ide = '1' then
TB_DATA <= idata;
else
TB_DATA <= (others=>'Z');
end if;
write(oline, now, right, 12);
write(oline, string'(": wdo "));
write(oline, string'(" ce="));
write(oline, ice);
write(oline, string'(" oe="));
write(oline, ioe);
write(oline, string'(" we="));
write(oline, iwe);
if icre = '0' then
write(oline, string'(" be="));
write(oline, ibe, right, 2);
else
write(oline, string'(" cre=1"));
end if;
write(oline, string'(" a="));
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" de="));
write(oline, ide);
if ide = '1' then
write(oline, string'(" d="));
writegen(oline, idata, right, 4, 16);
end if;
readtagval_ea(iline, "D", imatch, idchk, 16);
if imatch then
write(oline, string'(" D="));
writegen(oline, TB_DATA, right, 4, 16);
write(oline, string'(" CHECK"));
if TB_DATA = idchk then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL exp="));
writegen(oline, idchk, right, 4, 16);
end if;
end if;
writeline(output, oline);
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop;
write(oline, now, right, 12);
write(oline, string'(": DONE"));
writeline(output, oline);
wait; -- suspend proc_stim forever
-- no clock, sim will end
end process proc_stim;
end sim;

141
rtl/bplib/micron/tb/tb_mt45w8mw16b_stim.dat Normal file
View File

@@ -0,0 +1,141 @@
# $Id: tb_mt45w8mw16b_stim.dat 787 2016-07-16 14:40:41Z mueller $
#
C Write first 8 cells, full words
#
wdo 100 ns ce=1 be=11 a=000000 de=1 d=1000
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000001 de=1 d=1101
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000002 de=1 d=1202
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000003 de=1 d=1303
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000004 de=1 d=1404
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000005 de=1 d=1505
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000006 de=1 d=1606
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000007 de=1 d=1707
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 0 ns be=11 de=0
wdo 20 ns
#
C Read first 8 cells (full cycle per read)
#
wdo 0 ns ce=1 oe=1 a=000000
wdo 100 ns ce=0 D=1000
wdo 20 ns ce=1 a=000001
wdo 100 ns ce=0 D=1101
wdo 20 ns ce=1 a=000002
wdo 100 ns ce=0 D=1202
wdo 20 ns ce=1 a=000003
wdo 100 ns ce=0 D=1303
wdo 20 ns ce=1 a=000004
wdo 100 ns ce=0 D=1404
wdo 20 ns ce=1 a=000005
wdo 100 ns ce=0 D=1505
wdo 20 ns ce=1 a=000006
wdo 100 ns ce=0 D=1606
wdo 20 ns ce=1 a=000007
wdo 100 ns ce=0 D=1707
wdo 0 ns oe=0
wdo 20 ns
#
C Read first 4 cells (all in one CE, page mode timing, will be expect XXXX)
#
wdo 0 ns ce=1 oe=1 a=000000
wdo 100 ns a=000001 D=1000
wdo 40 ns a=000002 D=XXXX
wdo 40 ns a=000003 D=XXXX
wdo 40 ns D=XXXX
wdo 0 ns oe=0
wdo 20 ns
#
C Enable page mode
# addr to set rcr with pmode=1
# a(19:18) = 00 select
# a( 7) = 1 pmode
# a( 4) = 1 dpd (disable)
# --> addr = 00090
wdo 0 ns ce=1 cre=1 we=1 a=000090
wdo 80 ns ce=0 cre=0 we=0
wdo 20 ns
#
C Read first 8 cells (page mode, all in one CE)
#
wdo 0 ns ce=1 oe=1 a=000000
wdo 100 ns a=000001 D=1000
wdo 40 ns a=000002 D=1101
wdo 40 ns a=000003 D=1202
wdo 40 ns a=000004 D=1303
wdo 40 ns a=000005 D=1404
wdo 40 ns a=000006 D=1505
wdo 40 ns a=000007 D=1606
wdo 40 ns ce=0 D=1707
#
wdo 0 ns oe=0
wdo 20 ns
#
C Byte write in last 4 cells
wdo 0 ns ce=1 be=00 a=000004 de=1 d=3414 -- no write
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=01 a=000005 de=1 d=3515 -- low byte write
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=10 a=000006 de=1 d=3616 -- high byte write
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 20 ns ce=1 be=11 a=000007 de=1 d=3717 -- full word write
wdo 10 ns we=1
wdo 100 ns we=0
wdo 20 ns ce=0
#
wdo 0 ns be=11 de=0
wdo 20 ns
#
C Read again first 8 cells (page mode, all in one CE)
#
wdo 0 ns ce=1 oe=1 a=000000
wdo 100 ns a=000001 D=1000
wdo 40 ns a=000002 D=1101
wdo 40 ns a=000003 D=1202
wdo 40 ns a=000004 D=1303
wdo 40 ns a=000005 D=1404
wdo 40 ns a=000006 D=1515
wdo 40 ns a=000007 D=3606
wdo 40 ns ce=0 D=3717
#
wdo 20 ns
#

13
rtl/bplib/micron/tb/tbrun.yml Normal file
View File

@@ -0,0 +1,13 @@
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-00-10 806 1.1 use nossim because no _ssim support available
# 2016-08-22 800 1.0 Initial version
#
- default:
mode: ${viv_modes_nossim}
#
- tag: [default, viv, bplib, micron, cram]
test: |
tbrun_tbw tb_mt45w8mw16b${ms}

7
rtl/bplib/nexys2/tb/nexys2_dummy.vbom Normal file
View File

@@ -0,0 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys2_dummy.vhd

86
rtl/bplib/nexys2/tb/nexys2_dummy.vhd Normal file
View File

@@ -0,0 +1,86 @@
-- $Id: nexys2_dummy.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-23 294 1.0 Initial version (derived from s3board_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_dummy is -- NEXYS 2 dummy (base; loopback)
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end nexys2_dummy;
architecture syn of nexys2_dummy is
begin
O_TXD <= I_RXD; -- loop back
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;

7
rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vbom Normal file
View File

@@ -0,0 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys2_fusp_cuff_dummy.vhd

100
rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vhd Normal file
View File

@@ -0,0 +1,100 @@
-- $Id: nexys2_fusp_cuff_dummy.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_fusp_cuff_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.0 Initial version (derived nexys2_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_fusp_cuff_dummy is -- NEXYS 2 dummy (+fusp+cuff; loopback)
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end nexys2_fusp_cuff_dummy;
architecture syn of nexys2_fusp_cuff_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet
O_FX2_SLWR_N <= '1';
O_FX2_SLOE_N <= '1';
O_FX2_PKTEND_N <= '1';
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;

7
rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vbom Normal file
View File

@@ -0,0 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys2_fusp_dummy.vhd

92
rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd Normal file
View File

@@ -0,0 +1,92 @@
-- $Id: nexys2_fusp_dummy.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys2_fusp_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys2_fusp_dummy;
architecture syn of nexys2_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;

42
rtl/bplib/nexys2/tb/sys_conf_sim.vhd Normal file
View File

@@ -0,0 +1,42 @@
-- $Id: sys_conf_sim.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys2_fusp_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 2;
constant sys_conf_clkfx_multiply : positive := 3; -- ==> 75 MHz
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

23
rtl/bplib/nexys2/tb/tb_nexys2.vbom Normal file
View File

@@ -0,0 +1,23 @@
# Not meant for direct top level usage. Used with
# tb_nexys2_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/xlib/xlib.vhd
../nexys2lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
${nexys2_aif := nexys2_dummy.vbom} -UUT
# design
tb_nexys2.vhd
@top:tb_nexys2

226
rtl/bplib/nexys2/tb/tb_nexys2.vhd Normal file
View File

@@ -0,0 +1,226 @@
-- $Id: tb_nexys2.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2 - sim
-- Description: Test bench for nexys2 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/dcm_sfs
-- tb_nexys2_core
-- nexys2_aif [UUT]
-- serport/tb/serport_master_tb
--
-- To test: generic, any nexys2_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.2 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.0.2 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.0.1 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.3 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.2 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0.1 use serport_uart_rxtx
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2 is
end tb_nexys2;
architecture sim of tb_nexys2 is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;

2
rtl/bplib/nexys2/tb/tb_nexys2_core.vbom
View File

@@ -1,7 +1,9 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simbididly.vhd
../../micron/mt45w8mw16b.vbom
# design
tb_nexys2_core.vhd

63
rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_core.vhd 724 2016-01-03 22:53:53Z mueller $
-- $Id: tb_nexys2_core.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -15,14 +15,16 @@
-- Module Name: tb_nexys2_core - sim
-- Description: Test bench for nexys2 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
-- Dependencies: simlib/simbididly
-- vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-20 791 1.2 use simbididly
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 1.1 update O_FLA_CE_N usage
-- 2011-11-19 427 1.0.1 now numeric_std clean
@@ -36,6 +38,7 @@ use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
entity tb_nexys2_core is
@@ -57,27 +60,57 @@ end tb_nexys2_core;
architecture sim of tb_nexys2_core is
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= O_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= O_MEM_CLK after pcb_delay;
MM_MEM_CRE <= O_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
I_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
proc_simbus: process (SB_VAL)

12
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_nexys2_fusp.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx
@@ -65,7 +66,6 @@ architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -116,8 +116,8 @@ architecture sim of tb_nexys2_fusp is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
@@ -126,8 +126,7 @@ begin
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
DCM_COM : dcm_sfs
@@ -146,7 +145,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,

16
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_fusp_cuff.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_nexys2_fusp_cuff.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,10 +27,11 @@
-- To test: generic, any nexys2_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
@@ -60,7 +61,6 @@ architecture sim of tb_nexys2_fusp_cuff is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -132,8 +132,8 @@ architecture sim of tb_nexys2_fusp_cuff is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
@@ -142,12 +142,9 @@ begin
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
SB_CLKSTOP <= CLK_STOP;
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
@@ -164,7 +161,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,

7
rtl/bplib/nexys3/tb/nexys3_fusp_cuff_dummy.vbom Normal file
View File

@@ -0,0 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys3_fusp_cuff_dummy.vhd

102
rtl/bplib/nexys3/tb/nexys3_fusp_cuff_dummy.vhd Normal file
View File

@@ -0,0 +1,102 @@
-- $Id: nexys3_fusp_cuff_dummy.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version (derived nexys3_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_cuff_dummy is -- NEXYS 3 dummy (+fusp+cuff; loopback)
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end nexys3_fusp_cuff_dummy;
architecture syn of nexys3_fusp_cuff_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet
O_FX2_SLWR_N <= '1';
O_FX2_SLOE_N <= '1';
O_FX2_PKTEND_N <= '1';
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;

7
rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vbom Normal file
View File

@@ -0,0 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys3_fusp_dummy.vhd

90
rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd Normal file
View File

@@ -0,0 +1,90 @@
-- $Id: nexys3_fusp_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1 use nxcramlib
-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys3_fusp_dummy;
architecture syn of nexys3_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;

46
rtl/bplib/nexys3/tb/sys_conf_sim.vhd Normal file
View File

@@ -0,0 +1,46 @@
-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys3_fusp_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-25 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 4;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 75 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 75 MHz
constant sys_conf_clksys_gentype : string := "DCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

2
rtl/bplib/nexys3/tb/tb_nexys3_core.vbom
View File

@@ -1,7 +1,9 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simbididly.vhd
../../micron/mt45w8mw16b.vbom
# design
tb_nexys3_core.vhd

63
rtl/bplib/nexys3/tb/tb_nexys3_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys3_core.vhd 724 2016-01-03 22:53:53Z mueller $
-- $Id: tb_nexys3_core.vhd 791 2016-07-21 22:01:10Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -15,14 +15,16 @@
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
-- Dependencies: simlib/simbididly
-- vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-20 791 1.1 use simbididly
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
@@ -33,6 +35,7 @@ use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
entity tb_nexys3_core is
@@ -54,27 +57,57 @@ end tb_nexys3_core;
architecture sim of tb_nexys3_core is
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= O_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= O_MEM_CLK after pcb_delay;
MM_MEM_CRE <= O_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
I_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
proc_simbus: process (SB_VAL)

14
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys3_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_nexys3_fusp.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,10 +26,11 @@
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
@@ -60,7 +61,6 @@ architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -112,8 +112,8 @@ architecture sim of tb_nexys3_fusp is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
@@ -122,8 +122,7 @@ begin
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : s6_cmt_sfs
@@ -146,7 +145,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,

16
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys3_fusp_cuff.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_nexys3_fusp_cuff.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,10 +27,11 @@
-- To test: generic, any nexys3_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
@@ -61,7 +62,6 @@ architecture sim of tb_nexys3_fusp_cuff is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -133,8 +133,8 @@ architecture sim of tb_nexys3_fusp_cuff is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
@@ -143,12 +143,9 @@ begin
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
SB_CLKSTOP <= CLK_STOP;
CLKGEN_COM : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
@@ -169,7 +166,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,

13
rtl/bplib/nexys4/tb/nexys4_cram_dummy.ucf_cpp Normal file
View File

@@ -0,0 +1,13 @@
## $Id: nexys4_cram_dummy.ucf_cpp 643 2015-02-07 17:41:53Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2015-02-06 463 1.1 factor out memory
## 2013-09-21 534 1.0 Initial version
##
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
#include "bplib/nexys4/nexys4_pins_cram.ucf"
##

8
rtl/bplib/nexys4/tb/nexys4_cram_dummy.vbom Normal file
View File

@@ -0,0 +1,8 @@
# libs
../../../vlib/slvtypes.vhd
../../nxcramlib/nxcramlib.vhd
# components
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys4_cram_dummy.vhd
@ucf_cpp: nexys4_cram_dummy.ucf

93
rtl/bplib/nexys4/tb/nexys4_cram_dummy.vhd Normal file
View File

@@ -0,0 +1,93 @@
-- $Id: nexys4_cram_dummy.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys4_cram_dummy - syn
-- Description: nexys4 target (base; serport loopback, cram protect)
--
-- Dependencies: -
-- To test: tb_nexys4_cram
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys4_cram_dummy is -- NEXYS 4 dummy (base+cram)
-- implements nexys4_cram_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end nexys4_cram_dummy;
architecture syn of nexys4_cram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;

11
rtl/bplib/nexys4/tb/nexys4_dummy.ucf_cpp Normal file
View File

@@ -0,0 +1,11 @@
## $Id: nexys4_dummy.ucf_cpp 534 2013-09-22 21:37:24Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-09-21 534 1.0 Initial version
##
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
##

5
rtl/bplib/nexys4/tb/nexys4_dummy.vbom Normal file
View File

@@ -0,0 +1,5 @@
# libs
../../../vlib/slvtypes.vhd
# design
nexys4_dummy.vhd
@ucf_cpp: nexys4_dummy.ucf

69
rtl/bplib/nexys4/tb/nexys4_dummy.vhd Normal file
View File

@@ -0,0 +1,69 @@
-- $Id: nexys4_dummy.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys4_dummy - syn
-- Description: nexys4 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys4
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.3 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nexys4_dummy is -- NEXYS 4 dummy (base; loopback)
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end nexys4_dummy;
architecture syn of nexys4_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;

54
rtl/bplib/nexys4/tb/sys_conf_sim.vhd Normal file
View File

@@ -0,0 +1,54 @@
-- $Id: sys_conf_sim.vhd 641 2015-02-01 22:12:15Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys4_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;

14
rtl/bplib/nexys4/tb/tb_nexys4.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys4.vhd 734 2016-02-20 22:43:20Z mueller $
-- $Id: tb_nexys4.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,10 +26,11 @@
-- To test: generic, any nexys4_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.4 tbcore_rlink without CLK_STOP now
-- 2016-02-20 734 1.3.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
@@ -62,7 +63,6 @@ architecture sim of tb_nexys4 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -92,8 +92,8 @@ architecture sim of tb_nexys4 is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
@@ -102,8 +102,7 @@ begin
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
@@ -126,7 +125,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,

1
rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom
View File

@@ -16,6 +16,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_nexys4_core.vbom
../../../vlib/simlib/simbididly.vbom
../../micron/mt45w8mw16b.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
${nexys4_cram_aif := nexys4_cram_dummy.vbom} -UUT

109
rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys4_cram.vhd 734 2016-02-20 22:43:20Z mueller $
-- $Id: tb_nexys4_cram.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,15 +22,18 @@
-- tb_nexys4_core
-- serport/tb/serport_master_tb
-- nexys4_cram_aif [UUT]
-- simlib/simbididly
-- vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys4_cram_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.1 tbcore_rlink without CLK_STOP now
-- 2016-07-20 791 1.3 use simbididly
-- 2016-02-20 734 1.2.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
@@ -62,7 +65,6 @@ architecture sim of tb_nexys4_cram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -87,23 +89,36 @@ architecture sim of tb_nexys4_cram is
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal TB_MEM_CE_N : slbit := '1';
signal TB_MEM_BE_N : slv2 := (others=>'1');
signal TB_MEM_WE_N : slbit := '1';
signal TB_MEM_OE_N : slbit := '1';
signal TB_MEM_ADV_N : slbit := '1';
signal TB_MEM_CLK : slbit := '0';
signal TB_MEM_CRE : slbit := '0';
signal TB_MEM_WAIT : slbit := '0';
signal TB_MEM_ADDR : slv23 := (others=>'Z');
signal TB_MEM_DATA : slv16 := (others=>'0');
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant pcb_delay : Delay_length := 1 ns;
begin
@@ -112,8 +127,7 @@ begin
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
@@ -136,7 +150,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
@@ -166,31 +179,49 @@ begin
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
O_MEM_CE_N => TB_MEM_CE_N,
O_MEM_BE_N => TB_MEM_BE_N,
O_MEM_WE_N => TB_MEM_WE_N,
O_MEM_OE_N => TB_MEM_OE_N,
O_MEM_ADV_N => TB_MEM_ADV_N,
O_MEM_CLK => TB_MEM_CLK,
O_MEM_CRE => TB_MEM_CRE,
I_MEM_WAIT => TB_MEM_WAIT,
O_MEM_ADDR => TB_MEM_ADDR,
IO_MEM_DATA => TB_MEM_DATA
);
MM_MEM_CE_N <= TB_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= TB_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= TB_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= TB_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= TB_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= TB_MEM_CLK after pcb_delay;
MM_MEM_CRE <= TB_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= TB_MEM_ADDR after pcb_delay;
TB_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => TB_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
SERMSTR : entity work.serport_master_tb

37
rtl/bplib/nxcramlib/Makefile Normal file
View File

@@ -0,0 +1,37 @@
# $Id: Makefile 761 2016-04-17 08:53:48Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-04-15 761 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#

204
rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: nx_cram_memctl_as.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: nx_cram_memctl_as.vhd 789 2016-07-17 08:26:55Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,18 +20,29 @@
-- vlib/xlib/iob_reg_io_gen
-- Test bench: tb/tb_nx_cram_memctl_as
-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3
-- sys_gen/tst_sram/nexys4/tb/tb_tst_sram_n4
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.1; ghdl 0.26-0.33
-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.2; ghdl 0.26-0.33
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2016-07-03 783 2016.3 xc7a100t-1 91 87 0 0 43
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-07-03 767 14.7 131013 xc6slx16-2 100 134 0 60 s 4.2
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.2.2 don't init N_REGS (vivado fix for fsm inference)
-- 2016-07-16 788 2.1 change *DELAY generics, now absolute delay cycles
-- add s_init1; drop "KEEP" for data (better for dbg)
-- 2016-07-10 786 2.0 add page mode support
-- 2016-05-22 767 1.2.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-26 718 1.2.1 BUGFIX: do_dispatch(): always define imem_oe
-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as
-- 2011-11-19 432 1.1 remove O_FLA_CE_N port
@@ -44,41 +55,23 @@
-- 2010-05-23 293 1.0 Initial version
--
-- Notes:
-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
-- short READ1 delay works in sim, but not on fpga where the data of the
-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
-- 40ns or 50 ns, only T_apa 60 ns fails !
-- Unclear what is wrong here, the timing of the memory model seems ok.
-- 2. There is no 'bus-turn-around' cycle needed for a write->read change
-- 1. There is no 'bus-turn-around' cycle needed for a write->read change
-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
-- transition simultaneously. The FPGA will go high-Z quickly, the memory
-- low-Z delay by the IOB and internal memory delays. No clash.
-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
-- 2. There is a hidden 'bus-turn-around' cycle for a read->write change.
-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
-- some delay. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
-- Again no clash due to the 1 cycle delay.
--
-- Nominal timings:
-- READ0/1 = N_rd_cycle - 2
-- WRITE = N_wr_cycle - 1
-- READ0 = (T_aa + ext_read_delay) in cycles
-- READ1 = (T_pa + ext_read_delay) in cycles
-- WRITE = (T_aa + ext_write_delay) in cycles
-- with
-- ext_read_delay: output_IOB + 2*PCB_delay + input_IOB + skew
-- ext_write_delay: skew
--
-- from notes_nexys2.txt (Rev 339):
-- clksys RD WR < use for > Test case
-- MHz div mul
-- <51.20 2 3 <-- 50 50 1 1
-- 51.20- 54.80 3 3 <-- 52,54 54 25 27
-- 54.80- 64.10 3 4 <-- 55,56,58,60,62,64 64 25 32
-- 64.10- 68.50 4 4 <-- 65 65 10 13
-- 68.50- 76.92 4 5 <-- 70,75 75 2 3
-- 76.92- 82.19 5 5 <-- 80 80 5 8
-- 82.19- 89.74 5 6 <-- 85 85 10 17
-- 89.74- 95.89 6 6 <-- 90,95 95 10 19
-- 95.89-102.56 6 7 <-- 100 100 1 2
-- remark added 2015-12-26
-- - for sys_w11a_n3 one gets in simulation errors for 72 MHz and RD=4 !!
-- - so far unclear whether controller or memory model is wrong !!
--
-- Timing of some signals:
--
@@ -126,9 +119,9 @@ use work.xlib.all;
entity nx_cram_memctl_as is -- CRAM driver (async+page mode)
generic (
READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
READ0DELAY : positive := 4; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 3); -- write delay in clock cycles
WRITEDELAY : positive := 4); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -160,6 +153,13 @@ end nx_cram_memctl_as;
architecture syn of nx_cram_memctl_as is
type state_type is (
s_init, -- s_init: startup state
s_init1, -- s_init1: reset released
s_wcinit, -- s_wcinit: write rcr init
s_wcwait, -- s_wcwait: write rcr wait
s_wcput, -- s_wcput: write rcr done
s_rainit, -- s_rainit: read array init
s_rawait, -- s_rawait: wait read array
s_idle, -- s_idle: wait for req
s_rdinit, -- s_rdinit: read init cycle
s_rdwait0, -- s_rdwait0: read wait low word
@@ -187,7 +187,7 @@ architecture syn of nx_cram_memctl_as is
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
s_init, -- state
'0', -- ackr
'0', -- addr0
"00", -- be2nd
@@ -197,7 +197,16 @@ architecture syn of nx_cram_memctl_as is
(others=>'0'), -- memdo0
(others=>'0') -- memdi
);
constant c_addrh_rcr_setup : slv22 :=
"000" & -- 22:20 reserved MBZ
"00" & -- 19:18 reg sel 00=RCR
"0000000000" & -- 17: 8 reserved MBZ
'1' & -- 7 page mode enable (1=enable)
"00" & -- 6: 5 reserved MBZ
'1' & -- 4 dpd disaable (1=disable)
"000"; -- 3: 1 rest is reserved or PAR, which should be 0
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
@@ -206,9 +215,11 @@ architecture syn of nx_cram_memctl_as is
signal MEM_BE_N : slv2 := "11";
signal MEM_WE_N : slbit := '1';
signal MEM_OE_N : slbit := '1';
signal MEM_CRE : slbit := '0';
signal BE_CE : slbit := '0';
signal ADDRH_CE : slbit := '0';
signal ADDR0_CE : slbit := '0';
signal ADDRH : slv22 := (others=>'0');
signal ADDR0 : slbit := '0';
signal DATA_CEI : slbit := '0';
signal DATA_CEO : slbit := '0';
@@ -216,16 +227,22 @@ architecture syn of nx_cram_memctl_as is
signal MEM_DO : slv16 := (others=>'0');
signal MEM_DI : slv16 := (others=>'0');
-- these attributes aren't accepted by ghdl 0.26
-- attribute s : string;
-- attribute s of I_MEM_WAIT : signal is "true";
begin
assert READ0DELAY<=2**R_REGS.cntdly'length and
READ1DELAY<=2**R_REGS.cntdly'length and
WRITEDELAY<=2**R_REGS.cntdly'length
report "assert(READ0,READ1,WRITEDELAY <= 2**cntdly'length)"
-- Notes:
-- used READ0DELAY-2 and READ0DELAY-3
-- used READ1DELAY-2
-- used WRITEDELAY-2
assert READ0DELAY-2 < 2**R_REGS.cntdly'length and
READ1DELAY-2 < 2**R_REGS.cntdly'length and
WRITEDELAY-2 < 2**R_REGS.cntdly'length
report "assert( (READ0,READ1,WRITE)DELAY-2 < 2**cntdly'length)"
severity failure;
assert READ0DELAY >= 3 and
READ1DELAY >= 2 and
WRITEDELAY >= 2
report "assert( (READ0,READ1,WRITE)DELAY-2 >= 2 or 3)"
severity failure;
CLK_180 <= not CLK;
@@ -271,13 +288,23 @@ begin
PAD => O_MEM_OE_N
);
IOB_MEM_CRE : iob_reg_o
generic map (
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DO => MEM_CRE,
PAD => O_MEM_CRE
);
IOB_MEM_ADDRH : iob_reg_o_gen
generic map (
DWIDTH => 22)
port map (
CLK => CLK,
CE => ADDRH_CE,
DO => ADDR,
DO => ADDRH,
PAD => O_MEM_ADDR(22 downto 1)
);
@@ -292,7 +319,7 @@ begin
IOB_MEM_DATA : iob_reg_io_gen
generic map (
DWIDTH => 16,
PULL => "KEEP")
PULL => "NONE")
port map (
CLK => CLK,
CEI => DATA_CEI,
@@ -305,7 +332,6 @@ begin
O_MEM_ADV_N <= '0';
O_MEM_CLK <= '0';
O_MEM_CRE <= '0';
proc_regs: process (CLK)
begin
@@ -320,7 +346,7 @@ begin
end process proc_regs;
proc_next: process (R_REGS, REQ, WE, BE, DI, MEM_DO)
proc_next: process (R_REGS, REQ, WE, BE, DI, ADDR, MEM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
@@ -328,13 +354,15 @@ begin
variable iackw : slbit := '0';
variable iactr : slbit := '0';
variable iactw : slbit := '0';
variable imem_ce : slbit := '0';
variable imem_be : slv2 := "00";
variable imem_we : slbit := '0';
variable imem_oe : slbit := '0';
variable imem_ce : slbit := '0';
variable imem_be : slv2 := "00";
variable imem_we : slbit := '0';
variable imem_oe : slbit := '0';
variable imem_cre : slbit := '0';
variable ibe_ce : slbit := '0';
variable iaddrh_ce : slbit := '0';
variable iaddr0_ce : slbit := '0';
variable iaddrh : slv22 := (others=>'0');
variable iaddr0 : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
@@ -385,13 +413,15 @@ begin
iactr := '0';
iactw := '0';
imem_ce := '0';
imem_be := "11";
imem_we := '0';
imem_oe := '0';
imem_ce := '0';
imem_be := "11";
imem_we := '0';
imem_oe := '0';
imem_cre := '0';
ibe_ce := '0';
iaddrh_ce := '0';
iaddr0_ce := '0';
iaddrh := ADDR;
iaddr0 := '0';
idata_cei := '0';
idata_ceo := '0';
@@ -402,6 +432,54 @@ begin
end if;
case r.state is
when s_init => -- s_init: startup state
ibusy := '1'; -- signal busy, unable to handle req
n.state := s_init1;
when s_init1 => -- s_init1: reset released
ibusy := '1'; -- signal busy, unable to handle req
iaddrh := c_addrh_rcr_setup;
iaddr0 := '0';
iaddrh_ce := '1';
iaddr0_ce := '1';
imem_ce := '1'; -- ce CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
n.state := s_wcinit;
when s_wcinit => -- s_wcinit: write rcr init
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
n.cntdly := slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wcwait;
when s_wcwait => -- s_wcinit: write rcr wait
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM next cycle
imem_cre := '1'; -- cre CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_wcput; -- next: write rcr done
end if;
when s_wcput => -- s_wcput: write rcr done
ibusy := '1'; -- signal busy, unable to handle req
n.state := s_rainit; -- next: read array init
when s_rainit => -- s_rainit: read array init
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
n.cntdly:= slv(to_unsigned(READ0DELAY-2, n.cntdly'length));
n.state := s_rawait ; -- next: wait read array
when s_rawait => -- s_rawait: wait read array
ibusy := '1'; -- signal busy, unable to handle req
imem_ce := '1'; -- ce CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_idle; -- next: wait for req
end if;
when s_idle => -- s_idle: wait for req
if REQ = '1' then -- if IO requested
do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
@@ -413,8 +491,8 @@ begin
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length));
n.state := s_rdwait0; -- next: wait
n.cntdly:= slv(to_unsigned(READ0DELAY-3, n.cntdly'length));
n.state := s_rdwait0; -- next: wait low word
when s_rdwait0 => -- s_rdwait0: read wait low word
ibusy := '1'; -- signal busy, unable to handle req
@@ -433,7 +511,7 @@ begin
idata_cei := '1'; -- latch input data
iaddr0_ce := '1'; -- latch address 0 bit
iaddr0 := '1'; -- now go for high word
n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length));
n.cntdly:= slv(to_unsigned(READ1DELAY-2, n.cntdly'length));
n.state := s_rdwait1; -- next: wait high word
when s_rdwait1 => -- s_rdwait1: read wait high word
@@ -442,7 +520,7 @@ begin
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
if unsigned(r.cntdly) = 0 then -- wait expired ?
n.state := s_rdget1; -- next: get low word
n.state := s_rdget1; -- next: get high word
end if; --
when s_rdget1 => -- s_rdget1: read get high word
@@ -468,7 +546,7 @@ begin
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
n.cntdly:= slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wrwait0; -- next: wait
when s_wrwait0 => -- s_rdput0: write wait 1st word
@@ -511,7 +589,7 @@ begin
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
n.cntdly:= slv(to_unsigned(WRITEDELAY-2, n.cntdly'length));
n.state := s_wrwait1; -- next: wait
when s_wrwait1 => -- s_wrwait1: write wait 2nd word
@@ -565,6 +643,7 @@ begin
MEM_WE_N <= not imem_we;
MEM_BE_N <= not imem_be;
MEM_OE_N <= not imem_oe;
MEM_CRE <= imem_cre;
if r.addr0 = '0' then
MEM_DI <= r.memdi(15 downto 0);
@@ -575,6 +654,7 @@ begin
BE_CE <= ibe_ce;
ADDRH_CE <= iaddrh_ce;
ADDR0_CE <= iaddr0_ce;
ADDRH <= iaddrh;
ADDR0 <= iaddr0;
DATA_CEI <= idata_cei;
DATA_CEO <= idata_ceo;

61
rtl/bplib/nxcramlib/nxcramlib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: nxcramlib.vhd 641 2015-02-01 22:12:15Z mueller $
-- $Id: nxcramlib.vhd 788 2016-07-16 22:23:23Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,10 +16,11 @@
-- Description: Nexys 2/3 CRAM drivers
--
-- Dependencies: -
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
-- Tool versions: ise 11.4-14.7; viv 2014.4-2016.2; ghdl 0.26-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.1 add cram_(read0|read1|write)delay functions
-- 2011-11-26 433 1.0 Initial version (extracted from nexys2lib)
------------------------------------------------------------------------------
@@ -29,6 +30,16 @@ use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nxcramlib is
pure function cram_delay(clk_mhz : positive;
delay_ps : positive) return positive;
pure function cram_read0delay(clk_mhz : positive) return positive;
pure function cram_read1delay(clk_mhz : positive) return positive;
pure function cram_writedelay(clk_mhz : positive) return positive;
constant cram_read0delay_ps : positive := 80000; -- initial read delay
constant cram_read1delay_ps : positive := 30000; -- page read delay
constant cram_writedelay_ps : positive := 75000; -- write delay
component nx_cram_dummy is -- CRAM protection dummy
port (
@@ -47,9 +58,9 @@ end component;
component nx_cram_memctl_as is -- CRAM driver (async+page mode)
generic (
READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
READ0DELAY : positive := 4; -- read word 0 delay in clock cycles
READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
WRITEDELAY : positive := 3); -- write delay in clock cycles
WRITEDELAY : positive := 4); -- write delay in clock cycles
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -78,3 +89,43 @@ component nx_cram_memctl_as is -- CRAM driver (async+page mode)
end component;
end package nxcramlib;
-- ----------------------------------------------------------------------------
package body nxcramlib is
-- -------------------------------------
pure function cram_delay( -- calculate delay in clock cycles
clk_mhz : positive; -- clock frequency in MHz
delay_ps : positive) -- delay in ps
return positive is
variable period_ps : natural := 0; -- clk period in ps
begin
period_ps := 1000000 / clk_mhz;
return (delay_ps + period_ps - 10) / period_ps;
end function cram_delay;
-- -------------------------------------
pure function cram_read0delay( -- read0 delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_read0delay_ps);
end function cram_read0delay;
-- -------------------------------------
pure function cram_read1delay( -- read1 delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_read1delay_ps);
end function cram_read1delay;
-- -------------------------------------
pure function cram_writedelay( -- write delay in clock cycles
clk_mhz : positive) -- clock frequency in MHz
return positive is
begin
return cram_delay(clk_mhz, cram_writedelay_ps);
end function cram_writedelay;
end package body nxcramlib;

1
rtl/bplib/nxcramlib/tb/.cvsignore
View File

@@ -1,2 +1,3 @@
tb_nx_cram_memctl_as
tb_nx_cram_memctl_stim
list_cram_delay

42
rtl/bplib/nxcramlib/tb/Makefile Normal file
View File

@@ -0,0 +1,42 @@
# $Id: Makefile 788 2016-07-16 22:23:23Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-04-17 761 1.0 Initial version
#
EXE_all = tb_nx_cram_memctl_as
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
endif
#

5
rtl/bplib/nxcramlib/tb/Makefile.ise
View File

@@ -1,4 +1,4 @@
# $Id: Makefile.ise 761 2016-04-17 08:53:48Z mueller $
# $Id: Makefile.ise 788 2016-07-16 22:23:23Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -6,7 +6,8 @@
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2011-11-26 433 1.0 Initial version (cloned)
#
EXE_all = tb_nx_cram_memctl_as
EXE_all = tb_nx_cram_memctl_as
EXE_all += list_cram_delay
#
ifndef XTW_BOARD
XTW_BOARD=nexys3

11
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nx_cram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_nx_cram_memctl.vhd 802 2016-08-27 19:00:23Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -113,10 +113,11 @@ end component;
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 7.5 ns; -- compatible ucf for
constant c2out_time : time := 12.0 ns; -- tbd_nx_cram_memctl_as
constant clock_period : Delay_length := 20 ns; -- when changed update also
-- READ0DELAY ect delays !!
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 7.5 ns; -- compatible ucf for
constant c2out_time : Delay_length := 12.0 ns; -- tbd_nx_cram_memctl_as
begin

2
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as.vbom
View File

@@ -1,6 +1,8 @@
# configure tb_nx_cram_memctl with tbd_nx_cram_memctl_as target;
# use vhdl configure file (tb_nx_cram_memctl_as.vhd) to allow
# that all configurations will co-exist in work library
# configure
uut = tbd_nx_cram_memctl_as.vbom
tb_nx_cram_memctl.vbom
# design
tb_nx_cram_memctl_as.vhd

3
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl_as_ssim.vbom
View File

@@ -1,5 +1,6 @@
# configure for _*sim case
#
# configure
uut = tbd_nx_cram_memctl_as_ssim.vhd
# design
tb_nx_cram_memctl_as.vbom
@top:tb_nx_cram_memctl_as

40
rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.ucf Normal file
View File

@@ -0,0 +1,40 @@
## $Id: tbd_nx_cram_memctl_as.ucf 433 2011-11-27 22:04:39Z mueller $
##
## drive strength defs and timing defs for tbd_nx_cram_memctl_as test target
##
## Revision History:
## Date Rev Version Comment
## 2011-11-26 433 1.1 renamed from tbd_n2_cram_memctl_as.ucf
## 2010-05-30 297 1.0 Initial version
##
## Note: default is DRIVE=12 | SLEW=SLOW
##
## The OFFSET rules are compatible with the setup and c2out times
## used in the test bench tb_nx_cram_memctl.
##
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
OFFSET = IN 7.5 ns BEFORE "CLK";
OFFSET = OUT 12.0 ns AFTER "CLK";
##
NET "O_MEM_WE_N" OFFSET = OUT 12.0 ns AFTER "CLK" FALLING;
##
## -- define defaults
##
INST "/" IOSTANDARD=LVCMOS33;
##
## CRAM ----------------------------------------------------------------------
NET "O_MEM_CE_N" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_WE_N" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_OE_N" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_BE_N<*>" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_ADV_N" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CLK" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CRE" IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "I_MEM_WAIT" IOSTANDARD=LVCMOS33 | PULLDOWN;
##
NET "O_MEM_ADDR<*>" IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=FAST;
NET "IO_MEM_DATA<*>" IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW | KEEPER;
##

15
rtl/bplib/nxcramlib/tb/tbd_nx_cram_memctl_as.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tbd_nx_cram_memctl_as.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tbd_nx_cram_memctl_as.vhd 802 2016-08-27 19:00:23Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -30,6 +30,7 @@
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-08-27 802 1.2.1 use cram_read0delay ect
-- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_memctl
-- 2010-06-03 298 1.0.1 add hack to force IOB'FFs to O_MEM_ADDR
@@ -78,7 +79,7 @@ architecture syn of tbd_nx_cram_memctl_as is
begin
-- Note: This is a HACk to ensure that the IOB flops are on the O_MEM_ADDR
-- Note: This is a hack to ensure that the IOB flops are on the O_MEM_ADDR
-- pins. Without par might choose to use IFF's on ADDR, causing varying
-- routing delays to O_MEM_ADDR. Didn't find a better way, setting
-- iob "false" attributes in ADDR didn't help.
@@ -87,11 +88,11 @@ begin
ADDR_X <= ADDR when RESET='0' else (others=>'0');
MEMCTL : nx_cram_memctl_as
CRAMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => 2,
READ1DELAY => 2,
WRITEDELAY => 3)
READ0DELAY => cram_read0delay(50), -- assume 50 MHz system clock. Must be
READ1DELAY => cram_read1delay(50), -- modified when clock_period is
WRITEDELAY => cram_writedelay(50)) -- changed in tb_nx_cram_memctl !!
port map (
CLK => CLK,
RESET => RESET,

12
rtl/bplib/nxcramlib/tb/tbrun.yml Normal file
View File

@@ -0,0 +1,12 @@
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-22 800 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [default, viv, bplib, cram_memctl_as]
test: |
tbrun_tbw tb_nx_cram_memctl_as${ms}

7
rtl/bplib/s3board/s3_sram_memctl.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: s3_sram_memctl.vhd 793 2016-07-23 19:38:55Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.0.7 drop "KEEP" for data (better for dbg)
-- 2011-11-19 427 1.0.6 now numeric_std clean
-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl
@@ -200,7 +201,7 @@ begin
IOB_MEM_DATA : iob_reg_io_gen
generic map (
DWIDTH => 32,
PULL => "KEEP")
PULL => "NONE")
port map (
CLK => CLK,
CEI => DATA_CEI,

2
rtl/bplib/s3board/tb/Makefile
View File

@@ -10,8 +10,6 @@
# 2007-11-26 98 1.1 use make includes
# 2007-09-23 84 1.0 Initial version
#
EXE_all = tb_s3board_dummy
EXE_all += tb_s3board_fusp_dummy
EXE_all += tb_s3_sram_memctl
#
ifndef XTW_BOARD

7
rtl/bplib/s3board/tb/s3board_dummy.vbom Normal file
View File

@@ -0,0 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../s3boardlib.vbom
# components
../s3_sram_dummy.vbom
# design
s3board_dummy.vhd

73
rtl/bplib/s3board/tb/s3board_dummy.vhd Normal file
View File

@@ -0,0 +1,73 @@
-- $Id: s3board_dummy.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s3board_dummy - syn
-- Description: s3board minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_s3board
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.1.3 rename input pin CLK -> I_CLK50
-- 2010-04-17 278 1.1.2 rename sram_dummy -> s3_sram_dummy
-- 2007-12-16 101 1.1.1 use _N for active low
-- 2007-12-09 100 1.1 add sram memory signals, dummy handle them
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.s3boardlib.all;
entity s3board_dummy is -- S3BOARD dummy (base; loopback)
-- implements s3board_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end s3board_dummy;
architecture syn of s3board_dummy is
begin
O_TXD <= I_RXD;
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;

10
rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_s3_sram_memctl.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_s3_sram_memctl.vhd 790 2016-07-20 18:52:44Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -90,10 +90,10 @@ architecture sim of tb_s3_sram_memctl is
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin

2
rtl/bplib/s3board/tb/tb_s3_sram_memctl_ssim.vbom
View File

@@ -1,4 +1,6 @@
# configure for _*sim case
# configure
uut = s3_sram_memctl_ssim.vhd
# design
tb_s3_sram_memctl.vbom
@top:tb_s3_sram_memctl

20
rtl/bplib/s3board/tb/tb_s3board.vbom Normal file
View File

@@ -0,0 +1,20 @@
# Not meant for direct top level usage. Used with
# tb_s3board_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../s3boardlib.vbom
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
tb_s3board_core.vbom
${s3board_aif := s3board_dummy.vbom} -UUT
../../../vlib/serport/tb/serport_master_tb.vbom
# design
tb_s3board.vhd
@top:tb_s3board

205
rtl/bplib/s3board/tb/tb_s3board.vhd Normal file
View File

@@ -0,0 +1,205 @@
-- $Id: tb_s3board.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board - sim
-- Description: Test bench for s3board (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- tb_s3board_core
-- s3board_aif [UUT]
-- serport/tb/serport_master_tb
--
-- To test: generic, any s3board_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.2 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-21 432 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 2.0.3 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 2.0.2 use serport_uart_rxtx
-- 2010-05-01 286 2.0.1 use rritb_core as component again (rriv1 is gone..)
-- 2010-04-25 283 2.0 factor out basic device handling to tb_s3board_core
-- and_conf/_stim file processing to rri/tb/rritb_core
-- 2010-04-24 281 1.3.2 use serport_uart_[tr]x directly again
-- 2007-12-16 101 1.3.1 use _N for active low, add sram memory model
-- 2007-12-09 100 1.3 add sram memory signals
-- 2007-11-23 97 1.2 use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-10-26 92 1.1.1 use DONE timestamp at end of execution
-- 2007-10-19 90 1.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- use CLKDIV="00 --> sim with max. serport speed
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board is
end tb_s3board;
architecture sim of tb_s3board is
signal CLK : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'1');
signal O_MEM_BE_N : slv4 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADDR : slv18 := (others=>'Z');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
S3CORE : entity work.tb_s3board_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : s3board_aif
port map (
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;

2
rtl/bplib/s3board/tb/tb_s3board_core.vbom
View File

@@ -1,7 +1,9 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simbididly.vhd
../../issi/is61lv25616al.vbom
# design
tb_s3board_core.vhd

59
rtl/bplib/s3board/tb/tb_s3board_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_s3board_core.vhd 724 2016-01-03 22:53:53Z mueller $
-- $Id: tb_s3board_core.vhd 793 2016-07-23 19:38:55Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,14 +15,16 @@
-- Module Name: tb_s3board_core - sim
-- Description: Test bench for s3board - core device handling
--
-- Dependencies: vlib/parts/issi/is61lv25616al
-- Dependencies: simlib/simbididly
-- vlib/parts/issi/is61lv25616al
--
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.1 use simbididly
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
@@ -35,6 +37,7 @@ use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board_core is
@@ -52,34 +55,56 @@ end tb_s3board_core;
architecture sim of tb_s3board_core is
signal MM_MEM_CE_N : slv2 := (others=>'1');
signal MM_MEM_BE_N : slv4 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADDR : slv18 := (others=>'Z');
signal MM_MEM_DATA : slv32 := (others=>'0');
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 32)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(15 downto 0)
CE_N => MM_MEM_CE_N(0),
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(1),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(3),
LB_N => O_MEM_BE_N(2),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(31 downto 16)
CE_N => MM_MEM_CE_N(1),
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(3),
LB_N => MM_MEM_BE_N(2),
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA(31 downto 16)
);
proc_simbus: process (SB_VAL)

14
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_s3board_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
-- $Id: tb_s3board_fusp.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -25,9 +25,10 @@
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
@@ -60,7 +61,6 @@ architecture sim of tb_s3board_fusp is
signal CLK : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal RESET : slbit := '0';
@@ -106,8 +106,8 @@ architecture sim of tb_s3board_fusp is
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
@@ -116,8 +116,7 @@ begin
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
CLK => CLK
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
@@ -125,7 +124,6 @@ begin
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,

12
rtl/bplib/s3board/tb/tbrun.yml Normal file
View File

@@ -0,0 +1,12 @@
# $Id: tbrun.yml 807 2016-09-17 07:49:26Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-08-27 802 1.0 Initial version
#
- default:
mode: ${ise_modes}
#
- tag: [default, ise, bplib, sram_memctl]
test: |
tbrun_tbw tb_s3_sram_memctl${ms}

4
rtl/bplib/sysmon/sysmon_rbus_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sysmon_rbus_core.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: sysmon_rbus_core.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -24,7 +24,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-25 787 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-25 767 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- BUGFIX: use s_init in regs_init (was s_idle)
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft

37
rtl/ibus/Makefile Normal file
View File

@@ -0,0 +1,37 @@
# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#

4
rtl/ibus/ibd_iist.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ibd_iist.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: ibd_iist.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2009-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -29,7 +29,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 0.8.2 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 0.8.2 don't init N_REGS (vivado fix for fsm inference)
-- 2011-11-18 427 0.8.1 now numeric_std clean
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im

4
rtl/ibus/ibdr_rhrp.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ibdr_rhrp.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: ibdr_rhrp.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -28,7 +28,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2015-06-20 692 1.0.3 BUGFIX: fix func-go when drive/init busy checks
-- 2015-06-05 690 1.0.2 use 'not unit' for lsb of rpsn to avoid SI detect
-- BUGFIX: set rmr only for write to busy unit

4
rtl/ibus/ibdr_rk11.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ibdr_rk11.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: ibdr_rk11.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -29,7 +29,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.3.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.3.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;

4
rtl/ibus/ibdr_rl11.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ibdr_rl11.vhd 767 2016-05-26 07:47:51Z mueller $
-- $Id: ibdr_rl11.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,7 +27,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 787 1.0.2 don't init N_REGS (vivado fix for fsm inference)
-- 2016-05-22 767 1.0.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore
-- 2015-02-28 653 1.0 Initial verison
-- 2014-06-09 561 0.1 First draft

47
rtl/ibus/sys_conf.vhd Normal file
View File

@@ -0,0 +1,47 @@
-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Default definitions for ibdr_maxisys
--
-- Dependencies: -
-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-03-14 658 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure character and communication devices
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11
constant sys_conf_ibd_pc11 : boolean := true; -- PC11
constant sys_conf_ibd_lp11 : boolean := true; -- LP11
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
end package sys_conf;

Some files were not shown because too many files have changed in this diff Show More