mirror of
https://github.com/wfjm/w11.git
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14362b2a56
- arty board support - viv_tools_build: export log and rpt generated in OOC synthesis runs - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model
38 lines
730 B
Makefile
38 lines
730 B
Makefile
# $Id: Makefile 1067 2018-11-11 08:30:29Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2018-11-10 1067 1.0 Initial version
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#
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VBOM_all = $(wildcard *.vbom)
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DCP_all = $(VBOM_all:.vbom=_syn.dcp)
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#
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# reference board for test synthesis is Artix-7 based Nexys4
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ifndef XTW_BOARD
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XTW_BOARD=nexys4
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endif
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include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
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#
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.PHONY : catch all clean
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#
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catch :
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@echo "no default target defined, use"
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@echo " make all"
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@echo " make <module>_syn.dcp"
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@exit 1
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#
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all : $(DCP_all)
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#
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clean : viv_clean
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#
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#-----
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#
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include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
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#
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VBOM_all = $(wildcard *.vbom)
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#
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ifndef DONTINCDEP
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include $(VBOM_all:.vbom=.dep_vsyn)
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endif
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#
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