mirror of
https://github.com/wfjm/w11.git
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cb7b906089
- sys_tst_sram_arty: add system and tb - sramif_mig_arty: add SRAM to DDR via MIG adapter for arty - cdc_pulse: add clock domain crossing for a slowly changing value - cdc_vector_s0: add ENA port (now used in cdc_pulse) - tst_mig/util.tcl: test_rwait: add optional lena argument - viv_tools_build.tcl: downgrade SSN critical warnings to warnings
This directory sub-tree contains HDL sources for top level designs and is organized in
| Directory | Content |
|---|---|
| tst_mig | MIG core tester |
| tst_rlink | rlink tester (over serial links) |
| tst_rlink_cuff | rlink tester (over Cypress FX2 USB) |
| tst_serloop | serial port loop back tester |
| tst_snhumanio | Digilent board human IO tester |
| tst_sram | memory tester (SRAM or CRAM) |
| w11a | w11a systems |