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wfjm cb7b906089 Add memory tester for Arty and MIG
- sys_tst_sram_arty: add system and tb
- sramif_mig_arty: add SRAM to DDR via MIG adapter for arty
- cdc_pulse: add clock domain crossing for a slowly changing value
- cdc_vector_s0: add ENA port (now used in cdc_pulse)
- tst_mig/util.tcl: test_rwait: add optional lena argument
- viv_tools_build.tcl: downgrade SSN critical warnings to warnings
2019-01-03 09:15:07 +01:00
..
2019-01-03 09:15:07 +01:00
2018-12-31 10:00:14 +01:00
2016-12-26 21:27:33 +01:00
2016-12-23 15:51:48 +01:00

This directory sub-tree contains a wide range of support modules and is organized in

Directory Content
cdclib modules for clock domain crossing
comlib modules for communication
genlib grab bag of other modules
memlib wrappers for distributed and block RAM; fifos
rbus modules for rbus fabric; some basic rbus devices
rlink rlink interface
serport serial port interface
simlib helper modules for test benches
xlib warppers for some Xilinx components