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2b5cfb7d96
- xsim support complete (but many issues to be resolved yet) - Added configurable w11a cache - Removed some never documented and now strategically obsolete designs
65 lines
1.8 KiB
VHDL
65 lines
1.8 KiB
VHDL
-- $Id: gray2bin_gen.vhd 751 2016-03-25 19:46:11Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: gray2bin_gen - syn
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-- Description: Gray code to binary converter
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--
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-- Dependencies: -
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-- Test bench: tb/tb_gray_cnt_n
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-- Target Devices: generic
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-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-12-26 106 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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entity gray2bin_gen is -- gray->bin converter, generic vector
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generic (
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DWIDTH : positive := 4); -- data width
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port (
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DI : in slv(DWIDTH-1 downto 0); -- gray code input
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DO : out slv(DWIDTH-1 downto 0) -- binary code output
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);
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end entity gray2bin_gen;
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architecture syn of gray2bin_gen is
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begin
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proc_comb: process (DI)
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variable ido : slv(DWIDTH-1 downto 0);
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begin
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ido := (others=>'0');
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ido(DWIDTH-1) := DI(DWIDTH-1);
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for i in DWIDTH-2 downto 0 loop
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ido(i) := ido(i+1) xor DI(i);
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end loop;
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DO <= ido;
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end process proc_comb;
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end syn;
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