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3f455d5236
- re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std
105 lines
3.9 KiB
VHDL
105 lines
3.9 KiB
VHDL
-- $Id: ram_2swsr_rfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
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--
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: ram_2swsr_rfirst_gen - syn
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-- Description: Dual-Port RAM with with two synchronous read/write ports
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-- and 'read-before-write' semantics (as block RAM).
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-- The code is inspired by Xilinx example rams_16.vhd. The
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-- 'ram_style' attribute is set to 'block', this will
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-- force in XST a synthesis as block RAM.
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic Spartan, Virtex
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-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-08 422 1.0.4 now numeric_std clean
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-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
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-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
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-- now initialize DO to all '0' at start
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-- 2008-03-02 122 1.0.1 change generic default for BRAM models
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-- 2007-06-03 45 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
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generic (
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AWIDTH : positive := 11; -- address port width
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DWIDTH : positive := 9); -- data port width
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port(
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CLKA : in slbit; -- clock port A
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CLKB : in slbit; -- clock port B
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ENA : in slbit; -- enable port A
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ENB : in slbit; -- enable port B
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WEA : in slbit; -- write enable port A
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WEB : in slbit; -- write enable port B
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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DIA : in slv(DWIDTH-1 downto 0); -- data in port A
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DIB : in slv(DWIDTH-1 downto 0); -- data in port B
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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);
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end ram_2swsr_rfirst_gen;
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architecture syn of ram_2swsr_rfirst_gen is
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constant memsize : positive := 2**AWIDTH;
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constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
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type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
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shared variable sv_ram : ram_type := (others=>datzero);
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attribute ram_style : string;
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attribute ram_style of sv_ram : variable is "block";
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signal R_DOA : slv(DWIDTH-1 downto 0) := datzero;
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signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
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begin
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proc_clka: process (CLKA)
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begin
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if rising_edge(CLKA) then
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if ENA = '1' then
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R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
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if WEA = '1' then
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sv_ram(to_integer(unsigned(ADDRA))) := DIA;
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end if;
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end if;
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end if;
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end process proc_clka;
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proc_clkb: process (CLKB)
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begin
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if rising_edge(CLKB) then
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if ENB = '1' then
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R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
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if WEB = '1' then
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sv_ram(to_integer(unsigned(ADDRB))) := DIB;
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end if;
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end if;
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end if;
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end process proc_clkb;
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DOA <= R_DOA;
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DOB <= R_DOB;
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end syn;
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