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4732555297
- new reference system
- switched from ISE 13.3 to 14.7.
- map/par behaviour changed, unfortunately unfavorably for w11a.
On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can
be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
43 lines
1.4 KiB
Plaintext
43 lines
1.4 KiB
Plaintext
FLOWTYPE = FPGA_SYNTHESIS;
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#
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# $Id: syn_7a_speed.opt 540 2013-10-13 18:42:50Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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# 2013-10-13 540 1.2 use -shreg_min_size=3
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# 2013-09-21 534 1.0 Initial version (cloned from imp_s6_speed.opt)
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#
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# Derived from ISE xst_mixed.opt
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#
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# ----------------------------------------------------------------------------
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# Options for XST
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#
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Program xst
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-ifn <design>_xst.scr; # input XST script file
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-ofn <design>_xst.log; # output XST log file
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-intstyle xflow; # Message Reporting Style
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#
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# ParamFile lists the XST Properties that can be set by the user.
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#
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ParamFile: <design>_xst.scr
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"run";
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#
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# Global Synthesis Options
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#
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"-ifn <synthdesign>"; # Input/Project File Name
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"-ifmt mixed"; # Input Format (Verilog and VHDL)
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"-ofn <design>"; # Output File Name
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"-ofmt ngc"; # Output File Format
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"-top $top_entity"; # Top Design Name
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"-p <partname>"; # Target Device
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"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
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"-opt_level 2"; # Optimization Effort Criteria: 2=High
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"-shreg_min_size 3"; # default is 2 !!
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"-uc <design>.xcf"; # Constraint File name
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#
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# The following are HDL Options
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#
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End ParamFile
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End Program xst
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#
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