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3f455d5236
- re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std
6 lines
67 B
Plaintext
6 lines
67 B
Plaintext
# libs
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../slvtypes.vhd
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@lib:unisim
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# design
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dcm_sfs_unisim_s3e.vhd
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