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106 lines
4.4 KiB
Tcl
106 lines
4.4 KiB
Tcl
# -*- tcl -*-
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# $Id: arty_pins.xdc 1190 2019-07-13 17:05:39Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Digilent Arty core functionality
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# - Configuration setup
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# - config voltage
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# - enable bitstream timestamp
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# - Pin Locks for
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# - USB UART
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# - human I/O (switches, buttons, leds)
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#
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# Revision History:
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# Date Rev Version Comment
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# 2016-04-02 758 1.2 add BITSTREAM.CONFIG.USR_ACCESS setup
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# 2016-03-06 740 1.1 add A_VPWRP/N to baseline config
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# 2016-01-31 726 1.0 Initial version
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#
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# config setup --------------------------------------------------------------
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
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# clocks -- in bank 35 ------------------------------------------------------
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set_property PACKAGE_PIN e3 [get_ports {I_CLK100}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}]
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#
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# USB UART Interface -- in bank 16 ------------------------------------------
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set_property PACKAGE_PIN a9 [get_ports {I_RXD}]
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set_property PACKAGE_PIN d10 [get_ports {O_TXD}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD}]
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set_property DRIVE 12 [get_ports {O_TXD}]
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set_property SLEW SLOW [get_ports {O_TXD}]
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#
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# switches -- in bank 16 ----------------------------------------------------
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set_property PACKAGE_PIN a8 [get_ports {I_SWI[0]}]
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set_property PACKAGE_PIN c11 [get_ports {I_SWI[1]}]
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set_property PACKAGE_PIN c10 [get_ports {I_SWI[2]}]
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set_property PACKAGE_PIN a10 [get_ports {I_SWI[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}]
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#
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# buttons -- in bank 16 -----------------------------------------------------
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set_property PACKAGE_PIN d9 [get_ports {I_BTN[0]}]
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set_property PACKAGE_PIN c9 [get_ports {I_BTN[1]}]
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set_property PACKAGE_PIN b9 [get_ports {I_BTN[2]}]
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set_property PACKAGE_PIN b8 [get_ports {I_BTN[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}]
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#
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# LEDs -- in bank 14+35 -----------------------------------------------------
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set_property PACKAGE_PIN h5 [get_ports {O_LED[0]}]
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set_property PACKAGE_PIN j5 [get_ports {O_LED[1]}]
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set_property PACKAGE_PIN t9 [get_ports {O_LED[2]}]
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set_property PACKAGE_PIN t10 [get_ports {O_LED[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}]
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set_property DRIVE 12 [get_ports {O_LED[*]}]
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set_property SLEW SLOW [get_ports {O_LED[*]}]
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#
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# RGB-LEDs -- in bank 35 ----------------------------------------------------
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# Note: [0] red [1] green [2] blue
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set_property PACKAGE_PIN g6 [get_ports {O_RGBLED0[0]}]
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set_property PACKAGE_PIN f6 [get_ports {O_RGBLED0[1]}]
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set_property PACKAGE_PIN e1 [get_ports {O_RGBLED0[2]}]
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set_property PACKAGE_PIN g3 [get_ports {O_RGBLED1[0]}]
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set_property PACKAGE_PIN j4 [get_ports {O_RGBLED1[1]}]
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set_property PACKAGE_PIN g4 [get_ports {O_RGBLED1[2]}]
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set_property PACKAGE_PIN j3 [get_ports {O_RGBLED2[0]}]
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set_property PACKAGE_PIN j2 [get_ports {O_RGBLED2[1]}]
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set_property PACKAGE_PIN h4 [get_ports {O_RGBLED2[2]}]
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set_property PACKAGE_PIN k1 [get_ports {O_RGBLED3[0]}]
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set_property PACKAGE_PIN h6 [get_ports {O_RGBLED3[1]}]
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set_property PACKAGE_PIN k2 [get_ports {O_RGBLED3[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
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set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
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set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED2[*] O_RGBLED3[*]}]
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set_property DRIVE 12 [get_ports {O_RGBLED2[*] O_RGBLED3[*]}]
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set_property SLEW SLOW [get_ports {O_RGBLED2[*] O_RGBLED3[*]}]
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#
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# power measurements -- in bank 15 ------------------------------------------
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set_property PACKAGE_PIN c12 [get_ports {A_VPWRP[0]}]; # ad1p -> vaux(1)
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set_property PACKAGE_PIN b12 [get_ports {A_VPWRN[0]}]; # ad1n (VU volt)
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set_property PACKAGE_PIN b16 [get_ports {A_VPWRP[1]}]; # ad2p -> vaux(2)
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set_property PACKAGE_PIN b17 [get_ports {A_VPWRN[1]}]; # ad2n (5V0 volt)
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set_property PACKAGE_PIN f13 [get_ports {A_VPWRP[2]}]; # ad9p -> vaux(9)
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set_property PACKAGE_PIN f14 [get_ports {A_VPWRN[2]}]; # ad9n (5V0 curr)
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set_property PACKAGE_PIN a15 [get_ports {A_VPWRP[3]}]; # ad10p -> vaux(10)
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set_property PACKAGE_PIN a16 [get_ports {A_VPWRN[3]}]; # ad10n (0V95 curr)
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set_property IOSTANDARD LVCMOS33 [get_ports {A_VPWRP[*] A_VPWRN[*]}]
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