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48 lines
1.9 KiB
Markdown
48 lines
1.9 KiB
Markdown
The Artix-7 based designs contain now a module which makes the data of the
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FPGA system monitor, called XADC in 7Series and SYSMON otherwise, available
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on the rbus and therefore from `ti_rri`.
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To set this up in `ti_rri` or `ti_w11` use
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package require rbsysmon
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rbsysmon::setup_xadc_arty; # for arty
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rbsysmon::setup_xadc_base; # for b3,n4
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Two procedures allow to read and nicely print the XADC data
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rbsysmon::print
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--> gives on an Arty for example
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Value cur val min val max val low lim high lim alarm
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temp 34.3 d 30.8 36.0 60.0 85.0
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Vccint 0.948 V 0.944 0.953 0.920 0.980
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Vccaux 1.799 V 1.787 1.802 1.710 1.890
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Vccbram 0.948 V 0.944 0.954 0.920 0.980
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V 5V0 4.978 V
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V VU 0.088 V
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A 5V0 0.173 A
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A 0V95 0.087 A
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rbsysmon::print_raw
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--> produces a full list of all defined registers, like
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name description : hex other
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sm.temp cur temp : 9a50 30.6 deg
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sm.vint cur Vccint : 50ce 0.947 V
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sm.vaux cur Vccaux : 9962 1.797 V
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sm.vrefp cur Vrefp : 0000 0.000 V
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....
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sm.flag flag reg : 0000 0000000000000000
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sm.conf0 conf 0 : 9000 1001000000000000
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sm.conf1 conf 1 : 2ef0 0010111011110000
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sm.conf2 conf 2 : 0400 0000010000000000
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....
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For simulation proper setup files are included and activated by tbw to that
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one sees in simulation nominal readings for the power monitor values. To
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test this do for example
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cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb
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make
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ti_rri --fifo=,xon --run='tbw tb_tst_rlink_arty'
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.. commands above ...
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