mirror of
https://github.com/wfjm/w11.git
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e91847f8db
- added support for Nexys4 and Basys3 boards - added RL11 disk support - lots of documentation updated
157 lines
4.4 KiB
VHDL
157 lines
4.4 KiB
VHDL
-- $Id: byte2cdata.vhd 641 2015-02-01 22:12:15Z mueller $
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--
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-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: byte2cdata - syn
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-- Description: Byte stream to 9 bit comma,data converter
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2014-10-17 596 2.0 re-write, commas now 2 byte sequences
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-- 2011-11-19 427 1.0.2 now numeric_std clean
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-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
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-- 2007-08-27 76 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.comlib.all;
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entity byte2cdata is -- byte stream -> 9bit comma,data
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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DI : in slv8; -- input data
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ENA : in slbit; -- input data enable
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ERR : in slbit; -- input data error
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BUSY : out slbit; -- input data busy
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DO : out slv9; -- output data; bit 8 = comma flag
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VAL : out slbit; -- output data valid
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HOLD : in slbit -- output data hold
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);
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end byte2cdata;
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architecture syn of byte2cdata is
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type regs_type is record
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data : slv9; -- data
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dataval : slbit; -- data valid
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edpend : slbit; -- edata pending
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end record regs_type;
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constant regs_init : regs_type := (
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(others=>'0'), -- data
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'0','0' -- dataval,edpend
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);
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signal R_REGS : regs_type := regs_init; -- state registers
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signal N_REGS : regs_type := regs_init; -- next value state regs
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begin
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, DI, ENA, ERR, HOLD)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable idata : slv9 := (others=>'0');
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variable iesc : slbit := '0';
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variable ibusy : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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-- data path logic
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idata := '1' & "00000" & "100"; -- clobber
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iesc := '0';
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if r.edpend = '1' then
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if DI(c_cdata_edf_pref) = c_cdata_ed_pref and
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(not DI(c_cdata_edf_eci)) = DI(c_cdata_edf_ec) then
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case DI(c_cdata_edf_ec) is
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when c_cdata_ec_xon =>
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idata := '0' & c_cdata_xon;
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when c_cdata_ec_xoff =>
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idata := '0' & c_cdata_xoff;
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when c_cdata_ec_fill =>
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idata := '0' & c_cdata_fill;
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when c_cdata_ec_esc =>
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idata := '0' & c_cdata_escape;
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when others =>
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idata := '1' & "00000" & DI(c_cdata_edf_ec);
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end case;
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end if;
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else
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idata := '0' & DI;
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if DI = c_cdata_escape then
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iesc := '1';
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end if;
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end if;
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-- control path logic
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ibusy := '1';
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if HOLD = '0' then
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ibusy := '0';
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n.dataval := '0';
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n.data := idata;
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if ENA = '1' then
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if r.edpend = '0' then
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if iesc = '0' then
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n.dataval := '1';
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else
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n.edpend := '1';
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end if;
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else
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n.dataval := '1';
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n.edpend := '0';
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end if;
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elsif ERR = '1' then
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n.dataval := '1';
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end if;
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end if;
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N_REGS <= n;
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DO <= r.data;
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VAL <= r.dataval;
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BUSY <= ibusy;
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end process proc_next;
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end syn;
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