mirror of
https://github.com/wfjm/w11.git
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2b5cfb7d96
- xsim support complete (but many issues to be resolved yet) - Added configurable w11a cache - Removed some never documented and now strategically obsolete designs
298 lines
15 KiB
VHDL
298 lines
15 KiB
VHDL
-- $Id: serportlib.vhd 755 2016-03-28 17:59:59Z mueller $
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--
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-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: serportlib
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-- Description: serial port interface components
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--
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-- Dependencies: -
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-03-25 752 1.3.2 add serport_2clock2
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-- 2015-04-11 666 1.3.1 add serport_master
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-- 2015-02-01 641 1.3 add CLKDIV_F for autobaud
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-- 2013-01-26 476 1.2.6 renamed package to serportlib
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-- 2011-12-09 437 1.2.5 rename stat->moni port
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-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts
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-- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs
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-- 2011-10-14 416 1.2.2 add c_serport defs
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-- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab
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-- 2010-04-10 276 1.2 add clock divider constant defs
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-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned
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-- 2007-06-03 45 1.0 Initial version
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------------------------------------------------------------------------------
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-- Note: for test bench usage a copy of many serport_* entities, with -tb
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-- appended to the name, has been created in the /tb sub folder.
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-- Ensure to update the copy when this file is changed !!
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package serportlib is
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constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11
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constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13
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constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B
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component serport_uart_rxtx is -- serial port uart: rx+tx combo
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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RXSD : in slbit; -- receive serial data (uart view)
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXACT : out slbit; -- receiver active
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TXSD : out slbit; -- transmit serial data (uart view)
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit -- transmit busy
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);
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end component;
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component serport_uart_rx is -- serial port uart: receive part
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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RXSD : in slbit; -- receive serial data (uart view)
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXACT : out slbit -- receiver active
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);
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end component;
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component serport_uart_tx is -- serial port uart: transmit part
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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TXSD : out slbit; -- transmit serial data (uart view)
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit -- transmit busy
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);
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end component;
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component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT: natural := 15); -- clk divider initial/reset setting
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- 1 msec clock enable
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RESET : in slbit; -- reset
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RXSD : in slbit; -- receive serial data (uart view)
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXACT : out slbit; -- receiver active
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TXSD : out slbit; -- transmit serial data (uart view)
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit; -- transmit busy
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ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
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ABDONE : out slbit; -- autobaud resync done
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ABCLKDIV : out slv(CDWIDTH-1 downto 0); -- autobaud clock divider setting
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ABCLKDIV_F : out slv3 -- autobaud clock divider fraction
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);
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end component;
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component serport_uart_autobaud is -- serial port uart: autobauder
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT: natural := 15); -- clk divider initial/reset setting
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- 1 msec clock enable
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RESET : in slbit; -- reset
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RXSD : in slbit; -- receive serial data (uart view)
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CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
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CLKDIV_F: out slv3; -- clock divider fractional part
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ACT : out slbit; -- active; if 1 clkdiv is invalid
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DONE : out slbit -- resync done
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);
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end component;
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component serport_xonrx is -- serial port: xon/xoff logic rx path
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAESC : in slbit; -- enable xon/xoff escaping
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UART_RXDATA : in slv8; -- uart data out
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UART_RXVAL : in slbit; -- uart data valid
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RXDATA : out slv8; -- user data out
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RXVAL : out slbit; -- user data valid
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RXHOLD : in slbit; -- user data hold
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RXOVR : out slbit; -- user data overrun
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TXOK : out slbit -- tx channel ok
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);
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end component;
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component serport_xontx is -- serial port: xon/xoff logic tx path
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAESC : in slbit; -- enable xon/xoff escaping
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UART_TXDATA : out slv8; -- uart data in
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UART_TXENA : out slbit; -- uart data enable
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UART_TXBUSY : in slbit; -- uart data busy
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TXDATA : in slv8; -- user data in
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TXENA : in slbit; -- user data enable
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TXBUSY : out slbit; -- user data busy
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RXOK : in slbit; -- rx channel ok
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TXOK : in slbit -- tx channel ok
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);
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end component;
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type serport_moni_type is record -- serport monitor port
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rxerr : slbit; -- receiver data error (frame error)
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rxovr : slbit; -- receiver data overrun
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rxact : slbit; -- receiver active
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txact : slbit; -- transceiver active
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abact : slbit; -- autobauder active;if 1 clkdiv invalid
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abdone : slbit; -- autobauder resync done
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abclkdiv : slv16; -- autobauder clock divider
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abclkdiv_f : slv3; -- autobauder clock divider fraction
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rxok : slbit; -- rx channel ok
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txok : slbit; -- tx channel ok
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end record serport_moni_type;
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constant serport_moni_init : serport_moni_type := (
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'0','0', -- rxerr,rxovr
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'0','0', -- rxact,txact
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'0','0', -- abact,abdone
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(others=>'0'), -- abclkdiv
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(others=>'0'), -- abclkdiv_f
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'0','0' -- rxok,txok
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);
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component serport_1clock is -- serial port module, 1 clock domain
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15; -- clk divider initial/reset setting
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RXFAWIDTH : natural := 5; -- rx fifo address width
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TXFAWIDTH : natural := 5); -- tx fifo address width
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port (
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CLK : in slbit; -- clock
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CE_MSEC : in slbit; -- 1 msec clock enable
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RESET : in slbit; -- reset
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ENAXON : in slbit; -- enable xon/xoff handling
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ENAESC : in slbit; -- enable xon/xoff escaping
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXHOLD : in slbit; -- receiver data hold
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit; -- transmit busy
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MONI : out serport_moni_type; -- serport monitor port
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RXSD : in slbit; -- receive serial data (uart view)
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TXSD : out slbit; -- transmit serial data (uart view)
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RXRTS_N : out slbit; -- receive rts (uart view, act.low)
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TXCTS_N : in slbit -- transmit cts (uart view, act.low)
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);
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end component;
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component serport_2clock is -- serial port module, 2 clock domain
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15; -- clk divider initial/reset setting
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RXFAWIDTH : natural := 5; -- rx fifo address width
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TXFAWIDTH : natural := 5); -- tx fifo address width
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port (
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CLKU : in slbit; -- clock (backend:user)
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RESET : in slbit; -- reset
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CLKS : in slbit; -- clock (frontend:serial)
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CES_MSEC : in slbit; -- S|1 msec clock enable
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ENAXON : in slbit; -- U|enable xon/xoff handling
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ENAESC : in slbit; -- U|enable xon/xoff escaping
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RXDATA : out slv8; -- U|receiver data out
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RXVAL : out slbit; -- U|receiver data valid
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RXHOLD : in slbit; -- U|receiver data hold
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TXDATA : in slv8; -- U|transmit data in
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TXENA : in slbit; -- U|transmit data enable
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TXBUSY : out slbit; -- U|transmit busy
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MONI : out serport_moni_type; -- U|serport monitor port
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RXSD : in slbit; -- S|receive serial data (uart view)
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TXSD : out slbit; -- S|transmit serial data (uart view)
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RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
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TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
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);
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end component;
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component serport_2clock2 is -- serial port module, 2 clock dom. (v2)
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generic (
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CDWIDTH : positive := 13; -- clk divider width
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CDINIT : natural := 15; -- clk divider initial/reset setting
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RXFAWIDTH : natural := 5; -- rx fifo address width
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TXFAWIDTH : natural := 5); -- tx fifo address width
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port (
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CLKU : in slbit; -- U|clock (backend:user)
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RESET : in slbit; -- U|reset
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CLKS : in slbit; -- S|clock (frontend:serial)
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CES_MSEC : in slbit; -- S|1 msec clock enable
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ENAXON : in slbit; -- U|enable xon/xoff handling
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ENAESC : in slbit; -- U|enable xon/xoff escaping
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RXDATA : out slv8; -- U|receiver data out
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RXVAL : out slbit; -- U|receiver data valid
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RXHOLD : in slbit; -- U|receiver data hold
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TXDATA : in slv8; -- U|transmit data in
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TXENA : in slbit; -- U|transmit data enable
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TXBUSY : out slbit; -- U|transmit busy
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MONI : out serport_moni_type; -- U|serport monitor port
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RXSD : in slbit; -- S|receive serial data (uart view)
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TXSD : out slbit; -- S|transmit serial data (uart view)
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RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
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TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
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);
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end component;
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component serport_master is -- serial port module, master side
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generic (
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CDWIDTH : positive := 13); -- clk divider width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
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ENAXON : in slbit := '0'; -- enable xon/xoff handling
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ENAESC : in slbit := '0'; -- enable xon/xoff escaping
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RXDATA : out slv8; -- receiver data out
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RXVAL : out slbit; -- receiver data valid
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RXERR : out slbit; -- receiver data error (frame error)
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RXOK : in slbit := '1'; -- rx channel ok
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TXDATA : in slv8; -- transmit data in
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TXENA : in slbit; -- transmit data enable
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TXBUSY : out slbit; -- transmit busy
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RXSD : in slbit; -- receive serial data (uart view)
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TXSD : out slbit; -- transmit serial data (uart view)
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RXRTS_N : out slbit; -- receive rts (uart view, act.low)
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TXCTS_N : in slbit :='0' -- transmit cts (uart view, act.low)
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);
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end component;
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end package serportlib;
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