mirror of
https://github.com/wfjm/w11.git
synced 2026-04-19 10:19:40 +00:00
ef5c6b1ee3
- rtl/w11a
- pdp11.vhd: dm_stat_se_type: rename vfetch -> vstart;
mmu_moni_type: drop pc,idone, add vstart,vflow
pdp11_mmu_mmr12: add VADDR port
- pdp11_dmcmon.vhd: dm_stat_se_type: rename vfetch -> vstart
- pdp11_mmu.vhd: implement MMR0 instruction complete
- pdp11_mmu_mmr12.vhd: implement MMR2 instruction complete
- pdp11_sequencer.vhd: implement MMR0,MMR2 instruction complete
- pdp11_sys70.vhd: dm_stat_se_type: rename vfetch -> vstart
- tools
- tbench/w11a_pcnt/test_pcnt_basics.tcl: rename vfetch -> vstart
- tbench/w11a_pcnt/test_pcnt_codes.tcl: rename vfetch -> vstart
- tcl/rw11/dmcmon.tcl: rename vfetch -> vstart
- tcl/rw11/dmpcnt.tcl: rename vfetch -> vstart
- tcode/cpu_mmu.mac: rename C2.7 -> C2.10, add C2.7-9
- xxdp/ekbee1_patch_w11a.tcl: now patch for MMR1, not longer skip
1.2 KiB
1.2 KiB
Known differences between w11a and KB11-C (11/70)
MMR0 instruction complete implementation differences
The 11/70 and 11/45 are the only PDP-11 processors that also support the
recovery of an MMU abort of a stack push during trap or interrupt processing.
To distinguish between an instruction and a trap processing abort, the
MMR0 has a bit called instruction completed. It is set to 0
when an instruction is aborted and to 1 when a vector service flow is
aborted. The MMR2 contains the vector address in the latter case.
w11 supports this feature, but has two implementation differences:
- the
instruction completedflag is set andMMR2is loaded with the vector address for all vector flows. The 11/70 does this only for traps, aborts and interrupts, but not for trap instructions (BPT,IOT,TRAP,EMT). - the w11 decrements the
SPbefore each vector push, while the 11/70 decrements theSPtwice before the 1st vector push. Therefore, after an MMU abort of the 1st vector push,MMR1has000336on the w11 and173366on the 11/70.ekbee1test 067 checks thisMMR1response and has been modified (see patch).