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pdp11_sequencer: implement MMR0,MMR2 instruction complete

Browse Source 
- rtl/w11a
  - pdp11.vhd: dm_stat_se_type: rename vfetch -> vstart;
               mmu_moni_type: drop pc,idone, add vstart,vflow
               pdp11_mmu_mmr12: add VADDR port
  - pdp11_dmcmon.vhd: dm_stat_se_type: rename vfetch -> vstart
  - pdp11_mmu.vhd: implement MMR0 instruction complete
  - pdp11_mmu_mmr12.vhd: implement MMR2 instruction complete
  - pdp11_sequencer.vhd: implement MMR0,MMR2 instruction complete
  - pdp11_sys70.vhd: dm_stat_se_type: rename vfetch -> vstart
- tools
  - tbench/w11a_pcnt/test_pcnt_basics.tcl: rename vfetch -> vstart
  - tbench/w11a_pcnt/test_pcnt_codes.tcl: rename vfetch -> vstart
  - tcl/rw11/dmcmon.tcl: rename vfetch -> vstart
  - tcl/rw11/dmpcnt.tcl: rename vfetch -> vstart
  - tcode/cpu_mmu.mac: rename C2.7 -> C2.10, add C2.7-9
  - xxdp/ekbee1_patch_w11a.tcl: now patch for MMR1, not longer skip
This commit is contained in:
wfjm
2022-12-16 19:18:50 +01:00
parent 2407e662a9
commit ef5c6b1ee3
17 changed files with 320 additions and 125 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
doc/CHANGELOG.md
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@@ -46,14 +46,17 @@ The full set of tests is only run for tagged releases.
- pdp11.vhd: rename, eg srv->ser; cpustat_type: drop trap_done, add in_vecysv,
treq_tbit,resetcnt; decode_stat_type: op_rti instead of op_rtt
- pdp11_decode.vhd: use op_rti instead of op_rtt
- pdp11_sequencer.vhd:
- tbit logic overhaul; use treq_tbit; cleanups; use resetcnt for 8 cycle
RESET wait, see [ECO-035](ECO-035-stklim-tbit-fixes.md)
- implement MMR0,MMR2 instruction complete,
see [ECO-037](ECO-037-mmu-instruction_complete.md)
- pdp11_vmbox.vhd: rename some rsv->ser; remove obsolete trap_done
- pdp11_sequencer.vhd: tbit logic overhaul; use treq_tbit; cleanups;
use resetcnt for 8 cycle RESET wait see
[ECO-035](ECO-035-stklim-tbit-fixes.md)
- rtl/sys_gen/w11a/s3board/sys_conf.vhd: disable monitors for timing closure
- rtl/sys_gen/w11a/\*/\*.vmfset: drop removed signals
- general changes
- rename _gpr to _gr, use 'general registers' not 'general purpose registers'
- rename vfetch -> vstart
### Bug Fixes
- rtl/w11a
- pdp11_sequencer:

47
doc/ECO-037-mmu-instruction_complete.md Normal file
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@@ -0,0 +1,47 @@
# ECO-037: implement MMR0,MMR2 instruction complete (2022-12-16)
### Scope
- was in w11a since 2008
- affects: all w11a systems
### Symptom summary
Test 067 of `ekbee1` ends in an infinite loop.
### Analysis
The 11/70 supports the recovery of MMU aborts in the push phase of a vector
flow. The documentation of this feature is scarce and in some places
misleading or just plain wrong. What is actually done is quite simple:
- an MMU abort during a push to a non-kernel stack during a vector flow
sets bit `MMR0(7)` to '1' and `MMR2` to the vector address.
- a vector push abort to the kernel stack is converted into a fatal stack error.
- all other MMU aborts set `MMR0(7)` to '0' and `MMR2` to the address of the
aborted instruction.
The bit `MMR0(7)` is named `instruction complete` in the DEC documentation.
That's technically correct but highly misleading.
A much better name would have been `vector push abort`, because that's what
this flag signifies.
The 11/70 sets `MMR0(7)` only for aborts, traps and interrupt flows, but not
in vector flows started via the trap instructions `BPT`, `IOT`, `EMT` and
`TRAP`.
### Changes
To simplify things, the w11 handles all vector flows uniformly, trap
instructions have no special treatment as in the 11/70. With this,
the implementation of the `instruction complete` feature is quite simple.
The `MMR0(7)` bit is loaded in each cycle from the `cpu_status` state flag
`in_vecfow` if the `MMR0` abort status bits are not locked. This ensures that
the bit is '1' after a vector push abort and '0' in all other cases.
The `MMR2` register is loaded from the virtual address
- at the beginning of vector flow in state `s_vec_getpc` (VA = vector address)
- at the beginning of an instruction fetch (VA = instruction address)
### Hindsight
This is the most mysterious feature of an 11/70. It was only exercised in one
xxdp test and never used. Because of poor documentation, it took a long time to
understand what it really does and what it can be used for. Nevertheless,
the goal of the w11 is to be an as precise as feasible replica of the 11/70,
and it was time to finally implement this esoteric feature.

4
doc/simh_diff_instruction_complete.md
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@@ -20,5 +20,5 @@ SimH does not support the `MMR0` `instruction completed` flag and the
associated `MMR2` behavior.
xxdp `ekbee1` test 67 verifies this behavior and is skipped.
w11 also doesn't support this behavior currently, this is documented as
[w11 known difference](w11a_diff_70_instruction_complete.md).
w11 supports `instruction completed` with some minor implementation differences,
see [w11 known difference](w11a_diff_70_instruction_complete.md).

32
doc/w11a_diff_70_instruction_complete.md
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@@ -1,24 +1,22 @@
## Known differences between w11a and KB11-C (11/70)
### The 'instruction completed flag' in `MMR0` is not implemented
All PDP-11 processors with a fully functional MMU (11/45, 11/70, 11/44, and J11)
support the re-execution of an instruction after an MMU abort.
`MMR2` holds the virtual address of aborted instruction and `MMR1` holds
information about register changes. This can be used by a handler to roll back
the register changes and restart the instruction. This can be used to
implement demand paging or dynamic extension of stack segments.
### `MMR0` instruction complete implementation differences
The 11/70 and 11/45 are the only PDP-11 processors that also support the
recovery of an MMU abort of a stack push during trap or interrupt processing.
To distinguish between an instruction and a trap processing abort the
`MMR1` has a bit called `instruction completed`. It is will be set to 0
whenever an instruction is aborted and is 1 after a trap service flow is
To distinguish between an instruction and a trap processing abort, the
`MMR0` has a bit called `instruction completed`. It is set to 0
when an instruction is aborted and to 1 when a vector service flow is
aborted. The `MMR2` contains the vector address in the latter case.
Only the 11/70 and the 11/45 support this. No OS uses this.
And it's very difficult to construct a practical use case.
The w11a doesn't support the 'instruction completed' bit in `MMR1`. It is
always 0. And `MMR2` holds always the virtual address of the last instruction.
w11 supports this feature, but has two implementation differences:
- the `instruction completed` flag is set and `MMR2` is loaded with the vector
address for _all_ vector flows. The 11/70 does this only for traps,
aborts and interrupts, but not for trap instructions (`BPT`, `IOT`,
`TRAP`, `EMT`).
- the w11 decrements the `SP` before each vector push, while the 11/70
decrements the `SP` twice before the 1st vector push. Therefore, after an
MMU abort of the 1st vector push, `MMR1` has `000336` on the w11 and `173366`
on the 11/70.
`ekbee1` test 067 checks this `MMR1` response and has been modified
(see [patch](../tools/xxdp/ekbee1_patch_w11a.tcl)).

4
doc/w11a_known_differences.md
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@@ -6,11 +6,11 @@ The issues of the w11 CPU and systems are listed in a separate document
### Known differences between w11a and KB11-C (11/70)
- [Instruction fetch after `SPL`](w11a_diff_70_spl_bug.md)
- [Stack limit checks done independent of register set](w11a_diff_70_stklim_rset.md)
- ['instruction completed flag' in `MMR0` is not implemented](w11a_diff_70_instruction_complete.md)
- [`CLR` and `SXT` do a write](w11a_diff_70_clr_sxt_write.md)
- [`jsr sp` pushes original `sp` value](w11a_diff_70_jsr_sp.md)
- [Stack limit checks done independent of register set](w11a_diff_70_stklim_rset.md)
- [18-bit UNIBUS address space not mapped](w11a_diff_70_unibus_mapping.md)
- [`MMR0` instruction complete implementation differences](w11a_diff_70_instruction_complete.md)
- [MMU traps not suppressed when MMU register accessed](w11a_diff_70_mmu_trap_suppression.md)
- [MMU aborts have priority over NXM aborts](w11a_diff_70_mmu_nxm_prio.md)
- [`MMR0` abort flags are set when stack limit abort done](w11a_diff_70_mmu_stklim_prio.md)

16
rtl/w11a/pdp11.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11.vhd 1329 2022-12-11 17:28:28Z mueller $
-- $Id: pdp11.vhd 1330 2022-12-16 17:52:40Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -11,6 +11,9 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-12 1330 1.5.21 dm_stat_se_type: rename vfetch -> vstart;
-- mmu_moni_type: drop pc,idone, add vstart,vflow
-- pdp11_mmu_mmr12: add VADDR port
-- 2022-12-10 1329 1.5.20 add cpustat_type in_vecflow
-- 2022-12-05 1324 1.5.19 add cpustat_type treq_tbit and resetcnt;
-- use op_rti rather op_rtt;
@@ -504,8 +507,8 @@ package pdp11 is
type mmu_moni_type is record -- mmu monitor port
istart : slbit; -- instruction start
idone : slbit; -- instruction done
pc : slv16; -- PC of new instruction
vstart : slbit; -- vector start
vflow : slbit; -- in vector flow
regmod : slbit; -- register modified
regnum : slv3; -- register number
delta : slv4; -- register offset
@@ -514,7 +517,7 @@ package pdp11 is
end record mmu_moni_type;
constant mmu_moni_init : mmu_moni_type := (
'0','0',(others=>'0'), -- istart, idone, pc
'0','0','0', -- istart, vstart, vflow
'0',"000","0000", -- regmod, regnum, delta
'0','0' -- isdec, trace_prev
);
@@ -631,14 +634,14 @@ package pdp11 is
idone : slbit; -- instruction done
itimer : slbit; -- instruction timer (for ibdr_rhrp)
pcload : slbit; -- PC loaded (flow change)
vfetch : slbit; -- vector fetch
vstart : slbit; -- vector start
snum : slv8; -- current state number
end record dm_stat_se_type;
constant dm_stat_se_init : dm_stat_se_type := (
'0','0', -- idle,cpbusy
'0','0','0','0', -- istart,idec,idone,itimer
'0','0', -- pcload,vfetch
'0','0', -- pcload,vstart
(others=>'0') -- snum
);
@@ -967,6 +970,7 @@ component pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2
CRESET : in slbit; -- cpu reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
VADDR : in slv16; -- virtual address
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);

17
rtl/w11a/pdp11_dmcmon.vhd
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@@ -1,4 +1,4 @@
-- $Id: pdp11_dmcmon.vhd 1310 2022-10-27 16:15:50Z mueller $
-- $Id: pdp11_dmcmon.vhd 1330 2022-12-16 17:52:40Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,6 +19,7 @@
--
-- Revision History: -
-- Date Rev Version Comment
-- 2022-12-12 1330 2.0.3 dm_stat_se_type: rename vfetch -> vstart
-- 2022-10-25 1309 2.0.2 rename _gpr -> _gr
-- 2019-06-02 1159 2.0.1 use rbaddr_ constants
-- 2017-04-22 884 2.0 use DM_STAT_SE.idle; revised interface, add suspend
@@ -103,7 +104,7 @@
-- if imode = 1
-- 10 : -- unused --
-- 09 : -- unused --
-- 08 : se.vfetch
-- 08 : se.vstart
-- always
-- 07:05 : dp.psw.pri
-- 04 : dp.psw.tflag
@@ -226,7 +227,7 @@ architecture syn of pdp11_dmcmon is
constant dat5_rbf_ddst_we : integer := 9;
constant dat5_rbf_dsrc_we : integer := 8;
constant dat5_rbf_vfetch : integer := 8; -- if imode=1
constant dat5_rbf_vstart : integer := 8; -- if imode=1
subtype dat5_rbf_pri is integer range 7 downto 5;
constant dat5_rbf_tflag : integer := 4;
@@ -293,7 +294,7 @@ architecture syn of pdp11_dmcmon is
se_istart : slbit; -- se.istart
se_istart_1 : slbit; -- se.istart last cycle
se_idone : slbit; -- se.idone
se_vfetch : slbit; -- se.vfetch
se_vstart : slbit; -- se.vstart
se_snum : slv8; -- se.snum
mwdrop : slbit; -- mem wait drop flag
end record regs_type;
@@ -325,7 +326,7 @@ architecture syn of pdp11_dmcmon is
'0','0', -- vm_trap_*
'0', -- vm_pend
'0','0','0', -- se_idle,se_istart(_1)
'0','0', -- se_idone,se_vfetch
'0','0', -- se_idone,se_vstart
(others=>'0'), -- se_snum
'0' -- mwdrop
);
@@ -672,7 +673,7 @@ architecture syn of pdp11_dmcmon is
n.se_idle := DM_STAT_SE.idle;
n.se_istart := DM_STAT_SE.istart;
n.se_idone := DM_STAT_SE.idone;
n.se_vfetch := DM_STAT_SE.vfetch;
n.se_vstart := DM_STAT_SE.vstart;
n.se_snum := DM_STAT_SE.snum;
-- active state logic
@@ -715,7 +716,7 @@ architecture syn of pdp11_dmcmon is
end if;
end if;
else -- imode=1
itake := r.se_idone or r.se_vfetch or r.vm_err;
itake := r.se_idone or r.se_vstart or r.vm_err;
end if;
if iactive='1' and itake='1' then -- active and enabled
@@ -818,7 +819,7 @@ architecture syn of pdp11_dmcmon is
idat5(dat5_rbf_ddst_we) := R_REGS.dp_ddst_we;
idat5(dat5_rbf_dsrc_we) := R_REGS.dp_dsrc_we;
else
idat5(dat5_rbf_vfetch) := R_REGS.se_vfetch;
idat5(dat5_rbf_vstart) := R_REGS.se_vstart;
end if;
idat5(dat5_rbf_pri) := DM_STAT_DP.psw.pri;
idat5(dat5_rbf_tflag) := DM_STAT_DP.psw.tflag;

18
rtl/w11a/pdp11_mmu.vhd
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@@ -1,4 +1,4 @@
-- $Id: pdp11_mmu.vhd 1323 2022-12-01 08:00:41Z mueller $
-- $Id: pdp11_mmu.vhd 1330 2022-12-16 17:52:40Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -17,6 +17,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-12 1330 1.4.6 implement MMR0 instruction complete
-- 2022-11-29 1323 1.4.5 rename mmu_mmr0_type dspace->page_dspace
-- 2022-09-05 1294 1.4.4 BUGFIX: correct trap and PDR A logic
-- 2022-08-13 1279 1.4.3 ssr->mmr rename
@@ -129,6 +130,7 @@ begin
CRESET => CRESET,
TRACE => TRACE,
MONI => MONI,
VADDR => VADDR,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMR12);
@@ -364,14 +366,10 @@ begin
elsif nmmr0.ena_mmu='1' and CNTL.cacc='0' then
if dotrace = '1' then
if MONI.istart = '1' then
nmmr0.inst_compl := '0';
elsif MONI.idone = '1' then
nmmr0.inst_compl := '0'; -- disable instr.compl logic
end if;
if mmr_freeze = '0' then
nmmr0.inst_compl := MONI.vflow;
end if;
if CNTL.req = '1' then
AIB_WE <= '1';
if mmr_freeze = '0' then
@@ -391,8 +389,8 @@ begin
nmmr0.page_num := apf;
nmmr0.page_mode := CNTL.mode;
end if;
end if;
end if;
end if; -- CNTL.req = '1'
end if; -- nmmr0.ena_mmu='1' and CNTL.cacc='0'
if CNTL.req='1' and R_MMR0.ena_mmu='1' and CNTL.cacc='0' and
dotrap='1' then

10
rtl/w11a/pdp11_mmu_mmr12.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11_mmu_mmr12.vhd 1291 2022-09-03 07:00:27Z mueller $
-- $Id: pdp11_mmu_mmr12.vhd 1330 2022-12-16 17:52:40Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -13,6 +13,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-12 1330 1.2.5 implement MMR2 instruction complete
-- 2022-08-30 1291 1.2.4 use ra_delta to steer mmr1 updates
-- 2022-08-13 1279 1.2.3 ssr->mmr rename
-- 2011-11-18 427 1.2.2 now numeric_std clean
@@ -43,6 +44,7 @@ entity pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2
CRESET : in slbit; -- cpu reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
VADDR : in slv16; -- virtual address
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
@@ -118,7 +120,7 @@ begin
end process proc_regs;
proc_comb : process (CRESET, IBSEL_MMR1, IB_MREQ,
R_MMR1, R_MMR2, TRACE, MONI)
R_MMR1, R_MMR2, TRACE, MONI, VADDR)
variable nmmr1 : mmu_mmr1_type := mmu_mmr1_init;
variable nmmr2 : slv16 := (others=>'0');
@@ -147,9 +149,9 @@ begin
elsif TRACE = '1' then
if MONI.istart = '1' then
if MONI.istart='1' or MONI.vstart='1' then
nmmr1 := mmu_mmr1_init;
nmmr2 := MONI.pc;
nmmr2 := VADDR;
elsif MONI.regmod = '1' then
if R_MMR1.ra_delta = "00000" then

23
rtl/w11a/pdp11_sequencer.vhd
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@@ -1,4 +1,4 @@
-- $Id: pdp11_sequencer.vhd 1329 2022-12-11 17:28:28Z mueller $
-- $Id: pdp11_sequencer.vhd 1330 2022-12-16 17:52:40Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -13,6 +13,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-12 1330 1.6.25 implement MMR0,MMR2 instruction complete
-- 2022-12-10 1329 1.6.24 BUGFIX: get correct PS after vector push abort
-- 2022-12-05 1324 1.6.23 tbit logic overhaul; use treq_tbit; cleanups
-- use resetcnt for 8 cycle RESET wait
@@ -382,7 +383,6 @@ begin
variable idm_idec : slbit := '0'; -- idec for dm_stat_se
variable idm_idone : slbit := '0'; -- idone for dm_stat_se
variable idm_pcload : slbit := '0'; -- pcload for dm_stat_se
variable idm_vfetch : slbit := '0'; -- vfetch for dm_stat_se
alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
alias SRCDEF : slbit is IREG(9); -- src register mode defered
@@ -541,7 +541,7 @@ begin
pnstatus : inout cpustat_type;
pnmmumoni : inout mmu_moni_type) is
begin
pnmmumoni.idone := '1'; -- priority order
-- priority order
if pnstatus.treq_mmu='1' or -- mmu trap
pnstatus.treq_ysv='1' then -- ysv trap
pnstate := s_trap_disp;
@@ -566,7 +566,7 @@ begin
begin
pndpcntl := pndpcntl; -- dummy to add driver (vivado)
pnvmcntl := pnvmcntl; -- "
pnmmumoni.idone := '1'; -- priority order
-- priority order
if pnstatus.treq_mmu='1' or -- mmu trap
pnstatus.treq_ysv='1' then -- ysv trap
pnstate := s_trap_disp;
@@ -640,12 +640,11 @@ begin
idm_idec := '0';
idm_idone := '0';
idm_pcload := '0';
idm_vfetch := '0';
imemok := false;
nmmumoni := mmu_moni_init;
nmmumoni.pc := PC;
nmmumoni.vflow := R_STATUS.in_vecflow;
macc := '0';
bytop := '0';
@@ -1604,7 +1603,6 @@ begin
when s_op_halt => -- HALT -------------------------------
idm_idone := '1'; -- instruction done
if is_kmode = '1' then -- if in kernel mode execute
nmmumoni.idone := '1';
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_halt;
nstate := s_idle;
@@ -2219,7 +2217,7 @@ begin
-- vector flow states ------------------------------------------------------
when s_vec_getpc => -- -----------------------------------
idm_vfetch := '1'; -- signal vfetch
nmmumoni.vstart := '1'; -- signal vstart
nstatus.in_vecflow := '1'; -- signal vector flow
nstatus.treq_tbit := '0'; -- cancel pending tbit request
nvmcntl.mode := c_psw_kmode; -- fetch PC from kernel D space
@@ -2274,6 +2272,8 @@ begin
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP too
nmmumoni.regmod := '1'; -- record vector push in MMR1
nmmumoni.isdec := '1';
nstate := s_vec_pushps;
when s_vec_pushps => -- -----------------------------------
@@ -2301,6 +2301,8 @@ begin
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_we := '1'; -- update SP too
nmmumoni.regmod := '1'; -- record vector push in MMR1
nmmumoni.isdec := '1';
nstate := s_vec_pushpc;
end if;
@@ -2493,8 +2495,8 @@ begin
DM_STAT_SE.idone <= idm_idone;
DM_STAT_SE.itimer <= R_STATUS.itimer;
DM_STAT_SE.pcload <= idm_pcload;
DM_STAT_SE.vfetch <= idm_vfetch;
DM_STAT_SE.vstart <= nmmumoni.vstart;
end process proc_next;
proc_cpstat : process (R_STATUS)
@@ -2828,4 +2830,3 @@ begin
end generate SNUM0;
end syn;

9
rtl/w11a/pdp11_sys70.vhd
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@@ -1,6 +1,6 @@
-- $Id: pdp11_sys70.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: pdp11_sys70.vhd 1330 2022-12-16 17:52:40Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sys70 - syn
@@ -23,10 +23,11 @@
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.33-0.35
-- Tool versions: ise 14.7; viv 2014.4-2022.1; ghdl 0.33-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-12 1330 1.3.4 dm_stat_se_type: rename vfetch -> vstart
-- 2019-06-02 1159 1.3.3 use rbaddr_ constants
-- 2019-03-02 1116 1.3.2 add RESET_SYS; fix pdp11_mem70 reset
-- 2019-02-16 1112 1.3.1 add ibd_ibtst
@@ -344,7 +345,7 @@ begin
isig(6) := DM_STAT_SE.idec; -- cpu_idec
isig(7) := DM_STAT_SE.pcload; -- cpu_pcload
isig(8) := DM_STAT_SE.vfetch; -- cpu_vfetch
isig(8) := DM_STAT_SE.vstart; -- cpu_vstart
isig(9) := EI_ACKM_L; -- cpu_irupt (not counting PIRQ!)
isig(10) := DM_STAT_CA.rd; -- ca_rd

7
tools/tbench/w11a_pcnt/test_pcnt_basics.tcl
View File

@@ -1,9 +1,10 @@
# $Id: test_pcnt_basics.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_pcnt_basics.tcl 1330 2022-12-16 17:52:40Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-12-12 1330 1.0.1 rename vfetch -> vstart
# 2018-10-06 1053 1.0 Initial version
# 2018-09-23 1050 0.1 First draft
#
@@ -53,7 +54,7 @@ $cpu cp \
# 5 =0 cpu_um
# 6 67 cpu_inst
# 7 31 cpu_pcload
# 8 =0 cpu_vfetch
# 8 =0 cpu_vstart
# 9 =0 cpu_irupt
rlc log " A2: test random access (ainc=0) --------------------"
# read pc(6) twice, (9) once, (7) one, check status

21
tools/tbench/w11a_pcnt/test_pcnt_codes.tcl
View File

@@ -1,9 +1,10 @@
# $Id: test_pcnt_codes.tcl 1273 2022-08-07 18:40:56Z mueller $
# $Id: test_pcnt_codes.tcl 1330 2022-12-16 17:52:40Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-12-12 1330 1.0.2 rename vfetch -> vstart
# 2022-08-07 1273 1.0.1 ssr->mmr rename
# 2018-10-13 1055 1.0 Initial version
# 2018-10-06 1053 0.1 First draft
@@ -179,7 +180,7 @@ tmpproc_dotest $cpu $code \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 34 \
cpu_vfetch 0 \
cpu_vstart 0 \
cpu_irupt 0 \
cpu_pcload 31 \
ca_rd 35 \
@@ -211,7 +212,7 @@ tmpproc_dotest $cpu $code \
cpu_um 0 \
cpu_idec 67 \
cpu_pcload 31 \
cpu_vfetch 0 \
cpu_vstart 0 \
cpu_irupt 0 \
ca_rd 68 \
ca_wr 0 \
@@ -243,7 +244,7 @@ tmpproc_dotest $cpu $code \
cpu_um 0 \
cpu_idec 67 \
cpu_pcload 31 \
cpu_vfetch 0 \
cpu_vstart 0 \
cpu_irupt 0 \
ca_rd 133 \
ca_wr 33 \
@@ -278,7 +279,7 @@ tmpproc_dotest $cpu $code \
cpu_um 0 \
cpu_idec 99 \
cpu_pcload 31 \
cpu_vfetch 0 \
cpu_vstart 0 \
cpu_irupt 0 \
ca_rd 133 \
ca_wr 0 \
@@ -314,7 +315,7 @@ tmpproc_dotest $cpu $code \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 7 \
cpu_vfetch 0 \
cpu_vstart 0 \
cpu_irupt 0 \
cpu_pcload 0 \
ca_rd 11 \
@@ -346,7 +347,7 @@ tmpproc_dotest $cpu $code \
cpu_sm -4 \
cpu_um 0 \
cpu_idec 7 \
cpu_vfetch 0 \
cpu_vstart 0 \
cpu_irupt 0 \
cpu_pcload 0 \
ca_rd 11 \
@@ -378,7 +379,7 @@ tmpproc_dotest $cpu $code \
cpu_sm 0 \
cpu_um -4 \
cpu_idec 7 \
cpu_vfetch 0 \
cpu_vstart 0 \
cpu_irupt 0 \
cpu_pcload 0 \
ca_rd 11 \
@@ -423,7 +424,7 @@ tmpproc_dotest $cpu $code \
cpu_sm 0 \
cpu_um 0 \
cpu_idec 14 \
cpu_vfetch 4 \
cpu_vstart 4 \
cpu_irupt 0 \
cpu_pcload 8 \
ca_rd 34 \
@@ -480,5 +481,5 @@ tmpproc_dotest $cpu $code \
cpu_km_wait 0 \
cpu_sm 0 \
cpu_um 0 \
cpu_vfetch 3 \
cpu_vstart 3 \
cpu_irupt 3

13
tools/tcl/rw11/dmcmon.tcl
View File

@@ -1,9 +1,10 @@
# $Id: dmcmon.tcl 1177 2019-06-30 12:34:07Z mueller $
# $Id: dmcmon.tcl 1330 2022-12-16 17:52:40Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-12-12 1330 2.0.1 rename vfetch -> vstart
# 2017-04-23 885 2.0 revised interface, add suspend
# 2017-01-02 837 1.0.2 add procs cme,cml
# 2016-12-29 833 1.0.1 cm_print: protect against empty lists
@@ -39,7 +40,7 @@ namespace eval rw11 {
regdsc CM_D5 {cmode 15 2} {pmode 13 2} {rset 11} \
{pri 7 3 d} {tflag 4} {cc 3 4 "-"} {n 3} {z 2} {v 1} {c 0}
regdsc CM_D5IM0 {dres_val 10} {ddst_we 9} {dsrc_we 8}
regdsc CM_D5IM1 {vfetch 8}
regdsc CM_D5IM1 {vstart 8}
variable CM_D8_VMERR_ODD 01
variable CM_D8_VMERR_MMU 02
@@ -205,7 +206,7 @@ namespace eval rw11 {
reggetkv rw11::CM_D7 $d7 "d7_" pc idec
set d7_pc [expr {$d7_pc << 1}]
reggetkv rw11::CM_D5IM0 $d5 "d5_" dres_val ddst_we dsrc_we
reggetkv rw11::CM_D5IM1 $d5 "d5_" vfetch
reggetkv rw11::CM_D5IM1 $d5 "d5_" vstart
set p_iflag " "
if {$d8_istart} {set p_iflag "-"}
@@ -282,9 +283,9 @@ namespace eval rw11 {
append line " [cm_print_coct $d0 $p_new 0 $vmbytop]"
if {$imode} {
if {$d5_vfetch} {
if {$d5_vstart} {
set vnam [string toupper [rw11::dasm_vec2txt $d1]]
append line " !VFETCH [format %3.3o $d1] ${vnam}"
append line " !VSTART [format %3.3o $d1] ${vnam}"
} else {
# if vmerr and same pc,ireg as previous entry suppress dasm line
# that ensures that ifetch Eodd's will not give double dasm lines

7
tools/tcl/rw11/dmpcnt.tcl
View File

@@ -1,9 +1,10 @@
# $Id: dmpcnt.tcl 1177 2019-06-30 12:34:07Z mueller $
# $Id: dmpcnt.tcl 1330 2022-12-16 17:52:40Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-12-12 1330 1.1.2 rename vfetch -> vstart
# 2018-11-09 1066 1.1.1 pc_sta: fix default file name
# 2018-10-21 1058 1.1 add logger, pc_l* commands
# 2018-10-13 1055 1.0 Initial version
@@ -26,7 +27,7 @@ namespace eval rw11 {
# preliminary handling of counter names, hack in first version
variable pcnt_cnames [list cpu_cpbusy cpu_km_prix cpu_km_pri0 cpu_km_wait \
cpu_sm cpu_um cpu_idec cpu_pcload \
cpu_vfetch cpu_irupt ca_rd ca_wr \
cpu_vstart cpu_irupt ca_rd ca_wr \
ca_rdhit ca_wrhit ca_rdmem ca_wrmem \
ca_rdwait ca_wrwait ib_rd ib_wr \
ib_busy rb_rd rb_wr rb_busy \

197
tools/tcode/cpu_mmu.mac
View File

@@ -1,16 +1,16 @@
; $Id: cpu_mmu.mac 1329 2022-12-11 17:28:28Z mueller $
; $Id: cpu_mmu.mac 1330 2022-12-16 17:52:40Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2022-12-01 1324 1.0 Initial version
; 2022-12-16 1330 1.0 Initial version
; 2022-07-24 1262 0.1 First draft
;
; Test CPU MMU: all aspects of the MMU
; Section A: pdr,par registers
; Section B: mmr0,mmr3 registers, mapping, instructions
; Section C: mmr1+mmr0 register, aborts
; Section C: mmr2+mmr1+mmr0 register, aborts
; Section D: mmr2+mmr1+mmr0 register, abort recovery
; Section E: traps and pdr aia and aiw bits
; Section F: miscellaneous
@@ -20,8 +20,8 @@
; page 1 main code
; page 2
; page 3
; page 4 code mapped in user/super space; test E1.4 code
; page 5 code for test E1.4
; page 4 code mapped in user/super space; test E1.4 code (page 4->5 border)
; page 5 code for test E1.4 (page 4->5 border)
; page 6 data test target
; page 7 iopage
;
@@ -700,7 +700,7 @@ tb0402: tstb systyp ; skip if not on w11
;
9999$: iot
;
; Section C: mmr1+mmr0 register, aborts ======================================
; Section C: mmr2+mmr1+mmr0 register, aborts =================================
; C1 MMU response in mmr1 after a write to that fakes an abort
; C2 MMU abort response in mmr0 and mmr1
; C2.1 test unary/binary instructions
@@ -718,7 +718,10 @@ tb0402: tstb systyp ; skip if not on w11
; C2.4 mmu abort vs nxm abort
; C2.5 mmu abort in vector flow - kernel mode
; C2.6 mmu abort in vector flow - supervisor mode
; C2.7 mmu abort plus stack limit abort
; C2.7 mmu abort in 1st instruction after vector flow
; C2.8 mmu abort of prefetched instruction
; C2.9 mmu aborts and memory status
; C2.10 mmu abort plus stack limit abort
;
; Test C1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Verify MMU response in mmr1 after a write to that fakes an abort
@@ -1320,23 +1323,25 @@ tc0204: mov cp.los,kipar6 ; map begin of non-existent memory
;
; part1: MMU allows access to NXM memory --> NXM abort ---------------
;
clr cp.err ; clear CPUERR
mov #1000$,v..iit ; set vector 4 handler for NXM abort
1000$: clr cp.err ; clear CPUERR
mov #1100$,v..iit ; set vector 4 handler for NXM abort
clr @#p6p1p2 ; access
halt
1000$: mov #stack,sp ; vector 4 taken
1100$: mov #stack,sp ; vector 4 taken
hcmpeq cp.err,#cp.nxm ; NXM error seen
mov #v..iit+2,v..iit ; restore iit handler to catcher
;
; part2: MMU denies access to NXM memory --> MMU abort ---------------
;
mov #<127.*md.plf>!md.an7,kipdr6 ; deny access via acf=7
2000$: mov #<127.*md.plf>!md.an7,kipdr6 ; deny access via acf=7
clr cp.err ; clear CPUERR
mov #2000$,v..mmu ; set vector 250 handler for MMU abort
clr @#p6p1p2 ; access
mov #2100$,v..mmu ; set vector 250 handler for MMU abort
2010$: clr @#p6p1p2 ; access
halt
2000$: mov #stack,sp ; vector 250 taken
htsteq cp.err ; check CPUERR (no NXM expected)
2100$: mov #stack,sp ; vector 250 taken
htsteq cp.err ; check CPUERR: no NXM expected
hcmpeq #m0.anr!<6*m0.pno>!m0.ena,mmr0 ; check mmr0
hcmpeq #2010$,mmr2 ; check mmr2: failed instruction
mov #v..mmu+2,v..mmu ; restore mmu handler to catcher
;
reset ; mmu off ;! MMU off
@@ -1356,6 +1361,8 @@ tc0204: mov cp.los,kipar6 ; map begin of non-existent memory
; See also cpu_details test A3.5, checks vector push abort by stklim.
;
tc0205: mov #<127.*md.plf>,kipdr5 ; page 5 non-resident (afc=0)
mov #177777,p6base ; set signatures (will be overwritten)
mov #177777,p6base-2 ; set signatures (will stay)
mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
mov #200$,v..iit ; iit handler
mov #cp.pr1!cp000c,v..iit+2 ; use PR1+000C as signature iit
@@ -1389,8 +1396,12 @@ tc0205: mov #<127.*md.plf>,kipdr5 ; page 5 non-resident (afc=0)
hcmpeq (sp),#300$ ; PC: return after trap
hcmpeq 2(sp),#cp.pr5!cpnzvc ; PS: should be code signature
;
; restore
; check signatures, check that nothing written to page 5
reset ; mmu off ;! MMU off
hcmpeq #cp.pr4,p6base ; code signature of 1st push of TRAP
hcmpeq #177777,p6base-2 ; must be untouched
;
; restore
mov #<127.*md.plf>!md.arw,kipdr5 ; reset kipdr5
mov #v..iit+2,v..iit ; v..iit to catcher
clr v..iit+2
@@ -1411,6 +1422,7 @@ tc0205: mov #<127.*md.plf>,kipdr5 ; page 5 non-resident (afc=0)
; and a PIRQ handler in supervisor space.
; Verify that PS and PC at the beginning of the failed vector flow are saved.
; Test inspired by ekbee1 test 124.
; Verify also that MMR0,MMR2 instruction complete (unless on SimH)
;
tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1
mov kipar0,sipar0
@@ -1440,7 +1452,16 @@ tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1
hcmpeq (sp),#100$ ; PC: return after mov
hcmpeq 2(sp),#cp.cms!cp.pr1 ; PS: should be code signature
;
; check mmr0,mmr2 instruction complete (unless on SimH)
cmpb systyp,#sy.sih
beq 290$
hcmpeq #m0.anr!m0.ale!m0.ico!m0.pms!<5*m0.pno>!m0.ena,mmr0 ; check mmr0
hcmpeq #^b1111011011110110,mmr1 ; check mmr1: two SP decrements
hcmpeq #v..pir,mmr2 ; check mmr2: failed vector
290$:
;
; abort on 1st push ------------------------------
bic #m0.anr!m0.ale!m0.ard,mmr0 ; clear mmr0 abort flags
mov #400$,v..mmu ; mmu handler
mov #stack,sp ; set kernel SP
mov #cp.cms!cp.pr7,cp.psw ; switch to supervisor mode, PR7
@@ -1456,6 +1477,14 @@ tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1
hcmpeq (sp),#300$ ; PC: return after mov
hcmpeq 2(sp),#cp.cms!cp.pr2 ; PS: should be code signature
;
; check mmr0,mmr2 instruction complete (unless on SimH)
cmpb systyp,#sy.sih
beq 490$
hcmpeq #m0.anr!m0.ale!m0.ico!m0.pms!<5*m0.pno>!m0.ena,mmr0 ; check mmr0
hcmpeq #^b0000000011110110,mmr1 ; check mmr1: one SP decrement
hcmpeq #v..pir,mmr2 ; check mmr2: failed vector
490$:
;
; restore ----------------------------------------
clr cp.psw ; to kernel
reset ; mmu off ;! MMU off
@@ -1473,14 +1502,94 @@ tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1
;
9999$: iot ; end of test C2.6
;
; Test C2.7 -- mmu abort plus stack limit abort ++++++++++++++++++++++
; Test C2.7 -- mmu abort in 1st instruction after vector flow ++++++++
; Verifies that 1st instruction after a vector flow has correct MMR0,MMR2
; instruction complete signature, especially MMR0(ico)=0. Tested with an
; abort of the instruction fetch of 1st instruction. The TRAP handler
; address is set to page 6 which is made non-resident.
;
tc0207: clr kipdr6 ; kernel page 6 non-resident
mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
mov #p6base+10,v..trp ; TRAP handler in page 6
mov #200$,v..mmu ; mmu handler
100$: trap 100 ; will fail
halt
200$: hcmpeq #m0.anr!<6*m0.pno>!m0.ena,mmr0 ; check mmr0: ico=0
htsteq mmr1 ; check mmr1: no regs touched
hcmpeq v..trp,mmr2 ; check mmr2: point to 1st instruction
;
reset ; mmu off ;! MMU off
mov #<127.*md.plf>!md.arw,kipdr6 ; restore kipdr6
mov #v..mmu+2,v..mmu ; v..mmu to catcher
clr v..mmu+2
mov #v..trp+2,v..trp ; v..trp to catcher
clr v..trp+2
mov #stack,sp ; SP to default
;
9999$: iot ; end of test C2.7
;
; Test C2.8 -- mmu abort of prefetched instruction +++++++++++++++++++
; Verifies that MMR2 points to the correct instruction if the fetch
; of a prefetched instruction fails. Uses the code p5ce14 initially
; written for E1.4 located at the page 4 to page 5 border.
;
tc0208: clr kipdr5 ; kernel page 5 non-resident
mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
mov #200$,v..mmu ; mmu handler
clr r2 ; clear counter
mov #100$,r3 ; ptr to failed landing
jmp @#p5ce14 ; start test code
;
100$: halt ; lands here if no abort
200$: hcmpeq #3,r2 ; check, 3 executed inc
hcmpeq #m0.anr!<5*m0.pno>!m0.ena,mmr0 ; check mmr0
htsteq mmr1 ; check mmr1: no regs touched
hcmpeq #p5base,mmr2 ; check mmr2: point failed instruction
;
reset ; mmu off ;! MMU off
mov #<127.*md.plf>!md.arw,kipdr5 ; restore kipdr5
mov #v..mmu+2,v..mmu ; v..mmu to catcher
clr v..mmu+2
mov #stack,sp ; SP to default
;
9999$: iot ; end of test C2.8
;
; Test C2.9 -- mmu aborts and memory status ++++++++++++++++++++++++++
; Verifies, a bit late, that an aborted write didnt change memory
;
tc0209: clr kipdr6 ; kernel page 6 non-resident
mov #177777,p6base-2 ; set signatures (will be overwritten)
mov #177777,p6base ; set signatures (will stay)
mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
mov #200$,v..mmu ; mmu handler
mov #p6base-2,r1
clr (r1)+ ; succeeds
100$: clr (r1)+ ; fails
halt
;
200$: hcmpeq #m0.anr!<6*m0.pno>!m0.ena,mmr0 ; check mmr0
hcmpeq #^b00010001,mmr1 ; check mmr1: r1 +2
hcmpeq #100$,mmr2 ; check mmr2: point failed instruction
;
reset ; mmu off ;! MMU off
htsteq p6base-2 ; check signature
hcmpeq #177777,p6base ; check signature
;
mov #<127.*md.plf>!md.arw,kipdr6 ; restore kipdr6
mov #v..mmu+2,v..mmu ; v..mmu to catcher
clr v..mmu+2
mov #stack,sp ; SP to default
;
9999$: iot ; end of test C2.9
;
; Test C2.10 -- mmu abort plus stack limit abort +++++++++++++++++++++
; Consider an instruction that is aborted due to red stack violation an the
; destination address would cause an MMU abort. Tested in ekbee1 test 122
; 2nd part. The 11/70 and the simulators take a vector 4 and do not set MMR0
; abort bits. The w11 also takes a vector 4 but will set MMR0 abort bits.
; Verify this w11 specific behavior.
;
tc0207: tstb systyp ; skip if not on w11
tc0210: tstb systyp ; skip if not on w11
blt 9999$
;
mov #<127.*md.plf>,kipdr6 ; page 6 non-resident (afc=0)
@@ -1493,14 +1602,16 @@ tc0207: tstb systyp ; skip if not on w11
mov #p6base+336,sp ; in red zone
spl 4
ccc
inc (sp) ; fails (use inc to avoid dstw cc issue)
90$: inc (sp) ; fails (use inc to avoid dstw cc issue)
100$: halt ; label after clr
110$: halt ; mmu catcher
;
200$: htsteq sp ; check emergency stack done
hcmpeq (sp),#100$ ; PC: return after trap
hcmpeq 2(sp),#cp.pr4 ; PS: should be code signature
hcmpeq #m0.anr!<6*m0.pno>!m0.ena,mmr0 ; check mmr0, expect abort
hcmpeq #m0.anr!<6*m0.pno>!m0.ena,mmr0 ; check mmr0: expect abort
htsteq mmr1 ; check mmr1: no regs changed
hcmpeq #90$,mmr2 ; check mmr2: instruction
;
reset ; mmu off ;! MMU off
mov #stack,sp ; SP to default
@@ -1511,7 +1622,7 @@ tc0207: tstb systyp ; skip if not on w11
clr v..mmu+2
spl 0 ; back to PR0
;
9999$: iot ; end of test C2.7
9999$: iot ; end of test C2.10
;
; Section D: mmr2+mmr1+mmr0 register, abort recovery =========================
; D1 code in user mode with D space, simulated SP extend
@@ -1614,10 +1725,10 @@ td0101:
bic #^c7,r2 ; mask out regnum field
asl r2 ; word offset
add sp,r2 ; address of register on stack
movb r0,r3
movb r0,r3 ; sign extend
asr r3 ; and shift 3 bits right
asr r3
asr r3
asr r3 ; register correction
asr r3 ; to get register correction
sub r3,(r2) ; and correct register
swab r0 ; go for 2nd half
sob r1,2100$ ; and loop
@@ -1635,7 +1746,9 @@ td0101:
; roll back PC to re-run aborted instruction
mov mmr2,(sp) ; roll back PC
bic #<m0.anr!m0.ale!m0.ard>,mmr0 ; clear abort bits
rti ; return and restart instruction
rtt ; return and restart instruction
; MMU abort reruns must use rtt to avoid a
; spurious tbit trap in case traced instruction
;
3000$: .word 0 ; save mmr0
3001$: .word 0 ; save mmr1
@@ -2173,13 +2286,34 @@ tf0102: mov #154345,@#p6base ; inititialize target
9999$: iot ; end of test F1.2
;
; Summary
;; END OF ALL TESTS - loop closure ============================================
; END OF ALL TESTS - loop closure ============================================
;
mov tstno,r0 ; hack, for easy monitoring ...
hcmpeq tstno,#26. ; all tests done ?
hcmpeq tstno,#29. ; all tests done ?
call chkpdr ; kernel pdr/par OK ?
;
jmp loop
;
; pdr/par consistency checker
; Verify that kernel pdr/par are in default configuration set up by A1.2.
; Implentend as subroutine for debug purposes. Always called at end of tests.
;
chkpdr: mov #kipdr0,r0
mov #kipar0,r1
mov #<127.*md.plf>!md.arw,r2 ; default pdr
clr r3 ; current par
mov #200,r4 ; par increment
mov #7.,r5 ; check 0...6
100$: mov (r0),(r0) ; clear AI bits with re-write
hcmpeq r2,(r0)+ ; check pdr
hcmpeq r3,(r1)+ ; check par
add r4,r3 ; step to next par value
sob r5,100$
mov (r0),(r0) ; clear AI bits with re-write
hcmpeq r2,(r0)+ ; check pdr7
hcmpeq #177600,(r1)+ ; check par7
return
;
; kernel handlers and helpers ================================================
;
; vhmmua - expected mmu abort handler ++++++++++++++++++++++++++++++++++++++++
@@ -2259,12 +2393,13 @@ vhtpir: htstge (r5) ; r5 at fence ?
; They are located in page 4 at 100000 and above and are position-independent
; code. That allows to assemble and load them together with the main code.
;
; vc0 - simple code ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
. = 100000
;
; vc0 - simple code ++ used from B3.1 ++++++++++++++++++++++++++++++++++++++++
; uses jsr, has stack below 1000 (no problem in user/supervisor mode)
; does operations with vc0v0, vc0v1, vc0v2
; these location are usually set before and checked afterwards in kernel mode
;
. = 100000
vc0: jmp 100$
.blkw 14. ; small stack space
100$: mov #40,sp ; initialize stack
@@ -2281,7 +2416,7 @@ vc0v0: .word 0
vc0v1: .word 0
vc0v2: .word 0
;
; vc1 - simple I/D code ++++++++++++++++++++++++++++++++++++++++++++++++++++++
; vc1 - simple I/D code ++ used from B3.2 ++++++++++++++++++++++++++++++++++++
; uses jsr, has stack below 1000 (no problem in user/supervisor mode)
; does operations with vc1v0, vc1v1, vc1v2
; these locations are usually set before and checked afterwards in kernel mode
@@ -2307,7 +2442,7 @@ vc1v0: .word 0
vc1v1: .word 0
vc1v2: .word 0
;
; vc2 - stack push I/D code ++++++++++++++++++++++++++++++++++++++++++++++++++
; vc2 - stack push I/D code ++ used from D1.1 ++++++++++++++++++++++++++++++++
; set SP just above the stack page end; push data
; expect kernel handler to extend the stack and re-run failed push
;

11
tools/xxdp/ekbee1_patch_w11a.tcl
View File

@@ -1,4 +1,4 @@
# $Id: ekbee1_patch_w11a.tcl 1329 2022-12-11 17:28:28Z mueller $
# $Id: ekbee1_patch_w11a.tcl 1330 2022-12-16 17:52:40Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -63,11 +63,12 @@ dep 055404 000137
dep 055406 055554
#
# AP: skip test 067: verify MMR0(7) ------------------------------------------
# Tests verifies MMR0(7) instruction complete. Not implemented in w11.
# The test loops-up.
# w11 implements MMR0(7) instruction complete but has a different MMR1
# response. The 11/70 decrements SP twice before the 1st push, MMR1 has
# therefore 173366 after a 1st push abort. The w11 decrements SP before
# each push, MMR1 has therefore 000366 1st push abort. Test is patched.
#
dep 056536 000137
dep 056540 057120
dep 057010 000366
#
# AP: patch test 122: KT BEND ------------------------------------------------
# Tests MMU vs NXM,ODD,RED behavior