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4732555297
- new reference system
- switched from ISE 13.3 to 14.7.
- map/par behaviour changed, unfortunately unfavorably for w11a.
On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can
be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
34 lines
968 B
Plaintext
34 lines
968 B
Plaintext
## $Id: sys_w11a_n2.ucf_cpp 540 2013-10-13 18:42:50Z mueller $
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##
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## Revision History:
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## Date Rev Version Comment
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## 2013-10-13 540 1.1 add pad->clk constraints
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## 2013-04-20 509 1.1 add fx2 support
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## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
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## 2010-05-26 295 1.0 Initial version
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##
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NET "I_CLK50" TNM_NET = "I_CLK50";
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TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
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OFFSET = IN 10 ns BEFORE "I_CLK50";
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OFFSET = OUT 20 ns AFTER "I_CLK50";
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## constrain pad->net clock delay
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NET CLK TNM = TNM_CLK;
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TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK50) TO TNM_CLK 10 ns;
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NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
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TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;
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## std board
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##
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#include "bplib/nexys2/nexys2_pins.ucf"
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##
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## Pmod B0 - RS232
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##
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#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
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##
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## Cypress FX2
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##
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#include "bplib/nexys2/nexys2_pins_fx2.ucf"
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#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"
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