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- pdp11_sequencer.vhd: BUGFIX: use is_kstackdst1246 also in dstr flow - tools/asm-11/lib/ - defs_cpu.mac: rename cp.sli -> cp.slr - halt_checks.mac: add htstne, htsbne - tools/tcode - cpu_basics.mac: rename cp.sli -> cp.slr - cpu_details.mac: add Test A3: STKLIM - cpu_(eis|mmu).mac,tcode.ecmd: editorial changes
726 lines
37 KiB
Plaintext
726 lines
37 KiB
Plaintext
; $Id: cpu_eis.mac 1314 2022-11-09 10:55:29Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-07-25 1263 1.0 Initial version
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; 2022-07-11 1251 0.1 First draft
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;
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; Test CPU EIS instructions
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;
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.include |lib/tcode_std_base.mac|
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;
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; Section A: div =============================================================
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; This section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 111 001 rrr sss sss NZVC DIV
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;
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jmp ta0101
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;
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; driver for div tests
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;
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topdiv: mov (r5),r4 ; setup data pointer
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mov 2(r5),r5 ; setup end pointer
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mov #cp.psw,r3 ; setup psw pointer
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;
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100$: mov (r4)+,r0 ; load divident high
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mov (r4)+,r1 ; load divident low
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div (r4)+,r0 ; divide by divisor
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mov (r3),r2 ; get psw
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bit #cp00v0,r2 ; V set ?
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beq 101$ ; if yes
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bic #cpnz00,r2 ; ignore N and Z (differ in e11 and SimH)
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101$: hcmpeq (r4)+,r2 ; check psw
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bit #cp00vc, r2 ; V or C set ?
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beq 200$ ; eq if V=0 and C=0
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add #4,r4 ; skip q and r check
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br 300$
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;
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200$: hcmpeq (r4)+,r0 ; check quotient
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hcmpeq (r4)+,r1 ; check reminder
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;
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300$: cmp r4,r5 ; more to do ?
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blo 100$
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return
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;
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; Test A1.1 -- div test basics ++++++++++++++++++++++++++++++++++++++++++++++++
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; Notes:
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; - from test_w11a_div.tcl, div_testd2 cases, translated almost 1-to-1
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; - the state of Z,N is according to Processor Handbook 1979 undefined for
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; a DIV when V=1 (so after zero divide and overflow).
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; - SimH, e11, and real 11/70 differ in the Z state when V=1
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; - SimH: always Z=0 for overflow (V=1,C=0)
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; - 11/70: sometimes Z=1 after overflow
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; - e11: sometimes Z=1 after overflow, whether 11/70 precise unknown
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; - w11: always Z=0 for overflow, as in SimH
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; - should execute on w11, SimH and e11, so Z and N are excluded from PSW check
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;
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ta0101: mov #1000$,r5
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call topdiv
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jmp 9999$
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;
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1000$: .word 1010$
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.word 1011$
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;
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;
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; ddh ddl dr psw q r
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1010$:
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; --- dr>0
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.word 0, 0, 3, cp0z00, 0, 0
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.word 0, 1, 3, cp0z00, 0, 1
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.word 0, 2, 3, cp0z00, 0, 2
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.word 0, 3, 3, cp0000, 1, 0
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.word 0, 4, 3, cp0000, 1, 1
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.word -1, -1, 3, cp0z00, 0, -1
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.word -1, -2, 3, cp0z00, 0, -2
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.word -1, -3, 3, cpn000, -1, 0
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.word -1, -4, 3, cpn000, -1, -1
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; --- dr<0
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.word 0, 0, -3, cp0z00, 0, 0
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.word 0, 1, -3, cp0z00, 0, 1
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.word 0, 2, -3, cp0z00, 0, 2
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.word 0, 3, -3, cpn000, -1, 0
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.word 0, 4, -3, cpn000, -1, 1
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.word -1, -1, -3, cp0z00, 0, -1
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.word -1, -2, -3, cp0z00, 0, -2
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.word -1, -3, -3, cp0000, 1, 0
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.word -1, -4, -3, cp0000, 1, -1
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; --- dr==0
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.word 0, 0, 0, cp00vc, 0, 0 ; !vc
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.word 0, 1, 0, cp00vc, 0, 0 ; !vc
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.word -1, -1, 0, cp00vc, 0, 0 ; !vc
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; --- 4 quadrant basics
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.word 0, 34., 5., cp0000, 6., 4.
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.word 0, 34., -5., cpn000, -6., 4.
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.word -1, -34., 5., cpn000, -6., -4.
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.word -1, -34., -5., cp0000, 6., -4.
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; --- late div quite cases in 2 quadrant algorithm
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.word -1,-32767., -1., cp0000, 32767., 0. ;-32767/-1
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.word -1, 100000, -1., cp00v0, 0, 0 ;-32768/-1 !v
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.word -1, 077777, -1., cp00v0, 0, 0 ;-32769/-1 !v
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;
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.word -1, 000002, -2., cp0000, 32767., 0. ;-65534/-2
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.word -1, 000001, -2., cp0000, 32767., -1. ;-65535/-2
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.word -1, 000000, -2., cp00v0, 0, 0 ;-65536/-2 !v
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.word -2, 177777, -2., cp00v0, 0, 0 ;-65537/-2 !v
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; --- big divident overflow cases
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.word 77777, 177777, 1., cp00v0, 0, 0 ;0x7fffffff/ 1 !v
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.word 77777, 177777, 2., cp00v0, 0, 0 ;0x7fffffff/ 2 !v
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.word 77777, 177777, -1., cp00v0, 0, 0 ;0x7fffffff/-1 !v
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.word 77777, 177777, -2., cp00v0, 0, 0 ;0x7fffffff/-2 !v
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.word 100000, 000000, 1., cp00v0, 0, 0 ;0x80000000/ 1 !v
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.word 100000, 000000, 2., cp00v0, 0, 0 ;0x80000000/ 2 !v
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.word 100000, 000000, -1., cp00v0, 0, 0 ;0x80000000/-1 !v
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.word 100000, 000000, -2., cp00v0, 0, 0 ;0x80000000/-2 !v
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;
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1011$:
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9999$: iot ; end of test A1.1
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;
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; Test A1.2 -- div test systematic ++++++++++++++++++++++++++++++++++++++++++++
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; from test_w11a_div.tcl, div_testdqr cases, exported via div_show_exp
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;
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ta0102: mov #1000$,r5
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call topdiv
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jmp 9999$
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;
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1000$: .word 1010$
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.word 1011$
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;
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;
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; ddh ddl dr psw q r
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1010$:
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; test q=100000 boundary cases (q = max neg value)
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; case dd>0, dr<0 -- factor 21846
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.word 0025253,0000000, -21846., cpn000, -32768., 0.;dd= 715849728
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.word 0025253,0000001, -21846., cpn000, -32768., 1.;dd= 715849729
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.word 0025253,0052524, -21846., cpn000, -32768., 21844.;dd= 715871572
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.word 0025253,0052525, -21846., cpn000, -32768., 21845.;dd= 715871573
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.word 0025253,0052526, -21846., cp00v0, 10923., 21846.;dd= 715871574
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.word 0025253,0052527, -21846., cp00v0, 10923., 21847.;dd= 715871575
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; case dd<0, dr>0 -- factor 21846
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.word 0152525,0000000, 21846., cpn000, -32768., 0.;dd= -715849728
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.word 0152524,0177777, 21846., cpn000, -32768., -1.;dd= -715849729
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.word 0152524,0125254, 21846., cpn000, -32768., -21844.;dd= -715871572
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.word 0152524,0125253, 21846., cpn000, -32768., -21845.;dd= -715871573
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.word 0152524,0125252, 21846., cp00v0, -10924., -21846.;dd= -715871574
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.word 0152524,0125251, 21846., cp00v0, -10924., -21847.;dd= -715871575
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; case dd>0, dr<0 -- factor 21847
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.word 0025253,0100000, -21847., cpn000, -32768., 0.;dd= 715882496
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.word 0025253,0100001, -21847., cpn000, -32768., 1.;dd= 715882497
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.word 0025253,0152525, -21847., cpn000, -32768., 21845.;dd= 715904341
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.word 0025253,0152526, -21847., cpn000, -32768., 21846.;dd= 715904342
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.word 0025253,0152527, -21847., cp00v0, 10923., -10921.;dd= 715904343
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.word 0025253,0152530, -21847., cp00v0, 10923., -10920.;dd= 715904344
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; case dd<0, dr>0 -- factor 21847
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.word 0152524,0100000, 21847., cpn000, -32768., 0.;dd= -715882496
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.word 0152524,0077777, 21847., cpn000, -32768., -1.;dd= -715882497
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.word 0152524,0025253, 21847., cpn000, -32768., -21845.;dd= -715904341
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.word 0152524,0025252, 21847., cpn000, -32768., -21846.;dd= -715904342
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.word 0152524,0025251, 21847., cp00v0, -10924., 10921.;dd= -715904343
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.word 0152524,0025250, 21847., cp00v0, -10924., 10920.;dd= -715904344
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; test q=077777 boundary cases (q = max pos value)
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; case dd>0, dr>0 -- factor 21846
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.word 0025252,0125252, 21846., cp0000, 32767., 0.;dd= 715827882
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.word 0025252,0125253, 21846., cp0000, 32767., 1.;dd= 715827883
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.word 0025252,0177776, 21846., cp0000, 32767., 21844.;dd= 715849726
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.word 0025252,0177777, 21846., cp0000, 32767., 21845.;dd= 715849727
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.word 0025253,0000000, 21846., cp00v0, 10923., 0.;dd= 715849728
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.word 0025253,0000001, 21846., cp00v0, 10923., 1.;dd= 715849729
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; case dd<0, dr<0 -- factor 21846
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.word 0152525,0052526, -21846., cp0000, 32767., 0.;dd= -715827882
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.word 0152525,0052525, -21846., cp0000, 32767., -1.;dd= -715827883
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.word 0152525,0000002, -21846., cp0000, 32767., -21844.;dd= -715849726
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.word 0152525,0000001, -21846., cp0000, 32767., -21845.;dd= -715849727
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.word 0152525,0000000, -21846., cp00v0, -10923., 0.;dd= -715849728
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.word 0152524,0177777, -21846., cp00v0, -10924., -1.;dd= -715849729
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; case dd>0, dr>0 -- factor 21847
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.word 0025253,0025251, 21847., cp0000, 32767., 0.;dd= 715860649
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.word 0025253,0025252, 21847., cp0000, 32767., 1.;dd= 715860650
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.word 0025253,0077776, 21847., cp0000, 32767., 21845.;dd= 715882494
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.word 0025253,0077777, 21847., cp0000, 32767., 21846.;dd= 715882495
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.word 0025253,0100000, 21847., cp00v0, 10923., -32768.;dd= 715882496
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.word 0025253,0100001, 21847., cp00v0, 10923., -32767.;dd= 715882497
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; case dd<0, dr<0 -- factor 21847
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.word 0152524,0152527, -21847., cp0000, 32767., 0.;dd= -715860649
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.word 0152524,0152526, -21847., cp0000, 32767., -1.;dd= -715860650
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.word 0152524,0100002, -21847., cp0000, 32767., -21845.;dd= -715882494
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.word 0152524,0100001, -21847., cp0000, 32767., -21846.;dd= -715882495
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.word 0152524,0100001, -21847., cp0000, 32767., -21846.;dd= -715882495
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.word 0152524,0100000, -21847., cp00v0, -10924., -32768.;dd= -715882496
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; test dr=100000 boundary cases (dr = max neg value)
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; case dd<0, q>0
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.word 0177777,0100000, -32768., cp0000, 1., 0.;dd= -32768
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.word 0177777,0077777, -32768., cp0000, 1., -1.;dd= -32769
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.word 0177777,0000001, -32768., cp0000, 1., -32767.;dd= -65535
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.word 0177777,0000000, -32768., cp0000, 2., 0.;dd= -65536
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.word 0177776,0177777, -32768., cp0000, 2., -1.;dd= -65537
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.word 0177776,0100001, -32768., cp0000, 2., -32767.;dd= -98303
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.word 0177776,0100000, -32768., cp0000, 3., 0.;dd= -98304
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.word 0177776,0077777, -32768., cp0000, 3., -1.;dd= -98305
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.word 0177776,0000001, -32768., cp0000, 3., -32767.;dd= -131071
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.word 0177776,0000000, -32768., cp0000, 4., 0.;dd= -131072
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.word 0177775,0177777, -32768., cp0000, 4., -1.;dd= -131073
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.word 0177775,0100001, -32768., cp0000, 4., -32767.;dd= -163839
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.word 0177775,0000000, -32768., cp0000, 6., 0.;dd= -196608
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.word 0140003,0000000, -32768., cp0000, 32762., 0.;dd=-1073545216
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.word 0140002,0000000, -32768., cp0000, 32764., 0.;dd=-1073610752
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.word 0140001,0100000, -32768., cp0000, 32765., 0.;dd=-1073643520
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.word 0140001,0000000, -32768., cp0000, 32766., 0.;dd=-1073676288
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.word 0140000,0177777, -32768., cp0000, 32766., -1.;dd=-1073676289
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.word 0140000,0100001, -32768., cp0000, 32766., -32767.;dd=-1073709055
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.word 0140000,0100000, -32768., cp0000, 32767., 0.;dd=-1073709056
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.word 0140000,0077777, -32768., cp0000, 32767., -1.;dd=-1073709057
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.word 0140000,0000001, -32768., cp0000, 32767., -32767.;dd=-1073741823
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; case dd>0, q<0
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.word 0000000,0100000, -32768., cpn000, -1., 0.;dd= 32768
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.word 0000000,0100001, -32768., cpn000, -1., 1.;dd= 32769
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.word 0000000,0177777, -32768., cpn000, -1., 32767.;dd= 65535
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.word 0000001,0000000, -32768., cpn000, -2., 0.;dd= 65536
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.word 0000001,0000001, -32768., cpn000, -2., 1.;dd= 65537
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.word 0000001,0077777, -32768., cpn000, -2., 32767.;dd= 98303
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.word 0037777,0100000, -32768., cpn000, -32767., 0.;dd= 1073709056
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.word 0037777,0100001, -32768., cpn000, -32767., 1.;dd= 1073709057
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.word 0037777,0177777, -32768., cpn000, -32767., 32767.;dd= 1073741823
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.word 0040000,0000000, -32768., cpn000, -32768., 0.;dd= 1073741824
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.word 0040000,0000001, -32768., cpn000, -32768., 1.;dd= 1073741825
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.word 0040000,0077777, -32768., cpn000, -32768., 32767.;dd= 1073774591
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; test dr=077777 boundary cases (dr = max pos value)
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; case dd>0, q>0
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.word 0000000,0077777, 32767., cp0000, 1., 0.;dd= 32767
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.word 0000000,0100000, 32767., cp0000, 1., 1.;dd= 32768
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.word 0000000,0177775, 32767., cp0000, 1., 32766.;dd= 65533
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.word 0000000,0177776, 32767., cp0000, 2., 0.;dd= 65534
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.word 0000000,0177777, 32767., cp0000, 2., 1.;dd= 65535
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.word 0000001,0077774, 32767., cp0000, 2., 32766.;dd= 98300
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.word 0037776,0100002, 32767., cp0000, 32766., 0.;dd= 1073643522
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.word 0037776,0100003, 32767., cp0000, 32766., 1.;dd= 1073643523
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.word 0037777,0000000, 32767., cp0000, 32766., 32766.;dd= 1073676288
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.word 0037777,0000001, 32767., cp0000, 32767., 0.;dd= 1073676289
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.word 0037777,0000002, 32767., cp0000, 32767., 1.;dd= 1073676290
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.word 0037777,0077777, 32767., cp0000, 32767., 32766.;dd= 1073709055
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; case dd<0, q<0
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.word 0177777,0100001, 32767., cpn000, -1., 0.;dd= -32767
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.word 0177777,0100000, 32767., cpn000, -1., -1.;dd= -32768
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.word 0177777,0000003, 32767., cpn000, -1., -32766.;dd= -65533
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.word 0177777,0000002, 32767., cpn000, -2., 0.;dd= -65534
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.word 0177777,0000001, 32767., cpn000, -2., -1.;dd= -65535
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.word 0177776,0100004, 32767., cpn000, -2., -32766.;dd= -98300
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.word 0140000,0177777, 32767., cpn000, -32767., 0.;dd=-1073676289
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.word 0140000,0177776, 32767., cpn000, -32767., -1.;dd=-1073676290
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.word 0140000,0100001, 32767., cpn000, -32767., -32766.;dd=-1073709055
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.word 0140000,0100000, 32767., cpn000, -32768., 0.;dd=-1073709056
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.word 0140000,0077777, 32767., cpn000, -32768., -1.;dd=-1073709057
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.word 0140000,0000002, 32767., cpn000, -32768., -32766.;dd=-1073741822
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; test dd max cases
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; case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591
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.word 0037777,0177777, -32768., cpn000, -32767., 32767.;dd= 1073741823
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.word 0040000,0000000, -32768., cpn000, -32768., 0.;dd= 1073741824
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.word 0040000,0000001, -32768., cpn000, -32768., 1.;dd= 1073741825
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.word 0040000,0077776, -32768., cpn000, -32768., 32766.;dd= 1073774590
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.word 0040000,0077777, -32768., cpn000, -32768., 32767.;dd= 1073774591
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.word 0037777,0100000, -32768., cpn000, -32767., 0.;dd= 1073709056
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.word 0037777,0100001, -32768., cpn000, -32767., 1.;dd= 1073709057
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; case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055
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.word 0037777,0000000, 32767., cp0000, 32766., 32766.;dd= 1073676288
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.word 0037777,0000001, 32767., cp0000, 32767., 0.;dd= 1073676289
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.word 0037777,0000002, 32767., cp0000, 32767., 1.;dd= 1073676290
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.word 0037777,0077776, 32767., cp0000, 32767., 32765.;dd= 1073709054
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.word 0037777,0077777, 32767., cp0000, 32767., 32766.;dd= 1073709055
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.word 0037777,0100000, 32767., cp00v0, 16383., -32768.;dd= 1073709056
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.word 0037776,0100001, 32767., cp0000, 32765., 32766.;dd= 1073643521
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; case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822
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.word 0140000,0100001, 32767., cpn000, -32767., -32766.;dd=-1073709055
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.word 0140000,0100000, 32767., cpn000, -32768., 0.;dd=-1073709056
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.word 0140000,0077777, 32767., cpn000, -32768., -1.;dd=-1073709057
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.word 0140000,0000003, 32767., cpn000, -32768., -32765.;dd=-1073741821
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.word 0140000,0000002, 32767., cpn000, -32768., -32766.;dd=-1073741822
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.word 0140000,0000001, 32767., cp00v0, -16384., 1.;dd=-1073741823
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.word 0140000,0000000, 32767., cp00v0, -16384., 0.;dd=-1073741824
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; case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823
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.word 0140000,0100001, -32768., cp0000, 32766., -32767.;dd=-1073709055
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.word 0140000,0100000, -32768., cp0000, 32767., 0.;dd=-1073709056
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.word 0140000,0077777, -32768., cp0000, 32767., -1.;dd=-1073709057
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.word 0140000,0000002, -32768., cp0000, 32767., -32766.;dd=-1073741822
|
|
.word 0140000,0000001, -32768., cp0000, 32767., -32767.;dd=-1073741823
|
|
.word 0140000,0000000, -32768., cp00v0, -16384., 0.;dd=-1073741824
|
|
.word 0137777,0177777, -32768., cp00v0, -16385., -1.;dd=-1073741825
|
|
;
|
|
1011$:
|
|
;
|
|
9999$: iot ; end of test A1.2
|
|
;
|
|
;
|
|
; Test A1.3 -- div odd register +++++++++++++++++++++++++++++++++++++++
|
|
; check div odd register behavior
|
|
; Note: The div instruction has, in contrast to ashc, no useful semantics when
|
|
; called with an odd register. DEC documentation doesnt specify the
|
|
; behavior. SimH assumes, that register handling is done like for ashc,
|
|
; so effective dd is 'R<<16 | R' and reminder is stored. w11 implements
|
|
; div like this. This test briefly verifies this behavior.
|
|
|
|
ta0103: mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
mov #cp.psw,r3 ; setup psw pointer
|
|
clr r0 ; for tmu optics
|
|
100$: mov (r4)+,r1 ; load dd
|
|
div (r4)+,r1 ; div
|
|
hcmpeq (r4)+,(r3) ; check psw
|
|
hcmpeq (r4)+,r1 ; check res (reminder)
|
|
cmp r4,r5
|
|
blo 100$
|
|
jmp 9999$
|
|
;
|
|
; dd, dr, psw, res ;
|
|
1000$: .word 000000, 1., cp0z00, 000000 ; h: 000000
|
|
.word 000007, 16., cp0000, 000007 ; 458759/16: 28672, 7 h: 070000
|
|
.word 000007, 17., cp0000, 000016 ; 458759/17: 26985,14 h: 064551
|
|
.word 000007, 19., cp0000, 000004 ; 458759/19: 24145, 4 h: 057121
|
|
.word 000007, 15., cp0000, 000016 ; 458759/15: 30583,14 h: 073567
|
|
1010$:
|
|
;
|
|
9999$: iot ; end of test A1.3
|
|
;
|
|
; Section B: mul =============================================================
|
|
; This section verifies
|
|
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
|
|
; 0 111 000 rrr sss sss NZ0C MUL
|
|
;
|
|
; Test B1.1 -- mul even and odd ++++++++++++++++++++++++++++++++++++++
|
|
; check that mul works with even and odd destination register
|
|
;
|
|
jmp tb0101
|
|
;
|
|
; driver for mul even tests
|
|
;
|
|
tbmule: mov #cp.psw,r3 ; setup psw pointer
|
|
100$: mov (r4)+,r0 ; load f1
|
|
mul (r4)+,r0 ; mul
|
|
hcmpeq (r4)+,(r3) ; check psw
|
|
hcmpeq (r4)+,r0 ; check p_high
|
|
hcmpeq (r4)+,r1 ; check p_low
|
|
cmp r4,r5
|
|
blo 100$
|
|
return
|
|
;
|
|
; driver for mul odd tests
|
|
;
|
|
tbmulo: mov #cp.psw,r3 ; setup psw pointer
|
|
100$: mov (r4)+,r1 ; load f1
|
|
mul (r4)+,r1 ; mul
|
|
hcmpeq (r4)+,(r3) ; check psw
|
|
tst (r4)+ ; skip p_high
|
|
hcmpeq (r4)+,r1 ; check p_low
|
|
cmp r4,r5
|
|
blo 100$
|
|
return
|
|
;
|
|
tb0101: mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
call tbmule ; test even
|
|
;
|
|
mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
call tbmulo ; test odd
|
|
;
|
|
jmp 9999$
|
|
;
|
|
; fx, f2, psw, ph, pl ;
|
|
1000$: .word 0., 0., cp0z00, 0, 0 ; p = 0.
|
|
.word 0., 1., cp0z00, 0, 0 ; p = 0.
|
|
.word 0., -1., cp0z00, 0, 0 ; p = 0.
|
|
.word 1., 0., cp0z00, 0, 0 ; p = 0.
|
|
.word 1., 1., cp0000, 0, 1 ; p = 1.
|
|
.word 1., -1., cpn000, 177777, 177777 ; p = -1.
|
|
.word -1., 0., cp0z00, 0, 0 ; p = 0.
|
|
.word -1., 1., cpn000, 177777, 177777 ; p = -1.
|
|
.word -1., -1., cp0000, 0, 1 ; p = 1.
|
|
.word 181., 181., cp0000, 0, 077771 ; p = 32761.
|
|
.word 181., 182., cp000c, 0, 100256 ; p = 32942.
|
|
.word 181., -182., cpn00c, 177777, 077522 ; p = -32942.
|
|
.word 31022., 9562., cp000c, 010656, 040054 ; p = 296632364.
|
|
.word 18494.,-24041., cpn00c, 162577, 134622 ; p =-444614254.
|
|
.word -12549., 2397., cpn00c, 177065, 002057 ; p = -30079953.
|
|
.word -20493.,-23858., cp000c, 016444, 055612 ; p = 488921994.
|
|
1010$:
|
|
;
|
|
9999$: iot ; end of test B1.1
|
|
;
|
|
; Test B1.2 -- mul+div (and adc,adc,sxt) +++++++++++++++++++++++++++++
|
|
; combined div and mul test
|
|
;
|
|
tb0102: mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
;
|
|
100$: mov (r4)+,r0 ; load divident high
|
|
mov (r4)+,r1 ; load divident low
|
|
div (r4)+,r0 ; divide by divisor
|
|
mov r0,r2 ; get quotient
|
|
mul -2(r4),r2 ; multiply with divisor
|
|
add r1,r3 ; add reminder on p_low
|
|
adc r2 ; propagate carry to p_high
|
|
tst r1 ; sign extend reminder
|
|
sxt r1
|
|
add r1,r2 ; and add to p_high
|
|
hcmpeq -4(r4),r3 ; check p_low against divident low
|
|
hcmpeq -6(r4),r2 ; check p_high against divident high
|
|
cmp r4,r5
|
|
blo 100$
|
|
jmp 9999$
|
|
;
|
|
; ddh ddl dr
|
|
1000$: .word 0, 0, 0
|
|
.word 0, 1, 3
|
|
.word 0, 2, 3
|
|
.word 0, 3, 3
|
|
.word 0, 4, 3
|
|
.word -1, -1, 3
|
|
.word -1, -2, 3
|
|
.word -1, -3, 3
|
|
.word -1, -4, 3
|
|
.word 0, 0, -3
|
|
.word 0, 1, -3
|
|
.word 0, 2, -3
|
|
.word 0, 3, -3
|
|
.word 0, 4, -3
|
|
.word -1, -1, -3
|
|
.word -1, -2, -3
|
|
.word -1, -3, -3
|
|
.word -1, -4, -3
|
|
.word 010656, 040054, 9562. ; dd = 296632364.
|
|
.word 010656, 040053, 9562. ; dd = 296632363.
|
|
.word 010656, 040055, 9562. ; dd = 296632365.
|
|
.word 010656, 040054, -9562. ; dd = 296632364.
|
|
.word 010656, 040053, -9562. ; dd = 296632363.
|
|
.word 010656, 040055, -9562. ; dd = 296632365.
|
|
.word 162577, 134622, 24041. ; dd = -444614254.
|
|
.word 162577, 134621, 24041. ; dd = -444614255.
|
|
.word 162577, 134623, 24041. ; dd = -444614253.
|
|
.word 162577, 134622,-24041. ; dd = -444614254.
|
|
.word 162577, 134621,-24041. ; dd = -444614255.
|
|
.word 162577, 134623,-24041. ; dd = -444614253.
|
|
1010$:
|
|
;
|
|
9999$: iot ; end of test B1.2
|
|
;
|
|
; Section C: ash =============================================================
|
|
; This section verifies
|
|
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
|
|
; 0 111 010 rrr sss sss NZVC ASH
|
|
;
|
|
; Test C1.1 -- ash +++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
;
|
|
tc0101: mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
mov #cp.psw,r3 ; setup psw pointer
|
|
100$: mov (r4)+,r0 ; load src
|
|
ash (r4)+,r0 ; ash
|
|
hcmpeq (r4)+,(r3) ; check psw
|
|
hcmpeq (r4)+,r0 ; check
|
|
cmp r4,r5
|
|
blo 100$
|
|
jmp 9999$
|
|
;
|
|
200$: .word 0
|
|
;
|
|
; src, shift, psw, res ;
|
|
1000$: .word 000000, 0., cp0z00, 000000
|
|
.word 000200, 0., cp0000, 000200
|
|
.word 000200, 1., cp0000, 000400
|
|
.word 000200, 7., cp0000, 040000
|
|
.word 000200, 8., cpn0v0, 100000 ; sign!
|
|
.word 000200, 9., cp0zvc, 000000 ; sign!, C=1
|
|
.word 000200, 10., cp0zv0, 000000 ; sign!
|
|
.word 000200, 31., cp0zv0, 000000 ; sign!; max pos count
|
|
.word 000200, 32., cp0z00, 000000 ; !! 0040 --> like -32.
|
|
.word 000200, 60., cp0000, 000010 ; !! 0074 --> like -4.
|
|
.word 000200, 65., cp0000, 000400 ; !! 0101 --> like 1.
|
|
.word 000200, -1., cp0000, 000100
|
|
.word 000200, -7., cp0000, 000001
|
|
.word 000200, -8., cp0z0c, 000000 ; C=1
|
|
.word 000200, -9., cp0z00, 000000
|
|
.word 000200, -31., cp0z00, 000000
|
|
.word 000200, -32., cp0z00, 000000 ; max neg count
|
|
.word 000200, -33., cp0zv0, 000000 ; !! 0737 --> like 31.
|
|
.word 000200, -60., cp0000, 004000 ; !! 0704 --> like 4.
|
|
.word 000200, -65., cp0000, 000100 ; !! 0677 --> like -1.
|
|
.word 000200, 000077, cp0000, 000100 ; -1. only 6 bits
|
|
.word 000200, 000071, cp0000, 000001 ; -7. only 6 bits
|
|
.word 000200, 000070, cp0z0c, 000000 ; -8. only 6 bits
|
|
.word 100200, 0., cpn000, 100200
|
|
.word 100200, 1., cp00vc, 000400 ; sign change, C=1
|
|
.word 100200, 7., cp00v0, 040000 ; sign change
|
|
.word 100200, 8., cpn0v0, 100000 ; sign change
|
|
.word 100200, 9., cp0zvc, 000000 ; sign change, C=1
|
|
.word 100200, -1., cpn000, 140100
|
|
.word 100200, -7., cpn000, 177401
|
|
.word 100200, -8., cpn00c, 177600 ; C=1
|
|
.word 100200, -9., cpn000, 177700
|
|
.word 100200, -15., cpn000, 177777
|
|
.word 100200, -16., cpn00c, 177777 ; C=1
|
|
.word 100200, -17., cpn00c, 177777 ; C=1
|
|
1010$:
|
|
;
|
|
9999$: iot ; end of test C1.1
|
|
;
|
|
; Section D: ashc ============================================================
|
|
; This section verifies
|
|
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
|
|
; 0 111 011 rrr sss sss NZVC ASHC
|
|
;
|
|
; Test D1.1 -- ashc even register +++++++++++++++++++++++++++++++++++
|
|
;
|
|
td0101: mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
mov #cp.psw,r3 ; setup psw pointer
|
|
100$: mov (r4)+,r0 ; load src_h
|
|
mov (r4)+,r1 ; load src_l
|
|
ashc (r4)+,r0 ; ashc
|
|
hcmpeq (r4)+,(r3) ; check psw
|
|
hcmpeq (r4)+,r0 ; check res_h
|
|
hcmpeq (r4)+,r1 ; check res_l
|
|
cmp r4,r5
|
|
blo 100$
|
|
jmp 9999$
|
|
;
|
|
; src_h, src_h, shift, psw, res_h, res_l ;
|
|
1000$: .word 000000, 000000, 0., cp0z00, 000000, 000000
|
|
.word 000020, 000200, 0., cp0000, 000020, 000200
|
|
.word 000020, 000200, 1., cp0000, 000040, 000400
|
|
.word 000020, 000200, 8., cp0000, 010000, 100000
|
|
.word 000020, 000200, 9., cp0000, 020001, 000000
|
|
.word 000020, 000200, 10., cp0000, 040002, 000000
|
|
.word 000020, 000200, 11., cpn0v0, 100004, 000000 ; sign!
|
|
.word 000020, 000200, 12., cp00vc, 000010, 000000 ; sign! C=1
|
|
.word 000020, 000200, 13., cp00v0, 000020, 000000 ; sign!
|
|
.word 000020, 000200, 23., cp00v0, 040000, 000000 ; sign!
|
|
.word 000020, 000200, 24., cpn0v0, 100000, 000000 ; sign!
|
|
.word 000020, 000200, 25., cp0zvc, 000000, 000000 ; sign! C=1
|
|
.word 000020, 000200, 26., cp0zv0, 000000, 000000 ; sign!
|
|
.word 000020, 000200, 31., cp0zv0, 000000, 000000 ; sign! max pos
|
|
.word 000020, 000200, 32., cp0z00, 000000, 000000 ; 0040 like -32.
|
|
.word 000020, 000200, 60., cp0000, 000001, 000010 ; 0074 like -4.
|
|
.word 000020, 000200, 65., cp0000, 000040, 000400 ; 0101 like 1.
|
|
.word 000020, 000200, -1., cp0000, 000010, 000100
|
|
.word 000020, 000200, -4., cp0000, 000001, 000010
|
|
.word 000020, 000200, -5., cp0000, 000000, 100004
|
|
.word 000020, 000200, -7., cp0000, 000000, 020001
|
|
.word 000020, 000200, -8., cp000c, 000000, 010000 ; C=1
|
|
.word 000020, 000200, -9., cp0000, 000000, 004000
|
|
.word 000020, 000200, -20., cp0000, 000000, 000001
|
|
.word 000020, 000200, -21., cp0z0c, 000000, 000000 ; C=1
|
|
.word 000020, 000200, -22., cp0z00, 000000, 000000
|
|
.word 000020, 000200, -32., cp0z00, 000000, 000000 ; max neg
|
|
.word 000020, 000200, -33., cp0zv0, 000000, 000000 ; 0737 like 31.
|
|
.word 000020, 000200, -60., cp0000, 000400, 004000 ; 0704 like 4.
|
|
.word 000020, 000200, -65., cp0000, 000010, 000100 ; 0677 like -1.
|
|
.word 100020, 000200, 0., cpn000, 100020, 000200
|
|
.word 100020, 000200, 1., cp00vc, 000040, 000400 ; sign! C=1
|
|
.word 100020, 000200, 10., cp00v0, 040002, 000000 ; sign!
|
|
.word 100020, 000200, 11., cpn0v0, 100004, 000000 ; sign!
|
|
.word 100020, 000200, 12., cp00vc, 000010, 000000 ; sign! C=1
|
|
.word 100020, 000200, 13., cp00v0, 000020, 000000 ; sign!
|
|
.word 100020, 000200, -1., cpn000, 140010, 000100
|
|
.word 100020, 000200, -4., cpn000, 174001, 000010
|
|
.word 100020, 000200, -5., cpn000, 176000, 100004
|
|
.word 100020, 000200, -7., cpn000, 177400, 020001
|
|
.word 100020, 000200, -8., cpn00c, 177600, 010000 ; C=1
|
|
.word 100020, 000200, -9., cpn000, 177700, 004000
|
|
.word 100020, 000200, -15., cpn000, 177777, 000040
|
|
.word 100020, 000200, -16., cpn000, 177777, 100020
|
|
.word 100020, 000200, -20., cpn000, 177777, 174001
|
|
.word 100020, 000200, -21., cpn00c, 177777, 176000 ; C=1
|
|
.word 100020, 000200, -22., cpn000, 177777, 177000
|
|
.word 100020, 000200, -30., cpn000, 177777, 177776
|
|
.word 100020, 000200, -31., cpn000, 177777, 177777
|
|
.word 100020, 000200, -32., cpn00c, 177777, 177777 ; C=1
|
|
1010$:
|
|
;
|
|
9999$: iot ; end of test D1.1
|
|
;
|
|
; Test D1.2 -- ashc odd register ++++++++++++++++++++++++++++++++++++
|
|
; Note: ashc has very non-obvious cc semantics because the non visible
|
|
; upper half plays a role. see 'h:' in data below
|
|
;
|
|
td0102: mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
mov #cp.psw,r3 ; setup psw pointer
|
|
clr r0 ; for tmu optics
|
|
100$: mov (r4)+,r1 ; load src
|
|
ashc (r4)+,r1 ; ashc
|
|
hcmpeq (r4)+,(r3) ; check psw
|
|
hcmpeq (r4)+,r1 ; check res
|
|
cmp r4,r5
|
|
blo 100$
|
|
jmp 9999$
|
|
;
|
|
; src, shift, psw, res ;
|
|
1000$: .word 000000, 0., cp0z00, 000000 ; h: 000000
|
|
.word 002010, 0., cp0000, 002010 ; h: 002010
|
|
.word 002010, 1., cp0000, 004020 ; h: 004020
|
|
.word 002010, 4., cp0000, 040200 ; h: 040200
|
|
.word 002010, 5., cpn0v0, 100400 ; sign! h: 100400
|
|
.word 002010, 6., cp00vc, 001000 ; sign! C=1 h: 001001
|
|
.word 002010, 7., cp00v0, 002000 ; sign! h: 002002
|
|
.word 002010, 11., cp00v0, 040000 ; sign! h: 040004
|
|
.word 002010, 12., cpn0v0, 100000 ; sign! h: 100100
|
|
.word 002010, 13., cp00vc, 000000 ; sign! C=1 Z=0! h: 000201
|
|
.word 002010, 14., cp00v0, 000000 ; sign! Z=0! h: 000402
|
|
.word 002010, 20., cp00v0, 000000 ; sign! Z=0! h: 040200
|
|
.word 002010, 21., cpn0v0, 000000 ; sign! N=1! Z=0! h: 100400
|
|
.word 002010, 22., cp00vc, 000000 ; sign! C=1! Z=0! h: 001000
|
|
.word 002010, 23., cp00v0, 000000 ; sign! Z=0! h: 002000
|
|
.word 002010, 27., cp00v0, 000000 ; sign! Z=0! h: 040000
|
|
.word 002010, 28., cpn0v0, 000000 ; sign! N=1! Z=0! h: 100000
|
|
.word 002010, 29., cp0zvc, 000000 ; sign! h: 000000
|
|
.word 002010, 30., cp0zv0, 000000 ; sign! h: 000000
|
|
.word 002010, -1., cp0000, 001004 ; h: 001004
|
|
.word 002010, -3., cp0000, 000201 ; h: 000201
|
|
.word 002010, -4., cp000c, 100100 ; C=1 N=0! h: 000100
|
|
.word 002010, -5., cp0000, 040040 ; h: 000040
|
|
.word 002010, -10., cp0000, 001001 ; h: 000001
|
|
.word 002010, -11., cp000c, 100400 ; C=1 N=0! h: 000000
|
|
.word 002010, -12., cp0000, 040200 ; h: 000000
|
|
.word 002010, -15., cp0000, 004020 ; h: 000000
|
|
.word 002010, -16., cp0000, 002010 ; h: 000000
|
|
.word 002010, -19., cp0000, 000201 ; h: 000000
|
|
.word 002010, -20., cp000c, 000100 ; C=1 !no rol! h: 000000
|
|
.word 002010, -21., cp0000, 000040 ; h: 000000
|
|
.word 002010, -26., cp0000, 000001 ; h: 000000
|
|
.word 002010, -27., cp0z0c, 000000 ; C=1 Z=1 h: 000000
|
|
.word 002010, -28., cp0z00, 000000 ; Z=1 h: 000000
|
|
.word 102010, 0., cpn000, 102010 ; h: 102010
|
|
.word 102010, -1., cpn000, 041004 ; N=1! h: 141004
|
|
.word 102010, -3., cpn000, 010201 ; N=1! h: 170201
|
|
.word 102010, -4., cpn00c, 104100 ; C=1 N=1! h: 174100
|
|
.word 102010, -5., cpn000, 042040 ; N=1! h: 176040
|
|
.word 102010, -10., cpn000, 001041 ; N=1! h: 177741
|
|
.word 102010, -11., cpn00c, 100420 ; C=1 N=1! h: 177760
|
|
.word 102010, -12., cpn000, 040210 ; N=1! h: 177770
|
|
.word 102010, -15., cpn000, 004021 ; N=1! h: 177777
|
|
.word 102010, -16., cpn00c, 102010 ; C=1 h: 177777
|
|
.word 102010, -17., cpn000, 141004 ; h: 177777
|
|
.word 102010, -19., cpn000, 170201 ; h: 177777
|
|
.word 102010, -20., cpn00c, 174100 ; C=1 h: 177777
|
|
.word 102010, -21., cpn000, 176040 ; h: 177777
|
|
.word 102010, -26., cpn000, 177741 ; h: 177777
|
|
.word 102010, -27., cpn00c, 177760 ; C=1 h: 177777
|
|
.word 102010, -28., cpn000, 177770 ; h: 177777
|
|
.word 102010, -31., cpn000, 177777 ; h: 177777
|
|
1010$:
|
|
;
|
|
9999$: iot ; end of test D1.2
|
|
;
|
|
; Section E: xor =============================================================
|
|
; This section verifies
|
|
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
|
|
; 0 111 100 rrr ddd ddd NZ0- XOR
|
|
;
|
|
; Test E1.1 -- xor znvc=0 ++++++++++++++++++++++++++++++++++++++++++++
|
|
; check xor with all ccs cleared; memory destination
|
|
;
|
|
te0101: mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
mov #cp.psw,r3 ; setup psw pointer
|
|
mov #200$,r1 ; setup dst pointer
|
|
100$: mov (r4)+,r0 ; load src
|
|
mov (r4)+,(r1) ; load dst
|
|
ccc ; nzvc=0
|
|
xor r0,(r1) ; xor
|
|
hcmpeq (r4)+,(r3) ; check psw
|
|
hcmpeq (r4)+,(r1) ; check
|
|
cmp r4,r5
|
|
blo 100$
|
|
jmp 9999$
|
|
;
|
|
200$: .word 0
|
|
;
|
|
; dst, src, psw, res
|
|
1000$: .word 000000, 000000, cp0z00, 000000
|
|
.word 000011, 000000, cp0000, 000011
|
|
.word 000011, 000110, cp0000, 000101
|
|
.word 000011, 001100, cp0000, 001111
|
|
.word 110000, 011000, cpn000, 101000
|
|
.word 110000, 110000, cp0z00, 000000
|
|
1010$:
|
|
;
|
|
9999$: iot ; end of test E1.1
|
|
;
|
|
; Test E1.2 -- xor znvc=1 ++++++++++++++++++++++++++++++++++++++++++++
|
|
; check xor with all ccs set; register destination
|
|
;
|
|
te0102: mov #1000$,r4 ; setup data pointer
|
|
mov #1010$,r5 ; setup end pointer
|
|
mov #cp.psw,r3 ; setup psw pointer
|
|
100$: mov (r4)+,r0 ; load src
|
|
mov (r4)+,r1 ; load dst
|
|
scc ; nzvc=1
|
|
xor r0,r1 ; xor
|
|
hcmpeq (r4)+,(r3) ; check psw
|
|
hcmpeq (r4)+,r1 ; check
|
|
cmp r4,r5
|
|
blo 100$
|
|
jmp 9999$
|
|
;
|
|
; dst, src, psw, res
|
|
1000$: .word 000000, 000000, cp0z0c, 000000
|
|
.word 000011, 000000, cp000c, 000011
|
|
.word 000011, 000110, cp000c, 000101
|
|
.word 000011, 001100, cp000c, 001111
|
|
.word 110000, 011000, cpn00c, 101000
|
|
.word 110000, 110000, cp0z0c, 000000
|
|
1010$:
|
|
;
|
|
9999$: iot ; end of test E1.2
|
|
;
|
|
; END OF ALL TESTS - loop closure ============================================
|
|
;
|
|
mov tstno,r0 ; hack, for easy monitoring ...
|
|
hcmpeq tstno,#10. ; all tests done ?
|
|
;
|
|
jmp loop
|
|
;
|
|
.end start
|