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do STKLIM check for mode 1,2,4,6 in dstr flows
- pdp11_sequencer.vhd: BUGFIX: use is_kstackdst1246 also in dstr flow - tools/asm-11/lib/ - defs_cpu.mac: rename cp.sli -> cp.slr - halt_checks.mac: add htstne, htsbne - tools/tcode - cpu_basics.mac: rename cp.sli -> cp.slr - cpu_details.mac: add Test A3: STKLIM - cpu_(eis|mmu).mac,tcode.ecmd: editorial changes
This commit is contained in:
wfjm
@@ -32,6 +32,8 @@ The full set of tests is only run for tagged releases.
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- general changes
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- rename _gpr to _gr, use 'general registers' not 'general purpose registers'
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### Bug Fixes
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- rtl/w11a
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- pdp11_sequencer: BUGFIX: use is_kstackdst1246 also in dstr flow
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<!-- --------------------------------------------------------------------- -->
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---
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@@ -1,4 +1,4 @@
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-- $Id: pdp11_sequencer.vhd 1312 2022-10-29 15:03:06Z mueller $
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-- $Id: pdp11_sequencer.vhd 1316 2022-11-18 15:26:40Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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@@ -13,6 +13,7 @@
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2022-11-18 1316 1.6.18 BUGFIX: use is_kstackdst1246 also in dstr flow
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-- 2022-10-29 1312 1.6.17 rename s_int_* -> s_vec_*, s_trap_* -> s_abort_*
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-- 2022-10-25 1309 1.6.16 rename _gpr -> _gr
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-- 2022-10-03 1301 1.6.15 finalize fix for I space mode=1 in s_dstr_def
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@@ -47,7 +48,7 @@
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-- CNTL.cpdout_we instead of CPDOUT_WE
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-- 2010-06-12 304 1.2.8 signal cpuwait when spinning in s_op_wait
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-- 2009-05-30 220 1.2.7 final removal of snoopers (were already commented)
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-- 2009-05-09 213 1.2.6 BUGFIX: use is_dstkstack1246, stklim for mode=6
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-- 2009-05-09 213 1.2.6 BUGFIX: use is_kstackdst1246, stklim for mode=6
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-- 2009-05-02 211 1.2.5 BUGFIX: 11/70 spl semantics again in kernel mode
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-- 2009-04-26 209 1.2.4 BUGFIX: give interrupts priority over trap handling
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-- 2008-12-14 177 1.2.3 BUGFIX: use is_dstkstack124, fix stklim check bug
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@@ -363,7 +364,7 @@ begin
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variable brcond : slbit := '0'; -- br condition value
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variable is_kmode : slbit := '0'; -- cmode is kernel mode
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variable is_dstkstack1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6
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variable is_kstackdst1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6
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variable int_pending : slbit := '0'; -- an interrupt is pending
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@@ -399,13 +400,15 @@ begin
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pwstate : in state_type;
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pbytop : in slbit := '0';
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pmacc : in slbit := '0';
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pispace : in slbit := '0') is
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pispace : in slbit := '0';
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kstack : in slbit := '0') is
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begin
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pnvmcntl.dspace := not pispace;
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-- bytop := R_IDSTAT.is_bytop and not is_addr;
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pnvmcntl.bytop := pbytop;
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pnvmcntl.macc := pmacc;
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pnvmcntl.req := '1';
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pnvmcntl.bytop := pbytop;
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pnvmcntl.macc := pmacc;
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pnvmcntl.kstack := kstack;
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pnvmcntl.req := '1';
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pnstate := pwstate;
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end procedure do_memread_d;
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@@ -639,14 +642,14 @@ begin
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brcond := '1';
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is_kmode := '0';
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is_dstkstack1246 := '0';
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is_kstackdst1246 := '0';
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if PSW.cmode = c_psw_kmode then
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is_kmode := '1';
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if DSTREG = c_gr_sp and
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(DSTMODF="001" or DSTMODF="010" or
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DSTMODF="100" or DSTMODF="110") then
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is_dstkstack1246 := '1';
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is_kstackdst1246 := '1';
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end if;
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end if;
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@@ -1192,7 +1195,8 @@ begin
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ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
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do_memread_d(nstate, nvmcntl, s_dstr_def_w,
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pbytop=>R_IDSTAT.is_bytop, pmacc=>R_IDSTAT.is_rmwop,
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pispace=>R_IDSTAT.is_dstpcmode1);
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pispace=>R_IDSTAT.is_dstpcmode1,
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kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
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when s_dstr_def_w => -- -----------------------------------
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nstate := s_dstr_def_w;
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@@ -1217,7 +1221,8 @@ begin
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macc := R_IDSTAT.is_rmwop and not DSTDEF;
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bytop := R_IDSTAT.is_bytop and not DSTDEF;
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do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
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pbytop=>bytop, pmacc=>macc, pispace=>R_IDSTAT.is_dstpc);
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pbytop=>bytop, pmacc=>macc, pispace=>R_IDSTAT.is_dstpc,
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kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
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when s_dstr_inc_w => -- -----------------------------------
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nstate := s_dstr_inc_w;
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@@ -1252,7 +1257,8 @@ begin
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macc := R_IDSTAT.is_rmwop and not DSTDEF;
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bytop := R_IDSTAT.is_bytop and not DSTDEF;
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do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
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pbytop=>bytop, pmacc=>macc);
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pbytop=>bytop, pmacc=>macc,
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kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
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when s_dstr_ind => -- -----------------------------------
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do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w);
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@@ -1278,7 +1284,8 @@ begin
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macc := R_IDSTAT.is_rmwop and not DSTDEF;
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bytop := R_IDSTAT.is_bytop and not DSTDEF;
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do_memread_d(nstate, nvmcntl, s_dstr_ind2_w,
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pbytop=>bytop, pmacc=>macc);
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pbytop=>bytop, pmacc=>macc,
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kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
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when s_dstr_ind2_w => -- -----------------------------------
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nstate := s_dstr_ind2_w;
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@@ -1335,12 +1342,12 @@ begin
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-- s_dstw_def246 wreq @n(r)
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-- s_dstw_def_w ack @n(r)
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-- -> do_fork_next
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when s_dstw_def => -- -----------------------------------
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ndpcntl.psr_ccwe := '1';
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ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
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ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
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nvmcntl.kstack := is_dstkstack1246;
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nvmcntl.kstack := is_kstackdst1246;
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do_memwrite(nstate, nvmcntl, s_dstw_def_w, pispace=>R_IDSTAT.is_dstpc);
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when s_dstw_def_w => -- -----------------------------------
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@@ -1359,7 +1366,7 @@ begin
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ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else)
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if DSTDEF = '0' then
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ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
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nvmcntl.kstack := is_dstkstack1246;
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nvmcntl.kstack := is_kstackdst1246;
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do_memwrite(nstate, nvmcntl, s_dstw_inc_w, pispace=>R_IDSTAT.is_dstpc);
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nstatus.do_grwe := '1';
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else
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@@ -1421,7 +1428,7 @@ begin
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ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
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ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = from idec (for if)
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if DSTDEF = '0' then
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nvmcntl.kstack := is_dstkstack1246;
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nvmcntl.kstack := is_kstackdst1246;
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do_memwrite(nstate, nvmcntl, s_dstw_def_w);
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else
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do_memread_d(nstate, nvmcntl, s_dstw_incdef_w);
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@@ -1,11 +1,11 @@
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; $Id: defs_cpu.mac 1184 2019-07-10 20:39:44Z mueller $
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; $Id: defs_cpu.mac 1316 2022-11-18 15:26:40Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2014-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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; Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; definitions for basic CPU registers (as in defs_cpu.das)
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;
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cp.psw=177776
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cp.sli=177774 ; stack limit
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cp.slr=177774 ; stack limit
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cp.pir=177772 ; pirq
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cp.mbr=177770 ; mbrk
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cp.err=177766 ; cpuerr
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@@ -1,4 +1,4 @@
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; $Id: halt_checks.mac 1262 2022-07-25 09:44:55Z mueller $
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; $Id: halt_checks.mac 1316 2022-11-18 15:26:40Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -40,3 +40,15 @@
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beq .+4
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halt
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.endm
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; tst on ne
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.macro htstne,src
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tst src
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bne .+4
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halt
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.endm
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; tstb on ne
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.macro htsbne,src
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tstb src
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bne .+4
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halt
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.endm
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@@ -1,4 +1,4 @@
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; $Id: cpu_basics.mac 1287 2022-08-27 09:40:43Z mueller $
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; $Id: cpu_basics.mac 1316 2022-11-18 15:26:40Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -3005,13 +3005,13 @@ tf0201: mov #cp.psw,r0
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hbitne #kl.ie,kl.csr ; check that kl.ie bit is set
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movb #bit01,cp.pir+1 ; set PIRQ bit
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hcmbeq #bit01,cp.pir+1 ; check
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mov #400,cp.sli ; bump STKLIM
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hcmpeq #400,cp.sli ; check
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mov #400,cp.slr ; bump STKLIM
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hcmpeq #400,cp.slr ; check
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;
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reset ; and RESET
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hbiteq #kl.ie,kl.csr ; check that kl.ie bit is cleared
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htsbeq cp.pir+1 ; check that PIRQ cleared
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htsteq cp.sli ; check that STKLIM cleared
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htsteq cp.slr ; check that STKLIM cleared
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ccc ; clear cc
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hcmpeq (r0),#cp.pr7 ; check that prio still 7 (CPU not(!) reset)
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clr (r0) ; back to normal
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@@ -1,10 +1,10 @@
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; $Id: cpu_details.mac 1305 2022-10-23 07:44:21Z mueller $
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; $Id: cpu_details.mac 1316 2022-11-18 15:26:40Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-07-28 1264 1.0 Initial version
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; 2022-11-18 1316 1.0 Initial version
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; 2022-07-18 1259 0.1 First draft
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;
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; Test CPU details
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@@ -355,6 +355,180 @@ ta0210: cmpb systyp,#sy.sih ; this fatal stack error fails in SimH
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; end of A2.* tests, restore iit handler
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mov v..iit+2,v..iit ; restore iit handler
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;
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; Test A3: STKLIM +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies operation of STKLIM register
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; and the yellow stack trap and red stack abort functionality.
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;
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; Test A3.1 -- STKLIM write/read test ++++++++++++++++++++++++++++++++
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; STKLIM is a 16 bit register, upper byte is retained, lower reads always 0
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;
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ta0301: mov #1000$,r0 ; ptr to value list
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mov #<1010$-1000$>/2,r1 ; # of values
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mov #377,r2 ; LSB byte mask
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mov #cp.slr,r3 ; ptr to STKLIM
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;
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100$: mov (r0)+,r4 ; get value
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mov r4,(r3) ; load STKLIM
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bic r2,r4 ; clear LSB
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hcmpeq r4,(r3) ; read and ckeck STKLIM
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sob r1,100$ ; go for next STKLIM value
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br 9999$
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;
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1000$: .word ^b0101010101010101
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.word ^b1010101010101010
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.word ^b0000000011001100 ; STKLIM = 0 at end of test
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1010$:
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;
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9999$: iot ; end of test A3.1
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;
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; Test A3.2 -- yellow trap + red abort boundary ++++++++++++++++++++++
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; Verifies push to STKLIM+376 to STKLIM+340 causes a yellow trap
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; and a push to STKLIM+336 causes a red stack abort for STKLIM
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; 0 yellow below 000400
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; 1400 yellow below 002000
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; 157400 yellow below 156000
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;
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ta0302: mov #2000$,r0 ; ptr to value list
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mov #<2010$-2000$>/2,r1 ; # of values
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mov #1000$,v..iit ; set up iit handler
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clr v..iit+2
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;
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100$: mov (r0)+,r5 ; get value
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mov r5,cp.slr ; load STKLIM
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clr 336(r5) ; clear word on red boundary
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mov r5,sp ; load SP
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add #400,sp ; to yellow boundary
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clr r2 ; clear yellow trap counter
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mov #1.,-(sp) ; push to STKLIM+376 -> trap
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mov #2.,-(sp) ; push to STKLIM+374 -> trap
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mov #3.,-(sp) ; push to STKLIM+372 -> trap
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mov #4.,-(sp) ; push to STKLIM+370 -> trap
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mov #5.,-(sp) ; push to STKLIM+366 -> trap
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mov #6.,-(sp) ; push to STKLIM+364 -> trap
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mov #7.,-(sp) ; push to STKLIM+362 -> trap
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mov #8.,-(sp) ; push to STKLIM+360 -> trap
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mov #9.,-(sp) ; push to STKLIM+356 -> trap
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mov #10.,-(sp) ; push to STKLIM+354 -> trap
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mov #11.,-(sp) ; push to STKLIM+352 -> trap
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mov #12.,-(sp) ; push to STKLIM+350 -> trap
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mov #13.,-(sp) ; push to STKLIM+346 -> trap
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mov #14.,-(sp) ; push to STKLIM+344 -> trap
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sub #6,sp ; avoid abort in vector flow
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mov #123456,-(sp) ; push to STKLIM+336 -> abort
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halt
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;
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1000$: clr cp.err ; HACK: clear CPUERR !!!
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tst sp
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beq 1010$
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inc r2
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rti
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1010$: hcmpeq #14.,r2 ; all traps taken ?
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htsteq 336(r5) ; red zone border clean ?
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sob r1,100$ ; go for next STKLIM value
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;
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clr cp.slr ; STKLIM to default
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mov #stack,sp ; SP to default
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mov #v..iit+2,v..iit ; v..iit to catcher
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br 9999$
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;
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2000$: .word 000000
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.word 001400
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.word 157400
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2010$:
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;
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9999$: iot ; end of test A3.2
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;
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; Test A3.3 -- stack trap address modes ++++++++++++++++++++++++++++++
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; Verifies that mode 1,2,4,6 trap for dstw flows and dstr when rmw
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; Verifies that mode 3,5,7 writes do not trap
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; Verifies that mode 1-7 reads do not trap
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; Notes:
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; - dstw (mov,clr,..) and dstr (add,bis,...) flows write to stack -> test both
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; - inspired by eqkce0 test 041 that verifies do/dont trap instruction cases
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; - SimH and e11 currently do not support full 11/70 mode semantics
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;
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ta0303: tstb systyp ; skip if not on w11
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bge 100$
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jmp 9999$
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;
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100$: mov #1000$,v..iit ; set up iit handler
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clr v..iit+2
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mov #1100$,v..emt ; set up emt handler
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clr v..emt+2
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mov #1200$,v..trp ; set up trap handler
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clr v..trp+2
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mov #1400,cp.slr ; set yellow limit to 1776
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clr r2 ; clear trap counter
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;
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; part 1: test instructions that should trap -------------------------
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;
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; dstw mode 1,2,4,6
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mov #1000,-(sp) ; dstw mode 4: SP now 1776 (1)
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clr -(sp) ; dstw mode 4: SP now 1774 (2)
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mov (sp),(sp) ; dstw mode 1: SP now 1774 (3)
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clr (sp) ; dstw mode 1: SP now 1774 (4)
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mov (sp),(sp)+ ; dstw mode 2: SP now 1776 (5)
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clr 0(sp) ; dstw mode 6: SP now 1776 (6)
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mov (sp),0(sp) ; dstw mode 6: SP now 1776 (7)
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; implied push
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jsr pc,1300$ ; implied push: SP now 1176 (8)
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mfpi r0 ; implied push: SP now 1774 (9)
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; trap instrunctions
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emt 100 ; trap push: SP now 1174 (10)
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trap 200 ; trap push: SP now 1174 (11)
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; dstr mode 1,2,4,6 when rmw
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add (sp),(sp) ; dstr mode 1: SP now 1174 (12)
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bis (sp),-(sp) ; dstr mode 4: SP now 1172 (13)
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incb (sp)+ ; dstr mode 2: SP now 1174 (14)
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dec 0(sp) ; dstr mode 6: SP now 1174 (15)
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;
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br 1500$
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;
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1000$: clr cp.err ; HACK: clear CPUERR !!!
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htstne sp ; no red stack aborts expected
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inc r2
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rti
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;
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1100$: rti ; dummy emt handler
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1200$: rti ; dummy trap handler
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1300$: rts pc ; dummy routine
|
||||
;
|
||||
1500$: hcmpeq #15.,r2 ; all traps taken ?
|
||||
mov #v..iit+2,v..iit ; v..iit to catcher
|
||||
mov #v..emt+2,v..emt ; v..emt to catcher
|
||||
mov #v..trp+2,v..trp ; v..trp to catcher
|
||||
;
|
||||
; part 2: test instructions that should not trap ---------------------
|
||||
;
|
||||
mov #stack-2,r2 ; in yellow zone
|
||||
mov r2,(r2) ; load on stack (not using SP)
|
||||
mov r2,sp ; SP in yellow zone
|
||||
; dstw mode 3,5,7
|
||||
mov (sp)+,@-(sp) ; dstw mode 5: SP now 1176
|
||||
mov @0(sp),@(sp)+ ; dstw mode 3: SP now 1200
|
||||
mov -(sp),@0(sp) ; dstw mode 7: SP now 1176
|
||||
; dstr mode 3,5,7 when rmw
|
||||
bis (sp)+,@-(sp) ; dstw mode 5: SP now 1176
|
||||
bis @0(sp),@(sp)+ ; dstw mode 3: SP now 1200
|
||||
bis -(sp),@0(sp) ; dstw mode 7: SP now 1176
|
||||
; dstr mode 1,2,4,6 in read-only
|
||||
tst (sp) ; dstr mode 1: SP now 1176
|
||||
cmp (sp),-(sp) ; dstr mode 4: SP now 1174
|
||||
cmp (sp),(sp)+ ; dstr mode 2: SP now 1176
|
||||
cmp (sp),0(sp) ; dstr mode 6: SP now 1176
|
||||
; dstr mode 3,5,7 in read-only
|
||||
cmp (sp),@(sp)+ ; dstr mode 3: SP now 1200
|
||||
cmp (sp),@-(sp) ; dstr mode 5: SP now 1176
|
||||
cmp (sp),@0(sp) ; dstr mode 7: SP now 1176
|
||||
; check that EA is compared against STKLIM
|
||||
clr sp
|
||||
mov @#2000,2000(sp) ; SP=0, EA=2000 -> no trap
|
||||
;
|
||||
clr cp.slr ; STKLIM to default
|
||||
mov #stack,sp ; SP to default
|
||||
;
|
||||
9999$: iot ; end of test A3.3
|
||||
;
|
||||
; Section B: Stress tests ====================================================
|
||||
;
|
||||
; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++
|
||||
@@ -565,7 +739,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler
|
||||
; END OF ALL TESTS - loop closure ============================================
|
||||
;
|
||||
mov tstno,r0 ; hack, for easy monitoring ...
|
||||
hcmpeq tstno,#19. ; all tests done ?
|
||||
hcmpeq tstno,#22. ; all tests done ?
|
||||
;
|
||||
jmp loop
|
||||
;
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
; $Id: cpu_eis.mac 1264 2022-07-30 07:42:17Z mueller $
|
||||
; $Id: cpu_eis.mac 1314 2022-11-09 10:55:29Z mueller $
|
||||
; SPDX-License-Identifier: GPL-3.0-or-later
|
||||
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
;
|
||||
@@ -688,7 +688,7 @@ te0101: mov #1000$,r4 ; setup data pointer
|
||||
;
|
||||
9999$: iot ; end of test E1.1
|
||||
;
|
||||
; Test X1.2 -- xor znvc=1 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Test E1.2 -- xor znvc=1 ++++++++++++++++++++++++++++++++++++++++++++
|
||||
; check xor with all ccs set; register destination
|
||||
;
|
||||
te0102: mov #1000$,r4 ; setup data pointer
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
; $Id: cpu_mmu.mac 1311 2022-10-29 12:57:38Z mueller $
|
||||
; $Id: cpu_mmu.mac 1313 2022-11-04 14:01:08Z mueller $
|
||||
; SPDX-License-Identifier: GPL-3.0-or-later
|
||||
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
;
|
||||
@@ -1573,8 +1573,8 @@ te0102: mov #vhmmut,v..mmu ; setup MMU trap handler
|
||||
;
|
||||
; case r-abo: read, abort
|
||||
1200$: mov #vhmmua,v..mmu ; setup MMU abort handler
|
||||
mov (r5)+,1210$
|
||||
mov #1210$,(r2)
|
||||
mov (r5)+,1210$
|
||||
mov #1210$,(r2)
|
||||
tst (r3) ; probe read
|
||||
halt ; expect abort
|
||||
1210$: .word 0,0
|
||||
@@ -1593,16 +1593,16 @@ te0102: mov #vhmmut,v..mmu ; setup MMU trap handler
|
||||
;
|
||||
; case w-abo: write, abort
|
||||
1500$: mov #vhmmua,v..mmu ; setup MMU abort handler
|
||||
mov (r5)+,1510$
|
||||
mov #1510$,(r2)
|
||||
add r0,(r3) ; probe write
|
||||
mov (r5)+,1510$
|
||||
mov #1510$,(r2)
|
||||
add r0,(r3) ; probe write
|
||||
halt ; expect abort
|
||||
1510$: .word 0,0
|
||||
br 1910$ ; to tr-check
|
||||
;
|
||||
; case w-trap: write, trap
|
||||
1600$: mov #vhmmut,v..mmu ; setup MMU trap handler
|
||||
mov #1900$,(r2)
|
||||
mov #1900$,(r2)
|
||||
clr (r3) ; probe write
|
||||
halt ; expect trap
|
||||
;
|
||||
|
||||
@@ -1,25 +1,25 @@
|
||||
! $Id: tcode.ecmd 1311 2022-10-29 12:57:38Z mueller $
|
||||
! SPDX-License-Identifier: GPL-3.0-or-later
|
||||
! Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
!
|
||||
! setup w11 like processor configuration
|
||||
! set nouwin to disable UNIBUS window (17000000-17757777) to UNIBUS map
|
||||
! set memory to 3840
|
||||
! this way e11 behaves like w11 and SimH, which simplifies tcodes
|
||||
!
|
||||
; $Id: tcode.ecmd 1313 2022-11-04 14:01:08Z mueller $
|
||||
; SPDX-License-Identifier: GPL-3.0-or-later
|
||||
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
;
|
||||
; setup w11 like processor configuration
|
||||
; set nouwin to disable UNIBUS window (17000000-17757777) to UNIBUS map
|
||||
; set memory to 3840
|
||||
; this way e11 behaves like w11 and SimH, which simplifies tcodes
|
||||
;
|
||||
set cpu 70
|
||||
set cpu nouwin
|
||||
set memory 3840
|
||||
set cpu nofpp
|
||||
set idle delay=1
|
||||
! set ^E as break character (like in SimH)
|
||||
; set ^E as break character (like in SimH)
|
||||
set break 005
|
||||
! enable PC value logging (inspect with show pclog)
|
||||
; enable PC value logging (inspect with show pclog)
|
||||
set pclog on
|
||||
! set sysid, leading '1' indicates simulator, next '2' e11
|
||||
; set sysid, leading '1' indicates simulator, next '2' e11
|
||||
set cpu SYSID=0120345
|
||||
!
|
||||
! create log file, the only way to capture e11 output
|
||||
! no rediction to stdout possible
|
||||
!
|
||||
;
|
||||
; create log file, the only way to capture e11 output
|
||||
; no rediction to stdout possible
|
||||
;
|
||||
log tt0: tmp_e11_tt0
|
||||
|
||||
Reference in New Issue
Block a user