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38 lines
1.4 KiB
Tcl
38 lines
1.4 KiB
Tcl
# -*- tcl -*-
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# $Id: cdc_vector_s0.xdc 1190 2019-07-13 17:05:39Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# cdc constraints for cdc_vector_s0
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#
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# Revision History:
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# Date Rev Version Comment
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# 2019-01-02 1101 1.1 contrain on both input and output clock period
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# 2016-04-08 759 1.0 Initial version
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#
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# The following determines the input clock assuming that the synchronizer is
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# directly connected to a register. Will not work when logic is inbetween or
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# when driven by a dual-clocked BRAM.
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set clki [get_clocks -of_objects \
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[get_cells -of_objects \
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[get_pins -filter {DIRECTION==OUT && IS_LEAF==1} -of_objects \
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[get_nets -segments -of_objects \
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[get_ports -scoped_to_current_instance {DI[0]} ] ] ] ] ]
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set clko [get_clocks -of_objects [get_cells {R_DO_S0_reg[*]} ] ]
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set clki_per50 [expr {0.5 * [get_property -min PERIOD $clki]}]
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set clko_per50 [expr {0.5 * [get_property -min PERIOD $clko]}]
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set maxdly [expr { min($clki_per50,$clko_per50) }]
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#
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# CLKI->CLKO
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# Ensure delay and thus skew of the DI->R_DO datapath is smaller than
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# 80% of both the input and the output clock period. That should be
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# save in all usage modes.
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set_max_delay \
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-from $clki \
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-to [get_cells {R_DO_S0_reg[*]}] \
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-datapath_only $maxdly
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