mirror of
https://github.com/wfjm/w11.git
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c7e606d9b0
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port - pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer - sys_w11a_*.vhd: use DM_STAT_EXP - some re-wiring, no functional change to CPU or IO system
117 lines
3.4 KiB
VHDL
117 lines
3.4 KiB
VHDL
-- $Id: pdp11_dspmux.vhd 1055 2018-10-12 17:53:52Z mueller $
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--
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-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_dspmux - syn
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-- Description: pdp11: hio dsp mux
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--
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-- Dependencies: -
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
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-- 2015-02-22 650 1.0 Initial version
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-- 2015-02-21 649 0.1 First draft
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------------------------------------------------------------------------------
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-- selects display data
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-- 4 Digit Displays
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-- SEL(1:0) 00 ABCLKDIV
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-- 01 DM_STAT_EXP.dp_pc
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-- 10 DISPREG
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-- 11 DM_STAT_EXP.dp_dsrc
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--
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-- 8 Digit Displays
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-- SEL(1) select DSP(7:4)
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-- 0 ABCLKDIV
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-- 1 DM_STAT_EXP.dp_pc
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-- SEL(0) select DSP(7:4)
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-- 0 DISPREG
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-- 1 DM_STAT_EXP.dp_dsrc
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.pdp11.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_dspmux is -- hio dsp mux
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generic (
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DCWIDTH : positive := 2); -- digit counter width (2 or 3)
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port (
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SEL : in slv2; -- select
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ABCLKDIV : in slv16; -- serport clock divider
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DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
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DISPREG : in slv16; -- display register
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DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
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);
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end pdp11_dspmux;
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architecture syn of pdp11_dspmux is
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subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16;
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subtype dspdat_lsb is integer range 15 downto 0;
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begin
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assert DCWIDTH=2 or DCWIDTH=3
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report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
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severity failure;
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proc_mux: process (SEL, ABCLKDIV, DM_STAT_EXP, DISPREG)
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variable idat : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
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begin
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idat := (others=>'0');
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if DCWIDTH = 2 then
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case SEL is
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when "00" =>
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idat(dspdat_lsb) := ABCLKDIV;
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when "01" =>
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idat(dspdat_lsb) := DM_STAT_EXP.dp_pc;
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when "10" =>
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idat(dspdat_lsb) := DISPREG;
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when "11" =>
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idat(dspdat_lsb) := DM_STAT_EXP.dp_dsrc;
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when others => null;
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end case;
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else
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if SEL(1) = '0' then
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idat(dspdat_msb) := ABCLKDIV;
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else
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idat(dspdat_msb) := DM_STAT_EXP.dp_pc;
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end if;
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if SEL(0) = '0' then
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idat(dspdat_lsb) := DISPREG;
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else
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idat(dspdat_lsb) := DM_STAT_EXP.dp_dsrc;
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end if;
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end if;
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DSP_DAT <= idat;
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end process proc_mux;
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end syn;
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