wfjm 14362b2a56 Add basic DDR memory support ...

- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model

2018-12-31 10:00:14 +01:00

..

viv_default_build.tcl

Fix license disclaimer

2016-12-26 21:27:33 +01:00

viv_default_config.tcl

Fix license disclaimer

2016-12-26 21:27:33 +01:00

viv_default_model.tcl

Fix license disclaimer

2016-12-26 21:27:33 +01:00

viv_init.tcl

Fix license disclaimer

2016-12-26 21:27:33 +01:00

viv_tools_build.tcl

Add basic DDR memory support

2018-12-31 10:00:14 +01:00

viv_tools_config.tcl

code and comment cosmetics

2017-05-07 18:54:16 +02:00

viv_tools_model.tcl

code and comment cosmetics

2017-05-07 18:54:16 +02:00