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59 lines
1.8 KiB
Tcl
59 lines
1.8 KiB
Tcl
# -*- tcl -*-
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# $Id: fifo_2c_dram2.xdc 1190 2019-07-13 17:05:39Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# cdc constraints for fifo_2c_dram2 core
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#
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# Revision History:
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# Date Rev Version Comment
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# 2016-04-17 761 1.1 add false path for hold time through DRAM
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# 2016-03-26 752 1.0 Initial version
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#
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set clkw [get_clocks -of_objects [get_cells RW_RADDR_S0_reg[0]]]
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set clkr [get_clocks -of_objects [get_cells RR_WADDR_S0_reg[0]]]
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set clkw_per80 [expr {0.8 * [get_property -min PERIOD $clkw]}]
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set clkr_per80 [expr {0.8 * [get_property -min PERIOD $clkr]}]
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#
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# CLKR->CLKW
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# read address
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set_max_delay \
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-from [get_cells -regexp "GCR/.*/R_DATA_reg.*"] \
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-to [get_cells -regexp "RW_RADDR_S0_reg.*"] \
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-datapath_only $clkw_per80
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# reset
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set_max_delay \
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-from $clkr \
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-to [get_cells -regexp "RW_(RSTW_E|RSTR)_S0_reg.*"] \
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-datapath_only $clkw_per80
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#
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# CLKW->CLKR
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# read address
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set_max_delay \
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-from [get_cells -regexp "GCW/.*/R_DATA_reg.*"] \
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-to [get_cells -regexp "RR_WADDR_S0_reg.*"] \
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-datapath_only $clkr_per80
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# reset
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set_max_delay \
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-from $clkw \
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-to [get_cells -regexp "RR_(RSTR_E|RSTW)_S0_reg.*"] \
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-datapath_only $clkr_per80
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#
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# handle path from write clock to data output of dual port distributed RAM it's
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# conceptualy a false path (this timing should not be relevant). To be on the
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# save side only hold timing is set as false path and a set set_max_delay with
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# read side period is used to constrain setup time.
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#
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set_max_delay \
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-from $clkw \
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-to $clkr \
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-through [get_cells -regexp "RAM/.*"] \
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[get_property -min PERIOD $clkr]
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set_false_path -hold \
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-from $clkw \
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-to $clkr \
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-through [get_cells -regexp "RAM/.*"]
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