mirror of
https://github.com/wfjm/w11.git
synced 2026-01-15 00:12:31 +00:00
cbd8ce3468
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
84 lines
2.7 KiB
Makefile
84 lines
2.7 KiB
Makefile
# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
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#
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# 'Meta Makefile' for whole retro project
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# allows to make all synthesis targets
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# allows to make all test bench targets
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#
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# Revision History:
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# Date Rev Version Comment
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# 2012-12-29 466 1.0.5 add tst_rlink_cuff
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# 2011-12-26 445 1.0.4 add tst_fx2loop
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# 2011-12-23 444 1.0.3 enforce -j 1 in sub-makes
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# 2011-11-27 433 1.0.2 add new nexys3 ports
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# 2011-11-18 426 1.0.1 add tst_serport and tst_snhumanio
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# 2011-07-09 391 1.0 Initial version
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#
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SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic
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SYN_all += rtl/sys_gen/tst_fx2loop/nexys2/ic3
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SYN_all += rtl/sys_gen/tst_rlink/nexys2
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SYN_all += rtl/sys_gen/tst_rlink/nexys3
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SYN_all += rtl/sys_gen/tst_rlink/s3board
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SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
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SYN_all += rtl/sys_gen/tst_serloop/nexys2
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SYN_all += rtl/sys_gen/tst_serloop/nexys3
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SYN_all += rtl/sys_gen/tst_serloop/s3board
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SYN_all += rtl/sys_gen/tst_snhumanio/atlys
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SYN_all += rtl/sys_gen/tst_snhumanio/nexys2
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SYN_all += rtl/sys_gen/tst_snhumanio/nexys3
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SYN_all += rtl/sys_gen/tst_snhumanio/s3board
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SYN_all += rtl/sys_gen/w11a/nexys2
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SYN_all += rtl/sys_gen/w11a/nexys3
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SYN_all += rtl/sys_gen/w11a/s3board
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SIM_all += rtl/bplib/nxcramlib/tb
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SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb
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SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb
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SIM_all += rtl/sys_gen/tst_rlink/s3board/tb
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SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb
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SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb
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SIM_all += rtl/sys_gen/tst_serloop/s3board/tb
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SIM_all += rtl/sys_gen/w11a/nexys2/tb
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SIM_all += rtl/sys_gen/w11a/nexys3/tb
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SIM_all += rtl/sys_gen/w11a/s3board/tb
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SIM_all += rtl/vlib/rlink/tb
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SIM_all += rtl/vlib/serport/tb
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SIM_all += rtl/w11a/tb
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#
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.PHONY : all clean clean_sim clean_sym all_sim all_syn
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.PHONY : $(SYN_all) $(SIM_all)
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#
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all :
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@echo "no default action defined, use"
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@echo " make -j 4 all_sim"
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@echo " make -j 4 all_syn"
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@echo " make clean"
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@echo " make clean_sim"
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@echo " make clean_syn"
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#
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#
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clean : clean_sim clean_syn
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#
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clean_sim :
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for dir in $(SIM_all); do $(MAKE) -C $$dir clean; done
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clean_syn :
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for dir in $(SYN_all); do $(MAKE) -C $$dir clean; done
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#
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all_sim : $(SIM_all)
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#
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all_syn : $(SYN_all)
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@if [ -n "`find -name "*_par.log" | xargs grep -L 'All constraints were met'`" ] ; then \
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echo "++++++++++ some designs have no timing closure: ++++++++++"; \
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find -name "*_par.log" | xargs grep -L 'All constraints were met'; \
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echo "++++++++++ ++++++++++++++++++++++++++++++++++++ ++++++++++"; \
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fi
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#
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# Neither ghdl nor xst allow multiple parallel compiles in one directory.
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# The following ensures that the sub-makes are called with -j 1 and will
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# not try to run multiple compiles on one directory.
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#
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$(SIM_all):
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$(MAKE) -j 1 -C $@
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$(SYN_all):
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$(MAKE) -j 1 -C $@
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#
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