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This commit is contained in:
Marcel 2020-06-01 16:48:07 +02:00
parent c525056fb3
commit 0162f5d885
10 changed files with 4258 additions and 31 deletions
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42
Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/PKWARS_MiST.qsf
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@ -44,24 +44,6 @@ set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name SYSTEMVERILOG_FILE rtl/PKWARS_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/FPGA_PKWARS.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_VIDEO.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_SPRITE.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_SND.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_ROMARB.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_CLKGEN.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_HVGEN.v
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep_mod.vhd
set_global_assignment -name VHDL_FILE rtl/col.vhd
set_global_assignment -name VERILOG_FILE rtl/mems.v
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024.v
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
@ -242,4 +224,28 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# end ENTITY(PKWARS_MiST)
# -----------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/PKWARS_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/FPGA_PKWARS.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_VIDEO.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_SPRITE.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_SND.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_ROMARB.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_CLKGEN.v
set_global_assignment -name VERILOG_FILE rtl/PKWARS_HVGEN.v
set_global_assignment -name VHDL_FILE rtl/col.vhd
set_global_assignment -name VERILOG_FILE rtl/mems.v
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024.v
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/YM2149.vhd
set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/vol_table_array.vhd
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep_mod.vhd
set_global_assignment -name VHDL_FILE meta/gfx1.vhd
set_global_assignment -name VHDL_FILE meta/gfx2.vhd
set_global_assignment -name VHDL_FILE meta/gfx3.vhd
set_global_assignment -name VHDL_FILE meta/gfx4.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/meta/gfx1.vhd Normal file
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Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/meta/gfx2.vhd Normal file
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Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/meta/gfx3.vhd Normal file
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Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/meta/gfx4.vhd Normal file
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2
Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_MiST.sv
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@ -103,7 +103,7 @@ wire [13:0] gfx_rom_addr;
wire [31:0] gfx_rom_do;
wire [24:0] bg_ioctl_addr = ioctl_addr - 17'h8000;
wire [24:0] bg_ioctl_addr = ioctl_addr - 17'h10000;
reg port1_req, port2_req;
sdram sdram(

25
Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_ROMARB.v
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@ -16,13 +16,32 @@ module PKWARS_ROMS
input [31:0]gfx_rom_do
);
always @( posedge CLK ) PHASE <= PHASE+1;
always @( negedge CLK ) PHASE <= PHASE+1;
/*
wire [7:0] gfx1_do, gfx2_do, gfx3_do;
wire [7:0] gfx4_do = gfx_rom_do[31:24];
wire [31:0] gfx_do = {gfx4_do,gfx3_do,gfx2_do,gfx1_do};
gfx1 gfx1(
.clk(CLKx2),
.addr(AD),
.data(gfx1_do)
);
reg sd;
gfx2 gfx2(
.clk(CLKx2),
.addr(AD),
.data(gfx2_do)
);
gfx3 gfx3(
.clk(CLKx2),
.addr(AD),
.data(gfx3_do)
);*/
wire [13:0] AD = sd ? SPCAD : BGCAD;
reg sd;
assign gfx_rom_addr = AD;
always @( negedge CLKx2 ) begin

18
Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_SND.v
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@ -124,6 +124,24 @@ YM2149m sg
.I_IOA(IA),.I_IOB(IB),
.ENA(1'b1),.RESET_L(~RST),.CLK(CLK),.ACLK(ACLK)
);
/*
YM2149 sg(
.I_DA(ID),
.O_DA(OD),
.I_A9_L(~CS),
.I_BDIR(bd),
.I_BC1(bc),
.I_A8(1'b1),
.I_BC2(1'b1),
.I_SEL_L(1'b1),
.O_AUDIO(Sx),
.O_CHAN(Sc),
.I_IOA(IA),
.I_IOB(IB),
.ENA(1'b1),
.RESET_L(~RST),
.CLK(ACLK)
);*/
assign SO = SA+SB+SC;

2
Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/PKWARS_VIDEO.v
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@ -70,7 +70,7 @@ wire [4:0] PALAD;
wire [7:0] PALDT;
col col(
.clk(VCLKx4),
.clk(VCLK),
.addr(PALAD),
.data(PALDT)
);

16
Arcade_MiST/Nova2001_Hardware/Penguin-Kun Wars_MiST/rtl/pll.v
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@ -102,9 +102,9 @@ module pll (
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3,
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 8,
altpll_component.clk1_multiply_by = 16,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
@ -180,11 +180,11 @@ endmodule
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "72.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "48.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@ -210,10 +210,10 @@ endmodule
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "72.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "48.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
@ -263,9 +263,9 @@ endmodule
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"