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https://github.com/Gehstock/Mist_FPGA.git
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Nova2001: get rid of dataselector.v
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@@ -40,7 +40,7 @@
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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@@ -241,5 +241,5 @@ set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/vol_table_arr
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set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/YM2149.vhd
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
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set_global_assignment -name VERILOG_FILE rtl/dataselector.v
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set_global_assignment -name SMART_RECOMPILE ON
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@@ -1,70 +0,0 @@
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module dataselector_3D_8B
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(
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output [7:0] out,
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input [7:0] df,
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input en0,
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input [7:0] dt0,
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input en1,
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input [7:0] dt1,
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input en2,
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input [7:0] dt2
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);
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assign out = en0 ? dt0 :
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en1 ? dt1 :
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en2 ? dt2 :
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df;
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endmodule
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module dataselector_5D_8B
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(
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output [7:0] out,
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input en0,
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input [7:0] dt0,
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input en1,
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input [7:0] dt1,
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input en2,
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input [7:0] dt2,
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input en3,
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input [7:0] dt3,
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input en4,
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input [7:0] dt4
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);
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assign out = en0 ? dt0 :
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en1 ? dt1 :
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en2 ? dt2 :
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en3 ? dt3 :
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en4 ? dt4 :
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8'hFF;
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endmodule
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module dataselector_4D_9B
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(
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output [8:0] OUT,
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input EN1,
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input [8:0] IN1,
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input EN2,
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input [8:0] IN2,
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input EN3,
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input [8:0] IN3,
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input EN4,
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input [8:0] IN4,
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input [8:0] IND
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);
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assign OUT = EN1 ? IN1:
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EN2 ? IN2:
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EN3 ? IN3:
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EN4 ? IN4:
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IND;
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endmodule
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@@ -103,19 +103,12 @@ dpram #(8,10) bgv_hi(MCLK, CS_BGV & CPWRT & BGADR[10], BGADR[9:0], CPODT, BGDAT
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dpram #(8,11) spa (MCLK, CS_SPA & CPWRT, CPADR[10:0], CPODT, SPDAT, ~MCLK, 1'b0, SPAAD, 8'h0, SPADT);
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dpram #(8,9) pal (MCLK, CS_PAL & CPWRT, CPADR[8:0], CPODT, PLDAT, MCLK, 1'b0, PALET, 8'h0, POUT);
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dataselector_5D_8B cpxdsel(
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.out(CPIDT),
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.en0(CS_PSG),
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.dt0(PSDAT),
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.en1(CS_FGV),
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.dt1(FGDAT),
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.en2(CS_BGV),
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.dt2(BGDAT),
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.en3(CS_SPA),
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.dt3(SPDAT),
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.en4(CS_PAL),
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.dt4(PLDAT)
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);
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assign CPIDT = CS_PSG ? PSDAT :
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CS_FGV ? FGDAT :
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CS_BGV ? BGDAT :
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CS_SPA ? SPDAT :
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CS_PAL ? PLDAT :
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8'hFF;
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ninjakun_psg psg(
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.MCLK(MCLK),
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@@ -137,4 +130,4 @@ ninjakun_psg psg(
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.SNDO(SNDOUT)
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);
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endmodule
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endmodule
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@@ -137,26 +137,14 @@ ninjakun_input inps(
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.INPD1(INPD1)
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);
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dataselector_3D_8B cdt0(
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.out(CP0DT),
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.df(CP0ID),
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.en0(CS_IN0),
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.dt0(INPD0),
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.en1(CS_SH0),
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.dt1(SHDT0),
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.en2(~CP0AD[15]),
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.dt2(ROM0D)
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);
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assign CP0DT = CS_IN0 ? INPD0 :
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CS_SH0 ? SHDT0 :
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~CP0AD[15] ? ROM0D :
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CP0ID;
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dataselector_3D_8B cdt1(
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.out(CP1DT),
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.df(CP1ID),
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.en0(CS_IN1),
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.dt0(INPD1),
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.en1(CS_SH1),
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.dt1(SHDT1),
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.en2(~CP1AD[15]),
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.dt2(ROM1D)
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);
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assign CP1DT = CS_IN1 ? INPD1 :
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CS_SH1 ? SHDT1 :
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~CP1AD[15] ? ROM1D :
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CP1ID;
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endmodule
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