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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-02-07 00:27:10 +00:00

Nova2001: get rid of dataselector.v

This commit is contained in:
Gyorgy Szombathelyi
2021-06-13 01:53:23 +02:00
parent e912a2fefc
commit 051f8d196d
4 changed files with 17 additions and 106 deletions

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@@ -40,7 +40,7 @@
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
@@ -241,5 +241,5 @@ set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/vol_table_arr
set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/YM2149.vhd
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name VERILOG_FILE rtl/dataselector.v
set_global_assignment -name SMART_RECOMPILE ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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@@ -1,70 +0,0 @@
module dataselector_3D_8B
(
output [7:0] out,
input [7:0] df,
input en0,
input [7:0] dt0,
input en1,
input [7:0] dt1,
input en2,
input [7:0] dt2
);
assign out = en0 ? dt0 :
en1 ? dt1 :
en2 ? dt2 :
df;
endmodule
module dataselector_5D_8B
(
output [7:0] out,
input en0,
input [7:0] dt0,
input en1,
input [7:0] dt1,
input en2,
input [7:0] dt2,
input en3,
input [7:0] dt3,
input en4,
input [7:0] dt4
);
assign out = en0 ? dt0 :
en1 ? dt1 :
en2 ? dt2 :
en3 ? dt3 :
en4 ? dt4 :
8'hFF;
endmodule
module dataselector_4D_9B
(
output [8:0] OUT,
input EN1,
input [8:0] IN1,
input EN2,
input [8:0] IN2,
input EN3,
input [8:0] IN3,
input EN4,
input [8:0] IN4,
input [8:0] IND
);
assign OUT = EN1 ? IN1:
EN2 ? IN2:
EN3 ? IN3:
EN4 ? IN4:
IND;
endmodule

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@@ -103,19 +103,12 @@ dpram #(8,10) bgv_hi(MCLK, CS_BGV & CPWRT & BGADR[10], BGADR[9:0], CPODT, BGDAT
dpram #(8,11) spa (MCLK, CS_SPA & CPWRT, CPADR[10:0], CPODT, SPDAT, ~MCLK, 1'b0, SPAAD, 8'h0, SPADT);
dpram #(8,9) pal (MCLK, CS_PAL & CPWRT, CPADR[8:0], CPODT, PLDAT, MCLK, 1'b0, PALET, 8'h0, POUT);
dataselector_5D_8B cpxdsel(
.out(CPIDT),
.en0(CS_PSG),
.dt0(PSDAT),
.en1(CS_FGV),
.dt1(FGDAT),
.en2(CS_BGV),
.dt2(BGDAT),
.en3(CS_SPA),
.dt3(SPDAT),
.en4(CS_PAL),
.dt4(PLDAT)
);
assign CPIDT = CS_PSG ? PSDAT :
CS_FGV ? FGDAT :
CS_BGV ? BGDAT :
CS_SPA ? SPDAT :
CS_PAL ? PLDAT :
8'hFF;
ninjakun_psg psg(
.MCLK(MCLK),
@@ -137,4 +130,4 @@ ninjakun_psg psg(
.SNDO(SNDOUT)
);
endmodule
endmodule

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@@ -137,26 +137,14 @@ ninjakun_input inps(
.INPD1(INPD1)
);
dataselector_3D_8B cdt0(
.out(CP0DT),
.df(CP0ID),
.en0(CS_IN0),
.dt0(INPD0),
.en1(CS_SH0),
.dt1(SHDT0),
.en2(~CP0AD[15]),
.dt2(ROM0D)
);
assign CP0DT = CS_IN0 ? INPD0 :
CS_SH0 ? SHDT0 :
~CP0AD[15] ? ROM0D :
CP0ID;
dataselector_3D_8B cdt1(
.out(CP1DT),
.df(CP1ID),
.en0(CS_IN1),
.dt0(INPD1),
.en1(CS_SH1),
.dt1(SHDT1),
.en2(~CP1AD[15]),
.dt2(ROM1D)
);
assign CP1DT = CS_IN1 ? INPD1 :
CS_SH1 ? SHDT1 :
~CP1AD[15] ? ROM1D :
CP1ID;
endmodule