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Mr.Do: add the secret PAL
This commit is contained in:
Gyorgy Szombathelyi
parent
beff3a7607
commit
12acf4ff57
@ -41,7 +41,7 @@
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:07:52 FEBRUARY 01, 2013"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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@ -222,6 +222,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/mrdo.stp
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDo_mist.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDo_top.sv
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set_global_assignment -name VERILOG_FILE rtl/secret_pal.v
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set_global_assignment -name VERILOG_FILE rtl/video_timing.v
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set_global_assignment -name VERILOG_FILE rtl/ram_dp_1k.v
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set_global_assignment -name VERILOG_FILE rtl/cpu_ram.v
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@ -37,6 +37,5 @@
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<part crc="16ee4ca2" name="f10--1.bin"/>
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<part crc="ff7fe284" name="j10--4.bin"/>
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<part crc="badf5876" name="j2-u001.bin"/>
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<patch offset="0x049a"> 00 </patch>
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</rom>
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</misterromdescription>
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@ -37,6 +37,5 @@
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<part crc="16ee4ca2" name="f10--1.bin"/>
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<part crc="ff7fe284" name="j10--4.bin"/>
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<part crc="badf5876" name="j2-u001.bin"/>
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<patch offset="0x049a"> 00 </patch>
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</rom>
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</misterromdescription>
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@ -678,13 +678,8 @@ reg [15:0] unhandled_addr ;
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always @ (posedge clk_20M ) begin
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if ( rd_n == 0 ) begin
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// read program rom
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if (cpu_addr == 16'h049a ) begin
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// patch rom to bypass "secret" pal protection
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// cpu tries to read val from 0x9803 which is state machine pal
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// written to on all tile ram access. should try converting pal logic to verilog.
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cpu_din <= 0;
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end else if ( cpu_addr >= 16'h0000 && cpu_addr < 16'h8000 ) begin
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// read program rom
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if ( cpu_addr >= 16'h0000 && cpu_addr < 16'h8000 ) begin
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cpu_din <= rom_do; // 0x0000
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end else if ( cpu_addr >= 16'h8000 && cpu_addr < 16'h8400 ) begin
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cpu_din <= bg_ram0_data;
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@ -695,7 +690,7 @@ always @ (posedge clk_20M ) begin
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end else if ( cpu_addr >= 16'h8c00 && cpu_addr < 16'h9000 ) begin
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cpu_din <= fg_ram1_data;
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end else if ( cpu_addr == 16'h9803 ) begin
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cpu_din <= 0;
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cpu_din <= u001_dout;
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end else if ( cpu_addr == 16'ha000 ) begin
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cpu_din <= p1;
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end else if ( cpu_addr == 16'ha001 ) begin
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@ -755,6 +750,24 @@ always @ (posedge clk_20M ) begin
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end
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end
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// u001 "secret" pal protection
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// cpu tries to read val from 0x9803 which is state machine pal
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// written to on all tile ram access..
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wire [7:0] u001_dout ;
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reg gfx_ram_wr_old;
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always @(posedge clk_20M) gfx_ram_wr_old <= gfx_fg_ram0_wr | gfx_fg_ram1_wr;
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wire secret_pal_clk_en = ~gfx_ram_wr_old & (gfx_fg_ram0_wr | gfx_fg_ram1_wr);
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secret_pal u001
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(
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.clk( clk_20M ),
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.clk_en( secret_pal_clk_en ),
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.din( cpu_dout ),
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.dout( u001_dout )
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);
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// first 256 bytes are attribute data
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// bit 7 of attr == MSB of tile
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// bit 6 tile flip
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79
Arcade_MiST/Universal MrDo/rtl/secret_pal.v
Normal file
79
Arcade_MiST/Universal MrDo/rtl/secret_pal.v
Normal file
@ -0,0 +1,79 @@
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// PAL16R6 (IC U001)
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// no feedback used so a 128 byte lookup table could work too.
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module secret_pal
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(
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input clk,
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input clk_en,
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input [7:0] din,
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output [7:0] dout
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);
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wire [9:2] i ;
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reg [19:12] r ;
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// data bus d7 (msb) is pin 2 so reverse input bit order
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assign i = {din[0],din[1],din[2],din[3],din[4],din[5],din[6],din[7]};
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assign dout = r ;
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wire t1 = i[2] & ~i[3] & i[4] & ~i[5] & ~i[6] & ~i[8] & i[9] ;
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wire t2 = ~i[2] & ~i[3] & i[4] & i[5] & ~i[6] & i[8] & ~i[9] ;
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wire t3 = i[2] & i[3] & ~i[4] & ~i[5] & i[6] & ~i[8] & i[9] ;
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wire t4 = ~i[2] & i[3] & i[4] & ~i[5] & i[6] & i[8] & i[9] ;
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always @(posedge clk) begin
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if (clk_en) begin
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// pal output is registered clocked by pin 1 connected to (TRAM WE) $8800-$8fff
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// pal OE is enabled by reading address $9803 (SECRE)
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r[12] <= 0;
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// /rf13 := i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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r[13] <= ~ ( t1 );
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// /rf14 := /i2 & /i3 & i4 & i5 & /i6 & i8 & /i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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r[14] <= ~ ( t2 | t1 );
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// /rf15 := i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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r[15] <= ~ ( t3 | t1 );
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// /rf16 := i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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r[16] <= ~ ( t1 );
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// /rf17 := i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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r[17] <= ~ ( t3 | t1 );
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// /rf18 := /i2 & i3 & i4 & /i5 & i6 & i8 & i9 + i2 & i3 & /i4 & /i5 & i6 & /i8 & i9
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r[18] <= ~ ( t4 | t3 );
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r[19] <= 0;
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end
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end
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endmodule
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/*
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/rf13 := i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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rf13.oe = OE
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/rf14 := /i2 & /i3 & i4 & i5 & /i6 & i8 & /i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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rf14.oe = OE
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/rf15 := i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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rf15.oe = OE
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/rf16 := i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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rf16.oe = OE
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/rf17 := i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9
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rf17.oe = OE
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/rf18 := /i2 & i3 & i4 & /i5 & i6 & i8 & i9 + i2 & i3 & /i4 & /i5 & i6 & /i8 & i9
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rf18.oe = OE
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*/
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