mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-21 18:04:59 +00:00
MrJong: fixed, added flip
This commit is contained in:
Gyorgy Szombathelyi
parent
de715c11f7
commit
149a543e73
@ -43,25 +43,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrJong.sv
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set_global_assignment -name VERILOG_FILE rtl/core.v
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set_global_assignment -name VERILOG_FILE rtl/mcpu.v
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set_global_assignment -name VERILOG_FILE rtl/clk_en.v
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set_global_assignment -name VERILOG_FILE rtl/cpu_rom.v
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set_global_assignment -name VERILOG_FILE rtl/cpu_ram.v
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set_global_assignment -name VERILOG_FILE rtl/jg_decode.v
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set_global_assignment -name VERILOG_FILE rtl/video.v
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set_global_assignment -name VERILOG_FILE rtl/vdata.v
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set_global_assignment -name VERILOG_FILE rtl/hvgen.v
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set_global_assignment -name VERILOG_FILE rtl/audio.v
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set_global_assignment -name VHDL_FILE rtl/sn76489_audio.vhd
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set_global_assignment -name VERILOG_FILE rtl/rising_edge.v
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set_global_assignment -name VERILOG_FILE rtl/falling_edge.v
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set_global_assignment -name VERILOG_FILE rtl/ram.v
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set_global_assignment -name VERILOG_FILE rtl/dpram.v
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/CPU/T80/T80.qip"
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set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
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# Pin & Location Assignments
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# ==========================
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@ -173,7 +154,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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# SignalTap II Assignments
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# ========================
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu.stp
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# Power Estimation Assignments
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# ============================
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@ -235,10 +216,29 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# end ENTITY(MrJong)
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# ------------------
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# ------------------
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrJong.sv
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set_global_assignment -name VERILOG_FILE rtl/core.v
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set_global_assignment -name VERILOG_FILE rtl/mcpu.v
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set_global_assignment -name VERILOG_FILE rtl/clk_en.v
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set_global_assignment -name VERILOG_FILE rtl/cpu_rom.v
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set_global_assignment -name VERILOG_FILE rtl/cpu_ram.v
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set_global_assignment -name VERILOG_FILE rtl/jg_decode.v
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set_global_assignment -name VERILOG_FILE rtl/video.v
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set_global_assignment -name VERILOG_FILE rtl/vdata.v
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set_global_assignment -name VERILOG_FILE rtl/hvgen.v
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set_global_assignment -name VERILOG_FILE rtl/audio.v
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set_global_assignment -name VHDL_FILE rtl/sn76489_audio.vhd
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set_global_assignment -name VERILOG_FILE rtl/rising_edge.v
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set_global_assignment -name VERILOG_FILE rtl/falling_edge.v
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set_global_assignment -name VERILOG_FILE rtl/ram.v
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set_global_assignment -name VERILOG_FILE rtl/dpram.v
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
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set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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135
Arcade_MiST/Kiwako MrJong/MrJong.sdc
Normal file
135
Arcade_MiST/Kiwako MrJong/MrJong.sdc
Normal file
@ -0,0 +1,135 @@
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## Generated SDC file "vectrex_MiST.out.sdc"
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## Copyright (C) 1991-2013 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
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## DATE "Sun Jun 24 12:53:00 2018"
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##
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## DEVICE "EP3C25E144C8"
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##
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# Clock constraints
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# Automatically constrain PLL and other generated clocks
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derive_pll_clocks -create_base_clocks
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# Automatically calculate clock uncertainty to jitter and other effects.
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derive_clock_uncertainty
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# tsu/th constraints
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# tco constraints
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# tpd constraints
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
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set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
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set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
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set aud_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
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set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
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#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
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#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
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set_output_delay -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_L}]
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set_output_delay -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_R}]
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set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
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set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
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#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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set_multicycle_path -to {VGA_*[*]} -setup 2
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set_multicycle_path -to {VGA_*[*]} -hold 1
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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File diff suppressed because one or more lines are too long
@ -18,16 +18,16 @@
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<buttons names="Button1,Start1P,Start2P,CoinA,CoinB" default="A,Start,Select,R1,L1"></buttons>
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<rom index="0" zip="blkbustr.zip|mrjong.zip" md5="none">
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<!-- main cpu -->
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<part name="6a.bin" crc="e2a211a2"/>
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<part name="c2.a7" crc="75070978"/>
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<part name="8a.bin" crc="696ca502"/>
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<part name="c4.a8" crc="c7f5a247"/>
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<part name="6a.bin" crc="9e4b426c"/>
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<part name="c2.a7" crc="75070978"/>
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<part name="8a.bin" crc="0e803777"/>
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<part name="c4.a8" crc="c7f5a247"/>
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<!-- gfx -->
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<part name="4h.bin" crc="2b2af794"/>
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<part name="5h.bin" crc="98d13915"/>
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<part name="4h.bin" crc="67dd6c19"/>
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<part name="5h.bin" crc="50fba1d4"/>
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<!-- prom -->
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<part name="clr.j7" crc="ee1cf1d5"/>
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<part name="clr.g5" crc="bcb1e2e3"/>
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<part name="clr.j7" crc="ee1cf1d5"/>
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<part name="clr.g5" crc="bcb1e2e3"/>
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</rom>
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<rom index="1"></rom>
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<rom index="2"></rom>
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@ -18,16 +18,16 @@
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<buttons names="Button1,Start1P,Start2P,CoinA,CoinB" default="A,Start,Select,R1,L1"></buttons>
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<rom index="0" zip="mrjong.zip" md5="none">
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<!-- main cpu -->
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<part name="mj00" crc="e2a211a2"/>
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<part name="mj01" crc="75070978"/>
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<part name="mj02" crc="696ca502"/>
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<part name="mj03" crc="c7f5a247"/>
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<part name="mj00" crc="d211aed3"/>
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<part name="mj01" crc="49a9ca7e"/>
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<part name="mj02" crc="4b50ae6a"/>
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<part name="mj03" crc="2c375a17"/>
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<!-- gfx -->
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<part name="mj20" crc="2b2af794"/>
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<part name="mj21" crc="98d13915"/>
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<part name="mj21" crc="1ea99dab"/>
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<part name="mj20" crc="7eb1d381"/>
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<!-- prom -->
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<part name="mj61" crc="ee1cf1d5"/>
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<part name="mj60" crc="bcb1e2e3"/>
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<part name="mj61" crc="a85e9b27"/>
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<part name="mj60" crc="dd2b304f"/>
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</rom>
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<rom index="1"></rom>
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<rom index="2"></rom>
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@ -25,24 +25,27 @@ localparam CONF_STR = {
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"O34,Scanlines,Off,25%,50%,75%;",
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"O5,Blend,Off,On;",
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"O6,Joystick Swap,Off,On;",
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"O7,Cabinet,Cocktail,Upright;",
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"O8,Bonus Life,50k,30k;",
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"O9,Difficulty,Normal,Hard;",
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"OAB,Lives,6,4,5,3;",
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"OCD,Coin,1c/1c,1c/2c,1c/3c,2c/1c;",
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"O8,Cabinet,Cocktail,Upright;",
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"O9,Flip,Off,On;",
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"OA,Bonus Life,50k,30k;",
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"OB,Difficulty,Normal,Hard;",
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"OCD,Lives,6,4,5,3;",
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"OEF,Coin,1c/1c,1c/2c,1c/3c,2c/1c;",
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"T0,Reset;",
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"V,v1.0.",`BUILD_DATE
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};
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wire [1:0] orientation = 2'b01;
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wire flipped;
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wire [1:0] orientation = {flipped, 1'b1};
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wire rotate = status[2];
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wire [1:0] scanlines = status[4:3];
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wire blend = status[5];
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wire joyswap = status[6];
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wire cabinet = status[7];
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wire bonus = status[8];
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wire difficulty = status[9];
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wire [1:0] lives = status[11:10];
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wire [1:0] coins = status[13:12];
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wire cabinet = status[8];
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wire flip = status[9];
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wire bonus = status[10];
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wire difficulty = status[11];
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wire [1:0] lives = status[13:12];
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wire [1:0] coins = status[15:14];
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assign LED = ~ioctl_downl;
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assign AUDIO_R = AUDIO_L;
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@ -98,15 +101,15 @@ always @(posedge clk_sys) begin
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reset <= status[0] | buttons[1] | ~rom_loaded;
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end
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wire [7:0] dsw = {coins, lives, difficulty, bonus, 1'b0, cabinet};
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wire [7:0] p1 = { m_fireB, 1'b0, m_coin1, m_fireA, m_down, m_right, m_left, m_up };
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wire [7:0] p2 = { m_fire2B, m_two_players, m_one_player, m_fire2A, m_down2, m_right2, m_left2, m_up2 };
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wire [7:0] dsw = {coins, lives, difficulty, bonus, flip, cabinet};
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wire [7:0] p1 = { 1'b0, m_coin2, m_coin1, m_fireA, m_down, m_right, m_left, m_up };
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wire [7:0] p2 = { 1'b1, m_two_players, m_one_player, m_fire2A, m_down2, m_right2, m_left2, m_up2 };
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core core(
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.reset(reset),
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.clk_sys(clk_sys),
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.p1(p1),
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.p2(p2),
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.p1(p1),
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.p2(p2),
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.dsw(dsw),
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.ioctl_index(ioctl_index),
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.ioctl_download(ioctl_downl),
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@ -120,6 +123,7 @@ core core(
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.hb(hb),
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.vs(vs),
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.hs(hs),
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.flipped(flipped),
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.sound_mix(audio)
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);
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@ -22,6 +22,7 @@ module core(
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output vs,
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output hs,
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output ce_pix,
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output flipped,
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output [15:0] sound_mix
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@ -70,6 +71,8 @@ reg hflip;
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always @(posedge clk_sys)
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if (flip_wr) hflip <= cpu_dout[2];
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assign flipped = hflip;
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wire [7:0] cpu_din =
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p1_cs ? p1 :
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p2_cs ? p2 :
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@ -161,7 +164,7 @@ video u_video(
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.blue ( blue ),
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.vram_cs ( vram_cs ),
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.cram_cs ( cram_cs ),
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.flip ( dsw[1] ^ hflip )
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.flip ( flipped )
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);
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vdata u_vdata(
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@ -13,19 +13,15 @@ module cpu_ram(
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);
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wire [7:0] ram_din = cpu_dout;
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wire ram1_ce_n = ~ram1_cs;
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wire ram2_ce_n = ~ram2_cs;
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wire ram1_wr_n = (ram1_ce_n | ~cpu_wr);
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wire ram2_wr_n = (ram2_ce_n | ~cpu_wr);
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wire ram1_wr_n = ~(ram1_cs & cpu_wr);
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wire ram2_wr_n = ~(ram2_cs & cpu_wr);
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ram #(11,8) ram1(
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.clk ( clk_sys ),
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.addr ( cpu_ab[10:0] ),
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.din ( ram_din ),
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.q ( ram1_data ),
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.rd_n ( ~cpu_rd ),
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.wr_n ( ram1_wr_n ),
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.ce_n ( ~ram1_cs )
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.wr_n ( ram1_wr_n )
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);
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ram #(11,8) ram2(
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@ -33,9 +29,7 @@ ram #(11,8) ram2(
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.addr ( cpu_ab[10:0] ),
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.din ( ram_din ),
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.q ( ram2_data ),
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.rd_n ( ~cpu_rd ),
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.wr_n ( ram2_wr_n ),
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.ce_n ( ~ram2_cs )
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.wr_n ( ram2_wr_n )
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);
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endmodule
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|
||||
@ -19,9 +19,7 @@ ram #(15,8) rom(
|
||||
.addr ( rom_addr ),
|
||||
.din ( ioctl_dout ),
|
||||
.q ( rom_data ),
|
||||
.rd_n ( 1'b0 ),
|
||||
.wr_n ( ~rom_wr ),
|
||||
.ce_n ( 1'b0 )
|
||||
.wr_n ( ~rom_wr )
|
||||
);
|
||||
|
||||
|
||||
|
||||
@ -3,21 +3,20 @@ module hvgen(
|
||||
input clk_sys,
|
||||
output reg hb, vb, hs, vs,
|
||||
output reg [8:0] hcount, vcount,
|
||||
output reg ce_pix
|
||||
output ce_pix
|
||||
);
|
||||
|
||||
wire cen_6;
|
||||
clk_en #(7) hclk_en(clk_sys, cen_6);
|
||||
assign ce_pix = cen_6;
|
||||
|
||||
// 240x224
|
||||
always @(posedge clk_sys) begin
|
||||
ce_pix <= 1'b0;
|
||||
if (cen_6) begin
|
||||
ce_pix <= 1'b1;
|
||||
if (ce_pix) begin
|
||||
hcount <= hcount + 9'd1;
|
||||
case (hcount)
|
||||
4: hb <= 1'b0;
|
||||
244: hb <= 1'b1;
|
||||
18: hb <= 1'b0;
|
||||
258: hb <= 1'b1;
|
||||
308: hs <= 1'b0;
|
||||
340: hs <= 1'b1;
|
||||
383: begin
|
||||
|
||||
@ -31,15 +31,13 @@ clk_en #(17) cpu_clk_en(clk_sys, cen_26);
|
||||
|
||||
reg old_vb;
|
||||
reg [7:0] hold_nmi;
|
||||
reg [7:0] data_latch;
|
||||
always @(posedge clk_sys) begin
|
||||
old_vb <= vb;
|
||||
if (~old_vb & vb) hold_nmi <= 8'hff;
|
||||
if (hold_nmi != 8'd0) hold_nmi <= hold_nmi - 8'd1;
|
||||
if (~cpu_rd_n) data_latch <= cpu_din;
|
||||
end
|
||||
|
||||
T80se (
|
||||
T80se cpu (
|
||||
.RESET_n ( ~reset ),
|
||||
.CLK_n ( clk_sys ),
|
||||
.CLKEN ( cen_26 ),
|
||||
@ -56,7 +54,7 @@ T80se (
|
||||
.HALT_n ( ),
|
||||
.BUSAK_n ( ),
|
||||
.A ( cpu_ab ),
|
||||
.DI ( data_latch ),
|
||||
.DI ( cpu_din ),
|
||||
.DO ( cpu_dout )
|
||||
);
|
||||
|
||||
|
||||
@ -9,19 +9,17 @@ module ram
|
||||
input [addr_width-1:0] addr,
|
||||
input [data_width-1:0] din,
|
||||
output [data_width-1:0] q,
|
||||
input rd_n,
|
||||
input wr_n,
|
||||
input ce_n
|
||||
input wr_n
|
||||
);
|
||||
|
||||
reg [data_width-1:0] data;
|
||||
reg [data_width-1:0] mem[(1<<addr_width)-1:0];
|
||||
|
||||
assign q = ~ce_n ? data : 0;
|
||||
assign q = data;
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
if (~rd_n) data <= mem[addr];
|
||||
data <= mem[addr];
|
||||
if (~wr_n) mem[addr] <= din;
|
||||
|
||||
end
|
||||
|
||||
@ -66,9 +66,7 @@ ram #(5,16) palette(
|
||||
.addr ( pal_admux ),
|
||||
.din ( ioctl_dout ),
|
||||
.q ( pal_data ),
|
||||
.rd_n ( 1'b0 ),
|
||||
.wr_n ( ~pal_wr ),
|
||||
.ce_n ( 1'b0 )
|
||||
.wr_n ( ~pal_wr )
|
||||
);
|
||||
|
||||
ram #(7,8) prom(
|
||||
@ -76,9 +74,7 @@ ram #(7,8) prom(
|
||||
.addr ( prom_admux ),
|
||||
.din ( ioctl_dout ),
|
||||
.q ( prom_data ),
|
||||
.rd_n ( 1'b0 ),
|
||||
.wr_n ( ~prom_wr ),
|
||||
.ce_n ( 1'b0 )
|
||||
.wr_n ( ~prom_wr )
|
||||
);
|
||||
|
||||
|
||||
|
||||
@ -54,7 +54,7 @@ module video(
|
||||
input cpu_rd,
|
||||
input cpu_wr,
|
||||
|
||||
output reg [11:0] char_rom_addr,
|
||||
output [11:0] char_rom_addr,
|
||||
input [7:0] char_data1,
|
||||
input [7:0] char_data2,
|
||||
|
||||
@ -79,8 +79,8 @@ module video(
|
||||
|
||||
);
|
||||
|
||||
wire [8:0] hcount = flip ? (9'h200-hc)+1 : hc-1;
|
||||
wire [8:0] vcount = vc;
|
||||
wire [8:0] hcount = flip ? {hc[8], ~hc[7:0]} : hc;
|
||||
wire [8:0] vcount = flip ? {vc[8], ~vc[7:0]} : vc;
|
||||
wire [8:0] hc;
|
||||
wire [8:0] vc;
|
||||
|
||||
@ -104,13 +104,13 @@ wire spram3_wr = spram_cs[3] & cpu_wr;
|
||||
wire vram_wr = cpu_wr & vram_cs;
|
||||
wire cram_wr = cpu_wr & cram_cs;
|
||||
|
||||
reg [9:0] vram_addr;
|
||||
reg [9:0] cram_addr;
|
||||
wire [9:0] vram_addr;
|
||||
wire [9:0] cram_addr;
|
||||
wire [7:0] vram_data;
|
||||
wire [7:0] cram_data;
|
||||
reg [3:0] spram_addr;
|
||||
|
||||
reg [6:0] bg_color_data;
|
||||
wire [6:0] bg_color_data;
|
||||
|
||||
wire [7:0] spram_data0;
|
||||
wire [7:0] spram_data1;
|
||||
@ -122,7 +122,7 @@ wire [7:0] cpu_cdo;
|
||||
|
||||
assign cpu_vdata =
|
||||
vram_cs ? cpu_vdo :
|
||||
cram_cs ? cpu_cdo : 8'hff;
|
||||
cram_cs ? cpu_cdo : 8'h0;
|
||||
|
||||
dpram #(4,8) u_spram0 (
|
||||
.address_a ( cpu_ab[5:2] ),
|
||||
@ -132,7 +132,7 @@ dpram #(4,8) u_spram0 (
|
||||
.data_b ( ),
|
||||
.wren_a ( spram0_wr ),
|
||||
.wren_b ( ),
|
||||
.rden_a ( cpu_rd ),
|
||||
.rden_a ( 1'b0 ),
|
||||
.rden_b ( 1'b1 ),
|
||||
.q_a ( ),
|
||||
.q_b ( spram_data0 )
|
||||
@ -146,7 +146,7 @@ dpram #(4,8) u_spram1 (
|
||||
.data_b ( ),
|
||||
.wren_a ( spram1_wr ),
|
||||
.wren_b ( ),
|
||||
.rden_a ( cpu_rd ),
|
||||
.rden_a ( 1'b0 ),
|
||||
.rden_b ( 1'b1 ),
|
||||
.q_a ( ),
|
||||
.q_b ( spram_data1 )
|
||||
@ -160,7 +160,7 @@ dpram #(4,8) u_spram2 (
|
||||
.data_b ( ),
|
||||
.wren_a ( spram2_wr ),
|
||||
.wren_b ( ),
|
||||
.rden_a ( cpu_rd ),
|
||||
.rden_a ( 1'b0 ),
|
||||
.rden_b ( 1'b1 ),
|
||||
.q_a ( ),
|
||||
.q_b ( spram_data2 )
|
||||
@ -174,7 +174,7 @@ dpram #(4,8) u_spram3 (
|
||||
.data_b ( ),
|
||||
.wren_a ( spram3_wr ),
|
||||
.wren_b ( ),
|
||||
.rden_a ( cpu_rd ),
|
||||
.rden_a ( 1'b0 ),
|
||||
.rden_b ( 1'b1 ),
|
||||
.q_a ( ),
|
||||
.q_b ( spram_data3 )
|
||||
@ -188,7 +188,7 @@ dpram #(10,8) vram(
|
||||
.data_b ( ),
|
||||
.wren_a ( vram_wr ),
|
||||
.wren_b ( ),
|
||||
.rden_a ( cpu_rd ),
|
||||
.rden_a ( 1'b1 ),
|
||||
.rden_b ( 1'b1 ),
|
||||
.q_a ( cpu_vdo ),
|
||||
.q_b ( vram_data )
|
||||
@ -202,7 +202,7 @@ dpram #(10,8) cram(
|
||||
.data_b ( ),
|
||||
.wren_a ( cram_wr ),
|
||||
.wren_b ( ),
|
||||
.rden_a ( cpu_rd ),
|
||||
.rden_a ( 1'b1 ),
|
||||
.rden_b ( 1'b1 ),
|
||||
.q_a ( cpu_cdo ),
|
||||
.q_b ( cram_data )
|
||||
@ -210,15 +210,10 @@ dpram #(10,8) cram(
|
||||
|
||||
wire [2:0] hf = {3{cram_data[6]}};
|
||||
wire [2:0] vf = {3{cram_data[7]}};
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
if (ce_pix) begin
|
||||
vram_addr <= { vcount[7:3], hcount[7:3] };
|
||||
cram_addr <= { vcount[7:3], hcount[7:3] };
|
||||
end
|
||||
char_rom_addr <= { cram_data[5], vram_data, vcount[2:0]^vf };
|
||||
bg_color_data <= { cram_data[4:0], char_data1[hcount[2:0]^hf], char_data2[hcount[2:0]^hf] };
|
||||
end
|
||||
assign vram_addr = { vcount[7:3], hcount[7:3] };
|
||||
assign cram_addr = { vcount[7:3], hcount[7:3] };
|
||||
assign bg_color_data = { cram_data[4:0], char_data2[hcount[2:0]^hf], char_data1[hcount[2:0]^hf] };
|
||||
assign char_rom_addr = { cram_data[5], vram_data, vcount[2:0]^vf };
|
||||
|
||||
wire [6:0] sid = { spram_data3[5], spram_data1[7:2] };
|
||||
wire yflip = spram_data1[1];
|
||||
@ -230,7 +225,7 @@ wire spc0 = spr_data1[sxc[2:0]^{3{xflip}}];
|
||||
wire spc1 = spr_data2[sxc[2:0]^{3{xflip}}];
|
||||
|
||||
wire [3:0] syc = yflip ? 4'd15 - (vcount - sy) : vcount - sy;
|
||||
wire [7:0] sxc2 = flip ? spram_data2+31 + sxc - 8'd16 : spram_data2 + sxc - 8'd16;
|
||||
wire [7:0] sxc2 = spram_data2 + sxc + (flip ? -8'd16 : 8'd16);
|
||||
reg [6:0] spn;
|
||||
reg [6:0] dlbuf[511:0];
|
||||
reg [1:0] state, next_state;
|
||||
@ -245,7 +240,6 @@ always @(posedge clk_sys) begin
|
||||
else begin
|
||||
|
||||
oldv <= vcount;
|
||||
if (ce_pix && !hc[8]) dlbuf[{ ~vcount[0], hcount[7:0] }] <= 7'd0;
|
||||
|
||||
case (state)
|
||||
0: begin
|
||||
@ -268,7 +262,7 @@ always @(posedge clk_sys) begin
|
||||
end
|
||||
2: begin
|
||||
if (spc1|spc0) begin
|
||||
dlbuf[{ vcount[0], sxc2 }] <= { spram_data3[4:0], spc0, spc1 };
|
||||
dlbuf[{ vcount[0], sxc2 }] <= { spram_data3[4:0], spc1, spc0 };
|
||||
end
|
||||
sxc <= sxc + 4'd1;
|
||||
if (sxc == 4'd5) begin
|
||||
@ -295,8 +289,9 @@ end
|
||||
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
sp_color_data <= dlbuf[{ ~vcount[0], hcount[7:0] }];
|
||||
if (ce_pix) begin
|
||||
sp_color_data <= dlbuf[{ ~vcount[0], hcount[7:0] }];
|
||||
if (!hc[8]) dlbuf[{ ~vcount[0], hcount[7:0] }] <= 7'd0;
|
||||
prom_addr <= |sp_color_data[1:0] ? sp_color_data : bg_color_data;
|
||||
pal_addr <= prom_data[4:0];
|
||||
red <= pal_data[2:0];
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user