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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-20 01:34:38 +00:00

Change Directory, there a second Williams Rev1 Hardware

This commit is contained in:
Gehstock 2020-01-07 16:36:57 +01:00
parent ea33c889ed
commit 1f0d1b301a
18 changed files with 47 additions and 97 deletions

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@ -431,7 +431,7 @@ cpu_rom_addr <= (cpu_addr(14 downto 10) & cpu_addr(8 downto 7) & cpu_addr(0) & c
cpu_di <= cpu_rom_do_swp when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"8" else -- program rom 0000-7FFF 32Ko
wram_do_r when cpu_mreq_n = '0' and (cpu_addr and X"E000") = x"8000" else -- work ram 8000-87FF 2Ko + mirroring 1800
protection_do when cpu_mreq_n = '0' and (cpu_addr and X"FFFF") = x"E000" else -- protection E000
-- protection_do when cpu_mreq_n = '0' and (cpu_addr and X"FFFF") = x"E000" else -- protection E000
input_0 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "00") else
input_1 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "01") else
input_2 when cpu_ioreq_n = '0' and (cpu_addr(1 downto 0) = "10") else

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@ -28,4 +28,4 @@ DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "Williams6809rev1_MiST"
PROJECT_REVISION = "DefenderHardware"

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@ -1,6 +1,6 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
@ -17,15 +17,15 @@
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 20:24:55 June 11, 2019
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 16:34:25 January 07, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Williams6809rev1_MiST_assignment_defaults.qdf
# DefenderHardware_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@ -45,6 +45,18 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Defender_MiST.sv
set_global_assignment -name VHDL_FILE rtl/defender.vhd
set_global_assignment -name VHDL_FILE rtl/defender_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/defender_cmos_ram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name VHDL_FILE ../../../common/CPU/MC6809/cpu09l_128a.vhd
set_global_assignment -name VHDL_FILE ../../../common/IO/pia6821.vhd
# Pin & Location Assignments
# ==========================
@ -154,6 +166,11 @@ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/snd.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
@ -171,54 +188,39 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Defender_MiST)
# -------------------------
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/snd.stp
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Defender_MiST.sv
set_global_assignment -name VHDL_FILE rtl/defender.vhd
set_global_assignment -name VHDL_FILE rtl/defender_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/defender_cmos_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
set_global_assignment -name QIP_FILE rtl/pll_mist.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE ../../common/IO/pia6821.vhd
set_global_assignment -name VHDL_FILE ../../common/CPU/MC6809/cpu09l_128a.vhd
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# -------------------------

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@ -34,10 +34,10 @@ module Defender_MiST(
`include "rtl/build_id.v"
`define CORE_NAME "DEFENDER"
//`define CORE_NAME "DEFENDER"
//`define CORE_NAME "COLONY7"
//`define CORE_NAME "MAYDAY"
//`define CORE_NAME "JIN"
`define CORE_NAME "JIN"
localparam CONF_STR = {
`CORE_NAME,";ROM;",

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@ -1,48 +0,0 @@
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac is
generic (
C_bits : integer := 10
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(C_bits-1 downto 0);
dac_o : out std_logic
);
end dac;
architecture rtl of dac is
signal sig_in: unsigned(C_bits downto 0);
begin
seq: process(clk_i, res_n_i)
begin
if res_n_i = '0' then
sig_in <= to_unsigned(2**C_bits, sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
dac_o <= sig_in(C_bits);
end if;
end process seq;
end rtl;

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@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]