mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-31 19:26:48 +00:00
add common Controls on Dottory Kun(WIP)
This commit is contained in:
Gehstock
@@ -43,24 +43,6 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:44:34 AUGUST 14, 2017"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/DottoriKun_MiST.sv
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set_global_assignment -name VERILOG_FILE rtl/dottori.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
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set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
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set_global_assignment -name VERILOG_FILE rtl/RAM.v
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name VERILOG_FILE rtl/osd.v
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set_global_assignment -name VERILOG_FILE rtl/mist_io.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
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set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_reg.v
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set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_mcode.v
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set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_core.v
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set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_alu.v
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set_global_assignment -name VERILOG_FILE rtl/tv80/cpu_z80.v
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set_global_assignment -name VERILOG_FILE rtl/ROM1.v
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set_global_assignment -name VERILOG_FILE rtl/ROM2.v
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set_global_assignment -name VERILOG_FILE rtl/ROM3.v
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set_global_assignment -name VERILOG_FILE rtl/ROM4.v
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# Pin & Location Assignments
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# ==========================
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@@ -182,4 +164,15 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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# end ENTITY(DottoriKun_MiST)
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# ---------------------------
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/DottoriKun_MiST.sv
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set_global_assignment -name VERILOG_FILE rtl/dottori.v
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set_global_assignment -name VERILOG_FILE rtl/ROM1.v
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set_global_assignment -name VERILOG_FILE rtl/ROM2.v
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set_global_assignment -name VERILOG_FILE rtl/ROM3.v
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set_global_assignment -name VERILOG_FILE rtl/ROM4.v
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set_global_assignment -name VERILOG_FILE rtl/RAM.v
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name VERILOG_FILE rtl/cpu_z80.v
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set_global_assignment -name QIP_FILE ../../../common/CPU/tv80/TV80.qip
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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@@ -16,26 +16,17 @@ module DottoriKun_MiST(
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input CLOCK_27
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);
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`include "rtl\build_id.sv"
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`include "rtl\build_id.v"
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localparam CONF_STR = {
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"DottoriKun;;",
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"O12,ROM ,ORIG,ORIG,MINE,PACM;",
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"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
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"O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
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"O5,Blend,Off,On;",
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"T6,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire [9:0] kbjoy;
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wire [7:0] joy0, joy1;
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wire scandoubler_disable;
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wire ypbpr;
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wire ps2_kbd_clk, ps2_kbd_data;
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wire [7:0] audio;
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wire video;
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assign LED = 1;
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wire clk_32, clk_8, clk_4;
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pll pll
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@@ -46,6 +37,15 @@ pll pll
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.c2(clk_4)
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);
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wire [31:0] status;
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wire [1:0] buttons;
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wire [1:0] switches;
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wire [7:0] joystick_0, joystick_1;
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wire scandoublerD;
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wire ypbpr;
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wire r, g, b;
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wire hs, vs;
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dottori dottori (
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.CLK_4M(clk_4),
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.RED(r),
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@@ -55,72 +55,89 @@ dottori dottori (
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.vSYNC(vs),
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.hSYNC(hs),
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.nRESET(~(status[0] | status[6] | buttons[1])),
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.BUTTONS({ ~(kbjoy[5]), //Test Mode
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~(kbjoy[6]), //Start
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~(joy0[5] | joy1[5] | kbjoy[7]), //Button 2 - Pause
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~(joy0[4] | joy1[4] | kbjoy[4]), //Button 1
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~(joy0[0] | joy1[0] | kbjoy[0]), //Right
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~(joy0[1] | joy1[1] | kbjoy[1]), //Left
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~(joy0[2] | joy1[2] | kbjoy[2]), //Down
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~(joy0[3] | joy1[3] | kbjoy[3])})//Up
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.BUTTONS(~{btn_one_player, btn_coin, m_bomb, m_fire, m_right, m_left, m_down, m_up})
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);
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wire hs;
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wire vs;
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video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
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(
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.clk_sys(clk_32),
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.ce_pix(clk_8),
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.ce_pix_actual(clk_8),
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.SPI_SCK(SPI_SCK),
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.SPI_SS3(SPI_SS3),
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.SPI_DI(SPI_DI),
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.R({r,r,r}),
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.G({g,g,g}),
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.B({b,b,b}),
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.HSync(hs),
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.VSync(vs),
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.VGA_R(VGA_R),
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.VGA_G(VGA_G),
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.VGA_B(VGA_B),
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.VGA_VS(VGA_VS),
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.VGA_HS(VGA_HS),
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.scandoubler_disable(scandoubler_disable),
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.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
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.hq2x(status[4:3]==1),
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.ypbpr_full(1),
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.line_start(0),
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.mono(0)
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);
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mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
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(
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.clk_sys (clk_32 ),
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mist_video #(.COLOR_DEPTH(1), .SD_HCNT_WIDTH(10)) mist_video(
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.clk_sys ( clk_32 ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS3 ( SPI_SS3 ),
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.SPI_DI ( SPI_DI ),
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.R ( r ),
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.G ( g ),
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.B ( b ),
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.HSync ( hs ),
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.VSync ( vs ),
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.VGA_R ( VGA_R ),
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.VGA_G ( VGA_G ),
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.VGA_B ( VGA_B ),
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.VGA_VS ( VGA_VS ),
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.VGA_HS ( VGA_HS ),
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.rotate ( 2'b00 ),
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.ce_divider ( 1'b1 ),
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.blend ( status[5] ),
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.scandoubler_disable(scandoublerD ),
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.scanlines ( status[4:3] ),
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.ypbpr ( ypbpr )
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);
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user_io #(
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.STRLEN(($size(CONF_STR)>>3)))
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user_io(
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.clk_sys (clk_32 ),
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.conf_str (CONF_STR ),
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.SPI_SCK (SPI_SCK ),
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.CONF_DATA0 (CONF_DATA0 ),
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.SPI_SS2 (SPI_SS2 ),
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.SPI_DO (SPI_DO ),
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.SPI_DI (SPI_DI ),
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.SPI_CLK (SPI_SCK ),
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.SPI_SS_IO (CONF_DATA0 ),
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.SPI_MISO (SPI_DO ),
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.SPI_MOSI (SPI_DI ),
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.buttons (buttons ),
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.switches (switches ),
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.scandoubler_disable(scandoubler_disable),
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.switches (switches ),
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.scandoubler_disable (scandoublerD ),
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.ypbpr (ypbpr ),
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.ps2_kbd_clk (ps2_kbd_clk ),
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.ps2_kbd_data (ps2_kbd_data ),
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.joystick_0 (joy0 ),
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.joystick_1 (joy1 ),
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.key_strobe (key_strobe ),
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.key_pressed (key_pressed ),
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.key_code (key_code ),
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.joystick_0 (joystick_0 ),
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.joystick_1 (joystick_1 ),
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.status (status )
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);
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keyboard keyboard(
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.clk(clk_32),
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.reset(),
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.ps2_kbd_clk(ps2_kbd_clk),
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.ps2_kbd_data(ps2_kbd_data),
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.joystick(kbjoy)
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);
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wire m_up = btn_up | joystick_0[3] | joystick_1[3];
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wire m_down = btn_down | joystick_0[2] | joystick_1[2];
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wire m_left = btn_left | joystick_0[1] | joystick_1[1];
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wire m_right = btn_right | joystick_0[0] | joystick_1[0];
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wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
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wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
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endmodule
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reg btn_one_player = 0;
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reg btn_two_players = 0;
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reg btn_left = 0;
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reg btn_right = 0;
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reg btn_down = 0;
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reg btn_up = 0;
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reg btn_fire1 = 0;
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reg btn_fire2 = 0;
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reg btn_fire3 = 0;
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reg btn_coin = 0;
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wire key_strobe;
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wire key_pressed;
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wire [7:0] key_code;
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always @(posedge clk_32) begin
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if(key_strobe) begin
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case(key_code)
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'h75: btn_up <= key_pressed; // up
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'h72: btn_down <= key_pressed; // down
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'h6B: btn_left <= key_pressed; // left
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'h74: btn_right <= key_pressed; // right
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'h76: btn_coin <= key_pressed; // ESC
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'h05: btn_one_player <= key_pressed; // F1
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'h06: btn_two_players <= key_pressed; // F2
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'h14: btn_fire3 <= key_pressed; // ctrl
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'h11: btn_fire2 <= key_pressed; // alt
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'h29: btn_fire1 <= key_pressed; // Space
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endcase
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end
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end
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endmodule
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@@ -1,3 +0,0 @@
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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "13.1"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM1.v"]
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@@ -1,3 +0,0 @@
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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "13.1"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM2.v"]
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@@ -1,3 +0,0 @@
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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "13.1"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM3.v"]
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@@ -1,2 +0,0 @@
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`define BUILD_DATE "180816"
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`define BUILD_TIME "200421"
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@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
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set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
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# Create a Verilog file for output
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set outputFileName "sys/build_id.sv"
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set outputFileName "sys/build_id.v"
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set outputFile [open $outputFileName "w"]
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# Output the Verilog source
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@@ -26,6 +26,8 @@ module cpu_z80(
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tv80_core TV80( , IORQ, NO_READ, WRITE, , , , ADDRESS, DATA_OUT, M_CYCLE,
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T_STATE, nINTCYCLE, , , nRESET, CLK, 1'b1, 1'b1,
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nINT, nNMI, 1'b1, DATA_IN, DATA_IN_REG);
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always @(posedge CLK)
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begin
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@@ -1,454 +0,0 @@
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//
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//
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// Copyright (c) 2012-2013 Ludvig Strigeus
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// Copyright (c) 2017 Sorgelig
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//
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// This program is GPL Licensed. See COPYING for the full license.
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//
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//
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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`define BITS_TO_FIT(N) ( \
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N <= 2 ? 0 : \
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N <= 4 ? 1 : \
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N <= 8 ? 2 : \
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N <= 16 ? 3 : \
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N <= 32 ? 4 : \
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N <= 64 ? 5 : \
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N <= 128 ? 6 : \
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N <= 256 ? 7 : \
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N <= 512 ? 8 : \
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N <=1024 ? 9 : 10 )
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module hq2x_in #(parameter LENGTH, parameter DWIDTH)
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(
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input clk,
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input [AWIDTH:0] rdaddr,
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input rdbuf,
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output[DWIDTH:0] q,
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input [AWIDTH:0] wraddr,
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input wrbuf,
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input [DWIDTH:0] data,
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input wren
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);
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localparam AWIDTH = `BITS_TO_FIT(LENGTH);
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wire [DWIDTH:0] out[2];
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assign q = out[rdbuf];
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hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
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hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
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endmodule
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module hq2x_out #(parameter LENGTH, parameter DWIDTH)
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(
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input clk,
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input [AWIDTH:0] rdaddr,
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input [1:0] rdbuf,
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output[DWIDTH:0] q,
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input [AWIDTH:0] wraddr,
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input [1:0] wrbuf,
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input [DWIDTH:0] data,
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input wren
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);
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localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
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wire [DWIDTH:0] out[4];
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assign q = out[rdbuf];
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
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endmodule
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module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
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(
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input clock,
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input [DWIDTH:0] data,
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input [AWIDTH:0] rdaddress,
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input [AWIDTH:0] wraddress,
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input wren,
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output [DWIDTH:0] q
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);
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.address_b (rdaddress),
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.q_b(q),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({(DWIDTH+1){1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone III",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = NUMWORDS,
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altsyncram_component.numwords_b = NUMWORDS,
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altsyncram_component.operation_mode = "DUAL_PORT",
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||||
altsyncram_component.outdata_aclr_b = "NONE",
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||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
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||||
altsyncram_component.power_up_uninitialized = "FALSE",
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||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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||||
altsyncram_component.widthad_a = AWIDTH+1,
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||||
altsyncram_component.widthad_b = AWIDTH+1,
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||||
altsyncram_component.width_a = DWIDTH+1,
|
||||
altsyncram_component.width_b = DWIDTH+1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
endmodule
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module DiffCheck
|
||||
(
|
||||
input [17:0] rgb1,
|
||||
input [17:0] rgb2,
|
||||
output result
|
||||
);
|
||||
|
||||
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
|
||||
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
|
||||
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
|
||||
wire [6:0] t = $signed(r) + $signed(b);
|
||||
wire [6:0] gx = {g[5], g};
|
||||
wire [7:0] y = $signed(t) + $signed(gx);
|
||||
wire [6:0] u = $signed(r) - $signed(b);
|
||||
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
|
||||
|
||||
// if y is inside (-24..24)
|
||||
wire y_inside = (y < 8'h18 || y >= 8'he8);
|
||||
|
||||
// if u is inside (-4, 4)
|
||||
wire u_inside = (u < 7'h4 || u >= 7'h7c);
|
||||
|
||||
// if v is inside (-6, 6)
|
||||
wire v_inside = (v < 8'h6 || v >= 8'hfA);
|
||||
assign result = !(y_inside && u_inside && v_inside);
|
||||
endmodule
|
||||
|
||||
module InnerBlend
|
||||
(
|
||||
input [8:0] Op,
|
||||
input [5:0] A,
|
||||
input [5:0] B,
|
||||
input [5:0] C,
|
||||
output [5:0] O
|
||||
);
|
||||
|
||||
function [8:0] mul6x3;
|
||||
input [5:0] op1;
|
||||
input [2:0] op2;
|
||||
begin
|
||||
mul6x3 = 9'd0;
|
||||
if(op2[0]) mul6x3 = mul6x3 + op1;
|
||||
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
|
||||
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire OpOnes = Op[4];
|
||||
wire [8:0] Amul = mul6x3(A, Op[7:5]);
|
||||
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
|
||||
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
|
||||
wire [8:0] At = Amul;
|
||||
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
|
||||
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
|
||||
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
|
||||
assign O = Op[8] ? A : Res[9:4];
|
||||
endmodule
|
||||
|
||||
module Blend
|
||||
(
|
||||
input [5:0] rule,
|
||||
input disable_hq2x,
|
||||
input [17:0] E,
|
||||
input [17:0] A,
|
||||
input [17:0] B,
|
||||
input [17:0] D,
|
||||
input [17:0] F,
|
||||
input [17:0] H,
|
||||
output [17:0] Result
|
||||
);
|
||||
|
||||
reg [1:0] input_ctrl;
|
||||
reg [8:0] op;
|
||||
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
|
||||
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
|
||||
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
|
||||
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
|
||||
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
|
||||
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
|
||||
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
|
||||
localparam AB = 2'b00;
|
||||
localparam AD = 2'b01;
|
||||
localparam DB = 2'b10;
|
||||
localparam BD = 2'b11;
|
||||
wire is_diff;
|
||||
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
|
||||
|
||||
always @* begin
|
||||
casex({!is_diff, rule[5:2]})
|
||||
1,17: {op, input_ctrl} = {BLEND1, AB};
|
||||
2,18: {op, input_ctrl} = {BLEND1, DB};
|
||||
3,19: {op, input_ctrl} = {BLEND1, BD};
|
||||
4,20: {op, input_ctrl} = {BLEND2, DB};
|
||||
5,21: {op, input_ctrl} = {BLEND2, AB};
|
||||
6,22: {op, input_ctrl} = {BLEND2, AD};
|
||||
|
||||
8: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
9: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
10: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
11: {op, input_ctrl} = {BLEND1, AB};
|
||||
12: {op, input_ctrl} = {BLEND1, AB};
|
||||
13: {op, input_ctrl} = {BLEND1, AB};
|
||||
14: {op, input_ctrl} = {BLEND1, DB};
|
||||
15: {op, input_ctrl} = {BLEND1, BD};
|
||||
|
||||
24: {op, input_ctrl} = {BLEND2, DB};
|
||||
25: {op, input_ctrl} = {BLEND5, DB};
|
||||
26: {op, input_ctrl} = {BLEND6, DB};
|
||||
27: {op, input_ctrl} = {BLEND2, DB};
|
||||
28: {op, input_ctrl} = {BLEND4, DB};
|
||||
29: {op, input_ctrl} = {BLEND5, DB};
|
||||
30: {op, input_ctrl} = {BLEND3, BD};
|
||||
31: {op, input_ctrl} = {BLEND3, DB};
|
||||
default: {op, input_ctrl} = 11'bx;
|
||||
endcase
|
||||
|
||||
// Setting op[8] effectively disables HQ2X because blend will always return E.
|
||||
if (disable_hq2x) op[8] = 1;
|
||||
end
|
||||
|
||||
// Generate inputs to the inner blender. Valid combinations.
|
||||
// 00: E A B
|
||||
// 01: E A D
|
||||
// 10: E D B
|
||||
// 11: E B D
|
||||
wire [17:0] Input1 = E;
|
||||
wire [17:0] Input2 = !input_ctrl[1] ? A :
|
||||
!input_ctrl[0] ? D : B;
|
||||
|
||||
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
|
||||
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
|
||||
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
|
||||
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
|
||||
endmodule
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
input clk,
|
||||
input ce_x4,
|
||||
input [DWIDTH:0] inputpixel,
|
||||
input mono,
|
||||
input disable_hq2x,
|
||||
input reset_frame,
|
||||
input reset_line,
|
||||
input [1:0] read_y,
|
||||
input [AWIDTH+1:0] read_x,
|
||||
output [DWIDTH:0] outpixel
|
||||
);
|
||||
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
|
||||
|
||||
wire [5:0] hqTable[256] = '{
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
|
||||
};
|
||||
|
||||
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
|
||||
reg [17:0] A, B, D, F, G, H;
|
||||
reg [7:0] pattern, nextpatt;
|
||||
reg [1:0] i;
|
||||
reg [7:0] y;
|
||||
|
||||
wire curbuf = y[0];
|
||||
reg prevbuf = 0;
|
||||
wire iobuf = !curbuf;
|
||||
|
||||
wire diff0, diff1;
|
||||
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
|
||||
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
|
||||
|
||||
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
|
||||
|
||||
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
|
||||
wire [17:0] blend_result;
|
||||
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
|
||||
|
||||
reg Curr2_addr1;
|
||||
reg [AWIDTH:0] Curr2_addr2;
|
||||
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
|
||||
wire [DWIDTH:0] Curr2tmp;
|
||||
|
||||
reg [AWIDTH:0] wrin_addr2;
|
||||
reg [DWIDTH:0] wrpix;
|
||||
reg wrin_en;
|
||||
|
||||
function [17:0] h2rgb;
|
||||
input [8:0] v;
|
||||
begin
|
||||
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [8:0] rgb2h;
|
||||
input [17:0] v;
|
||||
begin
|
||||
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(Curr2_addr2),
|
||||
.rdbuf(Curr2_addr1),
|
||||
.q(Curr2tmp),
|
||||
|
||||
.wraddr(wrin_addr2),
|
||||
.wrbuf(iobuf),
|
||||
.data(wrpix),
|
||||
.wren(wrin_en)
|
||||
);
|
||||
|
||||
reg [1:0] wrout_addr1;
|
||||
reg [AWIDTH+1:0] wrout_addr2;
|
||||
reg wrout_en;
|
||||
reg [DWIDTH:0] wrdata;
|
||||
|
||||
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(read_x),
|
||||
.rdbuf(read_y),
|
||||
.q(outpixel),
|
||||
|
||||
.wraddr(wrout_addr2),
|
||||
.wrbuf(wrout_addr1),
|
||||
.data(wrdata),
|
||||
.wren(wrout_en)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [AWIDTH:0] offs;
|
||||
reg old_reset_line;
|
||||
reg old_reset_frame;
|
||||
|
||||
wrout_en <= 0;
|
||||
wrin_en <= 0;
|
||||
|
||||
if(ce_x4) begin
|
||||
|
||||
pattern <= new_pattern;
|
||||
|
||||
if(~&offs) begin
|
||||
if (i == 0) begin
|
||||
Curr2_addr1 <= prevbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 1) begin
|
||||
Prev2 <= Curr2;
|
||||
Curr2_addr1 <= curbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 2) begin
|
||||
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
|
||||
wrpix <= inputpixel;
|
||||
wrin_addr2 <= offs;
|
||||
wrin_en <= 1;
|
||||
end
|
||||
if (i == 3) begin
|
||||
offs <= offs + 1'd1;
|
||||
end
|
||||
|
||||
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
|
||||
else wrdata <= blend_result;
|
||||
|
||||
wrout_addr1 <= {curbuf, i[1]};
|
||||
wrout_addr2 <= {offs, i[1]^i[0]};
|
||||
wrout_en <= 1;
|
||||
end
|
||||
|
||||
if(i==3) begin
|
||||
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
|
||||
{A, G} <= {Prev0, Next0};
|
||||
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
|
||||
{Prev0, Prev1} <= {Prev1, Prev2};
|
||||
{Curr0, Curr1} <= {Curr1, Curr2};
|
||||
{Next0, Next1} <= {Next1, Next2};
|
||||
end else begin
|
||||
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
|
||||
{B, F, H, D} <= {F, H, D, B};
|
||||
end
|
||||
|
||||
i <= i + 1'b1;
|
||||
if(old_reset_line && ~reset_line) begin
|
||||
old_reset_frame <= reset_frame;
|
||||
offs <= 0;
|
||||
i <= 0;
|
||||
y <= y + 1'd1;
|
||||
prevbuf <= curbuf;
|
||||
if(old_reset_frame & ~reset_frame) begin
|
||||
y <= 0;
|
||||
prevbuf <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
old_reset_line <= reset_line;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // Hq2x
|
||||
@@ -1,79 +0,0 @@
|
||||
|
||||
|
||||
module keyboard
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
input ps2_kbd_clk,
|
||||
input ps2_kbd_data,
|
||||
|
||||
output reg[7:0] joystick
|
||||
);
|
||||
|
||||
reg [11:0] shift_reg = 12'hFFF;
|
||||
wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
|
||||
wire [7:0] kcode = kdata[9:2];
|
||||
reg release_btn = 0;
|
||||
|
||||
reg [7:0] code;
|
||||
reg input_strobe = 0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
reg old_reset = 0;
|
||||
|
||||
old_reset <= reset;
|
||||
|
||||
if(~old_reset & reset)begin
|
||||
joystick <= 0;
|
||||
end
|
||||
|
||||
if(input_strobe) begin
|
||||
case(code)
|
||||
'h75: joystick[3] <= ~release_btn; // arrow up
|
||||
'h72: joystick[2] <= ~release_btn; // arrow down
|
||||
'h6B: joystick[1] <= ~release_btn; // arrow left
|
||||
'h74: joystick[0] <= ~release_btn; // arrow right
|
||||
|
||||
'h29: joystick[4] <= ~release_btn; // Space
|
||||
'h05: joystick[5] <= ~release_btn; // F1
|
||||
'h06: joystick[6] <= ~release_btn; // F2
|
||||
'h76: joystick[7] <= ~release_btn; // Escape
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [3:0] prev_clk = 0;
|
||||
reg old_reset = 0;
|
||||
reg action = 0;
|
||||
|
||||
old_reset <= reset;
|
||||
input_strobe <= 0;
|
||||
|
||||
if(~old_reset & reset)begin
|
||||
prev_clk <= 0;
|
||||
shift_reg <= 12'hFFF;
|
||||
end else begin
|
||||
prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
|
||||
if(prev_clk == 1) begin
|
||||
if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
|
||||
shift_reg <= 12'hFFF;
|
||||
if (kcode == 8'he0) ;
|
||||
// Extended key code follows
|
||||
else if (kcode == 8'hf0)
|
||||
// Release code follows
|
||||
action <= 1;
|
||||
else begin
|
||||
// Cancel extended/release flags for next time
|
||||
action <= 0;
|
||||
release_btn <= action;
|
||||
code <= kcode;
|
||||
input_strobe <= 1;
|
||||
end
|
||||
end else begin
|
||||
shift_reg <= kdata;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@@ -1,530 +0,0 @@
|
||||
//
|
||||
// mist_io.v
|
||||
//
|
||||
// mist_io for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2015-2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
|
||||
// (Sorgelig)
|
||||
//
|
||||
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
|
||||
// clk_ps2 = clk_sys/(PS2DIV*2)
|
||||
//
|
||||
|
||||
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
(
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
|
||||
// Global clock. It should be around 100MHz (higher is better).
|
||||
input clk_sys,
|
||||
|
||||
// Global SPI clock from ARM. 24MHz
|
||||
input SPI_SCK,
|
||||
|
||||
input CONF_DATA0,
|
||||
input SPI_SS2,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
// output reg [31:0] joystick_2,
|
||||
// output reg [31:0] joystick_3,
|
||||
// output reg [31:0] joystick_4,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
output scandoublerD,
|
||||
output ypbpr,
|
||||
|
||||
output reg [31:0] status,
|
||||
|
||||
// SD config
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output [1:0] img_mounted, // signaling that new image has been mounted
|
||||
output reg [31:0] img_size, // size of image in bytes
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba,
|
||||
input [1:0] sd_rd,
|
||||
input [1:0] sd_wr,
|
||||
output reg sd_ack,
|
||||
output reg sd_ack_conf,
|
||||
|
||||
// SD byte level access. Signals for 2-PORT altsyncram.
|
||||
output reg [8:0] sd_buff_addr,
|
||||
output reg [7:0] sd_buff_dout,
|
||||
input [7:0] sd_buff_din,
|
||||
output reg sd_buff_wr,
|
||||
|
||||
// ps2 keyboard emulation
|
||||
output ps2_kbd_clk,
|
||||
output reg ps2_kbd_data,
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
|
||||
// ps2 alternative interface.
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0,
|
||||
|
||||
// ARM -> FPGA download
|
||||
input ioctl_ce,
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg [7:0] ioctl_index, // menu index used to upload the file
|
||||
output reg ioctl_wr = 0,
|
||||
output reg [24:0] ioctl_addr,
|
||||
output reg [7:0] ioctl_dout
|
||||
);
|
||||
|
||||
reg [7:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
reg [1:0] mount_strobe = 0;
|
||||
assign img_mounted = mount_strobe;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign scandoublerD = but_sw[4];
|
||||
assign ypbpr = but_sw[5];
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire drive_sel = sd_rd[1] | sd_wr[1];
|
||||
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
|
||||
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
|
||||
reg spi_do;
|
||||
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
|
||||
|
||||
reg [7:0] spi_data_out;
|
||||
|
||||
// SPI transmitter
|
||||
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
|
||||
|
||||
reg [7:0] spi_data_in;
|
||||
reg spi_data_ready = 0;
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [31:0] sd_lba_r;
|
||||
reg drive_sel_r;
|
||||
|
||||
if(CONF_DATA0) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= 0;
|
||||
spi_data_out <= core_type;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt <= bit_cnt + 1'd1;
|
||||
sbuf <= {sbuf[5:0], SPI_DI};
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
spi_data_in <= {sbuf, SPI_DI};
|
||||
spi_data_ready <= ~spi_data_ready;
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
|
||||
|
||||
spi_data_out <= 0;
|
||||
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
|
||||
// reading config string
|
||||
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
|
||||
|
||||
// reading sd card status
|
||||
8'h16: if(byte_cnt == 0) begin
|
||||
spi_data_out <= sd_cmd;
|
||||
sd_lba_r <= sd_lba;
|
||||
drive_sel_r <= drive_sel;
|
||||
end else if (byte_cnt == 1) begin
|
||||
spi_data_out <= drive_sel_r;
|
||||
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
|
||||
|
||||
// reading sd card write data
|
||||
8'h18: spi_data_out <= sd_buff_din;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
// transfer to clk_sys domain
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_ss1, old_ss2;
|
||||
reg old_ready1, old_ready2;
|
||||
reg [2:0] b_wr;
|
||||
reg got_ps2 = 0;
|
||||
|
||||
old_ss1 <= CONF_DATA0;
|
||||
old_ss2 <= old_ss1;
|
||||
old_ready1 <= spi_data_ready;
|
||||
old_ready2 <= old_ready1;
|
||||
|
||||
sd_buff_wr <= b_wr[0];
|
||||
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
if(old_ss2) begin
|
||||
got_ps2 <= 0;
|
||||
sd_ack <= 0;
|
||||
sd_ack_conf <= 0;
|
||||
sd_buff_addr <= 0;
|
||||
if(got_ps2) begin
|
||||
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
if(old_ready2 ^ old_ready1) begin
|
||||
|
||||
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
|
||||
if(byte_cnt < 2) begin
|
||||
|
||||
if (cmd == 8'h19) sd_ack_conf <= 1;
|
||||
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
|
||||
mount_strobe <= 0;
|
||||
|
||||
if(cmd == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
// buttons and switches
|
||||
8'h01: but_sw <= spi_data_in;
|
||||
8'h02: joystick_0 <= spi_data_in;
|
||||
8'h03: joystick_1 <= spi_data_in;
|
||||
// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// store incoming ps2 mouse bytes
|
||||
8'h04: begin
|
||||
got_ps2 <= 1;
|
||||
case(byte_cnt)
|
||||
2: ps2_mouse[7:0] <= spi_data_in;
|
||||
3: ps2_mouse[15:8] <= spi_data_in;
|
||||
4: ps2_mouse[23:16] <= spi_data_in;
|
||||
endcase
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
8'h05: begin
|
||||
got_ps2 <= 1;
|
||||
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
|
||||
end
|
||||
|
||||
8'h15: status[7:0] <= spi_data_in;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
8'h19,
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
8'h17: begin
|
||||
sd_buff_dout <= spi_data_in;
|
||||
b_wr <= 1;
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
8'h1a: begin
|
||||
// first byte is joystick index
|
||||
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
|
||||
else if(byte_cnt == 3) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
|
||||
end else if(byte_cnt == 4) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
|
||||
end
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
|
||||
|
||||
// send image info
|
||||
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
|
||||
// status, 32bit version
|
||||
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// PS2 ///////////////////////////////
|
||||
// 8 byte fifos to store ps2 bytes
|
||||
localparam PS2_FIFO_BITS = 3;
|
||||
|
||||
reg clk_ps2;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt == PS2DIV) begin
|
||||
clk_ps2 <= ~clk_ps2;
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// keyboard
|
||||
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_kbd_tx_state;
|
||||
reg [7:0] ps2_kbd_tx_byte;
|
||||
reg ps2_kbd_parity;
|
||||
|
||||
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_kbd_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_kbd_r_inc <= 0;
|
||||
|
||||
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_kbd_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
|
||||
ps2_kbd_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_kbd_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_kbd_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_kbd_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
|
||||
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
|
||||
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
|
||||
if(ps2_kbd_tx_byte[0])
|
||||
ps2_kbd_parity <= !ps2_kbd_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
|
||||
else ps2_kbd_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// mouse
|
||||
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_mouse_tx_state;
|
||||
reg [7:0] ps2_mouse_tx_byte;
|
||||
reg ps2_mouse_parity;
|
||||
|
||||
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_mouse_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_mouse_r_inc <= 0;
|
||||
|
||||
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_mouse_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
|
||||
ps2_mouse_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_mouse_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_mouse_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_mouse_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
|
||||
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
|
||||
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
|
||||
if(ps2_mouse_tx_byte[0])
|
||||
ps2_mouse_parity <= !ps2_mouse_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
|
||||
else ps2_mouse_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// DOWNLOADING ///////////////////////////////
|
||||
|
||||
reg [7:0] data_w;
|
||||
reg [24:0] addr_w;
|
||||
reg rclk = 0;
|
||||
|
||||
localparam UIO_FILE_TX = 8'h53;
|
||||
localparam UIO_FILE_TX_DAT = 8'h54;
|
||||
localparam UIO_FILE_INDEX = 8'h55;
|
||||
|
||||
reg rdownload = 0;
|
||||
|
||||
// data_io has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg [24:0] addr;
|
||||
|
||||
if(SPI_SS2) cnt <= 0;
|
||||
else begin
|
||||
// don't shift in last bit. It is evaluated directly
|
||||
// when writing to ram
|
||||
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
|
||||
|
||||
// count 0-7 8-15 8-15 ...
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
// finished command byte
|
||||
if(cnt == 7) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
// prepare/end transmission
|
||||
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
|
||||
// prepare
|
||||
if(SPI_DI) begin
|
||||
case(ioctl_index[4:0])
|
||||
1: addr <= 25'h200000; // TRD buffer at 2MB
|
||||
2: addr <= 25'h400000; // tape buffer at 4MB
|
||||
default: addr <= 25'h150000; // boot rom
|
||||
endcase
|
||||
rdownload <= 1;
|
||||
end else begin
|
||||
addr_w <= addr;
|
||||
rdownload <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// command 0x54: UIO_FILE_TX
|
||||
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
|
||||
addr_w <= addr;
|
||||
data_w <= {sbuf, SPI_DI};
|
||||
addr <= addr + 1'd1;
|
||||
rclk <= ~rclk;
|
||||
end
|
||||
|
||||
// expose file (menu) index
|
||||
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
|
||||
end
|
||||
end
|
||||
|
||||
// transfer to ioctl_clk domain.
|
||||
// ioctl_index is set before ioctl_download, so it's stable already
|
||||
always@(posedge clk_sys) begin
|
||||
reg rclkD, rclkD2;
|
||||
|
||||
if(ioctl_ce) begin
|
||||
ioctl_download <= rdownload;
|
||||
|
||||
rclkD <= rclk;
|
||||
rclkD2 <= rclkD;
|
||||
ioctl_wr <= 0;
|
||||
|
||||
if(rclkD != rclkD2) begin
|
||||
ioctl_dout <= data_w;
|
||||
ioctl_addr <= addr_w;
|
||||
ioctl_wr <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,194 +0,0 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd (
|
||||
// OSDs pixel clock, should be synchronous to cores pixel clock to
|
||||
// avoid jitter.
|
||||
input clk_sys,
|
||||
|
||||
// SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
input [1:0] rotate, //[0] - rotate [1] - left or right
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] R_in,
|
||||
input [5:0] G_in,
|
||||
input [5:0] B_in,
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] R_out,
|
||||
output [5:0] G_out,
|
||||
output [5:0] B_out
|
||||
);
|
||||
|
||||
parameter OSD_X_OFFSET = 10'd0;
|
||||
parameter OSD_Y_OFFSET = 10'd0;
|
||||
parameter OSD_COLOR = 3'd0;
|
||||
|
||||
localparam OSD_WIDTH = 10'd256;
|
||||
localparam OSD_HEIGHT = 10'd128;
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg osd_enable;
|
||||
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
|
||||
|
||||
// the OSD has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS3) begin
|
||||
reg [4:0] cnt;
|
||||
reg [10:0] bcnt;
|
||||
reg [7:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
|
||||
if(SPI_SS3) begin
|
||||
cnt <= 0;
|
||||
bcnt <= 0;
|
||||
end else begin
|
||||
sbuf <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// 0:7 is command, rest payload
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
|
||||
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
|
||||
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
|
||||
bcnt <= bcnt + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// *********************************************************************************
|
||||
// video timing and sync polarity anaylsis
|
||||
// *********************************************************************************
|
||||
|
||||
// horizontal counter
|
||||
reg [9:0] h_cnt;
|
||||
reg [9:0] hs_low, hs_high;
|
||||
wire hs_pol = hs_high < hs_low;
|
||||
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
|
||||
|
||||
// vertical counter
|
||||
reg [9:0] v_cnt;
|
||||
reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
|
||||
|
||||
wire doublescan = (dsp_height>350);
|
||||
|
||||
reg ce_pix;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt = 0;
|
||||
integer pixsz, pixcnt;
|
||||
reg hs;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
hs <= HSync;
|
||||
|
||||
pixcnt <= pixcnt + 1;
|
||||
if(pixcnt == pixsz) pixcnt <= 0;
|
||||
ce_pix <= !pixcnt;
|
||||
|
||||
if(hs && ~HSync) begin
|
||||
cnt <= 0;
|
||||
pixsz <= (cnt >> 9) - 1;
|
||||
pixcnt <= 0;
|
||||
ce_pix <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg hsD, hsD2;
|
||||
reg vsD, vsD2;
|
||||
|
||||
if(ce_pix) begin
|
||||
// bring hsync into local clock domain
|
||||
hsD <= HSync;
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of HSync
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of HSync
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_low <= h_cnt;
|
||||
v_cnt <= v_cnt + 1'd1;
|
||||
end else begin
|
||||
h_cnt <= h_cnt + 1'd1;
|
||||
end
|
||||
|
||||
vsD <= VSync;
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of VSync
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of VSync
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// area in which OSD is being displayed
|
||||
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
|
||||
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
|
||||
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
|
||||
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
|
||||
wire [9:0] osd_hcnt = h_cnt - h_osd_start;
|
||||
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
wire [9:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
|
||||
wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
|
||||
|
||||
wire osd_de = osd_enable &&
|
||||
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
|
||||
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
|
||||
|
||||
reg [10:0] osd_buffer_addr;
|
||||
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
|
||||
reg osd_pixel;
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
if(ce_pix) begin
|
||||
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
|
||||
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
|
||||
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
|
||||
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
|
||||
|
||||
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
|
||||
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
|
||||
end
|
||||
end
|
||||
|
||||
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
|
||||
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
|
||||
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
|
||||
|
||||
endmodule
|
||||
@@ -1,183 +0,0 @@
|
||||
//
|
||||
// scandoubler.v
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
// TODO: Delay vsync one line
|
||||
|
||||
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
// system interface
|
||||
input clk_sys,
|
||||
input ce_pix,
|
||||
input ce_pix_actual,
|
||||
|
||||
input hq2x,
|
||||
|
||||
// shifter video interface
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input line_start,
|
||||
|
||||
input [DWIDTH:0] r_in,
|
||||
input [DWIDTH:0] g_in,
|
||||
input [DWIDTH:0] b_in,
|
||||
input mono,
|
||||
|
||||
// output interface
|
||||
output reg hs_out,
|
||||
output vs_out,
|
||||
output [DWIDTH:0] r_out,
|
||||
output [DWIDTH:0] g_out,
|
||||
output [DWIDTH:0] b_out
|
||||
);
|
||||
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
assign vs_out = vs_in;
|
||||
|
||||
reg [2:0] phase;
|
||||
reg [2:0] ce_div;
|
||||
reg [7:0] pix_len = 0;
|
||||
wire [7:0] pl = pix_len + 1'b1;
|
||||
|
||||
reg ce_x1, ce_x4;
|
||||
reg req_line_reset;
|
||||
wire ls_in = hs_in | line_start;
|
||||
always @(negedge clk_sys) begin
|
||||
reg old_ce;
|
||||
reg [2:0] ce_cnt;
|
||||
|
||||
reg [7:0] pixsz2, pixsz4 = 0;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
if(~&pix_len) pix_len <= pix_len + 1'd1;
|
||||
|
||||
ce_x4 <= 0;
|
||||
ce_x1 <= 0;
|
||||
|
||||
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
|
||||
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
|
||||
phase <= phase + 1'd1;
|
||||
ce_x4 <= 1;
|
||||
end
|
||||
|
||||
if(~old_ce & ce_pix) begin
|
||||
pixsz2 <= {1'b0, pl[7:1]};
|
||||
pixsz4 <= {2'b00, pl[7:2]};
|
||||
ce_x1 <= 1;
|
||||
ce_x4 <= 1;
|
||||
pix_len <= 0;
|
||||
phase <= phase + 1'd1;
|
||||
|
||||
ce_cnt <= ce_cnt + 1'd1;
|
||||
if(ce_pix_actual) begin
|
||||
phase <= 0;
|
||||
ce_div <= ce_cnt + 1'd1;
|
||||
ce_cnt <= 0;
|
||||
req_line_reset <= 0;
|
||||
end
|
||||
|
||||
if(ls_in) req_line_reset <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg ce_sd;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: ce_sd = !phase[0];
|
||||
4: ce_sd = !phase[1:0];
|
||||
default: ce_sd <= 1;
|
||||
endcase
|
||||
end
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
|
||||
(
|
||||
.clk(clk_sys),
|
||||
.ce_x4(ce_x4 & ce_sd),
|
||||
.inputpixel({b_in,g_in,r_in}),
|
||||
.mono(mono),
|
||||
.disable_hq2x(~hq2x),
|
||||
.reset_frame(vs_in),
|
||||
.reset_line(req_line_reset),
|
||||
.read_y(sd_line),
|
||||
.read_x(sd_h_actual),
|
||||
.outpixel({b_out,g_out,r_out})
|
||||
);
|
||||
|
||||
reg [10:0] sd_h_actual;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: sd_h_actual = sd_h[10:1];
|
||||
4: sd_h_actual = sd_h[10:2];
|
||||
default: sd_h_actual = sd_h;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [10:0] sd_h;
|
||||
reg [1:0] sd_line;
|
||||
always @(posedge clk_sys) begin
|
||||
|
||||
reg [11:0] hs_max,hs_rise,hs_ls;
|
||||
reg [10:0] hcnt;
|
||||
reg [11:0] sd_hcnt;
|
||||
|
||||
reg hs, hs2, vs, ls;
|
||||
|
||||
if(ce_x1) begin
|
||||
hs <= hs_in;
|
||||
ls <= ls_in;
|
||||
|
||||
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
|
||||
|
||||
// falling edge of hsync indicates start of line
|
||||
if(hs && !hs_in) begin
|
||||
hs_max <= {hcnt,1'b1};
|
||||
hcnt <= 0;
|
||||
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
|
||||
end else begin
|
||||
hcnt <= hcnt + 1'd1;
|
||||
end
|
||||
|
||||
// save position of rising edge
|
||||
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
|
||||
|
||||
vs <= vs_in;
|
||||
if(vs && ~vs_in) sd_line <= 0;
|
||||
end
|
||||
|
||||
if(ce_x4) begin
|
||||
hs2 <= hs_in;
|
||||
|
||||
// output counter synchronous to input and at twice the rate
|
||||
sd_hcnt <= sd_hcnt + 1'd1;
|
||||
sd_h <= sd_h + 1'd1;
|
||||
if(hs2 && !hs_in) sd_hcnt <= hs_max;
|
||||
if(sd_hcnt == hs_max) sd_hcnt <= 0;
|
||||
|
||||
// replicate horizontal sync at twice the speed
|
||||
if(sd_hcnt == hs_max) hs_out <= 0;
|
||||
if(sd_hcnt == hs_rise) hs_out <= 1;
|
||||
|
||||
if(sd_hcnt == hs_ls) sd_h <= 0;
|
||||
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,442 +0,0 @@
|
||||
//
|
||||
// TV80 8-Bit Microprocessor Core
|
||||
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
|
||||
//
|
||||
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a
|
||||
// copy of this software and associated documentation files (the "Software"),
|
||||
// to deal in the Software without restriction, including without limitation
|
||||
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
// and/or sell copies of the Software, and to permit persons to whom the
|
||||
// Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
module tv80_alu (/*AUTOARG*/
|
||||
// Outputs
|
||||
Q, F_Out,
|
||||
// Inputs
|
||||
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
|
||||
);
|
||||
|
||||
parameter Mode = 0;
|
||||
parameter Flag_C = 0;
|
||||
parameter Flag_N = 1;
|
||||
parameter Flag_P = 2;
|
||||
parameter Flag_X = 3;
|
||||
parameter Flag_H = 4;
|
||||
parameter Flag_Y = 5;
|
||||
parameter Flag_Z = 6;
|
||||
parameter Flag_S = 7;
|
||||
|
||||
input Arith16;
|
||||
input Z16;
|
||||
input [3:0] ALU_Op ;
|
||||
input [5:0] IR;
|
||||
input [1:0] ISet;
|
||||
input [7:0] BusA;
|
||||
input [7:0] BusB;
|
||||
input [7:0] F_In;
|
||||
output [7:0] Q;
|
||||
output [7:0] F_Out;
|
||||
reg [7:0] Q;
|
||||
reg [7:0] F_Out;
|
||||
|
||||
function [4:0] AddSub4;
|
||||
input [3:0] A;
|
||||
input [3:0] B;
|
||||
input Sub;
|
||||
input Carry_In;
|
||||
begin
|
||||
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In};
|
||||
end
|
||||
endfunction // AddSub4
|
||||
|
||||
function [3:0] AddSub3;
|
||||
input [2:0] A;
|
||||
input [2:0] B;
|
||||
input Sub;
|
||||
input Carry_In;
|
||||
begin
|
||||
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In};
|
||||
end
|
||||
endfunction // AddSub4
|
||||
|
||||
function [1:0] AddSub1;
|
||||
input A;
|
||||
input B;
|
||||
input Sub;
|
||||
input Carry_In;
|
||||
begin
|
||||
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In};
|
||||
end
|
||||
endfunction // AddSub4
|
||||
|
||||
// AddSub variables (temporary signals)
|
||||
reg UseCarry;
|
||||
reg Carry7_v;
|
||||
reg OverFlow_v;
|
||||
reg HalfCarry_v;
|
||||
reg Carry_v;
|
||||
reg [7:0] Q_v;
|
||||
|
||||
reg [7:0] BitMask;
|
||||
|
||||
|
||||
always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
|
||||
begin
|
||||
case (IR[5:3])
|
||||
3'b000 : BitMask = 8'b00000001;
|
||||
3'b001 : BitMask = 8'b00000010;
|
||||
3'b010 : BitMask = 8'b00000100;
|
||||
3'b011 : BitMask = 8'b00001000;
|
||||
3'b100 : BitMask = 8'b00010000;
|
||||
3'b101 : BitMask = 8'b00100000;
|
||||
3'b110 : BitMask = 8'b01000000;
|
||||
default: BitMask = 8'b10000000;
|
||||
endcase // case(IR[5:3])
|
||||
|
||||
UseCarry = ~ ALU_Op[2] && ALU_Op[0];
|
||||
{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
|
||||
{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
|
||||
{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
|
||||
OverFlow_v = Carry_v ^ Carry7_v;
|
||||
end // always @ *
|
||||
|
||||
reg [7:0] Q_t;
|
||||
reg [8:0] DAA_Q;
|
||||
|
||||
always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
|
||||
or Carry_v or F_In or HalfCarry_v or IR or ISet
|
||||
or OverFlow_v or Q_v or Z16)
|
||||
begin
|
||||
Q_t = 8'hxx;
|
||||
DAA_Q = {9{1'bx}};
|
||||
|
||||
F_Out = F_In;
|
||||
case (ALU_Op)
|
||||
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
|
||||
begin
|
||||
F_Out[Flag_N] = 1'b0;
|
||||
F_Out[Flag_C] = 1'b0;
|
||||
|
||||
case (ALU_Op[2:0])
|
||||
|
||||
3'b000, 3'b001 : // ADD, ADC
|
||||
begin
|
||||
Q_t = Q_v;
|
||||
F_Out[Flag_C] = Carry_v;
|
||||
F_Out[Flag_H] = HalfCarry_v;
|
||||
F_Out[Flag_P] = OverFlow_v;
|
||||
end
|
||||
|
||||
3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
|
||||
begin
|
||||
Q_t = Q_v;
|
||||
F_Out[Flag_N] = 1'b1;
|
||||
F_Out[Flag_C] = ~ Carry_v;
|
||||
F_Out[Flag_H] = ~ HalfCarry_v;
|
||||
F_Out[Flag_P] = OverFlow_v;
|
||||
end
|
||||
|
||||
3'b100 : // AND
|
||||
begin
|
||||
Q_t[7:0] = BusA & BusB;
|
||||
F_Out[Flag_H] = 1'b1;
|
||||
end
|
||||
|
||||
3'b101 : // XOR
|
||||
begin
|
||||
Q_t[7:0] = BusA ^ BusB;
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
end
|
||||
|
||||
default : // OR 3'b110
|
||||
begin
|
||||
Q_t[7:0] = BusA | BusB;
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
end
|
||||
|
||||
endcase // case(ALU_OP[2:0])
|
||||
|
||||
if (ALU_Op[2:0] == 3'b111 )
|
||||
begin // CP
|
||||
F_Out[Flag_X] = BusB[3];
|
||||
F_Out[Flag_Y] = BusB[5];
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_X] = Q_t[3];
|
||||
F_Out[Flag_Y] = Q_t[5];
|
||||
end
|
||||
|
||||
if (Q_t[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
if (Z16 == 1'b1 )
|
||||
begin
|
||||
F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
end // else: !if(Q_t[7:0] == 8'b00000000 )
|
||||
|
||||
F_Out[Flag_S] = Q_t[7];
|
||||
case (ALU_Op[2:0])
|
||||
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
|
||||
;
|
||||
|
||||
default :
|
||||
F_Out[Flag_P] = ~(^Q_t);
|
||||
endcase // case(ALU_Op[2:0])
|
||||
|
||||
if (Arith16 == 1'b1 )
|
||||
begin
|
||||
F_Out[Flag_S] = F_In[Flag_S];
|
||||
F_Out[Flag_Z] = F_In[Flag_Z];
|
||||
F_Out[Flag_P] = F_In[Flag_P];
|
||||
end
|
||||
end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
|
||||
|
||||
4'b1100 :
|
||||
begin
|
||||
// DAA
|
||||
F_Out[Flag_H] = F_In[Flag_H];
|
||||
F_Out[Flag_C] = F_In[Flag_C];
|
||||
DAA_Q[7:0] = BusA;
|
||||
DAA_Q[8] = 1'b0;
|
||||
if (F_In[Flag_N] == 1'b0 )
|
||||
begin
|
||||
// After addition
|
||||
// Alow > 9 || H == 1
|
||||
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
|
||||
begin
|
||||
if ((DAA_Q[3:0] > 9) )
|
||||
begin
|
||||
F_Out[Flag_H] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
end
|
||||
DAA_Q = DAA_Q + 6;
|
||||
end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
|
||||
|
||||
// new Ahigh > 9 || C == 1
|
||||
if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 )
|
||||
begin
|
||||
DAA_Q = DAA_Q + 96; // 0x60
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
// After subtraction
|
||||
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
|
||||
begin
|
||||
if (DAA_Q[3:0] > 5 )
|
||||
begin
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
end
|
||||
DAA_Q[7:0] = DAA_Q[7:0] - 6;
|
||||
end
|
||||
if (BusA > 153 || F_In[Flag_C] == 1'b1 )
|
||||
begin
|
||||
DAA_Q = DAA_Q - 352; // 0x160
|
||||
end
|
||||
end // else: !if(F_In[Flag_N] == 1'b0 )
|
||||
|
||||
F_Out[Flag_X] = DAA_Q[3];
|
||||
F_Out[Flag_Y] = DAA_Q[5];
|
||||
F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
|
||||
Q_t = DAA_Q[7:0];
|
||||
|
||||
if (DAA_Q[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
end
|
||||
|
||||
F_Out[Flag_S] = DAA_Q[7];
|
||||
F_Out[Flag_P] = ~ (^DAA_Q);
|
||||
end // case: 4'b1100
|
||||
|
||||
4'b1101, 4'b1110 :
|
||||
begin
|
||||
// RLD, RRD
|
||||
Q_t[7:4] = BusA[7:4];
|
||||
if (ALU_Op[0] == 1'b1 )
|
||||
begin
|
||||
Q_t[3:0] = BusB[7:4];
|
||||
end
|
||||
else
|
||||
begin
|
||||
Q_t[3:0] = BusB[3:0];
|
||||
end
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
F_Out[Flag_N] = 1'b0;
|
||||
F_Out[Flag_X] = Q_t[3];
|
||||
F_Out[Flag_Y] = Q_t[5];
|
||||
if (Q_t[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
end
|
||||
F_Out[Flag_S] = Q_t[7];
|
||||
F_Out[Flag_P] = ~(^Q_t);
|
||||
end // case: when 4'b1101, 4'b1110
|
||||
|
||||
4'b1001 :
|
||||
begin
|
||||
// BIT
|
||||
Q_t[7:0] = BusB & BitMask;
|
||||
F_Out[Flag_S] = Q_t[7];
|
||||
if (Q_t[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
F_Out[Flag_P] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
F_Out[Flag_P] = 1'b0;
|
||||
end
|
||||
F_Out[Flag_H] = 1'b1;
|
||||
F_Out[Flag_N] = 1'b0;
|
||||
F_Out[Flag_X] = 1'b0;
|
||||
F_Out[Flag_Y] = 1'b0;
|
||||
if (IR[2:0] != 3'b110 )
|
||||
begin
|
||||
F_Out[Flag_X] = BusB[3];
|
||||
F_Out[Flag_Y] = BusB[5];
|
||||
end
|
||||
end // case: when 4'b1001
|
||||
|
||||
4'b1010 :
|
||||
// SET
|
||||
Q_t[7:0] = BusB | BitMask;
|
||||
|
||||
4'b1011 :
|
||||
// RES
|
||||
Q_t[7:0] = BusB & ~ BitMask;
|
||||
|
||||
4'b1000 :
|
||||
begin
|
||||
// ROT
|
||||
case (IR[5:3])
|
||||
3'b000 : // RLC
|
||||
begin
|
||||
Q_t[7:1] = BusA[6:0];
|
||||
Q_t[0] = BusA[7];
|
||||
F_Out[Flag_C] = BusA[7];
|
||||
end
|
||||
|
||||
3'b010 : // RL
|
||||
begin
|
||||
Q_t[7:1] = BusA[6:0];
|
||||
Q_t[0] = F_In[Flag_C];
|
||||
F_Out[Flag_C] = BusA[7];
|
||||
end
|
||||
|
||||
3'b001 : // RRC
|
||||
begin
|
||||
Q_t[6:0] = BusA[7:1];
|
||||
Q_t[7] = BusA[0];
|
||||
F_Out[Flag_C] = BusA[0];
|
||||
end
|
||||
|
||||
3'b011 : // RR
|
||||
begin
|
||||
Q_t[6:0] = BusA[7:1];
|
||||
Q_t[7] = F_In[Flag_C];
|
||||
F_Out[Flag_C] = BusA[0];
|
||||
end
|
||||
|
||||
3'b100 : // SLA
|
||||
begin
|
||||
Q_t[7:1] = BusA[6:0];
|
||||
Q_t[0] = 1'b0;
|
||||
F_Out[Flag_C] = BusA[7];
|
||||
end
|
||||
|
||||
3'b110 : // SLL (Undocumented) / SWAP
|
||||
begin
|
||||
if (Mode == 3 )
|
||||
begin
|
||||
Q_t[7:4] = BusA[3:0];
|
||||
Q_t[3:0] = BusA[7:4];
|
||||
F_Out[Flag_C] = 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Q_t[7:1] = BusA[6:0];
|
||||
Q_t[0] = 1'b1;
|
||||
F_Out[Flag_C] = BusA[7];
|
||||
end // else: !if(Mode == 3 )
|
||||
end // case: 3'b110
|
||||
|
||||
3'b101 : // SRA
|
||||
begin
|
||||
Q_t[6:0] = BusA[7:1];
|
||||
Q_t[7] = BusA[7];
|
||||
F_Out[Flag_C] = BusA[0];
|
||||
end
|
||||
|
||||
default : // SRL
|
||||
begin
|
||||
Q_t[6:0] = BusA[7:1];
|
||||
Q_t[7] = 1'b0;
|
||||
F_Out[Flag_C] = BusA[0];
|
||||
end
|
||||
endcase // case(IR[5:3])
|
||||
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
F_Out[Flag_N] = 1'b0;
|
||||
F_Out[Flag_X] = Q_t[3];
|
||||
F_Out[Flag_Y] = Q_t[5];
|
||||
F_Out[Flag_S] = Q_t[7];
|
||||
if (Q_t[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
end
|
||||
F_Out[Flag_P] = ~(^Q_t);
|
||||
|
||||
if (ISet == 2'b00 )
|
||||
begin
|
||||
F_Out[Flag_P] = F_In[Flag_P];
|
||||
F_Out[Flag_S] = F_In[Flag_S];
|
||||
F_Out[Flag_Z] = F_In[Flag_Z];
|
||||
end
|
||||
end // case: 4'b1000
|
||||
|
||||
|
||||
default :
|
||||
;
|
||||
|
||||
endcase // case(ALU_Op)
|
||||
|
||||
Q = Q_t;
|
||||
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
|
||||
endmodule // T80_ALU
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,77 +0,0 @@
|
||||
//
|
||||
// TV80 8-Bit Microprocessor Core
|
||||
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
|
||||
//
|
||||
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a
|
||||
// copy of this software and associated documentation files (the "Software"),
|
||||
// to deal in the Software without restriction, including without limitation
|
||||
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
// and/or sell copies of the Software, and to permit persons to whom the
|
||||
// Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
module tv80_reg (/*AUTOARG*/
|
||||
// Outputs
|
||||
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
|
||||
// Inputs
|
||||
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
|
||||
);
|
||||
input [2:0] AddrC;
|
||||
output [7:0] DOBH;
|
||||
input [2:0] AddrA;
|
||||
input [2:0] AddrB;
|
||||
input [7:0] DIH;
|
||||
output [7:0] DOAL;
|
||||
output [7:0] DOCL;
|
||||
input [7:0] DIL;
|
||||
output [7:0] DOBL;
|
||||
output [7:0] DOCH;
|
||||
output [7:0] DOAH;
|
||||
input clk, CEN, WEH, WEL;
|
||||
|
||||
reg [7:0] RegsH [0:7];
|
||||
reg [7:0] RegsL [0:7];
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (CEN)
|
||||
begin
|
||||
if (WEH) RegsH[AddrA] <= DIH;
|
||||
if (WEL) RegsL[AddrA] <= DIL;
|
||||
end
|
||||
end
|
||||
|
||||
assign DOAH = RegsH[AddrA];
|
||||
assign DOAL = RegsL[AddrA];
|
||||
assign DOBH = RegsH[AddrB];
|
||||
assign DOBL = RegsL[AddrB];
|
||||
assign DOCH = RegsH[AddrC];
|
||||
assign DOCL = RegsL[AddrC];
|
||||
|
||||
// break out ram bits for waveform debug
|
||||
// synopsys translate_off
|
||||
wire [7:0] B = RegsH[0];
|
||||
wire [7:0] C = RegsL[0];
|
||||
wire [7:0] D = RegsH[1];
|
||||
wire [7:0] E = RegsL[1];
|
||||
wire [7:0] H = RegsH[2];
|
||||
wire [7:0] L = RegsL[2];
|
||||
|
||||
wire [15:0] IX = { RegsH[3], RegsL[3] };
|
||||
wire [15:0] IY = { RegsH[7], RegsL[7] };
|
||||
// synopsys translate_on
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,243 +0,0 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
// LINE_LENGTH: Length of display line in pixels
|
||||
// Usually it's length from HSync to HSync.
|
||||
// May be less if line_start is used.
|
||||
//
|
||||
// HALF_DEPTH: If =1 then color dept is 3 bits per component
|
||||
// For half depth 6 bits monochrome is available with
|
||||
// mono signal enabled and color = {G, R}
|
||||
|
||||
module video_mixer
|
||||
#(
|
||||
parameter LINE_LENGTH = 768,
|
||||
parameter HALF_DEPTH = 0,
|
||||
|
||||
parameter OSD_COLOR = 3'd4,
|
||||
parameter OSD_X_OFFSET = 10'd0,
|
||||
parameter OSD_Y_OFFSET = 10'd0
|
||||
)
|
||||
(
|
||||
// master clock
|
||||
// it should be multiple by (ce_pix*4).
|
||||
input clk_sys,
|
||||
|
||||
// Pixel clock or clock_enable (both are accepted).
|
||||
input ce_pix,
|
||||
|
||||
// Some systems have multiple resolutions.
|
||||
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
|
||||
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
|
||||
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
|
||||
input ce_pix_actual,
|
||||
|
||||
// OSD SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
// scanlines (00-none 01-25% 10-50% 11-75%)
|
||||
input [1:0] scanlines,
|
||||
|
||||
// 0 = HVSync 31KHz, 1 = CSync 15KHz
|
||||
input scandoublerD,
|
||||
|
||||
// High quality 2x scaling
|
||||
input hq2x,
|
||||
|
||||
// YPbPr always uses composite sync
|
||||
input ypbpr,
|
||||
|
||||
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
|
||||
input ypbpr_full,
|
||||
input [1:0] rotate, //[0] - rotate [1] - left or right
|
||||
// color
|
||||
input [DWIDTH:0] R,
|
||||
input [DWIDTH:0] G,
|
||||
input [DWIDTH:0] B,
|
||||
|
||||
// Monochrome mode (for HALF_DEPTH only)
|
||||
input mono,
|
||||
|
||||
// interlace sync. Positive pulses.
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// Falling of this signal means start of informative part of line.
|
||||
// It can be horizontal blank signal.
|
||||
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
|
||||
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
|
||||
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
|
||||
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
|
||||
// before first informative pixel.
|
||||
input line_start,
|
||||
|
||||
// MiST video output signals
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_VS,
|
||||
output VGA_HS
|
||||
);
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
wire [DWIDTH:0] R_sd;
|
||||
wire [DWIDTH:0] G_sd;
|
||||
wire [DWIDTH:0] B_sd;
|
||||
wire hs_sd, vs_sd;
|
||||
|
||||
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
|
||||
(
|
||||
.*,
|
||||
.hs_in(HSync),
|
||||
.vs_in(VSync),
|
||||
.r_in(R),
|
||||
.g_in(G),
|
||||
.b_in(B),
|
||||
|
||||
.hs_out(hs_sd),
|
||||
.vs_out(vs_sd),
|
||||
.r_out(R_sd),
|
||||
.g_out(G_sd),
|
||||
.b_out(B_sd)
|
||||
);
|
||||
|
||||
wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd);
|
||||
wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd);
|
||||
wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd);
|
||||
|
||||
generate
|
||||
if(HALF_DEPTH) begin
|
||||
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
|
||||
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
|
||||
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
|
||||
end else begin
|
||||
wire [5:0] r = rt;
|
||||
wire [5:0] g = gt;
|
||||
wire [5:0] b = bt;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire hs = (scandoublerD ? HSync : hs_sd);
|
||||
wire vs = (scandoublerD ? VSync : vs_sd);
|
||||
|
||||
reg scanline = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg old_hs, old_vs;
|
||||
|
||||
old_hs <= hs;
|
||||
old_vs <= vs;
|
||||
|
||||
if(old_hs && ~hs) scanline <= ~scanline;
|
||||
if(old_vs && ~vs) scanline <= 0;
|
||||
end
|
||||
|
||||
wire [5:0] r_out, g_out, b_out;
|
||||
always @(*) begin
|
||||
case(scanlines & {scanline, scanline})
|
||||
1: begin // reduce 25% = 1/2 + 1/4
|
||||
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
|
||||
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
|
||||
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
2: begin // reduce 50% = 1/2
|
||||
r_out = {1'b0, r[5:1]};
|
||||
g_out = {1'b0, g[5:1]};
|
||||
b_out = {1'b0, b[5:1]};
|
||||
end
|
||||
|
||||
3: begin // reduce 75% = 1/4
|
||||
r_out = {2'b00, r[5:2]};
|
||||
g_out = {2'b00, g[5:2]};
|
||||
b_out = {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
default: begin
|
||||
r_out = r;
|
||||
g_out = g;
|
||||
b_out = b;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
wire [5:0] red, green, blue;
|
||||
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
|
||||
(
|
||||
.*,
|
||||
|
||||
.R_in(r_out),
|
||||
.G_in(g_out),
|
||||
.B_in(b_out),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.rotate(rotate),
|
||||
|
||||
.R_out(red),
|
||||
.G_out(green),
|
||||
.B_out(blue)
|
||||
);
|
||||
|
||||
wire [5:0] yuv_full[225] = '{
|
||||
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
|
||||
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
|
||||
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
|
||||
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
|
||||
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
|
||||
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
|
||||
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
|
||||
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
|
||||
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
|
||||
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
|
||||
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
|
||||
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
|
||||
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
|
||||
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
|
||||
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
|
||||
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
|
||||
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
|
||||
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
|
||||
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
|
||||
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
|
||||
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
|
||||
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
|
||||
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
|
||||
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
|
||||
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
|
||||
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
|
||||
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
|
||||
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
|
||||
6'd63
|
||||
};
|
||||
|
||||
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
|
||||
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
|
||||
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
|
||||
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
|
||||
|
||||
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
|
||||
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
|
||||
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
|
||||
|
||||
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
|
||||
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
|
||||
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
|
||||
assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
|
||||
assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
|
||||
|
||||
endmodule
|
||||
@@ -41,7 +41,7 @@
|
||||
# ========================
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
|
||||
@@ -53,7 +53,7 @@ localparam CONF_STR = {
|
||||
"O5,Blend,Off,On;",
|
||||
"O6,Service,Off,On;",
|
||||
"T0,Reset;",
|
||||
"V,v1.0.",`BUILD_DATE
|
||||
"V,v1.1.",`BUILD_DATE
|
||||
};
|
||||
|
||||
wire rotate = status[2];
|
||||
|
||||
@@ -41,7 +41,7 @@
|
||||
# ========================
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
|
||||
@@ -1,36 +0,0 @@
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- Arcade: Defender port to MiST by Gehstock
|
||||
-- 11 June 2019
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
-- A simulation model of Williams 6809 hardware
|
||||
-- by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- Only controls and OSD are rotated on Video output.
|
||||
--
|
||||
--
|
||||
-- Keyboard inputs :
|
||||
--
|
||||
-- Fire = Fire or Space
|
||||
-- Thrust = Fire2 or ALT
|
||||
-- Smart Bomb = Fire3 or CTRL
|
||||
-- Hyperspace = Fire4 or 1
|
||||
-- Change Direction = Left or Right
|
||||
-- Up = Up
|
||||
-- Down = Down
|
||||
|
||||
-- Advance = A
|
||||
-- Auto up = U
|
||||
-- Score_reset = H
|
||||
--
|
||||
-- Joystick support.
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
DEFENDER.ROM is required at the root of the SD-Card.
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
|
||||
@@ -1,13 +1,36 @@
|
||||
Games that should work on this Hardware
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- Arcade: Defender port to MiST by Gehstock
|
||||
-- 11 June 2019
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
-- A simulation model of Williams 6809 hardware
|
||||
-- by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- Only controls and OSD are rotated on Video output.
|
||||
--
|
||||
--
|
||||
-- Keyboard inputs :
|
||||
--
|
||||
-- Fire = Fire or Space
|
||||
-- Thrust = Fire2 or ALT
|
||||
-- Smart Bomb = Fire3 or CTRL
|
||||
-- Hyperspace = Fire4 or 1
|
||||
-- Change Direction = Left or Right
|
||||
-- Up = Up
|
||||
-- Down = Down
|
||||
|
||||
-- Advance = A
|
||||
-- Auto up = U
|
||||
-- Score_reset = H
|
||||
--
|
||||
-- Joystick support.
|
||||
--
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
DEFENDER.ROM is required at the root of the SD-Card.
|
||||
|
||||
Alien Arena
|
||||
Blaster
|
||||
Bubbles
|
||||
Joust
|
||||
Lotto Fun
|
||||
Playball!
|
||||
Robotron
|
||||
Sinistar
|
||||
Speed Ball
|
||||
Splat!
|
||||
Stargate
|
||||
@@ -28,4 +28,4 @@ DATE = "04:04:47 October 16, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Defender_MiST"
|
||||
PROJECT_REVISION = "Williams6809rev1_MiST"
|
||||
@@ -25,7 +25,7 @@
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Defender_MiST_assignment_defaults.qdf
|
||||
# Williams6809rev1_MiST_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
@@ -43,7 +43,7 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13 JUNE 04, 2019"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
|
||||
# Pin & Location Assignments
|
||||
@@ -171,26 +171,9 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
@@ -198,9 +181,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
@@ -218,7 +198,27 @@ set_global_assignment -name QIP_FILE rtl/pll_mist.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../common/IO/pia6821.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../common/CPU/MC6809/cpu09l_128a.vhd
|
||||
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
|
||||
set_global_assignment -name VHDL_FILE ../../common/IO/pia6821.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../common/CPU/MC6809/cpu09l_128a.vhd
|
||||
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Reference in New Issue
Block a user