mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-27 02:04:37 +00:00
Fix Atari Hardware Video, Cleanup
This commit is contained in:
Gehstock
@@ -1,113 +0,0 @@
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--------------------------------------------------------------------------------
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-- Copyright (c) 2015 David Banks
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ /
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-- \ \ \/
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-- \ \
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-- / / Filename : ElectronFpga.vhf
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-- /___/ /\ Timestamp : 28/07/2015
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-- \ \ / \
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-- \___\/\___\
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--
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--Design Name: ElectronFpga
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--Device: Spartan6 LX9
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity ElectronFpga_MiST is
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port (
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CLOCK_27 : in std_logic;
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VGA_R : out std_logic_vector (2 downto 0);
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VGA_G : out std_logic_vector (2 downto 0);
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VGA_B : out std_logic_vector (2 downto 0);
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VGA_VS : out std_logic;
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VGA_HS : out std_logic;
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AUDIO_L : out std_logic;
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AUDIO_R : out std_logic;
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casIn : in std_logic;
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casOut : out std_logic;
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LED : out std_logic;
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SDMISO : in std_logic;
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SDSS : out std_logic;
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SDCLK : out std_logic;
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SDMOSI : out std_logic
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);
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end;
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architecture behavioral of ElectronFpga_MiST is
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signal clk_16M00 : std_logic;
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signal clk_33M33 : std_logic;
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signal clk_40M00 : std_logic;
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signal ERSTn : std_logic;
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signal ps2_clk : std_logic;
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signal ps2_data : std_logic;
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signal pwrup_RSTn : std_logic;
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signal reset_ctr : std_logic_vector (7 downto 0) := (others => '0');
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component pll27
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PORT
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(
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC
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);
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end component;
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begin
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pll27_inst : pll27 PORT MAP (
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inclk0 => CLOCK_27,
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c0 => clk_40M00,
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c1 => clk_16M00,
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c2 => clk_33M33
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);
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inst_ElectronFpga_core : entity work.ElectronFpga_core
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port map (
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clk_16M00 => clk_16M00,
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clk_33M33 => clk_33M33,
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clk_40M00 => clk_40M00,
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ps2_clk => ps2_clk,
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ps2_data => ps2_data,
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ERSTn => ERSTn,
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red => VGA_R,
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green => VGA_G,
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blue => VGA_B,
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vsync => VGA_VS,
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hsync => VGA_HS,
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audiol => AUDIO_L,
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audioR => AUDIO_R,
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casIn => casIn,
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casOut => casOut,
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LED1 => LED,
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SDMISO => SDMISO,
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SDSS => SDSS,
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SDCLK => SDCLK,
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SDMOSI => SDMOSI
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);
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ERSTn <= pwrup_RSTn;
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-- This internal counter forces power up reset to happen
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-- This is needed by the GODIL to initialize some of the registers
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ResetProcess : process (clk_16M00)
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begin
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if rising_edge(clk_16M00) then
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if (pwrup_RSTn = '0') then
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reset_ctr <= reset_ctr + 1;
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end if;
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end if;
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end process;
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pwrup_RSTn <= reset_ctr(7);
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end behavioral;
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@@ -1,31 +0,0 @@
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# -------------------------------------------------------------------------- #
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||||
#
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# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
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||||
# Date created = 14:32:28 October 06, 2018
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||||
#
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||||
# -------------------------------------------------------------------------- #
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||||
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QUARTUS_VERSION = "13.0"
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DATE = "14:32:28 October 06, 2018"
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# Revisions
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PROJECT_REVISION = "Galaksija_Mist"
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PROJECT_REVISION = "AtomElectron_Mist"
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@@ -1,222 +0,0 @@
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# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||
# Date created = 23:16:13 October 05, 2018
|
||||
#
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||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# AtomElectron_Mist_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
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||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53 MARCH 09, 2017"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
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||||
set_location_assignment PIN_54 -to CLOCK_27
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||||
set_location_assignment PIN_144 -to VGA_R[5]
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||||
set_location_assignment PIN_143 -to VGA_R[4]
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||||
set_location_assignment PIN_142 -to VGA_R[3]
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||||
set_location_assignment PIN_141 -to VGA_R[2]
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||||
set_location_assignment PIN_137 -to VGA_R[1]
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||||
set_location_assignment PIN_135 -to VGA_R[0]
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||||
set_location_assignment PIN_133 -to VGA_B[5]
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||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
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||||
set_location_assignment PIN_121 -to VGA_B[2]
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||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PIN_31 -to UART_RXD
|
||||
set_location_assignment PIN_46 -to UART_TXD
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Galaksija_MiST
|
||||
set_global_assignment -name SEARCH_PATH roms/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/MC6522/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/RAM/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/T6502/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/ps2kybrd/ -tag from_archive
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# start EDA_TOOL_SETTINGS(eda_simulation)
|
||||
# ---------------------------------------
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
|
||||
# end EDA_TOOL_SETTINGS(eda_simulation)
|
||||
# -------------------------------------
|
||||
|
||||
# -------------------------------
|
||||
# start ENTITY(AtomElectron_Mist)
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(AtomElectron_Mist)
|
||||
# -----------------------------
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaksija_MiST.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/galaksija_top.v
|
||||
set_global_assignment -name VHDL_FILE rtl/spram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/osd.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/video.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/TV80/tv80n.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_reg.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_mcode.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_core.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_alu.v
|
||||
set_global_assignment -name VHDL_FILE rtl/galaksija_keyboard_v2.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ay8910.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,7 +0,0 @@
|
||||
WIP
|
||||
|
||||
VGA Only, No Keyboard
|
||||
|
||||
32k Ram
|
||||
Rom 1+2
|
||||
AY8910
|
||||
Binary file not shown.
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|
Before Width: | Height: | Size: 72 KiB |
@@ -1,278 +0,0 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Krzysztof Strzecha, Miodrag Milanovic
|
||||
/***************************************************************************
|
||||
Galaksija driver by Krzysztof Strzecha and Miodrag Milanovic
|
||||
|
||||
22/05/2008 Tape support added (Miodrag Milanovic)
|
||||
21/05/2008 Galaksija plus initial support (Miodrag Milanovic)
|
||||
20/05/2008 Added real video implementation (Miodrag Milanovic)
|
||||
18/04/2005 Possibilty to disable ROM 2. 2k, 22k, 38k and 54k memory
|
||||
configurations added.
|
||||
13/03/2005 Memory mapping improved. Palette corrected. Supprort for newer
|
||||
version of snapshots added. Lot of cleanups. Keyboard mapping
|
||||
corrected.
|
||||
19/09/2002 malloc() replaced by image_malloc().
|
||||
15/09/2002 Snapshot loading fixed. Code cleanup.
|
||||
31/01/2001 Snapshot loading corrected.
|
||||
09/01/2001 Fast mode implemented (many thanks to Kevin Thacker).
|
||||
07/01/2001 Keyboard corrected (still some keys unknown).
|
||||
Horizontal screen positioning in video subsystem added.
|
||||
05/01/2001 Keyboard implemented (some keys unknown).
|
||||
03/01/2001 Snapshot loading added.
|
||||
01/01/2001 Preliminary driver.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "includes/galaxy.h"
|
||||
|
||||
#include "cpu/z80/z80.h"
|
||||
#include "formats/gtp_cas.h"
|
||||
#include "imagedev/cassette.h"
|
||||
#include "imagedev/snapquik.h"
|
||||
#include "machine/ram.h"
|
||||
#include "sound/ay8910.h"
|
||||
#include "sound/wave.h"
|
||||
#include "emupal.h"
|
||||
#include "screen.h"
|
||||
#include "softlist.h"
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
void galaxy_state::galaxyp_io(address_map &map)
|
||||
{
|
||||
map.global_mask(0x01);
|
||||
map.unmap_value_high();
|
||||
map(0x00, 0x00).w("ay8910", FUNC(ay8910_device::address_w));
|
||||
map(0x01, 0x01).w("ay8910", FUNC(ay8910_device::data_w));
|
||||
}
|
||||
|
||||
|
||||
void galaxy_state::galaxy_mem(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x0fff).rom();
|
||||
map(0x2000, 0x2037).mirror(0x07c0).r(FUNC(galaxy_state::galaxy_keyboard_r));
|
||||
map(0x2038, 0x203f).mirror(0x07c0).w(FUNC(galaxy_state::galaxy_latch_w));
|
||||
}
|
||||
|
||||
void galaxy_state::galaxyp_mem(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x0fff).rom(); // ROM A
|
||||
map(0x1000, 0x1fff).rom(); // ROM B
|
||||
map(0x2000, 0x2037).mirror(0x07c0).r(FUNC(galaxy_state::galaxy_keyboard_r));
|
||||
map(0x2038, 0x203f).mirror(0x07c0).w(FUNC(galaxy_state::galaxy_latch_w));
|
||||
map(0xe000, 0xefff).rom(); // ROM C
|
||||
map(0xf000, 0xffff).rom(); // ROM D
|
||||
}
|
||||
|
||||
/* 2008-05 FP:
|
||||
Small note about natural keyboard support. Currently:
|
||||
- "List" is mapped to 'ESC'
|
||||
- "Break" is mapped to 'F1'
|
||||
- "Repeat" is mapped to 'F2' */
|
||||
|
||||
static INPUT_PORTS_START (galaxy_common)
|
||||
PORT_START("LINE0")
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNUSED)
|
||||
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('A')
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('B')
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('C')
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('D')
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('E')
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('F')
|
||||
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('G')
|
||||
|
||||
PORT_START("LINE1")
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('H')
|
||||
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('I')
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('J')
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('K')
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('L')
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('M')
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('N')
|
||||
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('O')
|
||||
|
||||
PORT_START("LINE2")
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('P')
|
||||
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q')
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('R')
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('S')
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('T')
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('U')
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('V')
|
||||
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('W')
|
||||
|
||||
PORT_START("LINE3")
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('X')
|
||||
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y')
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('Z')
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
|
||||
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
|
||||
|
||||
PORT_START("LINE4")
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('_')
|
||||
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
|
||||
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
|
||||
|
||||
PORT_START("LINE5")
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
|
||||
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*')
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('-')
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
|
||||
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
|
||||
|
||||
PORT_START("LINE6")
|
||||
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
|
||||
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Break") PORT_CODE(KEYCODE_PAUSE) PORT_CHAR(UCHAR_MAMEKEY(F1))
|
||||
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Repeat") PORT_CODE(KEYCODE_LALT) PORT_CHAR(UCHAR_MAMEKEY(F2))
|
||||
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Delete") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
|
||||
PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("List") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
|
||||
PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
|
||||
PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_UNUSED)
|
||||
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_UNUSED)
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( galaxy )
|
||||
PORT_INCLUDE( galaxy_common )
|
||||
PORT_START("ROM2")
|
||||
PORT_CONFNAME(0x01, 0x01, "ROM 2")
|
||||
PORT_CONFSETTING(0x01, "Installed")
|
||||
PORT_CONFSETTING(0x00, "Not installed")
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( galaxyp )
|
||||
PORT_INCLUDE( galaxy_common )
|
||||
INPUT_PORTS_END
|
||||
|
||||
#define XTAL 6144000
|
||||
|
||||
/* F4 Character Displayer */
|
||||
static const gfx_layout galaxy_charlayout =
|
||||
{
|
||||
8, 16, /* 8 x 16 characters */
|
||||
128, /* 128 characters */
|
||||
1, /* 1 bits per pixel */
|
||||
{ 0 }, /* no bitplanes */
|
||||
/* x offsets */
|
||||
{ 7, 6, 5, 4, 3, 2, 1, 0 },
|
||||
/* y offsets */
|
||||
{ 0, 1*128*8, 2*128*8, 3*128*8, 4*128*8, 5*128*8, 6*128*8, 7*128*8, 8*128*8, 9*128*8, 10*128*8, 11*128*8, 12*128*8, 13*128*8, 14*128*8, 15*128*8 },
|
||||
8 /* every char takes 1 x 16 bytes */
|
||||
};
|
||||
|
||||
static GFXDECODE_START( gfx_galaxy )
|
||||
GFXDECODE_ENTRY( "gfx1", 0x0000, galaxy_charlayout, 0, 1 )
|
||||
GFXDECODE_END
|
||||
|
||||
|
||||
MACHINE_CONFIG_START(galaxy_state::galaxy)
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", Z80, XTAL / 2)
|
||||
MCFG_DEVICE_PROGRAM_MAP(galaxy_mem)
|
||||
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", galaxy_state, galaxy_interrupt)
|
||||
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(galaxy_state,galaxy_irq_callback)
|
||||
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_REFRESH_RATE(50)
|
||||
MCFG_SCREEN_PALETTE("palette")
|
||||
|
||||
MCFG_MACHINE_RESET_OVERRIDE(galaxy_state, galaxy )
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SIZE(384, 212)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 384-1, 0, 208-1)
|
||||
MCFG_SCREEN_UPDATE_DRIVER(galaxy_state, screen_update_galaxy)
|
||||
|
||||
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_galaxy)
|
||||
MCFG_PALETTE_ADD_MONOCHROME("palette")
|
||||
|
||||
|
||||
/* snapshot */
|
||||
MCFG_SNAPSHOT_ADD("snapshot", galaxy_state, galaxy, "gal", 0)
|
||||
|
||||
SPEAKER(config, "mono").front_center();
|
||||
WAVE(config, "wave", "cassette").add_route(ALL_OUTPUTS, "mono", 0.25);
|
||||
|
||||
MCFG_CASSETTE_ADD( "cassette" )
|
||||
MCFG_CASSETTE_FORMATS(gtp_cassette_formats)
|
||||
MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_SPEAKER_ENABLED | CASSETTE_MOTOR_ENABLED)
|
||||
MCFG_CASSETTE_INTERFACE("galaxy_cass")
|
||||
|
||||
MCFG_SOFTWARE_LIST_ADD("cass_list","galaxy")
|
||||
|
||||
/* internal ram */
|
||||
RAM(config, RAM_TAG).set_default_size("6K").set_extra_options("2K,22K,38K,54K");
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
MACHINE_CONFIG_START(galaxy_state::galaxyp)
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", Z80, XTAL / 2)
|
||||
MCFG_DEVICE_PROGRAM_MAP(galaxyp_mem)
|
||||
MCFG_DEVICE_IO_MAP(galaxyp_io)
|
||||
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", galaxy_state, galaxy_interrupt)
|
||||
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(galaxy_state,galaxy_irq_callback)
|
||||
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_REFRESH_RATE(50)
|
||||
MCFG_SCREEN_PALETTE("palette")
|
||||
|
||||
MCFG_MACHINE_RESET_OVERRIDE(galaxy_state, galaxyp )
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_SIZE(384, 208)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 384-1, 0, 208-1)
|
||||
MCFG_SCREEN_UPDATE_DRIVER(galaxy_state, screen_update_galaxy)
|
||||
|
||||
MCFG_PALETTE_ADD_MONOCHROME("palette")
|
||||
|
||||
|
||||
/* snapshot */
|
||||
MCFG_SNAPSHOT_ADD("snapshot", galaxy_state, galaxy, "gal", 0)
|
||||
|
||||
/* sound hardware */
|
||||
SPEAKER(config, "mono").front_center();
|
||||
MCFG_DEVICE_ADD("ay8910", AY8910, XTAL/4) // FIXME: really no output routes for this AY?
|
||||
WAVE(config, "wave", "cassette").add_route(ALL_OUTPUTS, "mono", 0.25);
|
||||
|
||||
MCFG_CASSETTE_ADD( "cassette" )
|
||||
MCFG_CASSETTE_FORMATS(gtp_cassette_formats)
|
||||
MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_SPEAKER_ENABLED | CASSETTE_MOTOR_ENABLED)
|
||||
MCFG_CASSETTE_INTERFACE("galaxy_cass")
|
||||
|
||||
MCFG_SOFTWARE_LIST_ADD("cass_list","galaxy")
|
||||
|
||||
/* internal ram */
|
||||
RAM(config, RAM_TAG).set_default_size("38K");
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
ROM_START (galaxy)
|
||||
ROM_REGION (0x10000, "maincpu", ROMREGION_ERASEFF)
|
||||
ROM_LOAD ("galrom1.bin", 0x0000, 0x1000, CRC(dc970a32) SHA1(dfc92163654a756b70f5a446daf49d7534f4c739))
|
||||
ROM_LOAD_OPTIONAL ("galrom2.bin", 0x1000, 0x1000, CRC(5dc5a100) SHA1(5d5ab4313a2d0effe7572bb129193b64cab002c1))
|
||||
ROM_REGION(0x0800, "gfx1",0)
|
||||
ROM_LOAD ("galchr.bin", 0x0000, 0x0800, CRC(5c3b5bb5) SHA1(19429a61dc5e55ddec3242a8f695e06dd7961f88))
|
||||
ROM_END
|
||||
|
||||
ROM_START (galaxyp)
|
||||
ROM_REGION (0x10000, "maincpu", ROMREGION_ERASEFF)
|
||||
ROM_LOAD ("galrom1.bin", 0x0000, 0x1000, CRC(dc970a32) SHA1(dfc92163654a756b70f5a446daf49d7534f4c739))
|
||||
ROM_LOAD ("galrom2.bin", 0x1000, 0x1000, CRC(5dc5a100) SHA1(5d5ab4313a2d0effe7572bb129193b64cab002c1))
|
||||
ROM_LOAD ("galplus.bin", 0xe000, 0x1000, CRC(d4cfab14) SHA1(b507b9026844eeb757547679907394aa42055eee))
|
||||
ROM_REGION(0x0800, "gfx1",0)
|
||||
ROM_LOAD ("galchr.bin", 0x0000, 0x0800, CRC(5c3b5bb5) SHA1(19429a61dc5e55ddec3242a8f695e06dd7961f88))
|
||||
ROM_END
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */
|
||||
COMP( 1983, galaxy, 0, 0, galaxy, galaxy, galaxy_state, init_galaxy, "Voja Antonic / Elektronika inzenjering", "Galaksija", 0)
|
||||
COMP( 1985, galaxyp, galaxy, 0, galaxyp, galaxyp, galaxy_state, init_galaxyp, "Nenad Dunjic", "Galaksija plus", 0)
|
||||
@@ -1,69 +0,0 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Krzysztof Strzecha, Miodrag Milanovic
|
||||
/*****************************************************************************
|
||||
*
|
||||
* includes/galaxy.h
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef MAME_INCLUDES_GALAXY_H
|
||||
#define MAME_INCLUDES_GALAXY_H
|
||||
|
||||
#include "imagedev/snapquik.h"
|
||||
#include "imagedev/cassette.h"
|
||||
#include "machine/ram.h"
|
||||
#include "screen.h"
|
||||
|
||||
class galaxy_state : public driver_device
|
||||
{
|
||||
public:
|
||||
galaxy_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_screen(*this, "screen")
|
||||
, m_cassette(*this, "cassette")
|
||||
, m_ram(*this, RAM_TAG)
|
||||
, m_region_gfx1(*this, "gfx1") {}
|
||||
|
||||
void galaxy(machine_config &config);
|
||||
void galaxyp(machine_config &config);
|
||||
|
||||
void init_galaxy();
|
||||
void init_galaxyp();
|
||||
|
||||
private:
|
||||
DECLARE_READ8_MEMBER(galaxy_keyboard_r);
|
||||
DECLARE_WRITE8_MEMBER(galaxy_latch_w);
|
||||
virtual void video_start() override;
|
||||
DECLARE_MACHINE_RESET(galaxy);
|
||||
DECLARE_MACHINE_RESET(galaxyp);
|
||||
uint32_t screen_update_galaxy(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
INTERRUPT_GEN_MEMBER(galaxy_interrupt);
|
||||
TIMER_CALLBACK_MEMBER(gal_video);
|
||||
IRQ_CALLBACK_MEMBER(galaxy_irq_callback);
|
||||
void galaxy_set_timer();
|
||||
void galaxy_setup_snapshot (const uint8_t * data, uint32_t size);
|
||||
DECLARE_SNAPSHOT_LOAD_MEMBER( galaxy );
|
||||
void galaxy_mem(address_map &map);
|
||||
void galaxyp_io(address_map &map);
|
||||
void galaxyp_mem(address_map &map);
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<screen_device> m_screen;
|
||||
required_device<cassette_image_device> m_cassette;
|
||||
required_device<ram_device> m_ram;
|
||||
required_memory_region m_region_gfx1;
|
||||
ioport_port *m_io_ports[8];
|
||||
|
||||
int m_interrupts_enabled;
|
||||
uint8_t m_latch_value;
|
||||
uint32_t m_gal_cnt;
|
||||
uint8_t m_code;
|
||||
uint8_t m_first;
|
||||
uint32_t m_start_addr;
|
||||
emu_timer *m_gal_video_timer;
|
||||
bitmap_ind16 m_bitmap;
|
||||
};
|
||||
|
||||
|
||||
#endif // MAME_INCLUDES_GALAXY_H
|
||||
@@ -1,136 +0,0 @@
|
||||
module Galaksija_MiST(
|
||||
input CLOCK_27,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output LED,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0/*,
|
||||
output [12:0] SDRAM_A,
|
||||
inout [15:0] SDRAM_DQ,
|
||||
output SDRAM_DQML,
|
||||
output SDRAM_DQMH,
|
||||
output SDRAM_nWE,
|
||||
output SDRAM_nCAS,
|
||||
output SDRAM_nRAS,
|
||||
output SDRAM_nCS,
|
||||
output [1:0] SDRAM_BA,
|
||||
output SDRAM_CLK,
|
||||
output SDRAM_CKE*/
|
||||
);
|
||||
|
||||
`include "build_id.v"
|
||||
localparam CONF_STR = {
|
||||
"Galaksija;;",
|
||||
// "F,GAL,Load Program;",
|
||||
"O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
|
||||
"T9,Reset;",
|
||||
"V,v1.00.",`BUILD_DATE
|
||||
};
|
||||
wire clk_1p7, clk_25, clk_6p25;
|
||||
wire ps2_kbd_clk, ps2_kbd_data;
|
||||
wire [2:0] r, g;
|
||||
wire [1:0] b;
|
||||
wire hs, vs;
|
||||
wire [1:0] buttons, switches;
|
||||
wire ypbpr;
|
||||
wire forced_scandoubler;
|
||||
wire [31:0] status;
|
||||
wire [7:0] audio;
|
||||
|
||||
|
||||
pll pll (
|
||||
.inclk0 ( CLOCK_27 ),
|
||||
.c0 ( clk_1p7 ),
|
||||
.c1 ( clk_25 ),
|
||||
.c2 ( clk_6p25 )
|
||||
);
|
||||
|
||||
|
||||
mist_io #(
|
||||
.STRLEN($size(CONF_STR)>>3))
|
||||
user_io (
|
||||
.clk_sys(clk_25),
|
||||
.CONF_DATA0(CONF_DATA0),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_DI(SPI_DI),
|
||||
.SPI_DO(SPI_DO),
|
||||
.SPI_SS2(SPI_SS2),
|
||||
.conf_str(CONF_STR),
|
||||
.ypbpr(ypbpr),
|
||||
.status(status),
|
||||
.scandoubler_disable(forced_scandoubler),
|
||||
.buttons(buttons),
|
||||
.switches(switches),
|
||||
.ps2_kbd_clk(ps2_kbd_clk),
|
||||
.ps2_kbd_data(ps2_kbd_data)/*,
|
||||
.joystick_0(joystick_0),
|
||||
.joystick_1(joystick_1),
|
||||
.ioctl_wr(ioctl_wr),
|
||||
.ioctl_index(ioctl_index),
|
||||
.ioctl_download(ioctl_download),
|
||||
.ioctl_addr(ioctl_addr),
|
||||
.ioctl_dout(ioctl_dout)*/
|
||||
);
|
||||
|
||||
video_mixer #(
|
||||
.LINE_LENGTH(320),
|
||||
.HALF_DEPTH(0))
|
||||
video_mixer (
|
||||
.clk_sys ( clk_25 ),
|
||||
.ce_pix ( clk_6p25 ),
|
||||
.ce_pix_actual ( clk_6p25 ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.R ( {r,r}),
|
||||
.G ( {g,g}),
|
||||
.B ( {2'b0,b,b}),
|
||||
.HSync ( hs ),
|
||||
.VSync ( vs ),
|
||||
.VGA_R ( VGA_R ),
|
||||
.VGA_G ( VGA_G ),
|
||||
.VGA_B ( VGA_B ),
|
||||
.VGA_VS ( VGA_VS ),
|
||||
.VGA_HS ( VGA_HS ),
|
||||
.scanlines (forced_scandoubler ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}),
|
||||
.scandoubler_disable(1'b1),//forced_scandoubler),
|
||||
.hq2x (status[3:2]==1),
|
||||
.ypbpr ( ypbpr ),
|
||||
.ypbpr_full ( 1 ),
|
||||
.line_start ( 0 ),
|
||||
.mono ( 0 )
|
||||
);
|
||||
|
||||
galaksija_top galaksija_top (
|
||||
.clk(clk_25),
|
||||
.a_en(clk_1p7),
|
||||
.pixclk(clk_25),
|
||||
.reset_n(~(status[0] | status[9] | buttons[1])),
|
||||
.PS2_DATA(ps2_kbd_data),
|
||||
.PS2_CLK(ps2_kbd_clk),
|
||||
.audio(audio),
|
||||
.LCD_DAT({b,g,r}),//todo
|
||||
.LCD_HS(hs),
|
||||
.LCD_VS(vs)
|
||||
);
|
||||
|
||||
dac #(
|
||||
.msbi_g(7))
|
||||
dac (
|
||||
.clk_i(clk_25),
|
||||
.res_n_i(1'b1),
|
||||
.dac_i(audio),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
endmodule
|
||||
@@ -1,308 +0,0 @@
|
||||
// ports are not identical to the actual AY chip - no need for that.
|
||||
// Also the parallel ports are not very useful, so they are not connected
|
||||
|
||||
|
||||
|
||||
|
||||
module ay8910(rst_n,clk,clk_en,asel,wr_n,cs_n,din,dout,A,B,C,audio);
|
||||
input rst_n;
|
||||
input clk; // 28 MHz clock from the system
|
||||
input clk_en; // 1.7 (?) clock to run the sound timing
|
||||
input asel;
|
||||
input wr_n;
|
||||
input cs_n;
|
||||
input [7:0] din;
|
||||
output [7:0] dout;
|
||||
output [7:0] A;
|
||||
output [7:0] B;
|
||||
output [7:0] C;
|
||||
output [7:0] audio;
|
||||
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write Register
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
reg [3:0] addr;
|
||||
|
||||
|
||||
// registers
|
||||
reg [11:0] period_a,period_b,period_c;
|
||||
reg [4:0] period_n;
|
||||
reg [7:0] reg_en;
|
||||
reg [4:0] vol_a,vol_b,vol_c;
|
||||
reg [15:0] period_e;
|
||||
reg [3:0] shape_e;
|
||||
reg [7:0] pa_r,pb_r;
|
||||
|
||||
|
||||
wire pb_od = reg_en[7];
|
||||
wire pa_od = reg_en[6];
|
||||
wire na = reg_en[5];
|
||||
wire nb = reg_en[4];
|
||||
wire nc = reg_en[3];
|
||||
wire ena = reg_en[2];
|
||||
wire enb = reg_en[1];
|
||||
wire enc = reg_en[0];
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
if(~rst_n) begin
|
||||
vol_a <= 0;
|
||||
vol_b <= 0;
|
||||
vol_c <= 0;
|
||||
end else
|
||||
|
||||
|
||||
if(~wr_n && ~cs_n) begin
|
||||
if(asel)
|
||||
begin
|
||||
// address write
|
||||
addr <= din[3:0];
|
||||
end else begin
|
||||
// register write
|
||||
case(addr)
|
||||
0:period_a[ 7:0] <= din;
|
||||
1:period_a[11:8] <= din[3:0];
|
||||
2:period_b[ 7:0] <= din;
|
||||
3:period_b[11:8] <= din[3:0];
|
||||
4:period_c[ 7:0] <= din;
|
||||
5:period_c[11:8] <= din[3:0];
|
||||
6:period_n[ 4:0] <= din[4:0];
|
||||
7:reg_en <= din;
|
||||
8:vol_a <= din[4:0];
|
||||
9:vol_b <= din[4:0];
|
||||
10:vol_c <= din[4:0];
|
||||
11:period_e[7:0] <= din;
|
||||
12:period_e[15:8] <= din;
|
||||
13:shape_e <= din[3:0];
|
||||
14:pa_r <= din;
|
||||
15:pb_r <= din;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Read Register
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
assign dout = addr==4'h0 ? period_a[7:0] :
|
||||
addr==4'h1 ? {4'h0,period_a[11:0]} :
|
||||
addr==4'h2 ? period_b[7:0] :
|
||||
addr==4'h3 ? {4'h0,period_b[11:0]} :
|
||||
addr==4'h4 ? period_c[7:0] :
|
||||
addr==4'h5 ? {4'h0,period_c[11:0]} :
|
||||
addr==4'h6 ? {3'h0,period_n} :
|
||||
addr==4'h7 ? reg_en :
|
||||
addr==4'h8 ? {3'h0,vol_a} :
|
||||
addr==4'h9 ? {3'h0,vol_b} :
|
||||
addr==4'ha ? {3'h0,vol_c} :
|
||||
addr==4'hb ? period_e[7:0] :
|
||||
addr==4'hc ? period_e[15:8] :
|
||||
addr==4'hd ? {4'h0,shape_e} : 8'hff;
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// PSG
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
//
|
||||
// toneA 12bit | 12bit
|
||||
// toneB 12bit | 12bit
|
||||
// toneC 12bit | 12bit
|
||||
// env 15bit | 15bit
|
||||
//
|
||||
reg [2:0] pris;
|
||||
reg [11:0] cnt_a,cnt_b,cnt_c;
|
||||
|
||||
|
||||
reg out_a,out_b,out_c;
|
||||
|
||||
|
||||
always @(posedge clk)
|
||||
if(clk_en) begin
|
||||
pris <= pris + 1;
|
||||
if(pris==0)
|
||||
begin
|
||||
// tone generator
|
||||
cnt_a <= cnt_a + 1;
|
||||
if(cnt_a==period_a)
|
||||
begin
|
||||
out_a <= ~out_a;
|
||||
cnt_a <= 0;
|
||||
end
|
||||
cnt_b <= cnt_b + 1;
|
||||
if(cnt_b==period_b)
|
||||
begin
|
||||
out_b <= ~out_b;
|
||||
cnt_b <= 0;
|
||||
end
|
||||
cnt_c <= cnt_c + 1;
|
||||
if(cnt_c==period_c)
|
||||
begin
|
||||
out_c <= ~out_c;
|
||||
cnt_c <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// envelope generator
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
reg [15:0] env_cnt;
|
||||
reg [3:0] env_phase;
|
||||
reg env_start;
|
||||
reg env_en;
|
||||
reg env_inv;
|
||||
|
||||
|
||||
// write eshape
|
||||
wire env_clr = (addr==13) & ~cs_n & ~wr_n;
|
||||
|
||||
|
||||
// bit3 = turn reset , 0=on , 1=off
|
||||
// bit2 = start , 0=up , 1=down(inv)
|
||||
// bit1 = turn invert, 0=tggle , 1=fix
|
||||
// bit0 = turn repeat, 0=off, 1=on
|
||||
|
||||
|
||||
wire next_no_reset = shape_e[3];
|
||||
wire start_no_inv = shape_e[2];
|
||||
wire next_toggle = shape_e[1];
|
||||
wire next_repeat = shape_e[0];
|
||||
|
||||
|
||||
// envelope volume output
|
||||
wire [3:0] vol_e = env_phase ^ {4{env_inv}};
|
||||
|
||||
|
||||
//
|
||||
always @(posedge clk or posedge env_clr)
|
||||
begin
|
||||
if(env_clr) env_start <= 1'b1;
|
||||
else if(clk_en) env_start <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if(~rst_n)
|
||||
begin
|
||||
env_en <= 1'b0;
|
||||
end else
|
||||
if(clk_en)begin
|
||||
|
||||
|
||||
// start trigger
|
||||
if(env_start)
|
||||
begin
|
||||
env_cnt <= 0;
|
||||
env_phase <= 0;
|
||||
env_inv <= ~start_no_inv;
|
||||
env_en <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
// count
|
||||
if(pris==0 && env_en)
|
||||
begin
|
||||
// phase up
|
||||
env_cnt <= env_cnt + 1;
|
||||
if(env_cnt==period_e)
|
||||
begin
|
||||
env_cnt <= 0;
|
||||
env_phase <= env_phase+1;
|
||||
// turn over
|
||||
if(env_phase==15)
|
||||
begin
|
||||
if(~next_no_reset)
|
||||
begin
|
||||
env_inv <= (env_inv ^ next_toggle) & next_no_reset;
|
||||
env_en <= next_repeat & next_no_reset;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// noise generator
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
reg [16:0] shift_n;
|
||||
reg [4:0] cnt_n;
|
||||
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if(~rst_n)
|
||||
begin
|
||||
shift_n <= 17'b00000000000000001;
|
||||
end else if((pris==0) &&(clk_en))
|
||||
begin
|
||||
cnt_n <= cnt_n +1;
|
||||
if(cnt_n == period_n)
|
||||
begin
|
||||
cnt_n <= 0;
|
||||
shift_n <= {shift_n[0]^shift_n[3],shift_n[16:1]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
wire out_n = shift_n[0];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// volume table 3db / step
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
function [7:0] vol_tbl;
|
||||
input [4:0] vol;
|
||||
input [3:0] vole;
|
||||
input out;
|
||||
begin
|
||||
if(~out)
|
||||
vol_tbl = 0;
|
||||
else case(vol[4]?vole:vol[3:0])
|
||||
15:vol_tbl = 255;
|
||||
14:vol_tbl = 180;
|
||||
13:vol_tbl = 127;
|
||||
12:vol_tbl = 90;
|
||||
11:vol_tbl = 64;
|
||||
10:vol_tbl = 45;
|
||||
9:vol_tbl = 32;
|
||||
8:vol_tbl = 22;
|
||||
7:vol_tbl = 16;
|
||||
6:vol_tbl = 11;
|
||||
5:vol_tbl = 8;
|
||||
4:vol_tbl = 5;
|
||||
3:vol_tbl = 4;
|
||||
2:vol_tbl = 3;
|
||||
1:vol_tbl = 2;
|
||||
0:vol_tbl = 0; //1;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// output
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
assign A = vol_tbl(vol_a,vol_e,(out_a | ena) & (out_n | na) );
|
||||
assign B = vol_tbl(vol_b,vol_e,(out_b | enb) & (out_n | nb) );
|
||||
assign C = vol_tbl(vol_c,vol_e,(out_c | enc) & (out_n | nc) );
|
||||
assign audio = {"00",A} + {"00",B} + {"00",C};//todo gehstock
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -1,35 +0,0 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "sys/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
@@ -1,2 +0,0 @@
|
||||
`define BUILD_DATE "180816"
|
||||
`define BUILD_TIME "200421"
|
||||
@@ -1,71 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Delta-Sigma DAC
|
||||
--
|
||||
-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
|
||||
--
|
||||
-- Refer to Xilinx Application Note XAPP154.
|
||||
--
|
||||
-- This DAC requires an external RC low-pass filter:
|
||||
--
|
||||
-- dac_o 0---XXXXX---+---0 analog audio
|
||||
-- 3k3 |
|
||||
-- === 4n7
|
||||
-- |
|
||||
-- GND
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity dac is
|
||||
|
||||
generic (
|
||||
msbi_g : integer := 7
|
||||
);
|
||||
port (
|
||||
clk_i : in std_logic;
|
||||
res_n_i : in std_logic;
|
||||
dac_i : in std_logic_vector(msbi_g downto 0);
|
||||
dac_o : out std_logic
|
||||
);
|
||||
|
||||
end dac;
|
||||
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
architecture rtl of dac is
|
||||
|
||||
signal DACout_q : std_logic;
|
||||
signal DeltaAdder_s,
|
||||
SigmaAdder_s,
|
||||
SigmaLatch_q,
|
||||
DeltaB_s : unsigned(msbi_g+2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
|
||||
SigmaLatch_q(msbi_g+2);
|
||||
DeltaB_s(msbi_g downto 0) <= (others => '0');
|
||||
|
||||
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
|
||||
|
||||
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
|
||||
|
||||
seq: process (clk_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
|
||||
DACout_q <= '0';
|
||||
|
||||
elsif clk_i'event and clk_i = '1' then
|
||||
SigmaLatch_q <= SigmaAdder_s;
|
||||
DACout_q <= SigmaLatch_q(msbi_g+2);
|
||||
end if;
|
||||
end process seq;
|
||||
|
||||
dac_o <= DACout_q;
|
||||
|
||||
end rtl;
|
||||
@@ -1,131 +0,0 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY dpram IS
|
||||
GENERIC
|
||||
(
|
||||
init_file : string := "";
|
||||
--numwords_a : natural;
|
||||
widthad_a : natural;
|
||||
width_a : natural := 8;
|
||||
outdata_reg_a : string := "UNREGISTERED";
|
||||
outdata_reg_b : string := "UNREGISTERED"
|
||||
);
|
||||
PORT
|
||||
(
|
||||
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
clock_a : IN STD_LOGIC ;
|
||||
clock_b : IN STD_LOGIC ;
|
||||
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
wren_a : IN STD_LOGIC := '1';
|
||||
wren_b : IN STD_LOGIC := '1';
|
||||
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END dpram;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF dpram IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
address_reg_b : STRING;
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_input_b : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
clock_enable_output_b : STRING;
|
||||
indata_reg_b : STRING;
|
||||
init_file : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
numwords_b : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_aclr_b : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
outdata_reg_b : STRING;
|
||||
power_up_uninitialized : STRING;
|
||||
read_during_write_mode_port_a : STRING;
|
||||
read_during_write_mode_port_b : STRING;
|
||||
widthad_a : NATURAL;
|
||||
widthad_b : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_b : NATURAL;
|
||||
width_byteena_a : NATURAL;
|
||||
width_byteena_b : NATURAL;
|
||||
wrcontrol_wraddress_reg_b : STRING
|
||||
);
|
||||
PORT (
|
||||
wren_a : IN STD_LOGIC ;
|
||||
clock0 : IN STD_LOGIC ;
|
||||
wren_b : IN STD_LOGIC ;
|
||||
clock1 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q_a <= sub_wire0(width_a-1 DOWNTO 0);
|
||||
q_b <= sub_wire1(width_a-1 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_reg_b => "CLOCK1",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
indata_reg_b => "CLOCK1",
|
||||
init_file => init_file,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 2**widthad_a,
|
||||
numwords_b => 2**widthad_a,
|
||||
operation_mode => "BIDIR_DUAL_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_a => outdata_reg_a,
|
||||
outdata_reg_b => outdata_reg_a,
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
|
||||
widthad_a => widthad_a,
|
||||
widthad_b => widthad_a,
|
||||
width_a => width_a,
|
||||
width_b => width_a,
|
||||
width_byteena_a => 1,
|
||||
width_byteena_b => 1,
|
||||
wrcontrol_wraddress_reg_b => "CLOCK1"
|
||||
)
|
||||
PORT MAP (
|
||||
wren_a => wren_a,
|
||||
clock0 => clock_a,
|
||||
wren_b => wren_b,
|
||||
clock1 => clock_b,
|
||||
address_a => address_a,
|
||||
address_b => address_b,
|
||||
data_a => data_a,
|
||||
data_b => data_b,
|
||||
q_a => sub_wire0,
|
||||
q_b => sub_wire1
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
@@ -1,16 +0,0 @@
|
||||
module font_rom(
|
||||
input clk,
|
||||
input [10:0] addr,
|
||||
output reg [7:0] data_out
|
||||
);
|
||||
|
||||
reg [7:0] store[0:2047] /* verilator public_flat */;
|
||||
|
||||
initial
|
||||
begin
|
||||
$readmemh("galchr.mem", store);
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
data_out <= store[addr];
|
||||
endmodule
|
||||
@@ -1,454 +0,0 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2012-2013 Ludvig Strigeus
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
|
||||
`define BITS_TO_FIT(N) ( \
|
||||
N <= 2 ? 0 : \
|
||||
N <= 4 ? 1 : \
|
||||
N <= 8 ? 2 : \
|
||||
N <= 16 ? 3 : \
|
||||
N <= 32 ? 4 : \
|
||||
N <= 64 ? 5 : \
|
||||
N <= 128 ? 6 : \
|
||||
N <= 256 ? 7 : \
|
||||
N <= 512 ? 8 : \
|
||||
N <=1024 ? 9 : 10 )
|
||||
|
||||
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
wire [DWIDTH:0] out[2];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input [1:0] rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input [1:0] wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
|
||||
wire [DWIDTH:0] out[4];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
|
||||
(
|
||||
input clock,
|
||||
input [DWIDTH:0] data,
|
||||
input [AWIDTH:0] rdaddress,
|
||||
input [AWIDTH:0] wraddress,
|
||||
input wren,
|
||||
output [DWIDTH:0] q
|
||||
);
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (wraddress),
|
||||
.clock0 (clock),
|
||||
.data_a (data),
|
||||
.wren_a (wren),
|
||||
.address_b (rdaddress),
|
||||
.q_b(q),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_b ({(DWIDTH+1){1'b1}}),
|
||||
.eccstatus (),
|
||||
.q_a (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_b = "NONE",
|
||||
altsyncram_component.address_reg_b = "CLOCK0",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = NUMWORDS,
|
||||
altsyncram_component.numwords_b = NUMWORDS,
|
||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
||||
altsyncram_component.widthad_a = AWIDTH+1,
|
||||
altsyncram_component.widthad_b = AWIDTH+1,
|
||||
altsyncram_component.width_a = DWIDTH+1,
|
||||
altsyncram_component.width_b = DWIDTH+1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
endmodule
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module DiffCheck
|
||||
(
|
||||
input [17:0] rgb1,
|
||||
input [17:0] rgb2,
|
||||
output result
|
||||
);
|
||||
|
||||
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
|
||||
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
|
||||
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
|
||||
wire [6:0] t = $signed(r) + $signed(b);
|
||||
wire [6:0] gx = {g[5], g};
|
||||
wire [7:0] y = $signed(t) + $signed(gx);
|
||||
wire [6:0] u = $signed(r) - $signed(b);
|
||||
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
|
||||
|
||||
// if y is inside (-24..24)
|
||||
wire y_inside = (y < 8'h18 || y >= 8'he8);
|
||||
|
||||
// if u is inside (-4, 4)
|
||||
wire u_inside = (u < 7'h4 || u >= 7'h7c);
|
||||
|
||||
// if v is inside (-6, 6)
|
||||
wire v_inside = (v < 8'h6 || v >= 8'hfA);
|
||||
assign result = !(y_inside && u_inside && v_inside);
|
||||
endmodule
|
||||
|
||||
module InnerBlend
|
||||
(
|
||||
input [8:0] Op,
|
||||
input [5:0] A,
|
||||
input [5:0] B,
|
||||
input [5:0] C,
|
||||
output [5:0] O
|
||||
);
|
||||
|
||||
function [8:0] mul6x3;
|
||||
input [5:0] op1;
|
||||
input [2:0] op2;
|
||||
begin
|
||||
mul6x3 = 9'd0;
|
||||
if(op2[0]) mul6x3 = mul6x3 + op1;
|
||||
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
|
||||
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire OpOnes = Op[4];
|
||||
wire [8:0] Amul = mul6x3(A, Op[7:5]);
|
||||
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
|
||||
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
|
||||
wire [8:0] At = Amul;
|
||||
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
|
||||
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
|
||||
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
|
||||
assign O = Op[8] ? A : Res[9:4];
|
||||
endmodule
|
||||
|
||||
module Blend
|
||||
(
|
||||
input [5:0] rule,
|
||||
input disable_hq2x,
|
||||
input [17:0] E,
|
||||
input [17:0] A,
|
||||
input [17:0] B,
|
||||
input [17:0] D,
|
||||
input [17:0] F,
|
||||
input [17:0] H,
|
||||
output [17:0] Result
|
||||
);
|
||||
|
||||
reg [1:0] input_ctrl;
|
||||
reg [8:0] op;
|
||||
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
|
||||
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
|
||||
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
|
||||
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
|
||||
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
|
||||
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
|
||||
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
|
||||
localparam AB = 2'b00;
|
||||
localparam AD = 2'b01;
|
||||
localparam DB = 2'b10;
|
||||
localparam BD = 2'b11;
|
||||
wire is_diff;
|
||||
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
|
||||
|
||||
always @* begin
|
||||
case({!is_diff, rule[5:2]})
|
||||
1,17: {op, input_ctrl} = {BLEND1, AB};
|
||||
2,18: {op, input_ctrl} = {BLEND1, DB};
|
||||
3,19: {op, input_ctrl} = {BLEND1, BD};
|
||||
4,20: {op, input_ctrl} = {BLEND2, DB};
|
||||
5,21: {op, input_ctrl} = {BLEND2, AB};
|
||||
6,22: {op, input_ctrl} = {BLEND2, AD};
|
||||
|
||||
8: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
9: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
10: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
11: {op, input_ctrl} = {BLEND1, AB};
|
||||
12: {op, input_ctrl} = {BLEND1, AB};
|
||||
13: {op, input_ctrl} = {BLEND1, AB};
|
||||
14: {op, input_ctrl} = {BLEND1, DB};
|
||||
15: {op, input_ctrl} = {BLEND1, BD};
|
||||
|
||||
24: {op, input_ctrl} = {BLEND2, DB};
|
||||
25: {op, input_ctrl} = {BLEND5, DB};
|
||||
26: {op, input_ctrl} = {BLEND6, DB};
|
||||
27: {op, input_ctrl} = {BLEND2, DB};
|
||||
28: {op, input_ctrl} = {BLEND4, DB};
|
||||
29: {op, input_ctrl} = {BLEND5, DB};
|
||||
30: {op, input_ctrl} = {BLEND3, BD};
|
||||
31: {op, input_ctrl} = {BLEND3, DB};
|
||||
default: {op, input_ctrl} = 11'bx;
|
||||
endcase
|
||||
|
||||
// Setting op[8] effectively disables HQ2X because blend will always return E.
|
||||
if (disable_hq2x) op[8] = 1;
|
||||
end
|
||||
|
||||
// Generate inputs to the inner blender. Valid combinations.
|
||||
// 00: E A B
|
||||
// 01: E A D
|
||||
// 10: E D B
|
||||
// 11: E B D
|
||||
wire [17:0] Input1 = E;
|
||||
wire [17:0] Input2 = !input_ctrl[1] ? A :
|
||||
!input_ctrl[0] ? D : B;
|
||||
|
||||
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
|
||||
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
|
||||
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
|
||||
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
|
||||
endmodule
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
input clk,
|
||||
input ce_x4,
|
||||
input [DWIDTH:0] inputpixel,
|
||||
input mono,
|
||||
input disable_hq2x,
|
||||
input reset_frame,
|
||||
input reset_line,
|
||||
input [1:0] read_y,
|
||||
input [AWIDTH+1:0] read_x,
|
||||
output [DWIDTH:0] outpixel
|
||||
);
|
||||
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
|
||||
|
||||
wire [5:0] hqTable[256] = '{
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
|
||||
};
|
||||
|
||||
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
|
||||
reg [17:0] A, B, D, F, G, H;
|
||||
reg [7:0] pattern, nextpatt;
|
||||
reg [1:0] i;
|
||||
reg [7:0] y;
|
||||
|
||||
wire curbuf = y[0];
|
||||
reg prevbuf = 0;
|
||||
wire iobuf = !curbuf;
|
||||
|
||||
wire diff0, diff1;
|
||||
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
|
||||
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
|
||||
|
||||
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
|
||||
|
||||
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
|
||||
wire [17:0] blend_result;
|
||||
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
|
||||
|
||||
reg Curr2_addr1;
|
||||
reg [AWIDTH:0] Curr2_addr2;
|
||||
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
|
||||
wire [DWIDTH:0] Curr2tmp;
|
||||
|
||||
reg [AWIDTH:0] wrin_addr2;
|
||||
reg [DWIDTH:0] wrpix;
|
||||
reg wrin_en;
|
||||
|
||||
function [17:0] h2rgb;
|
||||
input [8:0] v;
|
||||
begin
|
||||
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [8:0] rgb2h;
|
||||
input [17:0] v;
|
||||
begin
|
||||
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(Curr2_addr2),
|
||||
.rdbuf(Curr2_addr1),
|
||||
.q(Curr2tmp),
|
||||
|
||||
.wraddr(wrin_addr2),
|
||||
.wrbuf(iobuf),
|
||||
.data(wrpix),
|
||||
.wren(wrin_en)
|
||||
);
|
||||
|
||||
reg [1:0] wrout_addr1;
|
||||
reg [AWIDTH+1:0] wrout_addr2;
|
||||
reg wrout_en;
|
||||
reg [DWIDTH:0] wrdata;
|
||||
|
||||
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(read_x),
|
||||
.rdbuf(read_y),
|
||||
.q(outpixel),
|
||||
|
||||
.wraddr(wrout_addr2),
|
||||
.wrbuf(wrout_addr1),
|
||||
.data(wrdata),
|
||||
.wren(wrout_en)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [AWIDTH:0] offs;
|
||||
reg old_reset_line;
|
||||
reg old_reset_frame;
|
||||
|
||||
wrout_en <= 0;
|
||||
wrin_en <= 0;
|
||||
|
||||
if(ce_x4) begin
|
||||
|
||||
pattern <= new_pattern;
|
||||
|
||||
if(~&offs) begin
|
||||
if (i == 0) begin
|
||||
Curr2_addr1 <= prevbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 1) begin
|
||||
Prev2 <= Curr2;
|
||||
Curr2_addr1 <= curbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 2) begin
|
||||
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
|
||||
wrpix <= inputpixel;
|
||||
wrin_addr2 <= offs;
|
||||
wrin_en <= 1;
|
||||
end
|
||||
if (i == 3) begin
|
||||
offs <= offs + 1'd1;
|
||||
end
|
||||
|
||||
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
|
||||
else wrdata <= blend_result;
|
||||
|
||||
wrout_addr1 <= {curbuf, i[1]};
|
||||
wrout_addr2 <= {offs, i[1]^i[0]};
|
||||
wrout_en <= 1;
|
||||
end
|
||||
|
||||
if(i==3) begin
|
||||
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
|
||||
{A, G} <= {Prev0, Next0};
|
||||
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
|
||||
{Prev0, Prev1} <= {Prev1, Prev2};
|
||||
{Curr0, Curr1} <= {Curr1, Curr2};
|
||||
{Next0, Next1} <= {Next1, Next2};
|
||||
end else begin
|
||||
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
|
||||
{B, F, H, D} <= {F, H, D, B};
|
||||
end
|
||||
|
||||
i <= i + 1'b1;
|
||||
if(old_reset_line && ~reset_line) begin
|
||||
old_reset_frame <= reset_frame;
|
||||
offs <= 0;
|
||||
i <= 0;
|
||||
y <= y + 1'd1;
|
||||
prevbuf <= curbuf;
|
||||
if(old_reset_frame & ~reset_frame) begin
|
||||
y <= 0;
|
||||
prevbuf <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
old_reset_line <= reset_line;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // Hq2x
|
||||
@@ -1,496 +0,0 @@
|
||||
//
|
||||
// mist_io.v
|
||||
//
|
||||
// mist_io for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2015-2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
|
||||
// (Sorgelig)
|
||||
//
|
||||
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
|
||||
// clk_ps2 = clk_sys/(PS2DIV*2)
|
||||
//
|
||||
|
||||
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
(
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
|
||||
// Global clock. It should be around 100MHz (higher is better).
|
||||
input clk_sys,
|
||||
|
||||
// Global SPI clock from ARM. 24MHz
|
||||
input SPI_SCK,
|
||||
|
||||
input CONF_DATA0,
|
||||
input SPI_SS2,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
output scandoubler_disable,
|
||||
output ypbpr,
|
||||
|
||||
output reg [31:0] status,
|
||||
|
||||
// SD config
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output [1:0] img_mounted, // signaling that new image has been mounted
|
||||
output reg [31:0] img_size, // size of image in bytes
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba,
|
||||
input [1:0] sd_rd,
|
||||
input [1:0] sd_wr,
|
||||
output reg sd_ack,
|
||||
output reg sd_ack_conf,
|
||||
|
||||
// SD byte level access. Signals for 2-PORT altsyncram.
|
||||
output reg [8:0] sd_buff_addr,
|
||||
output reg [7:0] sd_buff_dout,
|
||||
input [7:0] sd_buff_din,
|
||||
output reg sd_buff_wr,
|
||||
|
||||
// ps2 keyboard emulation
|
||||
output ps2_kbd_clk,
|
||||
output reg ps2_kbd_data,
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
|
||||
// ps2 alternative interface.
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0,
|
||||
|
||||
// ARM -> FPGA download
|
||||
input ioctl_ce,
|
||||
input ioctl_wait,
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg [7:0] ioctl_index, // menu index used to upload the file
|
||||
output reg ioctl_wr = 0,
|
||||
output reg [13:0] ioctl_addr,
|
||||
output reg [7:0] ioctl_dout
|
||||
);
|
||||
|
||||
reg [7:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
reg [1:0] mount_strobe = 0;
|
||||
assign img_mounted = mount_strobe;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign scandoubler_disable = but_sw[4];
|
||||
assign ypbpr = but_sw[5];
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire drive_sel = sd_rd[1] | sd_wr[1];
|
||||
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
|
||||
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
|
||||
reg spi_do;
|
||||
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
|
||||
|
||||
reg [7:0] spi_data_out;
|
||||
|
||||
// SPI transmitter
|
||||
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
|
||||
|
||||
reg [7:0] spi_data_in;
|
||||
reg spi_data_ready = 0;
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [31:0] sd_lba_r;
|
||||
reg drive_sel_r;
|
||||
|
||||
if(CONF_DATA0) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= 0;
|
||||
spi_data_out <= core_type;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt <= bit_cnt + 1'd1;
|
||||
sbuf <= {sbuf[5:0], SPI_DI};
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
spi_data_in <= {sbuf, SPI_DI};
|
||||
spi_data_ready <= ~spi_data_ready;
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
|
||||
|
||||
spi_data_out <= 0;
|
||||
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
|
||||
// reading config string
|
||||
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
|
||||
|
||||
// reading sd card status
|
||||
8'h16: if(byte_cnt == 0) begin
|
||||
spi_data_out <= sd_cmd;
|
||||
sd_lba_r <= sd_lba;
|
||||
drive_sel_r <= drive_sel;
|
||||
end else if (byte_cnt == 1) begin
|
||||
spi_data_out <= drive_sel_r;
|
||||
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
|
||||
|
||||
// reading sd card write data
|
||||
8'h18: spi_data_out <= sd_buff_din;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
// transfer to clk_sys domain
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_ss1, old_ss2;
|
||||
reg old_ready1, old_ready2;
|
||||
reg [2:0] b_wr;
|
||||
reg got_ps2 = 0;
|
||||
|
||||
old_ss1 <= CONF_DATA0;
|
||||
old_ss2 <= old_ss1;
|
||||
old_ready1 <= spi_data_ready;
|
||||
old_ready2 <= old_ready1;
|
||||
|
||||
sd_buff_wr <= b_wr[0];
|
||||
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
if(old_ss2) begin
|
||||
got_ps2 <= 0;
|
||||
sd_ack <= 0;
|
||||
sd_ack_conf <= 0;
|
||||
sd_buff_addr <= 0;
|
||||
if(got_ps2) begin
|
||||
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
if(old_ready2 ^ old_ready1) begin
|
||||
|
||||
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
|
||||
if(byte_cnt < 2) begin
|
||||
|
||||
if (cmd == 8'h19) sd_ack_conf <= 1;
|
||||
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
|
||||
mount_strobe <= 0;
|
||||
|
||||
if(cmd == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
// buttons and switches
|
||||
8'h01: but_sw <= spi_data_in;
|
||||
8'h02: joystick_0 <= spi_data_in;
|
||||
8'h03: joystick_1 <= spi_data_in;
|
||||
|
||||
// store incoming ps2 mouse bytes
|
||||
8'h04: begin
|
||||
got_ps2 <= 1;
|
||||
case(byte_cnt)
|
||||
2: ps2_mouse[7:0] <= spi_data_in;
|
||||
3: ps2_mouse[15:8] <= spi_data_in;
|
||||
4: ps2_mouse[23:16] <= spi_data_in;
|
||||
endcase
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
8'h05: begin
|
||||
got_ps2 <= 1;
|
||||
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
|
||||
end
|
||||
|
||||
8'h15: status[7:0] <= spi_data_in;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
8'h19,
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
8'h17: begin
|
||||
sd_buff_dout <= spi_data_in;
|
||||
b_wr <= 1;
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
8'h1a: begin
|
||||
// first byte is joystick index
|
||||
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
|
||||
else if(byte_cnt == 3) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
|
||||
end else if(byte_cnt == 4) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
|
||||
end
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
|
||||
|
||||
// send image info
|
||||
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
|
||||
// status, 32bit version
|
||||
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// PS2 ///////////////////////////////
|
||||
// 8 byte fifos to store ps2 bytes
|
||||
localparam PS2_FIFO_BITS = 3;
|
||||
|
||||
reg clk_ps2;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt == PS2DIV) begin
|
||||
clk_ps2 <= ~clk_ps2;
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// keyboard
|
||||
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_kbd_tx_state;
|
||||
reg [7:0] ps2_kbd_tx_byte;
|
||||
reg ps2_kbd_parity;
|
||||
|
||||
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_kbd_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_kbd_r_inc <= 0;
|
||||
|
||||
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_kbd_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
|
||||
ps2_kbd_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_kbd_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_kbd_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_kbd_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
|
||||
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
|
||||
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
|
||||
if(ps2_kbd_tx_byte[0])
|
||||
ps2_kbd_parity <= !ps2_kbd_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
|
||||
else ps2_kbd_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// mouse
|
||||
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_mouse_tx_state;
|
||||
reg [7:0] ps2_mouse_tx_byte;
|
||||
reg ps2_mouse_parity;
|
||||
|
||||
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_mouse_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_mouse_r_inc <= 0;
|
||||
|
||||
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_mouse_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
|
||||
ps2_mouse_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_mouse_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_mouse_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_mouse_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
|
||||
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
|
||||
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
|
||||
if(ps2_mouse_tx_byte[0])
|
||||
ps2_mouse_parity <= !ps2_mouse_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
|
||||
else ps2_mouse_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// DOWNLOADING ///////////////////////////////
|
||||
|
||||
localparam UIO_FILE_TX = 8'h53;
|
||||
localparam UIO_FILE_TX_DAT = 8'h54;
|
||||
localparam UIO_FILE_INDEX = 8'h55;
|
||||
|
||||
// data_io has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg [13:0] addr;
|
||||
|
||||
if(SPI_SS2) cnt <= 0;
|
||||
else begin
|
||||
// don't shift in last bit. It is evaluated directly
|
||||
// when writing to ram
|
||||
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
|
||||
|
||||
// count 0-7 8-15 8-15 ...
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
// finished command byte
|
||||
if(cnt == 7) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
// prepare/end transmission
|
||||
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
|
||||
// prepare
|
||||
if(SPI_DI) begin
|
||||
// addr <= ioctl_index ? 14'd9 : 14'd0; //.p files loaded at $4009, ROM is at 0
|
||||
addr <= 14'd0;
|
||||
ioctl_download <= 1;
|
||||
end else begin
|
||||
ioctl_addr <= addr;
|
||||
ioctl_download <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// command 0x54: UIO_FILE_TX
|
||||
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
|
||||
ioctl_addr <= addr;
|
||||
ioctl_dout <= {sbuf, SPI_DI};
|
||||
addr <= addr + 1'd1;
|
||||
ioctl_wr <= 1;
|
||||
end else
|
||||
ioctl_wr <= 0;
|
||||
|
||||
// expose file (menu) index
|
||||
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,179 +0,0 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd (
|
||||
// OSDs pixel clock, should be synchronous to cores pixel clock to
|
||||
// avoid jitter.
|
||||
input clk_sys,
|
||||
|
||||
// SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] R_in,
|
||||
input [5:0] G_in,
|
||||
input [5:0] B_in,
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] R_out,
|
||||
output [5:0] G_out,
|
||||
output [5:0] B_out
|
||||
);
|
||||
|
||||
parameter OSD_X_OFFSET = 10'd0;
|
||||
parameter OSD_Y_OFFSET = 10'd0;
|
||||
parameter OSD_COLOR = 3'd0;
|
||||
|
||||
localparam OSD_WIDTH = 10'd256;
|
||||
localparam OSD_HEIGHT = 10'd128;
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg osd_enable;
|
||||
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
|
||||
|
||||
// the OSD has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS3) begin
|
||||
reg [4:0] cnt;
|
||||
reg [10:0] bcnt;
|
||||
reg [7:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
|
||||
if(SPI_SS3) begin
|
||||
cnt <= 0;
|
||||
bcnt <= 0;
|
||||
end else begin
|
||||
sbuf <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// 0:7 is command, rest payload
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
|
||||
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
|
||||
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
|
||||
bcnt <= bcnt + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// *********************************************************************************
|
||||
// video timing and sync polarity anaylsis
|
||||
// *********************************************************************************
|
||||
|
||||
// horizontal counter
|
||||
reg [9:0] h_cnt;
|
||||
reg [9:0] hs_low, hs_high;
|
||||
wire hs_pol = hs_high < hs_low;
|
||||
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
|
||||
|
||||
// vertical counter
|
||||
reg [9:0] v_cnt;
|
||||
reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
|
||||
|
||||
wire doublescan = (dsp_height>350);
|
||||
|
||||
reg ce_pix;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt = 0;
|
||||
integer pixsz, pixcnt;
|
||||
reg hs;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
hs <= HSync;
|
||||
|
||||
pixcnt <= pixcnt + 1;
|
||||
if(pixcnt == pixsz) pixcnt <= 0;
|
||||
ce_pix <= !pixcnt;
|
||||
|
||||
if(hs && ~HSync) begin
|
||||
cnt <= 0;
|
||||
pixsz <= (cnt >> 9) - 1;
|
||||
pixcnt <= 0;
|
||||
ce_pix <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg hsD, hsD2;
|
||||
reg vsD, vsD2;
|
||||
|
||||
if(ce_pix) begin
|
||||
// bring hsync into local clock domain
|
||||
hsD <= HSync;
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of HSync
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of HSync
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_low <= h_cnt;
|
||||
v_cnt <= v_cnt + 1'd1;
|
||||
end else begin
|
||||
h_cnt <= h_cnt + 1'd1;
|
||||
end
|
||||
|
||||
vsD <= VSync;
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of VSync
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of VSync
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// area in which OSD is being displayed
|
||||
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
|
||||
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
|
||||
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
|
||||
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
|
||||
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
|
||||
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
|
||||
wire osd_de = osd_enable &&
|
||||
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
|
||||
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
|
||||
|
||||
reg [7:0] osd_byte;
|
||||
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
|
||||
|
||||
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
|
||||
|
||||
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
|
||||
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
|
||||
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
|
||||
|
||||
endmodule
|
||||
@@ -1,357 +0,0 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [2:2] sub_wire3 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire2 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire c0 = sub_wire2;
|
||||
wire c2 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire5),
|
||||
.clk (sub_wire0),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.locked (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 1000,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 63,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 25,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 108,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 25,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_UNUSED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1000"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "108"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.701000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.250000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "63"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.70000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.25000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1000"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "108"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -1,183 +0,0 @@
|
||||
//
|
||||
// scandoubler.v
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
// TODO: Delay vsync one line
|
||||
|
||||
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
// system interface
|
||||
input clk_sys,
|
||||
input ce_pix,
|
||||
input ce_pix_actual,
|
||||
|
||||
input hq2x,
|
||||
|
||||
// shifter video interface
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input line_start,
|
||||
|
||||
input [DWIDTH:0] r_in,
|
||||
input [DWIDTH:0] g_in,
|
||||
input [DWIDTH:0] b_in,
|
||||
input mono,
|
||||
|
||||
// output interface
|
||||
output reg hs_out,
|
||||
output vs_out,
|
||||
output [DWIDTH:0] r_out,
|
||||
output [DWIDTH:0] g_out,
|
||||
output [DWIDTH:0] b_out
|
||||
);
|
||||
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
assign vs_out = vs_in;
|
||||
|
||||
reg [2:0] phase;
|
||||
reg [2:0] ce_div;
|
||||
reg [7:0] pix_len = 0;
|
||||
wire [7:0] pl = pix_len + 1'b1;
|
||||
|
||||
reg ce_x1, ce_x4;
|
||||
reg req_line_reset;
|
||||
wire ls_in = hs_in | line_start;
|
||||
always @(negedge clk_sys) begin
|
||||
reg old_ce;
|
||||
reg [2:0] ce_cnt;
|
||||
|
||||
reg [7:0] pixsz2, pixsz4 = 0;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
if(~&pix_len) pix_len <= pix_len + 1'd1;
|
||||
|
||||
ce_x4 <= 0;
|
||||
ce_x1 <= 0;
|
||||
|
||||
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
|
||||
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
|
||||
phase <= phase + 1'd1;
|
||||
ce_x4 <= 1;
|
||||
end
|
||||
|
||||
if(~old_ce & ce_pix) begin
|
||||
pixsz2 <= {1'b0, pl[7:1]};
|
||||
pixsz4 <= {2'b00, pl[7:2]};
|
||||
ce_x1 <= 1;
|
||||
ce_x4 <= 1;
|
||||
pix_len <= 0;
|
||||
phase <= phase + 1'd1;
|
||||
|
||||
ce_cnt <= ce_cnt + 1'd1;
|
||||
if(ce_pix_actual) begin
|
||||
phase <= 0;
|
||||
ce_div <= ce_cnt + 1'd1;
|
||||
ce_cnt <= 0;
|
||||
req_line_reset <= 0;
|
||||
end
|
||||
|
||||
if(ls_in) req_line_reset <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg ce_sd;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: ce_sd = !phase[0];
|
||||
4: ce_sd = !phase[1:0];
|
||||
default: ce_sd <= 1;
|
||||
endcase
|
||||
end
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
|
||||
(
|
||||
.clk(clk_sys),
|
||||
.ce_x4(ce_x4 & ce_sd),
|
||||
.inputpixel({b_in,g_in,r_in}),
|
||||
.mono(mono),
|
||||
.disable_hq2x(~hq2x),
|
||||
.reset_frame(vs_in),
|
||||
.reset_line(req_line_reset),
|
||||
.read_y(sd_line),
|
||||
.read_x(sd_h_actual),
|
||||
.outpixel({b_out,g_out,r_out})
|
||||
);
|
||||
|
||||
reg [10:0] sd_h_actual;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: sd_h_actual = sd_h[10:1];
|
||||
4: sd_h_actual = sd_h[10:2];
|
||||
default: sd_h_actual = sd_h;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [10:0] sd_h;
|
||||
reg [1:0] sd_line;
|
||||
always @(posedge clk_sys) begin
|
||||
|
||||
reg [11:0] hs_max,hs_rise,hs_ls;
|
||||
reg [10:0] hcnt;
|
||||
reg [11:0] sd_hcnt;
|
||||
|
||||
reg hs, hs2, vs, ls;
|
||||
|
||||
if(ce_x1) begin
|
||||
hs <= hs_in;
|
||||
ls <= ls_in;
|
||||
|
||||
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
|
||||
|
||||
// falling edge of hsync indicates start of line
|
||||
if(hs && !hs_in) begin
|
||||
hs_max <= {hcnt,1'b1};
|
||||
hcnt <= 0;
|
||||
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
|
||||
end else begin
|
||||
hcnt <= hcnt + 1'd1;
|
||||
end
|
||||
|
||||
// save position of rising edge
|
||||
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
|
||||
|
||||
vs <= vs_in;
|
||||
if(vs && ~vs_in) sd_line <= 0;
|
||||
end
|
||||
|
||||
if(ce_x4) begin
|
||||
hs2 <= hs_in;
|
||||
|
||||
// output counter synchronous to input and at twice the rate
|
||||
sd_hcnt <= sd_hcnt + 1'd1;
|
||||
sd_h <= sd_h + 1'd1;
|
||||
if(hs2 && !hs_in) sd_hcnt <= hs_max;
|
||||
if(sd_hcnt == hs_max) sd_hcnt <= 0;
|
||||
|
||||
// replicate horizontal sync at twice the speed
|
||||
if(sd_hcnt == hs_max) hs_out <= 0;
|
||||
if(sd_hcnt == hs_rise) hs_out <= 1;
|
||||
|
||||
if(sd_hcnt == hs_ls) sd_h <= 0;
|
||||
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,90 +0,0 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY spram IS
|
||||
GENERIC
|
||||
(
|
||||
init_file : string := "";
|
||||
widthad_a : natural;
|
||||
width_a : natural := 8;
|
||||
outdata_reg_a : string := "UNREGISTERED"
|
||||
);
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
clock : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
wren : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END spram;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF spram IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
init_file : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
power_up_uninitialized : STRING;
|
||||
read_during_write_mode_port_a : STRING;
|
||||
widthad_a : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_byteena_a : NATURAL
|
||||
);
|
||||
PORT (
|
||||
wren_a : IN STD_LOGIC ;
|
||||
clock0 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(width_a-1 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
init_file => init_file,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 2**widthad_a,
|
||||
operation_mode => "SINGLE_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_reg_a => outdata_reg_a,
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
widthad_a => widthad_a,
|
||||
width_a => width_a,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
PORT MAP (
|
||||
wren_a => wren,
|
||||
clock0 => clock,
|
||||
address_a => address,
|
||||
data_a => data,
|
||||
q_a => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
@@ -1,82 +0,0 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY sprom IS
|
||||
GENERIC
|
||||
(
|
||||
init_file : string := "";
|
||||
widthad_a : natural;
|
||||
width_a : natural := 8;
|
||||
outdata_reg_a : string := "UNREGISTERED"
|
||||
);
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
clock : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END sprom;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF sprom IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
address_aclr_a : STRING;
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
init_file : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
widthad_a : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_byteena_a : NATURAL
|
||||
);
|
||||
PORT (
|
||||
clock0 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(width_a-1 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_aclr_a => "NONE",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
init_file => init_file,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 2**widthad_a,
|
||||
operation_mode => "ROM",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_reg_a => outdata_reg_a,
|
||||
widthad_a => widthad_a,
|
||||
width_a => width_a,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
PORT MAP (
|
||||
clock0 => clock,
|
||||
address_a => address,
|
||||
q_a => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
@@ -1,200 +0,0 @@
|
||||
------------------------------------------------------------------------
|
||||
-- vga_controller_640_60.vhd
|
||||
------------------------------------------------------------------------
|
||||
-- Author : Ulrich Zolt
|
||||
-- Copyright 2006 Digilent, Inc.
|
||||
------------------------------------------------------------------------
|
||||
-- Software version : Xilinx ISE 7.1.04i
|
||||
-- WebPack
|
||||
-- Device : 3s200ft256-4
|
||||
------------------------------------------------------------------------
|
||||
-- This file contains the logic to generate the synchronization signals,
|
||||
-- horizontal and vertical pixel counter and video disable signal
|
||||
-- for the 640x480@60Hz resolution.
|
||||
------------------------------------------------------------------------
|
||||
-- Behavioral description
|
||||
------------------------------------------------------------------------
|
||||
-- Please read the following article on the web regarding the
|
||||
-- vga video timings:
|
||||
-- http://www.epanorama.net/documents/pc/vga_timing.html
|
||||
|
||||
-- This module generates the video synch pulses for the monitor to
|
||||
-- enter 640x480@60Hz resolution state. It also provides horizontal
|
||||
-- and vertical counters for the currently displayed pixel and a blank
|
||||
-- signal that is active when the pixel is not inside the visible screen
|
||||
-- and the color outputs should be reset to 0.
|
||||
|
||||
-- timing diagram for the horizontal synch signal (HS)
|
||||
-- 0 648 744 800 (pixels)
|
||||
-- -------------------------|______|-----------------
|
||||
-- timing diagram for the vertical synch signal (VS)
|
||||
-- 0 482 484 525 (lines)
|
||||
-- -----------------------------------|______|-------
|
||||
|
||||
-- The blank signal is delayed one pixel clock period (40ns) from where
|
||||
-- the pixel leaves the visible screen, according to the counters, to
|
||||
-- account for the pixel pipeline delay. This delay happens because
|
||||
-- it takes time from when the counters indicate current pixel should
|
||||
-- be displayed to when the color data actually arrives at the monitor
|
||||
-- pins (memory read delays, synchronization delays).
|
||||
------------------------------------------------------------------------
|
||||
-- Port definitions
|
||||
------------------------------------------------------------------------
|
||||
-- rst - global reset signal
|
||||
-- pixel_clk - input pin, from dcm_25MHz
|
||||
-- - the clock signal generated by a DCM that has
|
||||
-- - a frequency of 25MHz.
|
||||
-- HS - output pin, to monitor
|
||||
-- - horizontal synch pulse
|
||||
-- VS - output pin, to monitor
|
||||
-- - vertical synch pulse
|
||||
-- hcount - output pin, 11 bits, to clients
|
||||
-- - horizontal count of the currently displayed
|
||||
-- - pixel (even if not in visible area)
|
||||
-- vcount - output pin, 11 bits, to clients
|
||||
-- - vertical count of the currently active video
|
||||
-- - line (even if not in visible area)
|
||||
-- blank - output pin, to clients
|
||||
-- - active when pixel is not in visible area.
|
||||
------------------------------------------------------------------------
|
||||
-- Revision History:
|
||||
-- 09/18/2006(UlrichZ): created
|
||||
------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- the vga_controller_640_60 entity declaration
|
||||
-- read above for behavioral description and port definitions.
|
||||
entity vga_controller_640_60 is
|
||||
port(
|
||||
rst : in std_logic;
|
||||
pixel_clk : in std_logic;
|
||||
|
||||
HS : out std_logic;
|
||||
VS : out std_logic;
|
||||
hcount : out std_logic_vector(10 downto 0);
|
||||
vcount : out std_logic_vector(10 downto 0);
|
||||
blank : out std_logic
|
||||
);
|
||||
end vga_controller_640_60;
|
||||
|
||||
architecture Behavioral of vga_controller_640_60 is
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- CONSTANTS
|
||||
------------------------------------------------------------------------
|
||||
|
||||
-- maximum value for the horizontal pixel counter
|
||||
constant HMAX : std_logic_vector(10 downto 0) := "01100100000"; -- 800
|
||||
-- maximum value for the vertical pixel counter
|
||||
constant VMAX : std_logic_vector(10 downto 0) := "01000001101"; -- 525
|
||||
-- total number of visible columns
|
||||
constant HLINES: std_logic_vector(10 downto 0) := "01010000000"; -- 640
|
||||
-- value for the horizontal counter where front porch ends
|
||||
constant HFP : std_logic_vector(10 downto 0) := "01010001000"; -- 648
|
||||
-- value for the horizontal counter where the synch pulse ends
|
||||
constant HSP : std_logic_vector(10 downto 0) := "01011101000"; -- 744
|
||||
-- total number of visible lines
|
||||
constant VLINES: std_logic_vector(10 downto 0) := "00111100000"; -- 480
|
||||
-- value for the vertical counter where the front porch ends
|
||||
constant VFP : std_logic_vector(10 downto 0) := "00111100010"; -- 482
|
||||
-- value for the vertical counter where the synch pulse ends
|
||||
constant VSP : std_logic_vector(10 downto 0) := "00111100100"; -- 484
|
||||
-- polarity of the horizontal and vertical synch pulse
|
||||
-- only one polarity used, because for this resolution they coincide.
|
||||
constant SPP : std_logic := '0';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- SIGNALS
|
||||
------------------------------------------------------------------------
|
||||
|
||||
-- horizontal and vertical counters
|
||||
signal hcounter : std_logic_vector(10 downto 0) := (others => '0');
|
||||
signal vcounter : std_logic_vector(10 downto 0) := (others => '0');
|
||||
|
||||
-- active when inside visible screen area.
|
||||
signal video_enable: std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- output horizontal and vertical counters
|
||||
hcount <= hcounter;
|
||||
vcount <= vcounter;
|
||||
|
||||
-- blank is active when outside screen visible area
|
||||
-- color output should be blacked (put on 0) when blank in active
|
||||
-- blank is delayed one pixel clock period from the video_enable
|
||||
-- signal to account for the pixel pipeline delay.
|
||||
blank <= not video_enable when rising_edge(pixel_clk);
|
||||
|
||||
-- increment horizontal counter at pixel_clk rate
|
||||
-- until HMAX is reached, then reset and keep counting
|
||||
h_count: process(pixel_clk)
|
||||
begin
|
||||
if(rising_edge(pixel_clk)) then
|
||||
if(rst = '1') then
|
||||
hcounter <= (others => '0');
|
||||
elsif(hcounter = HMAX) then
|
||||
hcounter <= (others => '0');
|
||||
else
|
||||
hcounter <= hcounter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process h_count;
|
||||
|
||||
-- increment vertical counter when one line is finished
|
||||
-- (horizontal counter reached HMAX)
|
||||
-- until VMAX is reached, then reset and keep counting
|
||||
v_count: process(pixel_clk)
|
||||
begin
|
||||
if(rising_edge(pixel_clk)) then
|
||||
if(rst = '1') then
|
||||
vcounter <= (others => '0');
|
||||
elsif(hcounter = HMAX) then
|
||||
if(vcounter = VMAX) then
|
||||
vcounter <= (others => '0');
|
||||
else
|
||||
vcounter <= vcounter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process v_count;
|
||||
|
||||
-- generate horizontal synch pulse
|
||||
-- when horizontal counter is between where the
|
||||
-- front porch ends and the synch pulse ends.
|
||||
-- The HS is active (with polarity SPP) for a total of 96 pixels.
|
||||
do_hs: process(pixel_clk)
|
||||
begin
|
||||
if(rising_edge(pixel_clk)) then
|
||||
if(hcounter >= HFP and hcounter < HSP) then
|
||||
HS <= SPP;
|
||||
else
|
||||
HS <= not SPP;
|
||||
end if;
|
||||
end if;
|
||||
end process do_hs;
|
||||
|
||||
-- generate vertical synch pulse
|
||||
-- when vertical counter is between where the
|
||||
-- front porch ends and the synch pulse ends.
|
||||
-- The VS is active (with polarity SPP) for a total of 2 video lines
|
||||
-- = 2*HMAX = 1600 pixels.
|
||||
do_vs: process(pixel_clk)
|
||||
begin
|
||||
if(rising_edge(pixel_clk)) then
|
||||
if(vcounter >= VFP and vcounter < VSP) then
|
||||
VS <= SPP;
|
||||
else
|
||||
VS <= not SPP;
|
||||
end if;
|
||||
end if;
|
||||
end process do_vs;
|
||||
|
||||
-- enable video output when pixel is in visible area
|
||||
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,242 +0,0 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
// LINE_LENGTH: Length of display line in pixels
|
||||
// Usually it's length from HSync to HSync.
|
||||
// May be less if line_start is used.
|
||||
//
|
||||
// HALF_DEPTH: If =1 then color dept is 3 bits per component
|
||||
// For half depth 6 bits monochrome is available with
|
||||
// mono signal enabled and color = {G, R}
|
||||
|
||||
module video_mixer
|
||||
#(
|
||||
parameter LINE_LENGTH = 768,
|
||||
parameter HALF_DEPTH = 0,
|
||||
|
||||
parameter OSD_COLOR = 3'd4,
|
||||
parameter OSD_X_OFFSET = 10'd0,
|
||||
parameter OSD_Y_OFFSET = 10'd0
|
||||
)
|
||||
(
|
||||
// master clock
|
||||
// it should be multiple by (ce_pix*4).
|
||||
input clk_sys,
|
||||
|
||||
// Pixel clock or clock_enable (both are accepted).
|
||||
input ce_pix,
|
||||
|
||||
// Some systems have multiple resolutions.
|
||||
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
|
||||
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
|
||||
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
|
||||
input ce_pix_actual,
|
||||
|
||||
// OSD SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
// scanlines (00-none 01-25% 10-50% 11-75%)
|
||||
input [1:0] scanlines,
|
||||
|
||||
// 0 = HVSync 31KHz, 1 = CSync 15KHz
|
||||
input scandoubler_disable,
|
||||
|
||||
// High quality 2x scaling
|
||||
input hq2x,
|
||||
|
||||
// YPbPr always uses composite sync
|
||||
input ypbpr,
|
||||
|
||||
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
|
||||
input ypbpr_full,
|
||||
|
||||
// color
|
||||
input [DWIDTH:0] R,
|
||||
input [DWIDTH:0] G,
|
||||
input [DWIDTH:0] B,
|
||||
|
||||
// Monochrome mode (for HALF_DEPTH only)
|
||||
input mono,
|
||||
|
||||
// interlace sync. Positive pulses.
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// Falling of this signal means start of informative part of line.
|
||||
// It can be horizontal blank signal.
|
||||
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
|
||||
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
|
||||
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
|
||||
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
|
||||
// before first informative pixel.
|
||||
input line_start,
|
||||
|
||||
// MiST video output signals
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_VS,
|
||||
output VGA_HS
|
||||
);
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
wire [DWIDTH:0] R_sd;
|
||||
wire [DWIDTH:0] G_sd;
|
||||
wire [DWIDTH:0] B_sd;
|
||||
wire hs_sd, vs_sd;
|
||||
|
||||
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
|
||||
(
|
||||
.*,
|
||||
.hs_in(HSync),
|
||||
.vs_in(VSync),
|
||||
.r_in(R),
|
||||
.g_in(G),
|
||||
.b_in(B),
|
||||
|
||||
.hs_out(hs_sd),
|
||||
.vs_out(vs_sd),
|
||||
.r_out(R_sd),
|
||||
.g_out(G_sd),
|
||||
.b_out(B_sd)
|
||||
);
|
||||
|
||||
wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
|
||||
wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
|
||||
wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
|
||||
|
||||
generate
|
||||
if(HALF_DEPTH) begin
|
||||
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
|
||||
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
|
||||
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
|
||||
end else begin
|
||||
wire [5:0] r = rt;
|
||||
wire [5:0] g = gt;
|
||||
wire [5:0] b = bt;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire hs = (scandoubler_disable ? HSync : hs_sd);
|
||||
wire vs = (scandoubler_disable ? VSync : vs_sd);
|
||||
|
||||
reg scanline = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg old_hs, old_vs;
|
||||
|
||||
old_hs <= hs;
|
||||
old_vs <= vs;
|
||||
|
||||
if(old_hs && ~hs) scanline <= ~scanline;
|
||||
if(old_vs && ~vs) scanline <= 0;
|
||||
end
|
||||
|
||||
wire [5:0] r_out, g_out, b_out;
|
||||
always @(*) begin
|
||||
case(scanlines & {scanline, scanline})
|
||||
1: begin // reduce 25% = 1/2 + 1/4
|
||||
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
|
||||
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
|
||||
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
2: begin // reduce 50% = 1/2
|
||||
r_out = {1'b0, r[5:1]};
|
||||
g_out = {1'b0, g[5:1]};
|
||||
b_out = {1'b0, b[5:1]};
|
||||
end
|
||||
|
||||
3: begin // reduce 75% = 1/4
|
||||
r_out = {2'b00, r[5:2]};
|
||||
g_out = {2'b00, g[5:2]};
|
||||
b_out = {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
default: begin
|
||||
r_out = r;
|
||||
g_out = g;
|
||||
b_out = b;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
wire [5:0] red, green, blue;
|
||||
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
|
||||
(
|
||||
.*,
|
||||
|
||||
.R_in(r_out),
|
||||
.G_in(g_out),
|
||||
.B_in(b_out),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
|
||||
.R_out(red),
|
||||
.G_out(green),
|
||||
.B_out(blue)
|
||||
);
|
||||
|
||||
wire [5:0] yuv_full[225] = '{
|
||||
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
|
||||
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
|
||||
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
|
||||
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
|
||||
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
|
||||
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
|
||||
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
|
||||
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
|
||||
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
|
||||
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
|
||||
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
|
||||
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
|
||||
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
|
||||
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
|
||||
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
|
||||
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
|
||||
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
|
||||
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
|
||||
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
|
||||
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
|
||||
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
|
||||
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
|
||||
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
|
||||
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
|
||||
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
|
||||
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
|
||||
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
|
||||
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
|
||||
6'd63
|
||||
};
|
||||
|
||||
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
|
||||
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
|
||||
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
|
||||
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
|
||||
|
||||
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
|
||||
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
|
||||
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
|
||||
|
||||
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
|
||||
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
|
||||
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
|
||||
assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
|
||||
assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
|
||||
|
||||
endmodule
|
||||
@@ -1,5 +0,0 @@
|
||||
HT 1080Z (TSR-80 clone)
|
||||
|
||||
|
||||
Copyright (c) 2016-2017 Jozsef Laszlo (rbendr@gmail.com)
|
||||
|
||||
@@ -1,38 +0,0 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
cd sys
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
cd ..
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del *.cdf
|
||||
del *.rpt
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
pause
|
||||
@@ -1,31 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||
# Date created = 00:15:27 November 10, 2018
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "00:15:27 November 10, 2018"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "ht1080z"
|
||||
PROJECT_REVISION = "ht1080z_mist"
|
||||
@@ -1,222 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||
# Date created = 18:00:14 October 22, 2018
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Galaksija_Mist_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53 MARCH 09, 2017"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PIN_31 -to UART_RXD
|
||||
set_location_assignment PIN_46 -to UART_TXD
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY ht1080z
|
||||
set_global_assignment -name SEARCH_PATH roms/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/MC6522/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/RAM/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/T6502/ -tag from_archive
|
||||
set_global_assignment -name SEARCH_PATH src/ps2kybrd/ -tag from_archive
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# start EDA_TOOL_SETTINGS(eda_simulation)
|
||||
# ---------------------------------------
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
|
||||
# end EDA_TOOL_SETTINGS(eda_simulation)
|
||||
# -------------------------------------
|
||||
|
||||
# ----------------------------
|
||||
# start ENTITY(Galaksija_MiST)
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(Galaksija_MiST)
|
||||
# --------------------------
|
||||
set_global_assignment -name VHDL_FILE rtl/ht1080z.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/videoctrl.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/user_io.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/sdram.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
|
||||
set_global_assignment -name VHDL_FILE rtl/rom16k.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ram16k.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ps2reader.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ps2kbd.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/pll.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/osd.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/data_io.v
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,371 +0,0 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_ALU;
|
||||
|
||||
architecture rtl of T80_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
|
||||
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
|
||||
process (Carry_v, Carry7_v, Q_v)
|
||||
begin
|
||||
if(Mode=2) then
|
||||
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
|
||||
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,220 +0,0 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T80_Pack is
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
XY_State : in std_logic_vector(1 downto 0);
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
XYbit_undoc : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
@@ -1,114 +0,0 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
|
||||
end;
|
||||
@@ -1,192 +0,0 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core, synchronous top level with clock enable
|
||||
-- Different timing than the original z80
|
||||
-- Inputs needs to be synchronous and outputs may glitch
|
||||
--
|
||||
-- Version : 0240
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0235 : First release
|
||||
--
|
||||
-- 0236 : Added T2Write generic
|
||||
--
|
||||
-- 0237 : Fixed T2Write with wait state
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0240 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80se is
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
||||
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CLKEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80se;
|
||||
|
||||
architecture rtl of T80se is
|
||||
|
||||
signal IntCycle_n : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => Mode,
|
||||
IOWait => IOWait)
|
||||
port map(
|
||||
CEN => CLKEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => RESET_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
CLK_n => CLK_n,
|
||||
A => A,
|
||||
DInst => DI,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
DI_Reg <= "00000000";
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if CLKEN = '1' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
if MCycle = "001" then
|
||||
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||
RD_n <= not IntCycle_n;
|
||||
MREQ_n <= not IntCycle_n;
|
||||
IORQ_n <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
MREQ_n <= '0';
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
|
||||
RD_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
if T2Write = 0 then
|
||||
if TState = "010" and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "010" and Wait_n = '1' then
|
||||
DI_Reg <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
@@ -1,623 +0,0 @@
|
||||
--
|
||||
-- A simulation model of YM2149 (AY-3-8910 with bells on)
|
||||
|
||||
-- Copyright (c) MikeJ - Jan 2005
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email support@fpgaarcade.com
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 001 initial release
|
||||
--
|
||||
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
|
||||
--
|
||||
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
|
||||
-- vol 15 .. 0
|
||||
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
|
||||
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
|
||||
-- to produced all the required values.
|
||||
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
|
||||
--
|
||||
-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
|
||||
-- accurate for designs where the outputs are buffered and not simply wired together.
|
||||
-- The ouput level is more complex in that case and requires a larger table.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity YM2149 is
|
||||
port (
|
||||
-- data bus
|
||||
I_DA : in std_logic_vector(7 downto 0);
|
||||
O_DA : out std_logic_vector(7 downto 0);
|
||||
O_DA_OE_L : out std_logic;
|
||||
-- control
|
||||
I_A9_L : in std_logic;
|
||||
I_A8 : in std_logic;
|
||||
I_BDIR : in std_logic;
|
||||
I_BC2 : in std_logic;
|
||||
I_BC1 : in std_logic;
|
||||
I_SEL_L : in std_logic;
|
||||
|
||||
O_AUDIO : out std_logic_vector(7 downto 0);
|
||||
-- port a
|
||||
I_IOA : in std_logic_vector(7 downto 0);
|
||||
O_IOA : out std_logic_vector(7 downto 0);
|
||||
O_IOA_OE_L : out std_logic;
|
||||
-- port b
|
||||
I_IOB : in std_logic_vector(7 downto 0);
|
||||
O_IOB : out std_logic_vector(7 downto 0);
|
||||
O_IOB_OE_L : out std_logic;
|
||||
|
||||
ENA : in std_logic; -- clock enable for higher speed operation
|
||||
RESET_L : in std_logic;
|
||||
CLK : in std_logic -- note 6 Mhz
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of YM2149 is
|
||||
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
|
||||
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
|
||||
|
||||
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
|
||||
signal noise_div : std_logic := '0';
|
||||
signal ena_div : std_logic;
|
||||
signal ena_div_noise : std_logic;
|
||||
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
|
||||
|
||||
-- registers
|
||||
signal addr : std_logic_vector(7 downto 0);
|
||||
signal busctrl_addr : std_logic;
|
||||
signal busctrl_we : std_logic;
|
||||
signal busctrl_re : std_logic;
|
||||
|
||||
signal reg : array_16x8;
|
||||
signal env_reset : std_logic;
|
||||
signal ioa_inreg : std_logic_vector(7 downto 0);
|
||||
signal iob_inreg : std_logic_vector(7 downto 0);
|
||||
|
||||
signal noise_gen_cnt : std_logic_vector(4 downto 0);
|
||||
signal noise_gen_op : std_logic;
|
||||
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
|
||||
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
|
||||
|
||||
signal env_gen_cnt : std_logic_vector(15 downto 0);
|
||||
signal env_ena : std_logic;
|
||||
signal env_hold : std_logic;
|
||||
signal env_inc : std_logic;
|
||||
signal env_vol : std_logic_vector(4 downto 0);
|
||||
|
||||
signal tone_ena_l : std_logic;
|
||||
signal tone_src : std_logic;
|
||||
signal noise_ena_l : std_logic;
|
||||
signal chan_vol : std_logic_vector(4 downto 0);
|
||||
|
||||
signal dac_amp : std_logic_vector(7 downto 0);
|
||||
signal audio_mix : std_logic_vector(9 downto 0);
|
||||
signal audio_final : std_logic_vector(9 downto 0);
|
||||
begin
|
||||
-- cpu i/f
|
||||
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
|
||||
variable cs : std_logic;
|
||||
variable sel : std_logic_vector(2 downto 0);
|
||||
begin
|
||||
-- BDIR BC2 BC1 MODE
|
||||
-- 0 0 0 inactive
|
||||
-- 0 0 1 address
|
||||
-- 0 1 0 inactive
|
||||
-- 0 1 1 read
|
||||
-- 1 0 0 address
|
||||
-- 1 0 1 inactive
|
||||
-- 1 1 0 write
|
||||
-- 1 1 1 read
|
||||
busctrl_addr <= '0';
|
||||
busctrl_we <= '0';
|
||||
busctrl_re <= '0';
|
||||
|
||||
cs := '0';
|
||||
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
|
||||
cs := '1';
|
||||
end if;
|
||||
|
||||
sel := (I_BDIR & I_BC2 & I_BC1);
|
||||
case sel is
|
||||
when "000" => null;
|
||||
when "001" => busctrl_addr <= '1';
|
||||
when "010" => null;
|
||||
when "011" => busctrl_re <= cs;
|
||||
when "100" => busctrl_addr <= '1';
|
||||
when "101" => null;
|
||||
when "110" => busctrl_we <= cs;
|
||||
when "111" => busctrl_addr <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
p_oe : process(busctrl_re)
|
||||
begin
|
||||
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
|
||||
O_DA_OE_L <= not (busctrl_re);
|
||||
end process;
|
||||
|
||||
--
|
||||
-- CLOCKED
|
||||
--
|
||||
--p_waddr : process
|
||||
--begin
|
||||
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
|
||||
--wait until rising_edge(CLK);
|
||||
|
||||
--if (RESET_L = '0') then
|
||||
--addr <= (others => '0');
|
||||
--else
|
||||
--if (busctrl_addr = '1') then
|
||||
--addr <= I_DA;
|
||||
--end if;
|
||||
--end if;
|
||||
--end process;
|
||||
|
||||
--p_wdata : process
|
||||
--begin
|
||||
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
|
||||
--wait until rising_edge(CLK);
|
||||
--env_reset <= '0';
|
||||
|
||||
--if (RESET_L = '0') then
|
||||
--reg <= (others => (others => '0'));
|
||||
--env_reset <= '1';
|
||||
--else
|
||||
--env_reset <= '0';
|
||||
--if (busctrl_we = '1') then
|
||||
--case addr(3 downto 0) is
|
||||
--when x"0" => reg(0) <= I_DA;
|
||||
--when x"1" => reg(1) <= I_DA;
|
||||
--when x"2" => reg(2) <= I_DA;
|
||||
--when x"3" => reg(3) <= I_DA;
|
||||
--when x"4" => reg(4) <= I_DA;
|
||||
--when x"5" => reg(5) <= I_DA;
|
||||
--when x"6" => reg(6) <= I_DA;
|
||||
--when x"7" => reg(7) <= I_DA;
|
||||
--when x"8" => reg(8) <= I_DA;
|
||||
--when x"9" => reg(9) <= I_DA;
|
||||
--when x"A" => reg(10) <= I_DA;
|
||||
--when x"B" => reg(11) <= I_DA;
|
||||
--when x"C" => reg(12) <= I_DA;
|
||||
--when x"D" => reg(13) <= I_DA; env_reset <= '1';
|
||||
--when x"E" => reg(14) <= I_DA;
|
||||
--when x"F" => reg(15) <= I_DA;
|
||||
--when others => null;
|
||||
--end case;
|
||||
--end if;
|
||||
--end if;
|
||||
--end process;
|
||||
|
||||
--
|
||||
-- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
|
||||
--
|
||||
p_waddr : process(reset_l, busctrl_addr)
|
||||
begin
|
||||
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
|
||||
if (RESET_L = '0') then
|
||||
addr <= (others => '0');
|
||||
elsif falling_edge(busctrl_addr) then -- yuk
|
||||
addr <= I_DA;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_wdata : process(reset_l, busctrl_we, addr)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
reg <= (others => (others => '0'));
|
||||
elsif falling_edge(busctrl_we) then
|
||||
case addr(3 downto 0) is
|
||||
when x"0" => reg(0) <= I_DA;
|
||||
when x"1" => reg(1) <= I_DA;
|
||||
when x"2" => reg(2) <= I_DA;
|
||||
when x"3" => reg(3) <= I_DA;
|
||||
when x"4" => reg(4) <= I_DA;
|
||||
when x"5" => reg(5) <= I_DA;
|
||||
when x"6" => reg(6) <= I_DA;
|
||||
when x"7" => reg(7) <= I_DA;
|
||||
when x"8" => reg(8) <= I_DA;
|
||||
when x"9" => reg(9) <= I_DA;
|
||||
when x"A" => reg(10) <= I_DA;
|
||||
when x"B" => reg(11) <= I_DA;
|
||||
when x"C" => reg(12) <= I_DA;
|
||||
when x"D" => reg(13) <= I_DA;
|
||||
when x"E" => reg(14) <= I_DA;
|
||||
when x"F" => reg(15) <= I_DA;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
env_reset <= '0';
|
||||
if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
|
||||
env_reset <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_rdata : process(busctrl_re, addr, reg)
|
||||
begin
|
||||
O_DA <= (others => '0'); -- 'X'
|
||||
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
|
||||
case addr(3 downto 0) is
|
||||
when x"0" => O_DA <= reg(0) ;
|
||||
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
|
||||
when x"2" => O_DA <= reg(2) ;
|
||||
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
|
||||
when x"4" => O_DA <= reg(4) ;
|
||||
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
|
||||
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
|
||||
when x"7" => O_DA <= reg(7) ;
|
||||
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
|
||||
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
|
||||
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
|
||||
when x"B" => O_DA <= reg(11);
|
||||
when x"C" => O_DA <= reg(12);
|
||||
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
|
||||
when x"E" => if (reg(7)(6) = '0') then -- input
|
||||
O_DA <= ioa_inreg;
|
||||
else
|
||||
O_DA <= reg(14); -- read output reg
|
||||
end if;
|
||||
when x"F" => if (Reg(7)(7) = '0') then
|
||||
O_DA <= iob_inreg;
|
||||
else
|
||||
O_DA <= reg(15);
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
p_divider : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
-- / 8 when SEL is high and /16 when SEL is low
|
||||
if (ENA = '1') then
|
||||
ena_div <= '0';
|
||||
ena_div_noise <= '0';
|
||||
if (cnt_div = "0000") then
|
||||
cnt_div <= (not I_SEL_L) & "111";
|
||||
ena_div <= '1';
|
||||
|
||||
noise_div <= not noise_div;
|
||||
if (noise_div = '1') then
|
||||
ena_div_noise <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt_div <= cnt_div - "1";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_noise_gen : process
|
||||
variable noise_gen_comp : std_logic_vector(4 downto 0);
|
||||
variable poly17_zero : std_logic;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
if (reg(6)(4 downto 0) = "00000") then
|
||||
noise_gen_comp := "00000";
|
||||
else
|
||||
noise_gen_comp := (reg(6)(4 downto 0) - "1");
|
||||
end if;
|
||||
|
||||
poly17_zero := '0';
|
||||
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
|
||||
|
||||
if (ENA = '1') then
|
||||
|
||||
if (ena_div_noise = '1') then -- divider ena
|
||||
|
||||
if (noise_gen_cnt >= noise_gen_comp) then
|
||||
noise_gen_cnt <= "00000";
|
||||
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
|
||||
else
|
||||
noise_gen_cnt <= (noise_gen_cnt + "1");
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
noise_gen_op <= poly17(0);
|
||||
|
||||
p_tone_gens : process
|
||||
variable tone_gen_freq : array_3x12;
|
||||
variable tone_gen_comp : array_3x12;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
-- looks like real chips count up - we need to get the Exact behaviour ..
|
||||
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
|
||||
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
|
||||
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
|
||||
-- period 0 = period 1
|
||||
for i in 1 to 3 loop
|
||||
if (tone_gen_freq(i) = x"000") then
|
||||
tone_gen_comp(i) := x"000";
|
||||
else
|
||||
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
if (ENA = '1') then
|
||||
for i in 1 to 3 loop
|
||||
if (ena_div = '1') then -- divider ena
|
||||
|
||||
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
|
||||
tone_gen_cnt(i) <= x"000";
|
||||
tone_gen_op(i) <= not tone_gen_op(i);
|
||||
else
|
||||
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_envelope_freq : process
|
||||
variable env_gen_freq : std_logic_vector(15 downto 0);
|
||||
variable env_gen_comp : std_logic_vector(15 downto 0);
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
env_gen_freq := reg(12) & reg(11);
|
||||
-- envelope freqs 1 and 0 are the same.
|
||||
if (env_gen_freq = x"0000") then
|
||||
env_gen_comp := x"0000";
|
||||
else
|
||||
env_gen_comp := (env_gen_freq - "1");
|
||||
end if;
|
||||
|
||||
if (ENA = '1') then
|
||||
env_ena <= '0';
|
||||
if (ena_div = '1') then -- divider ena
|
||||
if (env_gen_cnt >= env_gen_comp) then
|
||||
env_gen_cnt <= x"0000";
|
||||
env_ena <= '1';
|
||||
else
|
||||
env_gen_cnt <= (env_gen_cnt + "1");
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_envelope_shape : process(env_reset, CLK)
|
||||
variable is_bot : boolean;
|
||||
variable is_bot_p1 : boolean;
|
||||
variable is_top_m1 : boolean;
|
||||
variable is_top : boolean;
|
||||
begin
|
||||
-- envelope shapes
|
||||
-- C AtAlH
|
||||
-- 0 0 x x \___
|
||||
--
|
||||
-- 0 1 x x /___
|
||||
--
|
||||
-- 1 0 0 0 \\\\
|
||||
--
|
||||
-- 1 0 0 1 \___
|
||||
--
|
||||
-- 1 0 1 0 \/\/
|
||||
-- ___
|
||||
-- 1 0 1 1 \
|
||||
--
|
||||
-- 1 1 0 0 ////
|
||||
-- ___
|
||||
-- 1 1 0 1 /
|
||||
--
|
||||
-- 1 1 1 0 /\/\
|
||||
--
|
||||
-- 1 1 1 1 /___
|
||||
if (env_reset = '1') then
|
||||
-- load initial state
|
||||
if (reg(13)(2) = '0') then -- attack
|
||||
env_vol <= "11111";
|
||||
env_inc <= '0'; -- -1
|
||||
else
|
||||
env_vol <= "00000";
|
||||
env_inc <= '1'; -- +1
|
||||
end if;
|
||||
env_hold <= '0';
|
||||
|
||||
elsif rising_edge(CLK) then
|
||||
is_bot := (env_vol = "00000");
|
||||
is_bot_p1 := (env_vol = "00001");
|
||||
is_top_m1 := (env_vol = "11110");
|
||||
is_top := (env_vol = "11111");
|
||||
|
||||
if (ENA = '1') then
|
||||
if (env_ena = '1') then
|
||||
if (env_hold = '0') then
|
||||
if (env_inc = '1') then
|
||||
env_vol <= (env_vol + "00001");
|
||||
else
|
||||
env_vol <= (env_vol + "11111");
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- envelope shape control.
|
||||
if (reg(13)(3) = '0') then
|
||||
if (env_inc = '0') then -- down
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_top then env_hold <= '1'; end if;
|
||||
end if;
|
||||
else
|
||||
if (reg(13)(0) = '1') then -- hold = 1
|
||||
if (env_inc = '0') then -- down
|
||||
if (reg(13)(1) = '1') then -- alt
|
||||
if is_bot then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
end if;
|
||||
else
|
||||
if (reg(13)(1) = '1') then -- alt
|
||||
if is_top then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_top_m1 then env_hold <= '1'; end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
elsif (reg(13)(1) = '1') then -- alternate
|
||||
if (env_inc = '0') then -- down
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
|
||||
else
|
||||
if is_top_m1 then env_hold <= '1'; end if;
|
||||
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
|
||||
begin
|
||||
tone_ena_l <= '1'; tone_src <= '1';
|
||||
noise_ena_l <= '1'; chan_vol <= "00000";
|
||||
case cnt_div(1 downto 0) is
|
||||
when "00" =>
|
||||
tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(3);
|
||||
when "01" =>
|
||||
tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(4);
|
||||
when "10" =>
|
||||
tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(5);
|
||||
when "11" => null; -- tone gen outputs become valid on this clock
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
p_op_mixer : process
|
||||
variable chan_mixed : std_logic;
|
||||
variable chan_amp : std_logic_vector(4 downto 0);
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA = '1') then
|
||||
|
||||
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
|
||||
|
||||
chan_amp := (others => '0');
|
||||
if (chan_mixed = '1') then
|
||||
if (chan_vol(4) = '0') then
|
||||
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
|
||||
chan_amp := "00000";
|
||||
else
|
||||
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
|
||||
end if;
|
||||
else
|
||||
chan_amp := env_vol(4 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
dac_amp <= x"00";
|
||||
case chan_amp is
|
||||
when "11111" => dac_amp <= x"FF";
|
||||
when "11110" => dac_amp <= x"D9";
|
||||
when "11101" => dac_amp <= x"BA";
|
||||
when "11100" => dac_amp <= x"9F";
|
||||
when "11011" => dac_amp <= x"88";
|
||||
when "11010" => dac_amp <= x"74";
|
||||
when "11001" => dac_amp <= x"63";
|
||||
when "11000" => dac_amp <= x"54";
|
||||
when "10111" => dac_amp <= x"48";
|
||||
when "10110" => dac_amp <= x"3D";
|
||||
when "10101" => dac_amp <= x"34";
|
||||
when "10100" => dac_amp <= x"2C";
|
||||
when "10011" => dac_amp <= x"25";
|
||||
when "10010" => dac_amp <= x"1F";
|
||||
when "10001" => dac_amp <= x"1A";
|
||||
when "10000" => dac_amp <= x"16";
|
||||
when "01111" => dac_amp <= x"13";
|
||||
when "01110" => dac_amp <= x"10";
|
||||
when "01101" => dac_amp <= x"0D";
|
||||
when "01100" => dac_amp <= x"0B";
|
||||
when "01011" => dac_amp <= x"09";
|
||||
when "01010" => dac_amp <= x"08";
|
||||
when "01001" => dac_amp <= x"07";
|
||||
when "01000" => dac_amp <= x"06";
|
||||
when "00111" => dac_amp <= x"05";
|
||||
when "00110" => dac_amp <= x"04";
|
||||
when "00101" => dac_amp <= x"03";
|
||||
when "00100" => dac_amp <= x"03";
|
||||
when "00011" => dac_amp <= x"02";
|
||||
when "00010" => dac_amp <= x"02";
|
||||
when "00001" => dac_amp <= x"01";
|
||||
when "00000" => dac_amp <= x"00";
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
if (cnt_div(1 downto 0) = "10") then
|
||||
audio_mix <= (others => '0');
|
||||
audio_final <= audio_mix;
|
||||
else
|
||||
audio_mix <= audio_mix + ("00" & dac_amp);
|
||||
end if;
|
||||
|
||||
if (RESET_L = '0') then
|
||||
O_AUDIO(7 downto 0) <= "00000000";
|
||||
else
|
||||
if (audio_final(9) = '0') then
|
||||
O_AUDIO(7 downto 0) <= audio_final(8 downto 1);
|
||||
else -- clip
|
||||
O_AUDIO(7 downto 0) <= x"FF";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_io_ports : process(reg)
|
||||
begin
|
||||
O_IOA <= reg(14);
|
||||
|
||||
O_IOA_OE_L <= not reg(7)(6);
|
||||
O_IOB <= reg(15);
|
||||
O_IOB_OE_L <= not reg(7)(7);
|
||||
end process;
|
||||
|
||||
p_io_ports_inreg : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
ioa_inreg <= I_IOA;
|
||||
iob_inreg <= I_IOB;
|
||||
end process;
|
||||
end architecture RTL;
|
||||
@@ -1,35 +0,0 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
@@ -1,2 +0,0 @@
|
||||
`define BUILD_DATE "181110"
|
||||
`define BUILD_TIME "002457"
|
||||
@@ -1,71 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Delta-Sigma DAC
|
||||
--
|
||||
-- $Id: dac.vhd,v 1.1 2006/05/10 20:57:06 arnim Exp $
|
||||
--
|
||||
-- Refer to Xilinx Application Note XAPP154.
|
||||
--
|
||||
-- This DAC requires an external RC low-pass filter:
|
||||
--
|
||||
-- dac_o 0---XXXXX---+---0 analog audio
|
||||
-- 3k3 |
|
||||
-- === 4n7
|
||||
-- |
|
||||
-- GND
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity dac is
|
||||
|
||||
generic (
|
||||
msbi_g : integer := 7
|
||||
);
|
||||
port (
|
||||
clk_i : in std_logic;
|
||||
res_n_i : in std_logic;
|
||||
dac_i : in std_logic_vector(msbi_g downto 0);
|
||||
dac_o : out std_logic
|
||||
);
|
||||
|
||||
end dac;
|
||||
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
architecture rtl of dac is
|
||||
|
||||
signal DACout_q : std_logic;
|
||||
signal DeltaAdder_s,
|
||||
SigmaAdder_s,
|
||||
SigmaLatch_q,
|
||||
DeltaB_s : unsigned(msbi_g+2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
|
||||
SigmaLatch_q(msbi_g+2);
|
||||
DeltaB_s(msbi_g downto 0) <= (others => '0');
|
||||
|
||||
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
|
||||
|
||||
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
|
||||
|
||||
seq: process (clk_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
|
||||
DACout_q <= '0';
|
||||
|
||||
elsif clk_i'event and clk_i = '1' then
|
||||
SigmaLatch_q <= SigmaAdder_s;
|
||||
DACout_q <= SigmaLatch_q(msbi_g+2);
|
||||
end if;
|
||||
end process seq;
|
||||
|
||||
dac_o <= DACout_q;
|
||||
|
||||
end rtl;
|
||||
@@ -1,121 +0,0 @@
|
||||
//
|
||||
// data_io.v
|
||||
//
|
||||
// io controller writable ram for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// ZX Spectrum adapted version
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
module data_io (
|
||||
// io controller spi interface
|
||||
input sck,
|
||||
input ss,
|
||||
input sdi,
|
||||
|
||||
output downloading, // signal indicating an active download
|
||||
output reg [4:0] index, // menu index used to upload the file
|
||||
|
||||
// external ram interface
|
||||
input clk,
|
||||
output reg wr,
|
||||
output reg [24:0] addr,
|
||||
output reg [7:0] data
|
||||
);
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg rclk;
|
||||
|
||||
localparam UIO_FILE_TX = 8'h53;
|
||||
localparam UIO_FILE_TX_DAT = 8'h54;
|
||||
localparam UIO_FILE_INDEX = 8'h55;
|
||||
|
||||
assign downloading = downloading_reg;
|
||||
reg downloading_reg = 1'b0;
|
||||
|
||||
// data_io has its own SPI interface to the io controller
|
||||
always@(posedge sck, posedge ss) begin
|
||||
if(ss == 1'b1)
|
||||
cnt <= 5'd0;
|
||||
else begin
|
||||
rclk <= 1'b0;
|
||||
|
||||
// don't shift in last bit. It is evaluated directly
|
||||
// when writing to ram
|
||||
if(cnt != 15)
|
||||
sbuf <= { sbuf[5:0], sdi};
|
||||
|
||||
// increase target address after write
|
||||
if(rclk)
|
||||
addr <= addr + 1;
|
||||
|
||||
// count 0-7 8-15 8-15 ...
|
||||
if(cnt < 15) cnt <= cnt + 4'd1;
|
||||
else cnt <= 4'd8;
|
||||
|
||||
// finished command byte
|
||||
if(cnt == 7)
|
||||
cmd <= {sbuf, sdi};
|
||||
|
||||
// prepare/end transmission
|
||||
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
|
||||
// prepare
|
||||
if(sdi) begin
|
||||
//addr <= 25'd0;
|
||||
// pppppppp
|
||||
// xxxx....xxxx....
|
||||
if (index==5'b00000) addr <= 25'b0000000000000000000000000;
|
||||
else addr <= 25'b0000000010000000000000000;
|
||||
//addr <= 25'b0000000001100000000000000;
|
||||
downloading_reg <= 1'b1;
|
||||
end else
|
||||
downloading_reg <= 1'b0;
|
||||
end
|
||||
|
||||
// command 0x54: UIO_FILE_TX
|
||||
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
|
||||
data <= {sbuf, sdi};
|
||||
rclk <= 1'b1;
|
||||
end
|
||||
|
||||
// expose file (menu) index
|
||||
if((cmd == UIO_FILE_INDEX) && (cnt == 15))
|
||||
index <= {sbuf[3:0], sdi};
|
||||
end
|
||||
end
|
||||
|
||||
reg rclkD, rclkD2;
|
||||
always@(posedge clk) begin
|
||||
// bring rclk from spi clock domain into c64 clock domain
|
||||
rclkD <= rclk;
|
||||
rclkD2 <= rclkD;
|
||||
wr <= 1'b0;
|
||||
|
||||
if(rclkD && !rclkD2)
|
||||
wr <= 1'b1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,611 +0,0 @@
|
||||
--
|
||||
-- HT 1080Z (TSR-80 clone) top level
|
||||
--
|
||||
--
|
||||
-- Copyright (c) 2016-2017 Jozsef Laszlo (rbendr@gmail.com)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity ht1080z is
|
||||
Port (
|
||||
CLOCK_27 : in STD_LOGIC;
|
||||
SDRAM_nCS : out std_logic; -- Chip Select
|
||||
SDRAM_DQ : inout std_logic_vector(15 downto 0); -- SDRAM Data bus 16 Bits
|
||||
SDRAM_A : out std_logic_vector(12 downto 0); -- SDRAM Address bus 13 Bits
|
||||
SDRAM_DQMH : out std_logic; -- SDRAM High Data Mask
|
||||
SDRAM_DQML : out std_logic; -- SDRAM Low-byte Data Mask
|
||||
SDRAM_nWE : out std_logic; -- SDRAM Write Enable
|
||||
SDRAM_nCAS : out std_logic; -- SDRAM Column Address Strobe
|
||||
SDRAM_nRAS : out std_logic; -- SDRAM Row Address Strobe
|
||||
SDRAM_BA : out std_logic_vector(1 downto 0); -- SDRAM Bank Address
|
||||
SDRAM_CLK : out std_logic; -- SDRAM Clock
|
||||
SDRAM_CKE : out std_logic; -- SDRAM Clock Enable
|
||||
SPI_DO : out std_logic;
|
||||
SPI_DI : in std_logic;
|
||||
SPI_SCK : in std_logic;
|
||||
SPI_SS2 : in std_logic;
|
||||
SPI_SS3 : in std_logic;
|
||||
SPI_SS4 : in std_logic;
|
||||
CONF_DATA0 : in std_logic;
|
||||
VGA_R : out STD_LOGIC_VECTOR (5 downto 0);
|
||||
VGA_G : out STD_LOGIC_VECTOR (5 downto 0);
|
||||
VGA_B : out STD_LOGIC_VECTOR (5 downto 0);
|
||||
VGA_HS : out STD_LOGIC;
|
||||
VGA_VS : out STD_LOGIC;
|
||||
LED : out STD_LOGIC;
|
||||
AUDIO_L : out STD_LOGIC;
|
||||
AUDIO_R : out STD_LOGIC
|
||||
);
|
||||
end ht1080z;
|
||||
|
||||
architecture Behavioral of ht1080z is
|
||||
|
||||
component data_io
|
||||
port ( sck, ss, sdi : in std_logic;
|
||||
|
||||
-- download info
|
||||
downloading : out std_logic;
|
||||
--size : out std_logic_vector(24 downto 0);
|
||||
index : out std_logic_vector(4 downto 0);
|
||||
|
||||
-- external ram interface
|
||||
clk : in std_logic;
|
||||
wr : out std_logic;
|
||||
addr : out std_logic_vector(24 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component data_io;
|
||||
|
||||
component sdram is
|
||||
port( sd_data : inout std_logic_vector(15 downto 0);
|
||||
sd_addr : out std_logic_vector(12 downto 0);
|
||||
sd_dqm : out std_logic_vector(1 downto 0);
|
||||
sd_ba : out std_logic_vector(1 downto 0);
|
||||
sd_cs : out std_logic;
|
||||
sd_we : out std_logic;
|
||||
sd_ras : out std_logic;
|
||||
sd_cas : out std_logic;
|
||||
init : in std_logic;
|
||||
clk : in std_logic;
|
||||
clkref : in std_logic;
|
||||
din : in std_logic_vector(7 downto 0);
|
||||
dout : out std_logic_vector(7 downto 0);
|
||||
addr : in std_logic_vector(24 downto 0);
|
||||
oe : in std_logic;
|
||||
we : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component osd
|
||||
generic ( OSD_COLOR : integer );
|
||||
port ( pclk : in std_logic;
|
||||
sck, sdi, ss : in std_logic;
|
||||
|
||||
-- VGA signals coming from core
|
||||
red_in : in std_logic_vector(5 downto 0);
|
||||
green_in : in std_logic_vector(5 downto 0);
|
||||
blue_in : in std_logic_vector(5 downto 0);
|
||||
hs_in : in std_logic;
|
||||
vs_in : in std_logic;
|
||||
|
||||
-- VGA signals going to video connector
|
||||
red_out : out std_logic_vector(5 downto 0);
|
||||
green_out : out std_logic_vector(5 downto 0);
|
||||
blue_out : out std_logic_vector(5 downto 0);
|
||||
hs_out : out std_logic;
|
||||
vs_out : out std_logic
|
||||
);
|
||||
end component osd;
|
||||
|
||||
component user_io
|
||||
generic ( STRLEN : integer := 0 );
|
||||
port (
|
||||
-- ps2 interface
|
||||
SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
|
||||
SPI_MISO : out std_logic;
|
||||
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
|
||||
joystick_0 : out std_logic_vector(7 downto 0);
|
||||
joystick_1 : out std_logic_vector(7 downto 0);
|
||||
status: out std_logic_vector(7 downto 0);
|
||||
ps2_clk : in std_LOGIC;
|
||||
ps2_kbd_clk : out std_logic;
|
||||
ps2_kbd_data : out std_logic;
|
||||
ps2_mouse_clk : out std_logic;
|
||||
ps2_mouse_data : out std_logic;
|
||||
scandoubler_disable : out std_logic
|
||||
);
|
||||
end component user_io;
|
||||
|
||||
constant CONF_STR : string := "HT1080Z;CAS;O1,Scanlines,Off,On;T2,Reset";
|
||||
--"SMS;SMS;O1,Video,NTSC,PAL;O2,Scanlines,Off,On;O3,Joysticks,Normal,Swapped;T4,Pause;T5,Reset";
|
||||
|
||||
function to_slv(s: string) return std_logic_vector is
|
||||
constant ss: string(1 to s'length) := s;
|
||||
variable rval: std_logic_vector(1 to 8 * s'length);
|
||||
variable p: integer;
|
||||
variable c: integer;
|
||||
|
||||
begin
|
||||
for i in ss'range loop
|
||||
p := 8 * i;
|
||||
c := character'pos(ss(i));
|
||||
rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
|
||||
end loop;
|
||||
return rval;
|
||||
|
||||
end function;
|
||||
|
||||
|
||||
signal sdram_dqm : std_logic_vector(1 downto 0);
|
||||
signal ram_addr : std_logic_vector(24 downto 0);
|
||||
signal ram_din : STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal ram_dout : STD_LOGIC_VECTOR(7 downto 0);
|
||||
signal ram_we: std_logic;
|
||||
signal ram_oe: std_logic;
|
||||
|
||||
signal dn_go : std_logic;
|
||||
signal dn_wr : std_logic;
|
||||
signal dn_addr : std_logic_vector(24 downto 0);
|
||||
signal dn_data : std_logic_vector(7 downto 0);
|
||||
signal dn_idx : std_logic_vector(4 downto 0);
|
||||
|
||||
signal dn_wr_r : std_logic;
|
||||
signal dn_addr_r : std_logic_vector(24 downto 0);
|
||||
signal dn_data_r : std_logic_vector(7 downto 0);
|
||||
|
||||
signal res_cnt : std_logic_vector(5 downto 0) := "111111";
|
||||
signal autores : std_logic;
|
||||
|
||||
|
||||
signal pvsel : std_logic;
|
||||
signal ps2clkout : std_logic;
|
||||
|
||||
signal PS2CLK : std_logic;
|
||||
signal PS2DAT : std_logic;
|
||||
|
||||
signal MPS2CLK : std_logic;
|
||||
signal MPS2DAT : std_logic;
|
||||
|
||||
signal joy0 : std_logic_vector(7 downto 0);
|
||||
signal joy1 : std_logic_vector(7 downto 0);
|
||||
|
||||
signal status: std_logic_vector(7 downto 0);
|
||||
|
||||
signal clk56m : std_logic;
|
||||
signal clk42m,clk21m,clk7m : std_logic;
|
||||
signal pllLocked : std_logic;
|
||||
|
||||
signal cpua : std_logic_vector(15 downto 0);
|
||||
signal cpudo : std_logic_vector(7 downto 0);
|
||||
signal cpudi : std_logic_vector(7 downto 0);
|
||||
signal cpuwr,cpurd,cpumreq,cpuiorq,cpunmi,cpuint,cpum1,cpuclk,cpuClkEn : std_logic;
|
||||
|
||||
signal rgbi : std_logic_vector(3 downto 0);
|
||||
signal hs,vs : std_logic;
|
||||
signal romdo,vramdo,ramdo,ramHdo,kbdout : std_logic_vector(7 downto 0);
|
||||
signal vramcs : std_logic;
|
||||
|
||||
signal page,vcut,swres : std_logic;
|
||||
|
||||
signal romrd,ramrd,ramwr,vramsel,kbdsel : std_logic;
|
||||
signal ior,iow,memr,memw : std_logic;
|
||||
signal vdata : std_logic_vector(7 downto 0);
|
||||
|
||||
signal clk_download : std_logic;
|
||||
|
||||
-- 0 1 2 3 4
|
||||
-- 28 14 7 3.5 1.75
|
||||
signal clk56div : std_logic_vector(11 downto 0);
|
||||
|
||||
signal dacout : std_logic;
|
||||
signal sndBC1,sndBDIR,sndCLK : std_logic;
|
||||
signal oaudio,snddo : std_logic_vector(7 downto 0);
|
||||
|
||||
signal ht_rgb : std_logic_vector(17 downto 0);
|
||||
signal out_rgb : std_logic_vector(17 downto 0);
|
||||
signal p_hs,p_vs,vgahs,vgavs : std_logic;
|
||||
signal pclk : std_logic;
|
||||
|
||||
signal io_ram_addr : std_logic_vector(23 downto 0);
|
||||
signal iorrd,iorrd_r : std_logic;
|
||||
|
||||
signal audiomix : std_logic_vector(8 downto 0);
|
||||
signal tapebits : std_logic_vector(2 downto 0);
|
||||
signal speaker : std_logic_vector(7 downto 0);
|
||||
signal vga : std_logic := '0';
|
||||
signal scanlines : std_logic;
|
||||
signal oddline : std_logic;
|
||||
|
||||
signal inkpulse, paperpulse, borderpulse : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
led <= not scanlines; --not dn_go;--swres;
|
||||
|
||||
-- generate system clocks
|
||||
clkmgr : entity work.pll
|
||||
port map (
|
||||
inclk0 => CLOCK_27,
|
||||
c0 => clk56M,
|
||||
c1 => SDRAM_CLK,
|
||||
c2 => clk42m,
|
||||
locked => pllLocked
|
||||
);
|
||||
|
||||
process(clk56m)
|
||||
begin
|
||||
if rising_edge(clk56m) then
|
||||
clk56div <= clk56div - 1;
|
||||
end if;
|
||||
end process;
|
||||
clk7m <= clk56div(2);
|
||||
ps2clkout <= clk56div(11);
|
||||
|
||||
ior <= cpurd or cpuiorq or (not cpum1);
|
||||
iow <= cpuwr or cpuiorq;
|
||||
memr <= cpurd or cpumreq;
|
||||
memw <= cpuwr or cpumreq;
|
||||
|
||||
romrd <= '1' when memr='0' and cpua<x"3780" else '0';
|
||||
ramrd <= '1' when cpua(15 downto 14)="01" and memr='0' else '0';
|
||||
ramwr <= '1' when cpua(15 downto 14)="01" and memw='0' else '0';
|
||||
vramsel <= '1' when cpua(15 downto 10)="001111" and cpumreq='0' else '0';
|
||||
kbdsel <= '1' when cpua(15 downto 10)="001110" and memr='0' else '0';
|
||||
iorrd <= '1' when ior='0' and cpua(7 downto 0)=x"04" else '0'; -- in 04
|
||||
|
||||
cpuClk <= clk56div(4);
|
||||
clk_download <= clk56div(3);
|
||||
|
||||
cpu : entity work.T80se
|
||||
port map (
|
||||
RESET_n => autores, --swres,
|
||||
CLK_n => cpuClk, -- 1.75 MHz
|
||||
CLKEN => cpuClkEn,
|
||||
WAIT_n => '1',
|
||||
INT_n => '1',
|
||||
NMI_n => '1',
|
||||
BUSRQ_n => '1',
|
||||
M1_n => cpum1,
|
||||
MREQ_n => cpumreq,
|
||||
IORQ_n => cpuiorq,
|
||||
RD_n => cpurd,
|
||||
WR_n => cpuwr,
|
||||
RFSH_n => open,
|
||||
HALT_n => open,
|
||||
BUSAK_n => open,
|
||||
A => cpua,
|
||||
DI => cpudi,
|
||||
DO => cpudo
|
||||
);
|
||||
|
||||
cpudi <= --romdo when romrd='1' else
|
||||
--ramdo when ramrd='1' else
|
||||
--ram_dout when romrd='1' else
|
||||
--ram_dout when ramrd='1' else
|
||||
vramdo when vramsel='1' else
|
||||
kbdout when kbdsel='1' else
|
||||
x"30" when ior='0' and cpua(7 downto 0)=x"fd" else -- printer io read
|
||||
--ram_dout when iorrd='1' else
|
||||
--x"ff";
|
||||
ram_dout;
|
||||
|
||||
|
||||
vga <= not pvsel;
|
||||
vdata <= cpudo when cpudo>x"1f" else cpudo or x"40";
|
||||
-- video ram at 0x3C00
|
||||
video : entity work.videoctrl
|
||||
port map (
|
||||
reset => autores, --swres and pllLocked,
|
||||
clk42 => clk42m,
|
||||
-- clk7 => clk7m,
|
||||
a => cpua(13 downto 0),
|
||||
din => vdata,--cpudo,
|
||||
dout => vramdo,
|
||||
mreq => cpumreq,
|
||||
iorq => cpuiorq,
|
||||
wr => cpuwr,
|
||||
cs => not vramsel,
|
||||
vcut => vcut,
|
||||
vvga => vga,
|
||||
page => page,
|
||||
rgbi => rgbi,
|
||||
pclk => pclk,
|
||||
inkp => inkpulse,
|
||||
paperp => paperpulse,
|
||||
borderp => borderpulse,
|
||||
oddline => oddline,
|
||||
hsync => hs,
|
||||
vsync => vs
|
||||
);
|
||||
|
||||
VGA_HS <= hs when vga='1' else hs xor (not vs);
|
||||
VGA_VS <= vs when vga='1' else '1';
|
||||
|
||||
kbd : entity work.ps2kbd
|
||||
port map (
|
||||
RESET => not pllLocked,
|
||||
KBCLK => ps2clk,
|
||||
KBDAT => ps2dat,
|
||||
SWRES => swres,
|
||||
CLK => clk7m,
|
||||
A => cpua(7 downto 0),
|
||||
DOUT => kbdout,
|
||||
PAGE => page,
|
||||
VCUT => vcut,
|
||||
INKP => inkpulse,
|
||||
PAPERP => paperpulse,
|
||||
BORDERP => borderpulse
|
||||
);
|
||||
|
||||
-- PSG
|
||||
-- out 1e = data port
|
||||
-- out 1f = register index
|
||||
|
||||
soundchip : entity work.YM2149
|
||||
port map (
|
||||
-- data bus
|
||||
I_DA => cpudo,
|
||||
O_DA => open,
|
||||
O_DA_OE_L => open,
|
||||
-- control
|
||||
I_A9_L => '0',
|
||||
I_A8 => '1',
|
||||
I_BDIR => sndBDIR,
|
||||
I_BC2 => '1',
|
||||
I_BC1 => sndBC1,
|
||||
I_SEL_L => '1',
|
||||
|
||||
O_AUDIO => oaudio,
|
||||
-- port a
|
||||
I_IOA => "ZZZZZZZZ",
|
||||
O_IOA => open,
|
||||
O_IOA_OE_L => open,
|
||||
-- port b
|
||||
I_IOB => "ZZZZZZZZ",
|
||||
O_IOB => open,
|
||||
O_IOB_OE_L => open,
|
||||
--
|
||||
ENA => '1',
|
||||
RESET_L => autores,--swres and pllLocked,
|
||||
CLK => cpuClk
|
||||
);
|
||||
sndBDIR <= '1' when cpua(7 downto 1)="0001111" and iow='0' else '0';
|
||||
sndBC1 <= cpua(0);
|
||||
|
||||
-- Delta-Sigma DAC for audio (one channel, mono in this implementation)
|
||||
audiodac : entity work.dac
|
||||
port map (
|
||||
clk_i => clk7m,
|
||||
res_n_i => swres and pllLocked,
|
||||
dac_i => audiomix(8 downto 1), --oaudio,
|
||||
dac_o => dacout
|
||||
);
|
||||
|
||||
with tapebits select speaker <=
|
||||
"00100000" when "001",
|
||||
"00010000" when "000"|"011",
|
||||
"00000000" when others;
|
||||
|
||||
audiomix <= ('0' & oaudio) + ('0' & speaker);
|
||||
|
||||
AUDIO_L <= dacout;
|
||||
AUDIO_R <= dacout;
|
||||
|
||||
-- fix palette for now
|
||||
--with rgbi select rgb <=
|
||||
with rgbi select ht_rgb <=
|
||||
"000000000000000000" when "0000",
|
||||
"000000000000100000" when "0001",
|
||||
"000000100000000000" when "0010",
|
||||
"000000100000100000" when "0011",
|
||||
"100000000000000000" when "0100",
|
||||
"100000000000100000" when "0101",
|
||||
"110000011000000000" when "0110",
|
||||
"100000100000100000" when "0111",
|
||||
"110000110000110000" when "1000",
|
||||
"000000000000111100" when "1001",
|
||||
"000000111100000000" when "1010",
|
||||
"000000111100111100" when "1011",
|
||||
"111110000000000000" when "1100",
|
||||
"111100000000111100" when "1101",
|
||||
"111110111110000000" when "1110",
|
||||
"111110111110111110" when others;
|
||||
|
||||
scanlines <= status(1) and vga and oddline;
|
||||
|
||||
userio: user_io
|
||||
generic map (STRLEN => CONF_STR'length)
|
||||
port map (
|
||||
|
||||
conf_str => to_slv(CONF_STR),
|
||||
|
||||
SPI_CLK => SPI_SCK ,
|
||||
SPI_SS_IO => CONF_DATA0 ,
|
||||
SPI_MISO => SPI_DO ,
|
||||
SPI_MOSI => SPI_DI ,
|
||||
|
||||
status => status ,
|
||||
|
||||
-- ps2 interface
|
||||
ps2_clk => ps2clkout,
|
||||
ps2_kbd_clk => ps2CLK,
|
||||
ps2_kbd_data => ps2DAT,
|
||||
ps2_mouse_clk => mps2CLK,
|
||||
ps2_mouse_data => mps2DAT,
|
||||
|
||||
joystick_0 => joy0,
|
||||
joystick_1 => joy1,
|
||||
|
||||
scandoubler_disable => pvsel
|
||||
);
|
||||
|
||||
osd_d : osd
|
||||
generic map (OSD_COLOR => 6)
|
||||
port map (
|
||||
pclk => pclk,
|
||||
sck => SPI_SCK,
|
||||
ss => SPI_SS3,
|
||||
sdi => SPI_DI,
|
||||
|
||||
red_in => ht_rgb(5 downto 0),
|
||||
green_in => ht_rgb(11 downto 6),
|
||||
blue_in => ht_rgb(17 downto 12),
|
||||
hs_in => hs,
|
||||
vs_in => vs,
|
||||
|
||||
red_out => out_RGB(17 downto 12),
|
||||
green_out => out_RGB(11 downto 6),
|
||||
blue_out => out_RGB(5 downto 0),
|
||||
hs_out => open, --HSYNC,
|
||||
vs_out => open --VSYNC
|
||||
);
|
||||
|
||||
VGA_R <= out_RGB(17 downto 12) when scanlines='0' else "0" & out_RGB(17 downto 13);
|
||||
VGA_G <= out_RGB(11 downto 6) when scanlines='0' else "0" & out_RGB(11 downto 7);
|
||||
VGA_B <= out_RGB( 5 downto 0) when scanlines='0' else "0" & out_RGB( 5 downto 1);
|
||||
|
||||
sdram_inst : sdram
|
||||
port map( sd_data => SDRAM_DQ,
|
||||
sd_addr => SDRAM_A,
|
||||
sd_dqm => sdram_dqm,
|
||||
sd_cs => SDRAM_nCS,
|
||||
sd_ba => SDRAM_BA,
|
||||
sd_we => SDRAM_nWE,
|
||||
sd_ras => SDRAM_nRAS,
|
||||
sd_cas => SDRAM_nCAS,
|
||||
clk => clk56m,
|
||||
clkref => clk_download, --cpuClk,
|
||||
init => not pllLocked,
|
||||
din => ram_din,
|
||||
addr => ram_addr,
|
||||
we => ram_we,
|
||||
oe => ram_oe,
|
||||
dout => ram_dout
|
||||
);
|
||||
--ram_addr <= "000000000" & cpua when dn_go='0' else dn_addr_r;
|
||||
ram_din <= cpudo when dn_go='0' else dn_data_r;
|
||||
ram_we <= ((not memw) and (cpua(15) or cpua(14))) when dn_go='0' else dn_wr_r;
|
||||
--ram_oe <= not memr when dn_go='0' else '0';
|
||||
|
||||
ram_addr <= "0" & io_ram_addr when iorrd='1' else "000000000" & cpua when dn_go='0' else dn_addr_r;
|
||||
ram_oe <= '1' when iorrd='1' else not memr when dn_go='0' else '0';
|
||||
|
||||
-- sdram interface
|
||||
SDRAM_CKE <= '1';
|
||||
SDRAM_DQMH <= sdram_dqm(1);
|
||||
SDRAM_DQML <= sdram_dqm(0);
|
||||
|
||||
|
||||
dataio : data_io
|
||||
port map (
|
||||
sck => SPI_SCK,
|
||||
ss => SPI_SS2,
|
||||
sdi => SPI_DI,
|
||||
|
||||
downloading => dn_go,
|
||||
--size => ioctl_size,
|
||||
index => dn_idx,
|
||||
|
||||
-- ram interface
|
||||
clk => clk_download, -- ???
|
||||
wr => dn_wr,
|
||||
addr => dn_addr,
|
||||
data => dn_data
|
||||
);
|
||||
|
||||
process(clk_download)
|
||||
begin
|
||||
if rising_edge(clk_download) then
|
||||
if dn_wr='1' then
|
||||
dn_wr_r <= '1';
|
||||
dn_data_r <= dn_data;
|
||||
dn_addr_r <= dn_addr;
|
||||
else
|
||||
dn_wr_r <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (cpuClk)
|
||||
begin
|
||||
if rising_edge(cpuClk) then
|
||||
if pllLocked='0' or status(0)='1' or status(2)='1' then
|
||||
res_cnt <= "000000";
|
||||
else
|
||||
if (res_cnt/="111111") then
|
||||
res_cnt <= res_cnt+1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
cpuClkEn <= not dn_go;
|
||||
autores <= '1' when res_cnt="111111" else '0';
|
||||
|
||||
|
||||
process (cpuClk,dn_go,autores)
|
||||
begin
|
||||
if dn_go='1' or autores='0' then
|
||||
io_ram_addr <= x"010000"; -- above 64k
|
||||
iorrd_r<='0';
|
||||
else
|
||||
if rising_edge(cpuClk) then
|
||||
if iow='0' and cpua(7 downto 0)=x"ff" then
|
||||
tapebits <= cpudo(2 downto 0);
|
||||
end if;
|
||||
if iow='0' and cpua(7 downto 2)="000001" then -- out 4 5 6
|
||||
case cpua(1 downto 0) is
|
||||
when "00"=> io_ram_addr(7 downto 0) <= cpudo;
|
||||
when "01"=> io_ram_addr(15 downto 8) <= cpudo;
|
||||
when "10"=> io_ram_addr(23 downto 16) <= cpudo;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
iorrd_r<=iorrd;
|
||||
if iorrd='0' and iorrd_r='1' then
|
||||
io_ram_addr <= io_ram_addr + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,182 +0,0 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd (
|
||||
// OSDs pixel clock, should be synchronous to cores pixel clock to
|
||||
// avoid jitter.
|
||||
input pclk,
|
||||
|
||||
// SPI interface
|
||||
input sck,
|
||||
input ss,
|
||||
input sdi,
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] red_in,
|
||||
input [5:0] green_in,
|
||||
input [5:0] blue_in,
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] red_out,
|
||||
output [5:0] green_out,
|
||||
output [5:0] blue_out,
|
||||
output hs_out,
|
||||
output vs_out
|
||||
);
|
||||
|
||||
parameter OSD_X_OFFSET = 10'd0;
|
||||
parameter OSD_Y_OFFSET = 10'd0;
|
||||
parameter OSD_COLOR = 3'd0;
|
||||
|
||||
localparam OSD_WIDTH = 10'd256;
|
||||
localparam OSD_HEIGHT = 10'd128;
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg [7:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg [10:0] bcnt;
|
||||
reg osd_enable;
|
||||
|
||||
reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself
|
||||
|
||||
// the OSD has its own SPI interface to the io controller
|
||||
always@(posedge sck, posedge ss) begin
|
||||
if(ss == 1'b1) begin
|
||||
cnt <= 5'd0;
|
||||
bcnt <= 11'd0;
|
||||
end else begin
|
||||
sbuf <= { sbuf[6:0], sdi};
|
||||
|
||||
// 0:7 is command, rest payload
|
||||
if(cnt < 15)
|
||||
cnt <= cnt + 4'd1;
|
||||
else
|
||||
cnt <= 4'd8;
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], sdi};
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= { sbuf[1:0], sdi, 8'h00};
|
||||
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(sbuf[6:3] == 4'b0100)
|
||||
osd_enable <= sdi;
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
|
||||
osd_buffer[bcnt] <= {sbuf[6:0], sdi};
|
||||
bcnt <= bcnt + 11'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// *********************************************************************************
|
||||
// video timing and sync polarity anaylsis
|
||||
// *********************************************************************************
|
||||
|
||||
// horizontal counter
|
||||
reg [9:0] h_cnt;
|
||||
reg hsD, hsD2;
|
||||
reg [9:0] hs_low, hs_high;
|
||||
wire hs_pol = hs_high < hs_low;
|
||||
wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
|
||||
wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
|
||||
|
||||
always @(posedge pclk) begin
|
||||
// bring hsync into local clock domain
|
||||
hsD <= hs_in;
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of hs_in
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 10'd0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of hs_in
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 10'd0;
|
||||
hs_low <= h_cnt;
|
||||
end
|
||||
|
||||
else
|
||||
h_cnt <= h_cnt + 10'd1;
|
||||
end
|
||||
|
||||
// vertical counter
|
||||
reg [9:0] v_cnt;
|
||||
reg vsD, vsD2;
|
||||
reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
|
||||
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
|
||||
|
||||
always @(posedge hs_in) begin
|
||||
// bring vsync into local clock domain
|
||||
vsD <= vs_in;
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of vs_in
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 10'd0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of vs_in
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 10'd0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
|
||||
else
|
||||
v_cnt <= v_cnt + 10'd1;
|
||||
end
|
||||
|
||||
// area in which OSD is being displayed
|
||||
wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
|
||||
wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
|
||||
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
|
||||
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
|
||||
|
||||
reg h_osd_active, v_osd_active;
|
||||
always @(posedge pclk) begin
|
||||
if(hs_in != hs_pol) begin
|
||||
if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
|
||||
if(h_cnt == h_osd_end) h_osd_active <= 1'b0;
|
||||
end
|
||||
if(vs_in != vs_pol) begin
|
||||
if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
|
||||
if(v_cnt == v_osd_end) v_osd_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
wire osd_de = osd_enable && h_osd_active && v_osd_active;
|
||||
|
||||
wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
|
||||
wire [6:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
|
||||
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
|
||||
|
||||
reg [7:0] osd_byte;
|
||||
always @(posedge pclk)
|
||||
osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
|
||||
|
||||
wire [2:0] osd_color = OSD_COLOR;
|
||||
assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] };
|
||||
assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
|
||||
assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
|
||||
|
||||
assign hs_out = hs_in;
|
||||
assign vs_out = vs_in;
|
||||
|
||||
endmodule
|
||||
@@ -1,424 +0,0 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: pll.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY pll IS
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END pll;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF pll IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
self_reset_on_loss_lock : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire7_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
|
||||
sub_wire4 <= sub_wire0(2);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
locked <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
c2 <= sub_wire4;
|
||||
sub_wire5 <= inclk0;
|
||||
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 27,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 56,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 27,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 56,
|
||||
clk1_phase_shift => "-2000",
|
||||
clk2_divide_by => 9,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 14,
|
||||
clk2_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 37037,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "CBX_MODULE_PREFIX=pll",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_UNUSED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_USED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_UNUSED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
self_reset_on_loss_lock => "OFF",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
inclk => sub_wire6,
|
||||
clk => sub_wire0,
|
||||
locked => sub_wire2
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "56.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "56.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "42.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "56.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "56.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "42.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "56"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2000"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "14"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -1,312 +0,0 @@
|
||||
--
|
||||
-- HT 1080Z (TSR-80 clone) ps2 keyboard
|
||||
--
|
||||
--
|
||||
-- Copyright (c) 2016-2017 Jozsef Laszlo (rbendr@gmail.com)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
|
||||
entity ps2kbd is
|
||||
Port (
|
||||
RESET : in STD_LOGIC;
|
||||
KBCLK : in STD_LOGIC;
|
||||
KBDAT : in STD_LOGIC;
|
||||
SWRES : out STD_LOGIC;
|
||||
CLK : in STD_LOGIC;
|
||||
A : in STD_LOGIC_VECTOR(7 downto 0);
|
||||
DOUT : out STD_LOGIC_VECTOR(7 downto 0);
|
||||
PAGE : out STD_LOGIC;
|
||||
VCUT : out STD_LOGIC;
|
||||
INKP : out STD_LOGIC;
|
||||
PAPERP : out STD_LOGIC;
|
||||
BORDERP : out STD_LOGIC
|
||||
);
|
||||
|
||||
end ps2kbd;
|
||||
|
||||
architecture Behavioral of ps2kbd is
|
||||
|
||||
type keys is array(0 to 7) of std_logic_vector(7 downto 0);
|
||||
|
||||
signal keypress : std_logic:='0';
|
||||
signal extkey : std_logic:='0';
|
||||
|
||||
signal hasRead : std_logic;
|
||||
|
||||
signal keybits : keys;
|
||||
signal keysout : keys;
|
||||
signal lastkc : std_logic;
|
||||
|
||||
signal kbdsign : std_logic;
|
||||
signal kbddata : std_logic_vector(7 downto 0);
|
||||
signal swreset : std_logic := '1';
|
||||
|
||||
signal pageReg : std_logic := '0';
|
||||
signal vcutReg : std_logic := '0';
|
||||
|
||||
signal inkpulse, paperpulse, borderpulse : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
ps2rd : entity work.ps2reader
|
||||
port map (
|
||||
mclk => CLK,
|
||||
PS2C => KBCLK,
|
||||
PS2D => KBDAT,
|
||||
rst => RESET,
|
||||
Ps2Dout => kbddata,
|
||||
fRd => kbdsign
|
||||
);
|
||||
|
||||
process(RESET,kbdsign,kbddata)
|
||||
variable kk : std_logic_vector(6 downto 0);
|
||||
variable ix : integer;
|
||||
begin
|
||||
if RESET='1' then
|
||||
keypress <= '0';
|
||||
keybits(0) <= "00000000";
|
||||
keybits(1) <= "00000000";
|
||||
keybits(2) <= "00000000";
|
||||
keybits(3) <= "00000000";
|
||||
keybits(4) <= "00000000";
|
||||
keybits(5) <= "00000000";
|
||||
keybits(6) <= "00000000";
|
||||
keybits(7) <= "00000000";
|
||||
|
||||
swreset <= '1';
|
||||
pageReg <= '0';
|
||||
vcutReg <= '0';
|
||||
else
|
||||
if rising_edge(kbdsign) then
|
||||
if kbddata=x"F0" then
|
||||
keypress <= '0'; -- released
|
||||
--if shifrpress='1' then
|
||||
-- keybits(7)(0)<='0';
|
||||
-- shifrpress<='0';
|
||||
--end if;
|
||||
elsif kbddata=x"E0" then
|
||||
extkey<='1';
|
||||
else
|
||||
keypress <= '1'; -- pressed
|
||||
|
||||
-- this is for ps2 read. we convert 0x83 to 0x02 (keyboard F2)
|
||||
kk:= kbddata(6 downto 0);
|
||||
if kbddata=x"83" then
|
||||
kk:="0000010"; -- keyboard F7 code 0x83 converted to 0x02
|
||||
end if;
|
||||
|
||||
|
||||
|
||||
case '0' & kk is
|
||||
|
||||
when x"03" => inkpulse <= keypress; -- F1
|
||||
when x"0b" => paperpulse <= keypress; -- F2
|
||||
when x"02" => borderpulse <= keypress; -- F3
|
||||
|
||||
when x"78"=> swreset <= not keypress; -- F11
|
||||
|
||||
when x"01"=> --F9
|
||||
if keypress='1' then
|
||||
vcutReg <= not vcutReg;
|
||||
end if;
|
||||
|
||||
when x"09"=> --F10
|
||||
if keypress='1' then
|
||||
pageReg <= not pageReg;
|
||||
end if;
|
||||
|
||||
-- \|
|
||||
when x"5d"=> keybits(0)(0)<=keypress;
|
||||
-- A
|
||||
when x"1c"=> keybits(0)(1)<=keypress;
|
||||
-- B
|
||||
when x"32"=> keybits(0)(2)<=keypress;
|
||||
-- C
|
||||
when x"21"=> keybits(0)(3)<=keypress;
|
||||
-- D
|
||||
when x"23"=> keybits(0)(4)<=keypress;
|
||||
-- E
|
||||
when x"24"=> keybits(0)(5)<=keypress;
|
||||
-- F
|
||||
when x"2b"=> keybits(0)(6)<=keypress;
|
||||
-- G
|
||||
when x"34"=> keybits(0)(7)<=keypress;
|
||||
|
||||
-- H
|
||||
when x"33"=> keybits(1)(0)<=keypress;
|
||||
-- I
|
||||
when x"43"=> keybits(1)(1)<=keypress;
|
||||
-- J
|
||||
when x"3B"=> keybits(1)(2)<=keypress;
|
||||
-- K
|
||||
when x"42"=> keybits(1)(3)<=keypress;
|
||||
-- L
|
||||
when x"4B"=> keybits(1)(4)<=keypress;
|
||||
-- M
|
||||
when x"3A"=> keybits(1)(5)<=keypress;
|
||||
-- N
|
||||
when x"31"=> keybits(1)(6)<=keypress;
|
||||
-- O
|
||||
when x"44"=> keybits(1)(7)<=keypress;
|
||||
|
||||
-- P
|
||||
when x"4D"=> keybits(2)(0)<=keypress;
|
||||
-- Q
|
||||
when x"15"=> keybits(2)(1)<=keypress;
|
||||
-- R
|
||||
when x"2D"=> keybits(2)(2)<=keypress;
|
||||
-- S
|
||||
when x"1B"=> keybits(2)(3)<=keypress;
|
||||
-- T
|
||||
when x"2C"=> keybits(2)(4)<=keypress;
|
||||
-- U
|
||||
when x"3C"=> keybits(2)(5)<=keypress;
|
||||
-- V
|
||||
when x"2A"=> keybits(2)(6)<=keypress;
|
||||
-- W
|
||||
when x"1D"=> keybits(2)(7)<=keypress;
|
||||
|
||||
-- X
|
||||
when x"22"=> keybits(3)(0)<=keypress;
|
||||
-- Y
|
||||
when x"35"=> keybits(3)(1)<=keypress;
|
||||
-- Z
|
||||
when x"1A"=> keybits(3)(2)<=keypress;
|
||||
-- F2
|
||||
when x"06"=> keybits(3)(4)<=keypress;
|
||||
-- F3
|
||||
when x"04"=> keybits(3)(5)<=keypress;
|
||||
-- F4
|
||||
when x"0C"=> keybits(3)(6)<=keypress;
|
||||
-- F1
|
||||
when x"05"=> keybits(3)(7)<=keypress;
|
||||
|
||||
-- 0
|
||||
when x"45"=> keybits(4)(0)<=keypress;
|
||||
-- 1
|
||||
when x"16"=> keybits(4)(1)<=keypress;
|
||||
-- 2
|
||||
when x"1E"=> keybits(4)(2)<=keypress;
|
||||
-- 3
|
||||
when x"26"=> keybits(4)(3)<=keypress;
|
||||
-- 4
|
||||
when x"25"=> keybits(4)(4)<=keypress;
|
||||
-- 5
|
||||
when x"2E"=> keybits(4)(5)<=keypress;
|
||||
-- 6
|
||||
when x"36"=> keybits(4)(6)<=keypress;
|
||||
-- 7
|
||||
when x"3D"=> keybits(4)(7)<=keypress;
|
||||
|
||||
-- 8
|
||||
when x"3E"=> keybits(5)(0)<=keypress;
|
||||
-- 9
|
||||
when x"46"=> keybits(5)(1)<=keypress;
|
||||
-- *:
|
||||
when x"0E"|x"4e" => keybits(5)(2)<=keypress;
|
||||
-- +;
|
||||
when x"4C"=> keybits(5)(3)<=keypress;
|
||||
-- <,
|
||||
when x"41"=> keybits(5)(4)<=keypress;
|
||||
-- =-
|
||||
when x"55"|x"7b"=> keybits(5)(5)<=keypress;
|
||||
-- >.
|
||||
when x"49"=> keybits(5)(6)<=keypress;
|
||||
-- ?/
|
||||
when x"4A"=> keybits(5)(7)<=keypress;
|
||||
|
||||
-- NL
|
||||
when x"5A"=> keybits(6)(0)<=keypress;
|
||||
-- CLR
|
||||
when x"6C"=> keybits(6)(1)<=keypress;
|
||||
-- BRK
|
||||
when x"76"=> keybits(6)(2)<=keypress;
|
||||
-- up-arrow
|
||||
when x"75"=> keybits(6)(3)<=keypress;
|
||||
-- dn-arrow
|
||||
when x"72"=> keybits(6)(4)<=keypress;
|
||||
-- lf-arrow and backspace
|
||||
when x"6B"|x"66"=> keybits(6)(5)<=keypress;
|
||||
-- rg-arrow
|
||||
when x"74"=> keybits(6)(6)<=keypress;
|
||||
-- SPA
|
||||
when x"29"=> keybits(6)(7)<=keypress;
|
||||
|
||||
-- L-SHIFT R-SHIFT
|
||||
when x"12"|x"59"=> keybits(7)(0)<=keypress;
|
||||
|
||||
-- numpad *
|
||||
when x"7c"=> keybits(5)(2)<=keypress;
|
||||
keybits(7)(0)<=keypress;
|
||||
-- numpad +
|
||||
when x"79"=> keybits(5)(3)<=keypress;
|
||||
keybits(7)(0)<=keypress;
|
||||
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
extkey<='0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
SWRES <= swreset;
|
||||
VCUT <= vcutReg;
|
||||
PAGE <= pageReg;
|
||||
|
||||
keysout(0) <= keybits(0) when A(0)='1' else x"00";
|
||||
keysout(1) <= keybits(1) when A(1)='1' else x"00";
|
||||
keysout(2) <= keybits(2) when A(2)='1' else x"00";
|
||||
keysout(3) <= keybits(3) when A(3)='1' else x"00";
|
||||
keysout(4) <= keybits(4) when A(4)='1' else x"00";
|
||||
keysout(5) <= keybits(5) when A(5)='1' else x"00";
|
||||
keysout(6) <= keybits(6) when A(6)='1' else x"00";
|
||||
keysout(7) <= keybits(7) when A(7)='1' else x"00";
|
||||
DOUT <= keysout(0) or keysout(1) or keysout(2) or keysout(3) or keysout(4) or keysout(5) or keysout(6) or keysout(7);
|
||||
|
||||
INKP <= inkpulse;
|
||||
PAPERP <= paperpulse;
|
||||
BORDERP <= borderpulse;
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,198 +0,0 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company: Digilent Inc.
|
||||
-- Engineer: Claudia Goga
|
||||
--
|
||||
-- Create Date: 22:33:35 11/25/06
|
||||
-- Module Name: PS2_Reader - Behavioral
|
||||
-- Target Devices: CoolRunner2 CPLD
|
||||
-- Tool versions: Xilinx ISE v7.1i
|
||||
-- Description:
|
||||
-- This module reads scan codes from the PS2 Port. Every time a
|
||||
-- new scan code is entirely received it enables the fRd signal for one
|
||||
-- main clock period.
|
||||
--
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
|
||||
entity ps2reader is
|
||||
Port ( mclk : in std_logic; -- System Clock
|
||||
PS2C : in std_logic; -- PS2 Clock
|
||||
PS2D : in std_logic; -- PS2 data
|
||||
rst: in std_logic; -- Reset BTN0
|
||||
Ps2Dout : out std_logic_vector(7 downto 0); -- out data
|
||||
fRd : out std_logic); -- data valid flag
|
||||
end ps2reader;
|
||||
|
||||
architecture Behavioral of ps2reader is
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- SIGNAL and CONSTANT DECLARATIONS
|
||||
------------------------------------------------------------------------
|
||||
--The constants below define state codes for the PS2 Keyboard
|
||||
--reader using ONE HOT encoding.
|
||||
|
||||
constant idle: std_logic_vector (5 downto 0):="000000";
|
||||
constant shift_data: std_logic_vector (5 downto 0):="000001";
|
||||
constant check_parity: std_logic_vector (5 downto 0):="000010";
|
||||
constant check_stopbit:std_logic_vector (5 downto 0):="000100";
|
||||
constant frame_error: std_logic_vector (5 downto 0):="001000";
|
||||
constant parity_error: std_logic_vector (5 downto 0):="010000";
|
||||
constant end_char: std_logic_vector (5 downto 0):="100000";
|
||||
|
||||
--state register and next state register for the FSM
|
||||
signal state, next_state: std_logic_vector (5 downto 0):=idle;
|
||||
|
||||
signal D_PS2C: std_logic:='0'; -- debounced PS2C
|
||||
signal Q1, Q2: std_logic:='0';
|
||||
|
||||
--shift register; stores the received bits
|
||||
signal REG: std_logic_vector(7 downto 0):=X"00";
|
||||
|
||||
signal ptysum: std_logic:='0'; -- parity sum
|
||||
signal ptycheck: std_logic:='0'; -- parity check bit
|
||||
|
||||
signal cnt: integer range 0 to 7:=0; -- counter
|
||||
|
||||
--The attributes below prevent the ISE compiler from
|
||||
--optimizing the state machines. The states will be implemented as
|
||||
--described in the constant declarations above.
|
||||
|
||||
attribute fsm_extract : string;
|
||||
attribute fsm_extract of state: signal is "no";
|
||||
attribute fsm_extract of next_state: signal is "no";
|
||||
|
||||
attribute fsm_encoding : string;
|
||||
attribute fsm_encoding of state: signal is "user";
|
||||
attribute fsm_encoding of next_state: signal is "user";
|
||||
|
||||
attribute signal_encoding : string;
|
||||
attribute signal_encoding of state: signal is "user";
|
||||
attribute signal_encoding of next_state: signal is "user";
|
||||
|
||||
begin
|
||||
|
||||
----------------------------------------------------------------------
|
||||
-- MODULE IMPLEMENTATION
|
||||
----------------------------------------------------------------------
|
||||
|
||||
----------------- Sample Keyboard Inputs -----------------------------
|
||||
|
||||
debounce: process (mclk, PS2C, Q1, Q2)
|
||||
begin
|
||||
if mclk'event and mclk='1' then
|
||||
Q1<=PS2C;
|
||||
Q2<=Q1;
|
||||
end if;
|
||||
end process debounce;
|
||||
|
||||
D_PS2C<= (NOT Q1) and Q2;
|
||||
|
||||
----------------- Synchronization Process ----------------------------
|
||||
|
||||
regstate: process (mclk, next_state, rst)
|
||||
begin
|
||||
if rst='1' then
|
||||
state<=idle; -- state machine reset
|
||||
elsif mclk'EVENT and mclk='1' then
|
||||
state<=next_state;
|
||||
end if;
|
||||
end process regstate;
|
||||
|
||||
-------------------- State Transitions -------------------------------
|
||||
|
||||
transition: process (state, D_PS2C, PS2D, cnt, ptycheck)
|
||||
begin
|
||||
case state is
|
||||
when idle=>-- idle
|
||||
if D_PS2C='1' and PS2D='0' then -- check start bit
|
||||
next_state<=shift_data;
|
||||
else
|
||||
next_state<=idle;
|
||||
end if;
|
||||
|
||||
when shift_data=> -- shift in data
|
||||
if D_PS2C='1' and cnt=7 then
|
||||
next_state<=check_parity; -- go and check parity
|
||||
else
|
||||
next_state<=shift_data;
|
||||
end if;
|
||||
|
||||
when check_parity=> -- check parity
|
||||
if D_PS2C='1' and PS2D=ptycheck then
|
||||
next_state<=check_stopbit; -- valid parity bit
|
||||
-- go and check stopbit
|
||||
elsif D_PS2C='1' then
|
||||
next_state<=parity_error; -- parity error
|
||||
else
|
||||
next_state<=check_parity;
|
||||
end if;
|
||||
|
||||
when check_stopbit=> -- check stopbit;
|
||||
if D_PS2C='1' and PS2D='1' then
|
||||
next_state<=end_char; -- valid stopbit, end Char
|
||||
elsif D_PS2C='1' then
|
||||
next_state<=frame_error; -- Frame Error
|
||||
else
|
||||
next_state<=check_stopbit;
|
||||
end if;
|
||||
|
||||
when frame_error=> -- Frame Error
|
||||
next_state<=idle;
|
||||
|
||||
when parity_error=> -- Parity Error
|
||||
next_state<=idle;
|
||||
|
||||
when end_char=> -- end Char
|
||||
next_state<=idle;
|
||||
|
||||
when others => next_state<=idle;
|
||||
end case;
|
||||
end process transition;
|
||||
|
||||
|
||||
------Counting bits and registering when state=shift_data---------------
|
||||
|
||||
regin: process (mclk, D_PS2C, PS2D, cnt, ptysum, state)
|
||||
begin
|
||||
if state/=shift_data then
|
||||
cnt<=0;
|
||||
ptysum<='0';
|
||||
elsif mclk'EVENT and mclk='1' then
|
||||
if D_PS2C='1' then
|
||||
ptysum<=ptysum XOR PS2D; -- calculating the parity sum
|
||||
REG(7 downto 0)<=PS2D®(7 downto 1); -- shifting data into register
|
||||
|
||||
if cnt=7 then
|
||||
cnt<=0;
|
||||
else
|
||||
cnt<=cnt+1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process regin;
|
||||
|
||||
------------------PARITIY SUM-------------------------------------------
|
||||
|
||||
parity_sum: process (mclk, D_PS2C, PS2D, cnt, state, ptysum)
|
||||
begin
|
||||
if mclk'EVENT and mclk='1' then
|
||||
if state=shift_data and D_PS2C='1' and cnt=7 then
|
||||
ptycheck<=(NOT ptysum) XOR PS2D; --parity check bit
|
||||
end if;
|
||||
end if;
|
||||
end process parity_sum;
|
||||
|
||||
----------------OUTPUT ASSIGNEMENT--------------------------------------
|
||||
|
||||
Ps2Dout<=REG;
|
||||
fRd<='1' when state=end_char else '0';
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,34 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity ram16k is
|
||||
Port ( clk : in STD_LOGIC;
|
||||
a : in STD_LOGIC_VECTOR (13 downto 0);
|
||||
din : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
dout : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
wr : in STD_LOGIC);
|
||||
end ram16k;
|
||||
|
||||
architecture Behavioral of ram16k is
|
||||
|
||||
type
|
||||
ramarray is array(0 to 16383) of std_logic_vector(7 downto 0);
|
||||
|
||||
signal
|
||||
mem : ramarray;
|
||||
begin
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dout <= mem(conv_integer(a));
|
||||
if wr='0' then
|
||||
mem(conv_integer(a)) <= din;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,147 +0,0 @@
|
||||
//
|
||||
// scandoubler.v
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
module scandoubler (
|
||||
// system interface
|
||||
input clk_in,
|
||||
input clk_out,
|
||||
|
||||
input scanlines,
|
||||
|
||||
// shifter video interface
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input [5:0] r_in,
|
||||
input [5:0] g_in,
|
||||
input [5:0] b_in,
|
||||
|
||||
// output interface
|
||||
output reg [5:0] r_out,
|
||||
output reg [5:0] g_out,
|
||||
output reg [5:0] b_out,
|
||||
output reg vs_out,
|
||||
output reg hs_out
|
||||
);
|
||||
|
||||
// scan doubler output register
|
||||
reg [17:0] sd_out;
|
||||
|
||||
// --------------------- create output signals -----------------
|
||||
// latch everything once more to make it glitch free and apply scanline effect
|
||||
reg scanline;
|
||||
|
||||
always @(posedge clk_out) begin
|
||||
vs_out <= vs_in;
|
||||
hs_out <= hs_sd;
|
||||
|
||||
// reset scanlines at every new screen
|
||||
if(vs_out != vs_in)
|
||||
scanline <= 1'b0;
|
||||
|
||||
// toggle scanlines at begin of every hsync
|
||||
if(hs_out && !hs_sd)
|
||||
scanline <= !scanline;
|
||||
|
||||
// if no scanlines or not a scanline
|
||||
if(!scanlines || !scanline) begin
|
||||
r_out <= { sd_out[17:12] };
|
||||
g_out <= { sd_out[11:6] };
|
||||
b_out <= { sd_out[5:0] };
|
||||
end else begin
|
||||
r_out <= { 1'b0, sd_out[17:13] };
|
||||
g_out <= { 1'b0, sd_out[11:7] };
|
||||
b_out <= { 1'b0, sd_out[5:1] };
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
// ==================================================================
|
||||
// ======================== the line buffers ========================
|
||||
// ==================================================================
|
||||
|
||||
// 2 lines of 1024 pixels 3*6 bit RGB
|
||||
reg [17:0] sd_buffer [2047:0];
|
||||
|
||||
// use alternating sd_buffers when storing/reading data
|
||||
reg vsD;
|
||||
reg line_toggle;
|
||||
always @(negedge clk_in) begin
|
||||
vsD <= vs_in;
|
||||
|
||||
if(vsD != vs_in)
|
||||
line_toggle <= 1'b0;
|
||||
|
||||
// begin of incoming hsync
|
||||
if(hsD && !hs_in)
|
||||
line_toggle <= !line_toggle;
|
||||
end
|
||||
|
||||
always @(negedge clk_in) begin
|
||||
sd_buffer[{line_toggle, hcnt}] <= { r_in, g_in, b_in };
|
||||
end
|
||||
|
||||
// ==================================================================
|
||||
// =================== horizontal timing analysis ===================
|
||||
// ==================================================================
|
||||
|
||||
// total hsync time (in 16MHz cycles), hs_total reaches 1024
|
||||
reg [9:0] hs_max;
|
||||
reg [9:0] hs_rise;
|
||||
reg [9:0] hcnt;
|
||||
reg hsD;
|
||||
|
||||
always @(negedge clk_in) begin
|
||||
hsD <= hs_in;
|
||||
|
||||
// falling edge of hsync indicates start of line
|
||||
if(hsD && !hs_in) begin
|
||||
hs_max <= hcnt;
|
||||
hcnt <= 10'd0;
|
||||
end else
|
||||
hcnt <= hcnt + 10'd1;
|
||||
|
||||
// save position of rising edge
|
||||
if(!hsD && hs_in)
|
||||
hs_rise <= hcnt;
|
||||
end
|
||||
|
||||
// ==================================================================
|
||||
// ==================== output timing generation ====================
|
||||
// ==================================================================
|
||||
|
||||
reg [9:0] sd_hcnt;
|
||||
reg hs_sd;
|
||||
|
||||
// timing generation runs 32 MHz (twice the input signal analysis speed)
|
||||
always @(posedge clk_out) begin
|
||||
|
||||
// output counter synchronous to input and at twice the rate
|
||||
sd_hcnt <= sd_hcnt + 10'd1;
|
||||
if(hsD && !hs_in) sd_hcnt <= hs_max;
|
||||
if(sd_hcnt == hs_max) sd_hcnt <= 10'd0;
|
||||
|
||||
// replicate horizontal sync at twice the speed
|
||||
if(sd_hcnt == hs_max) hs_sd <= 1'b0;
|
||||
if(sd_hcnt == hs_rise) hs_sd <= 1'b1;
|
||||
|
||||
// read data from line sd_buffer
|
||||
sd_out <= sd_buffer[{~line_toggle, sd_hcnt}];
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,147 +0,0 @@
|
||||
//
|
||||
// sdram.v
|
||||
//
|
||||
// sdram controller implementation for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
module sdram (
|
||||
|
||||
// interface to the MT48LC16M16 chip
|
||||
inout [15:0] sd_data, // 16 bit bidirectional data bus
|
||||
output [12:0] sd_addr, // 13 bit multiplexed address bus
|
||||
output [1:0] sd_dqm, // two byte masks
|
||||
output [1:0] sd_ba, // two banks
|
||||
output sd_cs, // a single chip select
|
||||
output sd_we, // write enable
|
||||
output sd_ras, // row address select
|
||||
output sd_cas, // columns address select
|
||||
|
||||
// cpu/chipset interface
|
||||
input init, // init signal after FPGA config to initialize RAM
|
||||
input clk, // sdram is accessed at up to 128MHz
|
||||
input clkref, // reference clock to sync to
|
||||
|
||||
input [7:0] din, // data input from chipset/cpu
|
||||
output [7:0] dout, // data output to chipset/cpu
|
||||
input [24:0] addr, // 25 bit byte address
|
||||
input oe, // cpu/chipset requests read
|
||||
input we // cpu/chipset requests write
|
||||
);
|
||||
|
||||
// no burst configured
|
||||
localparam RASCAS_DELAY = 3'd3; // tRCD>=20ns -> 2 cycles@64MHz
|
||||
localparam BURST_LENGTH = 3'b000; // 000=none, 001=2, 010=4, 011=8
|
||||
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
|
||||
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
|
||||
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
|
||||
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
|
||||
|
||||
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------------ cycle state machine ------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
localparam STATE_IDLE = 3'd0; // first state in cycle
|
||||
localparam STATE_CMD_START = 3'd1; // state in which a new command can be started
|
||||
localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY - 3'd1; // 4 command can be continued
|
||||
localparam STATE_LAST = 3'd7; // last state in cycle
|
||||
|
||||
reg [2:0] q /* synthesis noprune */;
|
||||
always @(posedge clk) begin
|
||||
// 32Mhz counter synchronous to 4 Mhz clock
|
||||
// force counter to pass state 5->6 exactly after the rising edge of clkref
|
||||
// since clkref is two clocks early
|
||||
if(((q == 6) && ( clkref == 0)) ||
|
||||
((q == 7) && ( clkref == 1)) ||
|
||||
((q != 6) && (q != 7)))
|
||||
q <= q + 3'd1;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// --------------------------- startup/reset ---------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// wait 1ms (32 clkref cycles) after FPGA config is done before going
|
||||
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
|
||||
reg [4:0] reset;
|
||||
always @(posedge clk) begin
|
||||
if(init) reset <= 5'h1f;
|
||||
else if((q == STATE_LAST) && (reset != 0))
|
||||
reset <= reset - 5'd1;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------ generate ram control signals ---------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// all possible commands
|
||||
localparam CMD_INHIBIT = 4'b1111;
|
||||
localparam CMD_NOP = 4'b0111;
|
||||
localparam CMD_ACTIVE = 4'b0011;
|
||||
localparam CMD_READ = 4'b0101;
|
||||
localparam CMD_WRITE = 4'b0100;
|
||||
localparam CMD_BURST_TERMINATE = 4'b0110;
|
||||
localparam CMD_PRECHARGE = 4'b0010;
|
||||
localparam CMD_AUTO_REFRESH = 4'b0001;
|
||||
localparam CMD_LOAD_MODE = 4'b0000;
|
||||
|
||||
reg [3:0] sd_cmd; // current command sent to sd ram
|
||||
|
||||
// drive control signals according to current command
|
||||
assign sd_cs = sd_cmd[3];
|
||||
assign sd_ras = sd_cmd[2];
|
||||
assign sd_cas = sd_cmd[1];
|
||||
assign sd_we = sd_cmd[0];
|
||||
|
||||
assign sd_data = we?{din, din}:16'bZZZZZZZZZZZZZZZZ;
|
||||
|
||||
assign dout = sd_data[7:0];
|
||||
|
||||
always @(posedge clk) begin
|
||||
sd_cmd <= CMD_INHIBIT;
|
||||
|
||||
if(reset != 0) begin
|
||||
if(q == STATE_IDLE) begin
|
||||
if(reset == 13) sd_cmd <= CMD_PRECHARGE;
|
||||
if(reset == 2) sd_cmd <= CMD_LOAD_MODE;
|
||||
end
|
||||
end else begin
|
||||
if(q == STATE_IDLE) begin
|
||||
if(we || oe) sd_cmd <= CMD_ACTIVE;
|
||||
else sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end else if(q == STATE_CMD_CONT) begin
|
||||
if(we) sd_cmd <= CMD_WRITE;
|
||||
else if(oe) sd_cmd <= CMD_READ;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [12:0] reset_addr = (reset == 13)?13'b0010000000000:MODE;
|
||||
|
||||
wire [12:0] run_addr =
|
||||
(q == STATE_CMD_START)?addr[20:8]:{ 4'b0010, addr[23], addr[7:0]};
|
||||
|
||||
assign sd_addr = (reset != 0)?reset_addr:run_addr;
|
||||
|
||||
assign sd_ba = addr[22:21];
|
||||
|
||||
assign sd_dqm = 2'b00;
|
||||
|
||||
endmodule
|
||||
@@ -1,416 +0,0 @@
|
||||
//
|
||||
// user_io.v
|
||||
//
|
||||
// user_io for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
|
||||
module user_io #(parameter STRLEN=0) (
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
|
||||
input SPI_CLK,
|
||||
input SPI_SS_IO,
|
||||
output reg SPI_MISO,
|
||||
input SPI_MOSI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
|
||||
output reg [7:0] status,
|
||||
|
||||
// connection to sd card emulation
|
||||
input [31:0] sd_lba,
|
||||
input sd_rd,
|
||||
input sd_wr,
|
||||
output reg sd_ack,
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
|
||||
output reg sd_dout_strobe,
|
||||
input [7:0] sd_din,
|
||||
output reg sd_din_strobe,
|
||||
|
||||
|
||||
// ps2 keyboard emulation
|
||||
input ps2_clk, // 12-16khz provided by core
|
||||
output ps2_kbd_clk,
|
||||
output reg ps2_kbd_data,
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
|
||||
// pal/vga switch
|
||||
output scandoubler_disable,
|
||||
|
||||
// serial com port
|
||||
input [7:0] serial_data,
|
||||
input serial_strobe
|
||||
);
|
||||
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [7:0] byte_cnt; // counts bytes
|
||||
reg [5:0] joystick0;
|
||||
reg [5:0] joystick1;
|
||||
reg [4:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign scandoubler_disable = but_sw[4];
|
||||
assign sd_dout = { sbuf, SPI_MOSI};
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
|
||||
|
||||
// filter spi clock. the 8 bit gate delay is ~2.5ns in total
|
||||
wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
|
||||
wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
|
||||
|
||||
// drive MISO only when transmitting core id
|
||||
always@(negedge spi_sck or posedge SPI_SS_IO) begin
|
||||
if(SPI_SS_IO == 1) begin
|
||||
SPI_MISO <= 1'bZ;
|
||||
end else begin
|
||||
|
||||
// first byte returned is always core type, further bytes are
|
||||
// command dependent
|
||||
if(byte_cnt == 0) begin
|
||||
SPI_MISO <= core_type[~bit_cnt];
|
||||
|
||||
end else begin
|
||||
// reading serial fifo
|
||||
if(cmd == 8'h1b) begin
|
||||
// send alternating flag byte and data
|
||||
if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt];
|
||||
else SPI_MISO <= serial_out_byte[~bit_cnt];
|
||||
end
|
||||
|
||||
// reading config string
|
||||
else if(cmd == 8'h14) begin
|
||||
// returning a byte from string
|
||||
if(byte_cnt < STRLEN + 1)
|
||||
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
|
||||
else
|
||||
SPI_MISO <= 1'b0;
|
||||
end
|
||||
|
||||
// reading sd card status
|
||||
else if(cmd == 8'h16) begin
|
||||
if(byte_cnt == 1)
|
||||
SPI_MISO <= sd_cmd[~bit_cnt];
|
||||
else if((byte_cnt >= 2) && (byte_cnt < 6))
|
||||
SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
|
||||
else
|
||||
SPI_MISO <= 1'b0;
|
||||
end
|
||||
|
||||
// reading sd card write data
|
||||
else if(cmd == 8'h18)
|
||||
SPI_MISO <= sd_din[~bit_cnt];
|
||||
|
||||
else
|
||||
SPI_MISO <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------- PS2 ---------------------
|
||||
|
||||
// 8 byte fifos to store ps2 bytes
|
||||
localparam PS2_FIFO_BITS = 3;
|
||||
|
||||
// keyboard
|
||||
reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_kbd_tx_state;
|
||||
reg [7:0] ps2_kbd_tx_byte;
|
||||
reg ps2_kbd_parity;
|
||||
|
||||
assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_kbd_r_inc;
|
||||
always@(posedge ps2_clk) begin
|
||||
ps2_kbd_r_inc <= 1'b0;
|
||||
|
||||
if(ps2_kbd_r_inc)
|
||||
ps2_kbd_rptr <= ps2_kbd_rptr + 1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_kbd_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
|
||||
ps2_kbd_r_inc <= 1'b1;
|
||||
|
||||
// reset parity
|
||||
ps2_kbd_parity <= 1'b1;
|
||||
|
||||
// start transmitter
|
||||
ps2_kbd_tx_state <= 4'd1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_kbd_data <= 1'b0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
|
||||
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
|
||||
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
|
||||
if(ps2_kbd_tx_byte[0])
|
||||
ps2_kbd_parity <= !ps2_kbd_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_kbd_tx_state == 9)
|
||||
ps2_kbd_data <= ps2_kbd_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_kbd_tx_state == 10)
|
||||
ps2_kbd_data <= 1'b1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_kbd_tx_state < 11)
|
||||
ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
|
||||
else
|
||||
ps2_kbd_tx_state <= 4'd0;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// mouse
|
||||
reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_mouse_tx_state;
|
||||
reg [7:0] ps2_mouse_tx_byte;
|
||||
reg ps2_mouse_parity;
|
||||
|
||||
assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_mouse_r_inc;
|
||||
always@(posedge ps2_clk) begin
|
||||
ps2_mouse_r_inc <= 1'b0;
|
||||
|
||||
if(ps2_mouse_r_inc)
|
||||
ps2_mouse_rptr <= ps2_mouse_rptr + 1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_mouse_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
|
||||
ps2_mouse_r_inc <= 1'b1;
|
||||
|
||||
// reset parity
|
||||
ps2_mouse_parity <= 1'b1;
|
||||
|
||||
// start transmitter
|
||||
ps2_mouse_tx_state <= 4'd1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_mouse_data <= 1'b0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
|
||||
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
|
||||
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
|
||||
if(ps2_mouse_tx_byte[0])
|
||||
ps2_mouse_parity <= !ps2_mouse_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_mouse_tx_state == 9)
|
||||
ps2_mouse_data <= ps2_mouse_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_mouse_tx_state == 10)
|
||||
ps2_mouse_data <= 1'b1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_mouse_tx_state < 11)
|
||||
ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
|
||||
else
|
||||
ps2_mouse_tx_state <= 4'd0;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// fifo to receive serial data from core to be forwarded to io controller
|
||||
|
||||
// 16 byte fifo to store serial bytes
|
||||
localparam SERIAL_OUT_FIFO_BITS = 6;
|
||||
reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
|
||||
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
|
||||
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
|
||||
|
||||
wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
|
||||
wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
|
||||
wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
|
||||
|
||||
// status[0] is reset signal from io controller and is thus used to flush
|
||||
// the fifo
|
||||
always @(posedge serial_strobe or posedge status[0]) begin
|
||||
if(status[0] == 1) begin
|
||||
serial_out_wptr <= 0;
|
||||
end else begin
|
||||
serial_out_fifo[serial_out_wptr] <= serial_data;
|
||||
serial_out_wptr <= serial_out_wptr + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always@(negedge spi_sck or posedge status[0]) begin
|
||||
if(status[0] == 1) begin
|
||||
serial_out_rptr <= 0;
|
||||
end else begin
|
||||
if((byte_cnt != 0) && (cmd == 8'h1b)) begin
|
||||
// read last bit -> advance read pointer
|
||||
if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
|
||||
serial_out_rptr <= serial_out_rptr + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge spi_sck or posedge SPI_SS_IO) begin
|
||||
|
||||
if(SPI_SS_IO == 1) begin
|
||||
bit_cnt <= 3'd0;
|
||||
byte_cnt <= 8'd0;
|
||||
sd_ack <= 1'b0;
|
||||
sd_dout_strobe <= 1'b0;
|
||||
sd_din_strobe <= 1'b0;
|
||||
end else begin
|
||||
sd_dout_strobe <= 1'b0;
|
||||
sd_din_strobe <= 1'b0;
|
||||
|
||||
if(bit_cnt != 7)
|
||||
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
|
||||
|
||||
bit_cnt <= bit_cnt + 3'd1;
|
||||
if((bit_cnt == 7)&&(byte_cnt != 8'd255))
|
||||
byte_cnt <= byte_cnt + 8'd1;
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(byte_cnt == 0) begin
|
||||
cmd <= { sbuf, SPI_MOSI};
|
||||
|
||||
// fetch first byte when sectore FPGA->IO command has been seen
|
||||
if({ sbuf, SPI_MOSI} == 8'h18)
|
||||
sd_din_strobe <= 1'b1;
|
||||
|
||||
if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
|
||||
sd_ack <= 1'b1;
|
||||
|
||||
end else begin
|
||||
|
||||
// buttons and switches
|
||||
if(cmd == 8'h01)
|
||||
but_sw <= { sbuf[3:0], SPI_MOSI };
|
||||
|
||||
if(cmd == 8'h02)
|
||||
joystick_0 <= { sbuf, SPI_MOSI };
|
||||
|
||||
if(cmd == 8'h03)
|
||||
joystick_1 <= { sbuf, SPI_MOSI };
|
||||
|
||||
if(cmd == 8'h04) begin
|
||||
// store incoming ps2 mouse bytes
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI };
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1;
|
||||
end
|
||||
|
||||
if(cmd == 8'h05) begin
|
||||
// store incoming ps2 keyboard bytes
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI };
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1;
|
||||
end
|
||||
|
||||
if(cmd == 8'h15)
|
||||
status <= { sbuf[6:0], SPI_MOSI };
|
||||
|
||||
// send sector IO -> FPGA
|
||||
if(cmd == 8'h17) begin
|
||||
// flag that download begins
|
||||
// sd_dout <= { sbuf, SPI_MOSI};
|
||||
sd_dout_strobe <= 1'b1;
|
||||
end
|
||||
|
||||
// send sector FPGA -> IO
|
||||
if(cmd == 8'h18)
|
||||
sd_din_strobe <= 1'b1;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
if(cmd == 8'h19) begin
|
||||
// flag that download begins
|
||||
// sd_dout <= { sbuf, SPI_MOSI};
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
sd_dout_strobe <= 1'b1;
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
if(cmd == 8'h1a) begin
|
||||
// first byte is joystick indes
|
||||
if(byte_cnt == 1)
|
||||
stick_idx <= { sbuf[1:0], SPI_MOSI };
|
||||
else if(byte_cnt == 2) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0)
|
||||
joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
|
||||
else if(stick_idx == 1)
|
||||
joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
|
||||
end else if(byte_cnt == 3) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0)
|
||||
joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
|
||||
else if(stick_idx == 1)
|
||||
joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,629 +0,0 @@
|
||||
--
|
||||
-- HT 1080Z (TSR-80 clone) video controller PAL/VGA capable
|
||||
--
|
||||
--
|
||||
-- Copyright (c) 2016-2017 Jozsef Laszlo (rbendr@gmail.com)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity videoctrl is
|
||||
Generic (
|
||||
H_START : integer := 42+84+81-16;
|
||||
V_START : integer := 2+28+((266-192)/2)+4
|
||||
);
|
||||
Port (
|
||||
reset : in STD_LOGIC;
|
||||
clk42 : in STD_LOGIC;
|
||||
--clk7 : in STD_LOGIC;
|
||||
a : in STD_LOGIC_VECTOR (13 downto 0);
|
||||
din : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
dout : out STD_LOGIC_VECTOR (7 downto 0);
|
||||
mreq : in STD_LOGIC;
|
||||
iorq : in STD_LOGIC;
|
||||
wr : in STD_LOGIC;
|
||||
cs : in STD_LOGIC;
|
||||
vcut : in STD_LOGIC;
|
||||
vvga : in STD_LOGIC;
|
||||
page : in STD_LOGIC;
|
||||
inkp : in STD_LOGIC;
|
||||
paperp : in STD_LOGIC;
|
||||
borderp : in STD_LOGIC;
|
||||
oddline : out STD_LOGIC;
|
||||
rgbi : out STD_LOGIC_VECTOR (3 downto 0);
|
||||
pclk : out STD_LOGIC;
|
||||
hsync : out STD_LOGIC;
|
||||
vsync : out STD_LOGIC);
|
||||
end videoctrl;
|
||||
|
||||
architecture Behavioral of videoctrl is
|
||||
|
||||
type videomem is array(0 to 1023) of std_logic_vector(7 downto 0);
|
||||
|
||||
type charmem is array(0 to 4095) of std_logic_vector(7 downto 0);
|
||||
|
||||
signal vidmem : videomem:=(
|
||||
others => x"00"
|
||||
);
|
||||
|
||||
signal chrmem : charmem:=(
|
||||
--[PATCH_START]
|
||||
x"0e",x"11",x"15",x"17",x"16",x"10",x"0f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"0a",x"11",x"11",x"1f",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1e",x"09",x"09",x"0e",x"09",x"09",x"1e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"10",x"10",x"10",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1e",x"09",x"09",x"09",x"09",x"09",x"1e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"10",x"10",x"1e",x"10",x"10",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"10",x"10",x"1e",x"10",x"10",x"10",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0f",x"11",x"10",x"10",x"13",x"11",x"0f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"11",x"1f",x"11",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"04",x"04",x"04",x"04",x"04",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"01",x"01",x"01",x"01",x"01",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"12",x"14",x"18",x"14",x"12",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"10",x"10",x"10",x"10",x"10",x"10",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"1b",x"15",x"15",x"15",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"19",x"15",x"13",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"11",x"11",x"11",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1e",x"11",x"11",x"1e",x"10",x"10",x"10",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"11",x"11",x"15",x"12",x"0d",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1e",x"11",x"11",x"1e",x"14",x"12",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"10",x"0e",x"01",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"15",x"04",x"04",x"04",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"11",x"11",x"11",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"11",x"0a",x"0a",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"11",x"15",x"15",x"15",x"0a",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"0a",x"04",x"0a",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"0a",x"04",x"04",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"01",x"02",x"04",x"08",x"10",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"0e",x"15",x"04",x"04",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"10",x"08",x"04",x"02",x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"04",x"04",x"04",x"15",x"0e",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"04",x"0a",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"04",x"04",x"04",x"04",x"00",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0a",x"0a",x"0a",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0a",x"0a",x"1f",x"0a",x"1f",x"0a",x"0a",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"0f",x"14",x"0e",x"05",x"1e",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"18",x"19",x"02",x"04",x"08",x"13",x"03",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"08",x"14",x"14",x"08",x"15",x"12",x"0d",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"08",x"10",x"10",x"10",x"08",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"02",x"01",x"01",x"01",x"02",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"15",x"0e",x"04",x"0e",x"15",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"04",x"04",x"1f",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"04",x"04",x"08",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"01",x"02",x"04",x"08",x"10",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"13",x"15",x"19",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"0c",x"04",x"04",x"04",x"04",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"01",x"0e",x"10",x"10",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"01",x"02",x"06",x"01",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"02",x"06",x"0a",x"1f",x"02",x"02",x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"10",x"1e",x"01",x"01",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"08",x"10",x"1e",x"11",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"01",x"01",x"02",x"04",x"08",x"10",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"11",x"0e",x"11",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"11",x"0f",x"01",x"02",x"1c",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"04",x"00",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"04",x"00",x"04",x"04",x"08",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"02",x"04",x"08",x"10",x"08",x"04",x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"1f",x"00",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"08",x"04",x"02",x"01",x"02",x"04",x"08",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"01",x"06",x"04",x"00",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"15",x"17",x"16",x"10",x"0f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"0a",x"11",x"11",x"1f",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1e",x"09",x"09",x"0e",x"09",x"09",x"1e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"10",x"10",x"10",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1e",x"09",x"09",x"09",x"09",x"09",x"1e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"10",x"10",x"1e",x"10",x"10",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"10",x"10",x"1e",x"10",x"10",x"10",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0f",x"11",x"10",x"10",x"13",x"11",x"0f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"11",x"1f",x"11",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"04",x"04",x"04",x"04",x"04",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"01",x"01",x"01",x"01",x"01",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"12",x"14",x"18",x"14",x"12",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"10",x"10",x"10",x"10",x"10",x"10",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"1b",x"15",x"15",x"15",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"19",x"15",x"13",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"11",x"11",x"11",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1e",x"11",x"11",x"1e",x"10",x"10",x"10",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"11",x"11",x"15",x"12",x"0d",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1e",x"11",x"11",x"1e",x"14",x"12",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0e",x"11",x"10",x"0e",x"01",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"15",x"04",x"04",x"04",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"11",x"11",x"11",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"11",x"0a",x"0a",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"11",x"15",x"15",x"15",x"0a",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"0a",x"04",x"0a",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"11",x"11",x"0a",x"04",x"04",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1f",x"01",x"02",x"04",x"08",x"10",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"1c",x"10",x"10",x"10",x"10",x"10",x"1c",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"10",x"08",x"04",x"02",x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"01",x"01",x"01",x"01",x"01",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"0a",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"06",x"06",x"04",x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"0e",x"01",x"0f",x"11",x"0f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"10",x"10",x"1e",x"11",x"11",x"11",x"1e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"0f",x"10",x"10",x"10",x"0f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"01",x"01",x"0f",x"11",x"11",x"11",x"0f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"0e",x"11",x"1f",x"10",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"02",x"04",x"04",x"0e",x"04",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"0f",x"11",x"11",x"11",x"0f",x"01",x"06",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"10",x"10",x"1e",x"11",x"11",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"00",x"0c",x"04",x"04",x"04",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"02",x"00",x"06",x"02",x"02",x"02",x"12",x"0c",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"08",x"08",x"09",x"0a",x"0c",x"0a",x"09",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0c",x"04",x"04",x"04",x"04",x"04",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"1a",x"15",x"15",x"15",x"15",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"1e",x"11",x"11",x"11",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"0e",x"11",x"11",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"1e",x"11",x"11",x"11",x"1e",x"10",x"10",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"0f",x"11",x"11",x"11",x"0f",x"01",x"01",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"0b",x"0c",x"08",x"08",x"08",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"0f",x"10",x"0e",x"01",x"1e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"04",x"0e",x"04",x"04",x"04",x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"11",x"11",x"11",x"11",x"0e",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"11",x"11",x"11",x"0a",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"11",x"11",x"15",x"15",x"0a",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"11",x"0a",x"04",x"0a",x"11",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"11",x"11",x"11",x"11",x"0f",x"01",x"06",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"1f",x"02",x"04",x"08",x"1f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"02",x"04",x"04",x"08",x"04",x"04",x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"04",x"04",x"04",x"00",x"04",x"04",x"04",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"08",x"04",x"04",x"02",x"04",x"04",x"08",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"08",x"15",x"02",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"0a",x"15",x"0a",x"15",x"0a",x"15",x"0a",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"00",x"00",x"00",x"00",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"38",x"38",x"38",x"38",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"07",x"07",x"07",x"07",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00",
|
||||
x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"3f",x"00",x"00",x"00",x"00"
|
||||
--[PATCH_END]
|
||||
--others => x"ff"
|
||||
);
|
||||
|
||||
-- 0 1 2
|
||||
-- 21 10.5 5.25
|
||||
signal clkdiv : std_logic_vector(2 downto 0);
|
||||
alias clk21 : std_logic is clkdiv(0);
|
||||
alias clk10_5 : std_logic is clkdiv(1);
|
||||
alias clk5_25 : std_logic is clkdiv(2);
|
||||
|
||||
|
||||
signal hctr : std_logic_vector(9 downto 0);
|
||||
signal vctr : std_logic_vector(8 downto 0);
|
||||
signal vpos : std_logic_vector(3 downto 0); -- line pos in a chr 0..11
|
||||
signal hpos : std_logic_vector(2 downto 0); -- pixel pos in a chr 0..5
|
||||
signal hstart : std_logic_vector(9 downto 0);
|
||||
signal vstart : std_logic_vector(8 downto 0);
|
||||
signal vend : std_logic_vector(8 downto 0);
|
||||
|
||||
signal pxclk : std_logic;
|
||||
signal xpxclk : std_logic;
|
||||
|
||||
signal hact,vact : std_logic;
|
||||
|
||||
|
||||
signal border : std_logic_vector(3 downto 0) := "0010";
|
||||
signal paper : std_logic_vector(3 downto 0) := "0000";
|
||||
signal ink : std_logic_vector(3 downto 0) := "1000";
|
||||
signal pixel : std_logic_vector(3 downto 0);
|
||||
|
||||
signal screen : std_logic;
|
||||
signal hblank,vblank,blank : std_logic;
|
||||
|
||||
signal vaVert : std_logic_vector(3 downto 0); -- vertical line
|
||||
signal vaHoriz : std_logic_vector(5 downto 0); -- horizontal columnt pos
|
||||
|
||||
signal chraddr : std_logic_vector(11 downto 0); -- character bitmap data address in the charmem
|
||||
signal chrCode : std_logic_vector(7 downto 0);
|
||||
signal chrGrap : std_logic_vector(7 downto 0);
|
||||
signal shiftReg : std_logic_vector(7 downto 0);
|
||||
|
||||
signal xpxsel : std_logic_vector(1 downto 0);
|
||||
signal v1 : std_logic;
|
||||
|
||||
signal rinkp,rpaperp,rborderp : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
--pxclk <= clk10_5;
|
||||
--xpxclk <= clk10_5 when vcut='0' else clk5_25;
|
||||
--hstart <= conv_std_logic_vector(H_START,10);
|
||||
--vstart <= conv_std_logic_vector(V_START,9);
|
||||
--vend <= conv_std_logic_vector(311,9);
|
||||
|
||||
pxclk <= clk10_5 when vvga='0' else clk21;
|
||||
xpxsel <= vvga & vcut;
|
||||
with xpxsel select xpxclk <=
|
||||
clk10_5 when "00",
|
||||
clk5_25 when "01",
|
||||
clk21 when "10",
|
||||
clk10_5 when others;
|
||||
|
||||
hstart <= conv_std_logic_vector(H_START,10) when vvga='0' else conv_std_logic_vector(H_START,10);
|
||||
vstart <= conv_std_logic_vector(V_START,9) when vvga='0' else conv_std_logic_vector(V_START-30,9);
|
||||
vend <= conv_std_logic_vector(311,9) when vvga='0' else conv_std_logic_vector(262,9);
|
||||
|
||||
process(clk42)
|
||||
begin
|
||||
if rising_edge(clk42) then
|
||||
clkdiv <= clkdiv + 1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(RESET,clk10_5)
|
||||
begin
|
||||
if RESET='0' then
|
||||
ink <= "1000";
|
||||
paper <= "0000";
|
||||
border <= "0000";
|
||||
else
|
||||
if rising_edge(clk10_5) then
|
||||
|
||||
rinkp <= INKP;
|
||||
rpaperp <= PAPERP;
|
||||
rborderp <= BORDERP;
|
||||
if rinkp='0' and INKP='1' then
|
||||
ink <= ink+1;
|
||||
end if;
|
||||
if rpaperp='0' and PAPERP='1' then
|
||||
paper <= paper+1;
|
||||
end if;
|
||||
if rborderp='0' and BORDERP='1' then
|
||||
border <= border+1;
|
||||
end if;
|
||||
|
||||
if iorq='0' and wr='0' and a(7 downto 2)="000000" then
|
||||
case a(1 downto 0) is
|
||||
when "00"=> ink<=din(3 downto 0);
|
||||
when "01"=> paper<=din(3 downto 0);
|
||||
when "10"=> border<=din(3 downto 0);
|
||||
when others=>null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(clk10_5)
|
||||
begin
|
||||
if rising_edge(clk10_5) then
|
||||
chrCode <= vidmem(conv_integer( vaVert & vaHoriz ));
|
||||
chrGrap <= chrmem(conv_integer( chrCode & vpos ));
|
||||
dout <= vidmem(conv_integer( a(9 downto 0) ));
|
||||
if cs='0' and wr='0' then
|
||||
vidmem(conv_integer( a(9 downto 0) )) <= din;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- h and v counters
|
||||
-- 10.5 MHz pixelclock => 672 pixels per scan line
|
||||
-- 312 scanlines
|
||||
-- 64*6 pixels active screen = 384 pixels
|
||||
-- visible area: 52*10.5 = 546
|
||||
-- Horizontal: |42T-hsync|84T-porch|81T-border|384T-screen|81T-border|
|
||||
process(pxclk)
|
||||
begin
|
||||
if rising_edge(pxclk) then
|
||||
if hctr=671 then
|
||||
hctr<="0000000000";
|
||||
v1 <= not v1;
|
||||
if vctr>=vend then
|
||||
vctr<="000000000";
|
||||
v1 <= '0';
|
||||
else
|
||||
--vctr<=vctr+1;
|
||||
if v1='1' or vvga='0' then
|
||||
vctr<=vctr+1;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
hctr<=hctr+1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--process(pxclk)
|
||||
--begin
|
||||
-- if falling_edge(pxclk) then
|
||||
--
|
||||
-- -- 12*10.5
|
||||
-- if hctr<126 or hctr>654 then
|
||||
-- hblank <= '0';
|
||||
-- else
|
||||
-- hblank <= '1';
|
||||
-- end if;
|
||||
--
|
||||
-- if hctr<42 then -- 4*10.5
|
||||
-- hsync <= '0';
|
||||
-- else
|
||||
-- hsync <= '1';
|
||||
-- end if;
|
||||
--
|
||||
-- if vctr<6 or vctr>309 then
|
||||
-- vblank <= '0';
|
||||
-- else
|
||||
-- vblank <= '1';
|
||||
-- end if;
|
||||
--
|
||||
-- if vctr<2 then
|
||||
-- vsync <= '0';
|
||||
-- else
|
||||
-- vsync <= '1';
|
||||
-- end if;
|
||||
--
|
||||
-- end if;
|
||||
--end process;
|
||||
|
||||
process(pxclk)
|
||||
begin
|
||||
if falling_edge(pxclk) then
|
||||
|
||||
if vvga='0' then
|
||||
-- 12*10.5
|
||||
if hctr<126 or hctr>654 then
|
||||
hblank <= '0';
|
||||
else
|
||||
hblank <= '1';
|
||||
end if;
|
||||
else
|
||||
-- VGA 6us
|
||||
--
|
||||
--if hctr<64 or hctr>662 then
|
||||
if hctr<120 or hctr>654 then
|
||||
hblank <= '0';
|
||||
else
|
||||
hblank <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if vvga='0' then
|
||||
if hctr<42 then -- 4*10.5
|
||||
hsync <= '0';
|
||||
else
|
||||
hsync <= '1';
|
||||
end if;
|
||||
|
||||
if vctr<6 or vctr>309 then
|
||||
vblank <= '0';
|
||||
else
|
||||
vblank <= '1';
|
||||
end if;
|
||||
|
||||
else
|
||||
if hctr<79 then -- 4*21
|
||||
hsync <= '0';
|
||||
else
|
||||
hsync <= '1';
|
||||
end if;
|
||||
|
||||
if vctr<16 or vctr>257 then
|
||||
vblank <= '0';
|
||||
else
|
||||
vblank <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
|
||||
if vctr<2 then
|
||||
vsync <= '0';
|
||||
else
|
||||
vsync <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
hact <= '1' when hctr>=hstart and hctr<hstart+384 else '0';
|
||||
vact <= '1' when vctr>=vstart and vctr<vstart+192 else '0';
|
||||
|
||||
|
||||
process(xpxclk)
|
||||
begin
|
||||
if rising_edge(xpxclk) then
|
||||
if hact='1' and vact='1' then
|
||||
if hpos=5 then
|
||||
hpos <= "000";
|
||||
vaHoriz <= vaHoriz+1;
|
||||
shiftReg <= chrGrap;
|
||||
else
|
||||
shiftReg <= shiftReg(6 downto 0) & '0';
|
||||
hpos <= hpos+1;
|
||||
end if;
|
||||
screen<= '1';
|
||||
else
|
||||
screen<= '0';
|
||||
hpos <= "101";
|
||||
vaHoriz <= (page and vcut) & "00000";
|
||||
shiftReg <= "00000000"; -- keep it clear
|
||||
if vctr=0 then
|
||||
-- new frame
|
||||
vaVert<= "0000";
|
||||
vpos <= "0000";
|
||||
elsif vact='1' and hctr=hstart+384+2 and (v1='1' or vvga='0') then
|
||||
-- end of a scanline
|
||||
if vpos=11 then
|
||||
vpos <= "0000";
|
||||
vaVert <= vaVert+1;
|
||||
else
|
||||
vpos <= vpos+1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pixel <= border when screen='0' else paper when shiftReg(5)='0' else ink;
|
||||
blank <= hblank and vblank;
|
||||
rgbi <= pixel when blank='1' else "0000";
|
||||
pclk <= clk10_5 when vvga='0' else clk21;
|
||||
oddline <= v1;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,23 +0,0 @@
|
||||
# Copyright (C) 1991-2008 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "8.1"
|
||||
DATE = "20:32:23 January 19, 2009"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Oric_Mist"
|
||||
@@ -1,284 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 00:34:30 May 04, 2018
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Extender_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:32:23 JANUARY 19, 2009"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name MISC_FILE "C:/_fpga/_cone/C1Extender/SYMB_CPC/Extender.dpf"
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name TPD_REQUIREMENT "2 ns"
|
||||
set_global_assignment -name TSU_REQUIREMENT "2 ns"
|
||||
set_global_assignment -name TCO_REQUIREMENT "2 ns"
|
||||
set_global_assignment -name TH_REQUIREMENT "2 ns"
|
||||
set_global_assignment -name FMAX_REQUIREMENT "96 MHz"
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY oricatmos
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
|
||||
|
||||
# Simulator Assignments
|
||||
# =====================
|
||||
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
|
||||
|
||||
# SignalTap II Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "FAR END"
|
||||
|
||||
# start EDA_TOOL_SETTINGS(eda_blast_fpga)
|
||||
# ---------------------------------------
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
||||
|
||||
# end EDA_TOOL_SETTINGS(eda_blast_fpga)
|
||||
# -------------------------------------
|
||||
|
||||
# -----------------------
|
||||
# start ENTITY(oricatmos)
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
|
||||
|
||||
# start LOGICLOCK_REGION(Root Region)
|
||||
# -----------------------------------
|
||||
|
||||
# LogicLock Region Assignments
|
||||
# ============================
|
||||
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||||
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||||
|
||||
# end LOGICLOCK_REGION(Root Region)
|
||||
# ---------------------------------
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(oricatmos)
|
||||
# ---------------------
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name VHDL_FILE rtl/oricatmos.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/STOP_WATCH.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/t65_MCode.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/t65.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/t65_alu.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/pack_t65.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ula.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/pack_ula.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/m6522.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/vag.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/video.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/iodecode.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/addmemux.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/memmap.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ps2key.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ctrlseq.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ay3819x.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/tone_generator.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/noise_generator.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/GEN_CLK.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/MIXER.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/gen_env.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/manage_amplitude.vhd
|
||||
set_global_assignment -name QIP_FILE rtl/pll.qip
|
||||
set_global_assignment -name VHDL_FILE rtl/ram48k.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/scan_converter.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix.vhd
|
||||
set_global_assignment -name QIP_FILE rtl/RAMB16_S18_S18.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/osd.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/keymap.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/keymatrix.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/rom.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/spram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
|
||||
set_global_assignment -name QIP_FILE rtl/HC4051.qip
|
||||
set_global_assignment -name QIP_FILE rtl/rrom.qip
|
||||
set_global_assignment -name QIP_FILE rtl/RAM8X1D.qip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,4 +0,0 @@
|
||||
{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 13012 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
@@ -1,3 +0,0 @@
|
||||
Nothing is tested my MiST is Broken i can´t upload any Core
|
||||
|
||||
Need feedback
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,37 +0,0 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
cd sys
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
cd ..
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
|
||||
pause
|
||||
@@ -1,4 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "HC4051.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "HC4051.cmp"]
|
||||
@@ -1,148 +0,0 @@
|
||||
-- megafunction wizard: %LPM_MUX%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: LPM_MUX
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: HC4051.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- LPM_MUX
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY lpm;
|
||||
USE lpm.lpm_components.all;
|
||||
|
||||
ENTITY HC4051 IS
|
||||
PORT
|
||||
(
|
||||
data0 : IN STD_LOGIC ;
|
||||
data1 : IN STD_LOGIC ;
|
||||
data2 : IN STD_LOGIC ;
|
||||
data3 : IN STD_LOGIC ;
|
||||
data4 : IN STD_LOGIC ;
|
||||
data5 : IN STD_LOGIC ;
|
||||
data6 : IN STD_LOGIC ;
|
||||
data7 : IN STD_LOGIC ;
|
||||
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
result : OUT STD_LOGIC
|
||||
);
|
||||
END HC4051;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF hc4051 IS
|
||||
|
||||
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC_2D (7 DOWNTO 0, 0 DOWNTO 0);
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC ;
|
||||
SIGNAL sub_wire7 : STD_LOGIC ;
|
||||
SIGNAL sub_wire8 : STD_LOGIC ;
|
||||
SIGNAL sub_wire9 : STD_LOGIC ;
|
||||
SIGNAL sub_wire10 : STD_LOGIC ;
|
||||
|
||||
BEGIN
|
||||
sub_wire10 <= data0;
|
||||
sub_wire9 <= data1;
|
||||
sub_wire8 <= data2;
|
||||
sub_wire7 <= data3;
|
||||
sub_wire6 <= data4;
|
||||
sub_wire5 <= data5;
|
||||
sub_wire4 <= data6;
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
result <= sub_wire1;
|
||||
sub_wire2 <= data7;
|
||||
sub_wire3(7, 0) <= sub_wire2;
|
||||
sub_wire3(6, 0) <= sub_wire4;
|
||||
sub_wire3(5, 0) <= sub_wire5;
|
||||
sub_wire3(4, 0) <= sub_wire6;
|
||||
sub_wire3(3, 0) <= sub_wire7;
|
||||
sub_wire3(2, 0) <= sub_wire8;
|
||||
sub_wire3(1, 0) <= sub_wire9;
|
||||
sub_wire3(0, 0) <= sub_wire10;
|
||||
|
||||
LPM_MUX_component : LPM_MUX
|
||||
GENERIC MAP (
|
||||
lpm_size => 8,
|
||||
lpm_type => "LPM_MUX",
|
||||
lpm_width => 1,
|
||||
lpm_widths => 3
|
||||
)
|
||||
PORT MAP (
|
||||
data => sub_wire3,
|
||||
sel => sel,
|
||||
result => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
|
||||
-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
|
||||
-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
|
||||
-- Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL "data2"
|
||||
-- Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL "data3"
|
||||
-- Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL "data4"
|
||||
-- Retrieval info: USED_PORT: data5 0 0 0 0 INPUT NODEFVAL "data5"
|
||||
-- Retrieval info: USED_PORT: data6 0 0 0 0 INPUT NODEFVAL "data6"
|
||||
-- Retrieval info: USED_PORT: data7 0 0 0 0 INPUT NODEFVAL "data7"
|
||||
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
|
||||
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
|
||||
-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data 1 2 1 0 data2 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data 1 3 1 0 data3 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data 1 4 1 0 data4 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data 1 5 1 0 data5 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data 1 6 1 0 data6 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data 1 7 1 0 data7 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
|
||||
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
@@ -1,100 +0,0 @@
|
||||
--
|
||||
-- fg.vhd
|
||||
--
|
||||
-- Generate a random noise.
|
||||
--
|
||||
-- Copyright (C)2001 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: fg.vhd, v0.3 2001/11/14 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- from XAPP211.pdf & XAPP211.ZIP (XILINX APPLICATION)
|
||||
--
|
||||
--The following is example code that implements one LFSR which can be used as part of pn generators.
|
||||
--The number of taps, tap points, and LFSR width are parameratizable. When targetting Xilinx (Virtex)
|
||||
--all the latest synthesis vendors (Leonardo, Synplicity, and FPGA Express) will infer the shift
|
||||
--register LUTS (SRL16) resulting in a very efficient implementation.
|
||||
--
|
||||
--Control signals have been provided to allow external circuitry to control such things as filling,
|
||||
--puncturing, stalling (augmentation), etc.
|
||||
--
|
||||
--Mike Gulotta
|
||||
--11/4/99
|
||||
--Revised 3/17/00: Fixed "commented" block diagram to match polynomial.
|
||||
--
|
||||
--
|
||||
--###################################################################################################
|
||||
-- I Polinomials: #
|
||||
-- I(x) = X**17 + X**2 + 1 #
|
||||
-- #
|
||||
-- LFSR implementation format examples: #
|
||||
--###################################################################################################
|
||||
-- #
|
||||
-- I(x) = X**17 + X**2 + 1 #
|
||||
-- ________ #
|
||||
-- | |<<......................... #
|
||||
-- | Parity | | #
|
||||
-- .................| |<<... | #
|
||||
-- | |________| | | #
|
||||
-- | | | #
|
||||
-- | __________________ | ___ ___ | #
|
||||
-- |...|\ | | | | | | | | | pn_out_i #
|
||||
-- ||-->>| 16 | - - - -| 2 |-----| 1 | 0 | >>---------->> #
|
||||
--DataIn_i.|/ |____|________|____| |___|___| #
|
||||
-- | srl_i #
|
||||
-- FillSel..| #
|
||||
-- ---> shifting -->> #
|
||||
|
||||
library ieee ;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i_pn_gen is
|
||||
generic(NumOfTaps_i : integer := 2; -- # of taps for I channel LFSR, including output tap.
|
||||
Width : integer := 17); -- LFSR length (ie, total # of storage elements)
|
||||
port(clk, ShiftEn, FillSel, DataIn_i, RESET : in std_logic;
|
||||
pn_out_i : out std_logic);
|
||||
end i_pn_gen ;
|
||||
|
||||
|
||||
architecture rtl of i_pn_gen is
|
||||
|
||||
type TapPointArray_i is array (NumOfTaps_i-1 downto 0) of integer;
|
||||
constant Tap_i : TapPointArray_i := (2, 0);
|
||||
signal srl_i : std_logic_vector(Width-1 downto 0); -- shift register.
|
||||
signal par_fdbk_i : std_logic_vector(NumOfTaps_i downto 0); -- Parity feedback.
|
||||
signal lfsr_in_i : std_logic; -- mux output.
|
||||
|
||||
|
||||
begin
|
||||
|
||||
---------------------------------------------------------------------
|
||||
------------------ I Channel ----------------------------------------
|
||||
---------------------------------------------------------------------
|
||||
|
||||
Shift_i : process (clk, reset)
|
||||
begin
|
||||
if (RESET = '1') then
|
||||
SRL_I <= "00000000000000000";
|
||||
elsif clk'event and clk = '1' then
|
||||
if (ShiftEn = '1') then
|
||||
srl_i <= lfsr_in_i & srl_i(srl_i'high downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
par_fdbk_i(0) <= '0';
|
||||
|
||||
fdbk_i : for X in 0 to Tap_i'high generate -- parity generator
|
||||
par_fdbk_i(X+1) <= par_fdbk_i(X) xor srl_i(Tap_i(X));
|
||||
end generate fdbk_i;
|
||||
|
||||
lfsr_in_i <= DataIn_i when FillSel = '1' else par_fdbk_i(par_fdbk_i'high);
|
||||
|
||||
pn_out_i <= srl_i(srl_i'low); -- PN I channel output.
|
||||
|
||||
|
||||
end rtl;
|
||||
|
||||
|
||||
|
||||
@@ -1,79 +0,0 @@
|
||||
--
|
||||
-- MIXER.vhd
|
||||
--
|
||||
-- Mix tone generator and noise generator.
|
||||
--
|
||||
-- Copyright (C)2001 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: MIXER.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- A lot of work !!
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
|
||||
entity MIXER is
|
||||
Port ( CLK : in std_logic;
|
||||
CS : in std_logic;
|
||||
RST : in std_logic;
|
||||
WR : in std_logic;
|
||||
IN_A : in std_logic;
|
||||
IN_B : in std_logic;
|
||||
IN_C : in std_logic;
|
||||
IN_NOISE : in std_logic;
|
||||
DATA : in std_logic_vector(5 downto 0);
|
||||
OUT_A : out std_logic;
|
||||
OUT_B : out std_logic;
|
||||
OUT_C : out std_logic );
|
||||
end MIXER;
|
||||
|
||||
architecture Behavioral of MIXER is
|
||||
|
||||
|
||||
begin
|
||||
PROCESS(CLK, RST, CS, WR, DATA, IN_A, IN_B, IN_C, IN_NOISE)
|
||||
BEGIN
|
||||
if (RST = '1') then
|
||||
OUT_A <= '0';
|
||||
OUT_B <= '0';
|
||||
OUT_C <= '0';
|
||||
elsif ( CLK'event and CLK = '1') then
|
||||
if not (CS = '1' and WR = '1') then
|
||||
-- TONE A
|
||||
if (DATA(0) = '0') then
|
||||
if (DATA(3) = '0') then
|
||||
OUT_A <= IN_A xor IN_NOISE;
|
||||
else
|
||||
OUT_A <= IN_A;
|
||||
end if;
|
||||
else
|
||||
OUT_A <= '1';
|
||||
end if;
|
||||
|
||||
-- TONE B
|
||||
if (DATA(1) = '0') then
|
||||
if (DATA(4) = '0') then
|
||||
OUT_B <= IN_B xor IN_NOISE;
|
||||
else
|
||||
OUT_B <= IN_B;
|
||||
end if;
|
||||
else
|
||||
OUT_B <= '1';
|
||||
end if;
|
||||
|
||||
-- TONE C
|
||||
if (DATA(2) = '0') then
|
||||
if (DATA(5) = '0') then
|
||||
OUT_C <= IN_C xor IN_NOISE;
|
||||
else
|
||||
OUT_C <= IN_C;
|
||||
end if;
|
||||
else
|
||||
OUT_C <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
@@ -1,3 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "RAM8X1D.vhd"]
|
||||
@@ -1,206 +0,0 @@
|
||||
-- megafunction wizard: %RAM: 2-PORT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: RAM8X1D.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.altera_mf_components.all;
|
||||
|
||||
ENTITY RAM8X1D IS
|
||||
PORT
|
||||
(
|
||||
clock : IN STD_LOGIC := '1';
|
||||
data : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
enable : IN STD_LOGIC := '1';
|
||||
rdaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
rden : IN STD_LOGIC := '1';
|
||||
wraddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
wren : IN STD_LOGIC := '0';
|
||||
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
|
||||
);
|
||||
END RAM8X1D;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF ram8x1d IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(0 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_aclr_b => "NONE",
|
||||
address_reg_b => "CLOCK0",
|
||||
clock_enable_input_a => "NORMAL",
|
||||
clock_enable_input_b => "NORMAL",
|
||||
clock_enable_output_b => "NORMAL",
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 8,
|
||||
numwords_b => 8,
|
||||
operation_mode => "DUAL_PORT",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_b => "CLOCK0",
|
||||
power_up_uninitialized => "FALSE",
|
||||
rdcontrol_reg_b => "CLOCK0",
|
||||
read_during_write_mode_mixed_ports => "DONT_CARE",
|
||||
widthad_a => 3,
|
||||
widthad_b => 3,
|
||||
width_a => 1,
|
||||
width_b => 1,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
PORT MAP (
|
||||
address_a => wraddress,
|
||||
clock0 => clock,
|
||||
data_a => data,
|
||||
rden_b => rden,
|
||||
wren_a => wren,
|
||||
address_b => rdaddress,
|
||||
clocken0 => enable,
|
||||
q_b => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: enable NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "1"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "3"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
-- Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
|
||||
-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC "enable"
|
||||
-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
|
||||
-- Retrieval info: USED_PORT: rdaddress 0 0 3 0 INPUT NODEFVAL "rdaddress[2..0]"
|
||||
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
|
||||
-- Retrieval info: USED_PORT: wraddress 0 0 3 0 INPUT NODEFVAL "wraddress[2..0]"
|
||||
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 3 0 wraddress 0 0 3 0
|
||||
-- Retrieval info: CONNECT: @address_b 0 0 3 0 rdaddress 0 0 3 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 1 0 data 0 0 1 0
|
||||
-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q 0 0 1 0 @q_b 0 0 1 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
@@ -1,3 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "RAMB16_S18_S18.vhd"]
|
||||
@@ -1,234 +0,0 @@
|
||||
-- megafunction wizard: %RAM: 2-PORT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: RAMB16_S18_S18.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.altera_mf_components.all;
|
||||
|
||||
ENTITY RAMB16_S18_S18 IS
|
||||
PORT
|
||||
(
|
||||
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
|
||||
clock_a : IN STD_LOGIC := '1';
|
||||
clock_b : IN STD_LOGIC ;
|
||||
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
rden_a : IN STD_LOGIC := '1';
|
||||
rden_b : IN STD_LOGIC := '1';
|
||||
wren_a : IN STD_LOGIC := '0';
|
||||
wren_b : IN STD_LOGIC := '0';
|
||||
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
|
||||
);
|
||||
END RAMB16_S18_S18;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF ramb16_s18_s18 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
|
||||
|
||||
BEGIN
|
||||
q_a <= sub_wire0(15 DOWNTO 0);
|
||||
q_b <= sub_wire1(15 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_reg_b => "CLOCK1",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
indata_reg_b => "CLOCK1",
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 1024,
|
||||
numwords_b => 1024,
|
||||
operation_mode => "BIDIR_DUAL_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_a => "CLOCK0",
|
||||
outdata_reg_b => "CLOCK1",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
|
||||
widthad_a => 10,
|
||||
widthad_b => 10,
|
||||
width_a => 16,
|
||||
width_b => 16,
|
||||
width_byteena_a => 1,
|
||||
width_byteena_b => 1,
|
||||
wrcontrol_wraddress_reg_b => "CLOCK1"
|
||||
)
|
||||
PORT MAP (
|
||||
clock0 => clock_a,
|
||||
wren_a => wren_a,
|
||||
address_b => address_b,
|
||||
clock1 => clock_b,
|
||||
data_b => data_b,
|
||||
rden_a => rden_a,
|
||||
wren_b => wren_b,
|
||||
address_a => address_a,
|
||||
data_a => data_a,
|
||||
rden_b => rden_b,
|
||||
q_a => sub_wire0,
|
||||
q_b => sub_wire1
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "1"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
|
||||
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
|
||||
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
|
||||
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
|
||||
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
|
||||
-- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
|
||||
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
|
||||
-- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
|
||||
-- Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
|
||||
-- Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
|
||||
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
|
||||
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
|
||||
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
|
||||
-- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
@@ -1,27 +0,0 @@
|
||||
--
|
||||
-- REG_ADDR.vhd
|
||||
--
|
||||
-- DECODER of Registre.
|
||||
--
|
||||
-- Copyright (C)2001 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: REG_ADDR.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
|
||||
entity REG_ADRESSE is
|
||||
Port ( REG_ADDR : in std_logic_vector(3 downto 0);
|
||||
RST : in std_logic,
|
||||
SEL_REG : out std_logic_vector(15 downto 0) );
|
||||
end REG_ADRESSE;
|
||||
|
||||
architecture Behavioral of REG_ADRESSE is
|
||||
|
||||
-- DECODER 4 -> 16
|
||||
begin
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,3 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ROM256X1.vhd"]
|
||||
@@ -1,146 +0,0 @@
|
||||
-- megafunction wizard: %ROM: 1-PORT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: ROM256X1.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.altera_mf_components.all;
|
||||
|
||||
ENTITY ROM256X1 IS
|
||||
generic (
|
||||
init_file : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
)
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
clock : IN STD_LOGIC := '1';
|
||||
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
|
||||
);
|
||||
END ROM256X1;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF rom256x1 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(0 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_aclr_a => "NONE",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
init_file => init_file,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 256,
|
||||
operation_mode => "ROM",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_reg_a => "CLOCK0",
|
||||
widthad_a => 8,
|
||||
width_a => 1,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
PORT MAP (
|
||||
address_a => address,
|
||||
clock0 => clock,
|
||||
q_a => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/key1.hex"
|
||||
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: WidthData NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/key1.hex"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
@@ -1,78 +0,0 @@
|
||||
--===================================
|
||||
-- Listing 4.17
|
||||
--===================================
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
entity stop_watch is
|
||||
port(
|
||||
clk: in std_logic;
|
||||
go, clr: in std_logic;
|
||||
d2, d1, d0: out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end stop_watch;
|
||||
|
||||
--===================================
|
||||
-- Listing 4.18
|
||||
--===================================
|
||||
architecture if_arch of stop_watch is
|
||||
constant DVSR: integer:=5000000;
|
||||
signal ms_reg, ms_next: unsigned(22 downto 0);
|
||||
signal d2_reg, d1_reg, d0_reg: unsigned(3 downto 0);
|
||||
signal d2_next, d1_next, d0_next: unsigned(3 downto 0);
|
||||
signal ms_tick: std_logic;
|
||||
begin
|
||||
-- register
|
||||
process(clk)
|
||||
begin
|
||||
if (clk'event and clk='1') then
|
||||
ms_reg <= ms_next;
|
||||
d2_reg <= d2_next;
|
||||
d1_reg <= d1_next;
|
||||
d0_reg <= d0_next;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- next-state logic
|
||||
-- 0.1 sec tick generator: mod-5000000
|
||||
ms_next <=
|
||||
(others=>'0') when clr='1' or
|
||||
(ms_reg=DVSR and go='1') else
|
||||
ms_reg + 1 when go='1' else
|
||||
ms_reg;
|
||||
ms_tick <= '1' when ms_reg=DVSR else '0';
|
||||
-- 0.1 sec counter
|
||||
process(d0_reg,d1_reg,d2_reg,ms_tick,clr)
|
||||
begin
|
||||
-- defult
|
||||
d0_next <= d0_reg;
|
||||
d1_next <= d1_reg;
|
||||
d2_next <= d2_reg;
|
||||
if clr='1' then
|
||||
d0_next <= "0000";
|
||||
d1_next <= "0000";
|
||||
d2_next <= "0000";
|
||||
elsif ms_tick='1' then
|
||||
if (d0_reg/=9) then
|
||||
d0_next <= d0_reg + 1;
|
||||
else -- reach XX9
|
||||
d0_next <= "0000";
|
||||
if (d1_reg/=9) then
|
||||
d1_next <= d1_reg + 1;
|
||||
else -- reach X99
|
||||
d1_next <= "0000";
|
||||
if (d2_reg/=9) then
|
||||
d2_next <= d2_reg + 1;
|
||||
else -- reach 999
|
||||
d2_next <= "0000";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
-- output logic
|
||||
d0 <= std_logic_vector(d0_reg);
|
||||
d1 <= std_logic_vector(d1_reg);
|
||||
d2 <= std_logic_vector(d2_reg);
|
||||
end if_arch;
|
||||
|
||||
@@ -1,174 +0,0 @@
|
||||
|
||||
-- VHDL Test Bench Created from source file ay3819x.vhd -- 15:33:03 12/26/2001
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY testbench IS
|
||||
END testbench;
|
||||
|
||||
ARCHITECTURE behavior OF testbench IS
|
||||
|
||||
constant CLK_PERIOD : time := 60 nS; -- system clock period
|
||||
|
||||
COMPONENT ay3819x
|
||||
PORT(
|
||||
RESET : IN std_logic;
|
||||
CLOCK : IN std_logic;
|
||||
BDIR : IN std_logic;
|
||||
BC1 : IN std_logic;
|
||||
BC2 : IN std_logic;
|
||||
D : INOUT std_logic_vector(7 downto 0);
|
||||
IOA : INOUT std_logic_vector(7 downto 0);
|
||||
IOB : INOUT std_logic_vector(7 downto 0);
|
||||
AnalogA : OUT std_logic;
|
||||
AnalogB : OUT std_logic;
|
||||
AnalogC : OUT std_logic );
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL D : std_logic_vector(7 downto 0);
|
||||
SIGNAL RESET : std_logic;
|
||||
SIGNAL CLOCK : std_logic;
|
||||
SIGNAL BDIR : std_logic;
|
||||
SIGNAL BC1 : std_logic;
|
||||
SIGNAL BC2 : std_logic;
|
||||
SIGNAL IOA : std_logic_vector(7 downto 0);
|
||||
SIGNAL IOB : std_logic_vector(7 downto 0);
|
||||
SIGNAL AnalogA : std_logic;
|
||||
SIGNAL AnalogB : std_logic;
|
||||
SIGNAL AnalogC : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: ay3819x PORT MAP(
|
||||
D => D,
|
||||
RESET => RESET,
|
||||
CLOCK => CLOCK,
|
||||
BDIR => BDIR,
|
||||
BC1 => BC1,
|
||||
BC2 => BC2,
|
||||
IOA => IOA,
|
||||
IOB => IOB,
|
||||
AnalogA => AnalogA,
|
||||
AnalogB => AnalogB,
|
||||
AnalogC => AnalogC );
|
||||
|
||||
|
||||
-- *** Test Bench - User Defined Section ***
|
||||
|
||||
CREATE_CLK: process
|
||||
begin
|
||||
CLOCK <= '0';
|
||||
wait for CLK_PERIOD/2;
|
||||
CLOCK <= '1';
|
||||
wait for CLK_PERIOD/2;
|
||||
end process;
|
||||
|
||||
SIMUL_RESET: process
|
||||
begin
|
||||
RESET <= '1';
|
||||
wait until CLOCK'event and CLOCK = '1';
|
||||
wait until CLOCK'event and CLOCK = '1';
|
||||
wait for 15 ns;
|
||||
RESET <= '0';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
SIMUL_WR_TO_R0: process
|
||||
begin
|
||||
BDIR <= '0';
|
||||
BC1 <= '0';
|
||||
BC2 <= '0';
|
||||
wait for 150 ns;
|
||||
BDIR <= '1'; -- Latch
|
||||
BC1 <= '1';
|
||||
BC2 <= '1';
|
||||
wait for 15 ns;
|
||||
BDIR <= '0'; -- HIGH IMPEDANCE
|
||||
BC1 <= '0';
|
||||
BC2 <= '0';
|
||||
wait for 45 ns;
|
||||
BDIR <= '1'; -- write to register
|
||||
BC1 <= '0';
|
||||
BC2 <= '1';
|
||||
wait for 15 ns;
|
||||
BDIR <= '0'; -- HIGH IMPEDANCE
|
||||
BC1 <= '0';
|
||||
BC2 <= '0';
|
||||
wait for 45 ns;
|
||||
BDIR <= '1'; -- latch
|
||||
BC1 <= '1';
|
||||
BC2 <= '1';
|
||||
wait for 15 ns;
|
||||
BDIR <= '0'; -- High impedance
|
||||
BC1 <= '0';
|
||||
BC2 <= '0';
|
||||
wait for 45 ns;
|
||||
BDIR <= '1'; -- write to register
|
||||
BC1 <= '0';
|
||||
BC2 <= '1';
|
||||
wait for 15 ns;
|
||||
BDIR <= '0'; -- High impedance
|
||||
BC1 <= '0';
|
||||
BC2 <= '0';
|
||||
wait for 45 ns;
|
||||
BDIR <= '1'; -- Latch
|
||||
BC1 <= '1';
|
||||
BC2 <= '1';
|
||||
wait for 15 ns;
|
||||
BDIR <= '0'; -- High impedance
|
||||
BC1 <= '0';
|
||||
BC2 <= '0';
|
||||
wait for 45 ns;
|
||||
BDIR <= '0'; -- Read
|
||||
BC1 <= '1';
|
||||
BC2 <= '1';
|
||||
wait for 15 ns;
|
||||
BDIR <= '0'; -- High impedance
|
||||
BC1 <= '0';
|
||||
BC2 <= '0';
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
BUS_D : process
|
||||
begin
|
||||
D <= ( others => 'Z');
|
||||
wait for 150 ns;
|
||||
D <= "00001110";
|
||||
wait for 30 ns;
|
||||
D <= ( others => 'Z');
|
||||
wait for 30 ns; -- 195 ns
|
||||
D <= "00010101";
|
||||
wait for 30 ns; -- 225 ns
|
||||
D <= ( others => 'Z');
|
||||
wait for 30 ns; -- 255 ns
|
||||
D <= "00000001";
|
||||
wait for 30 ns; -- 285 ns
|
||||
D <= ( others => 'Z');
|
||||
wait for 30 ns; -- 315 ns
|
||||
D <= "10010001";
|
||||
wait for 30 ns; -- 345 ns
|
||||
D <= ( others => 'Z');
|
||||
wait for 30 ns; -- 375 ns
|
||||
D <= "00001110";
|
||||
wait for 30 ns; -- 405 ns
|
||||
D <= ( others => 'Z');
|
||||
wait;
|
||||
end process;
|
||||
|
||||
tb : PROCESS
|
||||
BEGIN
|
||||
wait for 1000 ns; -- will wait forever
|
||||
END PROCESS;
|
||||
-- *** End Test Bench - User Defined Section ***
|
||||
|
||||
END;
|
||||
@@ -1,597 +0,0 @@
|
||||
--
|
||||
-- A simulation model of YM2149 (AY-3-8910 with bells on)
|
||||
|
||||
-- Copyright (c) MikeJ - Jan 2005
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email support@fpgaarcade.com
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 001 initial release
|
||||
--
|
||||
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
|
||||
--
|
||||
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
|
||||
-- vol 15 .. 0
|
||||
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
|
||||
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
|
||||
-- to produced all the required values.
|
||||
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
|
||||
--
|
||||
-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
|
||||
-- accurate for designs where the outputs are buffered and not simply wired together.
|
||||
-- The ouput level is more complex in that case and requires a larger table.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity YM2149 is
|
||||
port (
|
||||
-- data bus
|
||||
I_DA : in std_logic_vector(7 downto 0);
|
||||
O_DA : out std_logic_vector(7 downto 0);
|
||||
O_DA_OE_L : out std_logic;
|
||||
-- control
|
||||
I_A9_L : in std_logic;
|
||||
I_A8 : in std_logic;
|
||||
I_BDIR : in std_logic;
|
||||
I_BC2 : in std_logic;
|
||||
I_BC1 : in std_logic;
|
||||
I_SEL_L : in std_logic;
|
||||
|
||||
O_AUDIO : out std_logic_vector(7 downto 0) := (others => '0');
|
||||
-- port a
|
||||
-- I_IOA : in std_logic_vector(7 downto 0);
|
||||
-- O_IOA : out std_logic_vector(7 downto 0);
|
||||
-- O_IOA_OE_L : out std_logic;
|
||||
-- port b
|
||||
-- I_IOB : in std_logic_vector(7 downto 0);
|
||||
-- O_IOB : out std_logic_vector(7 downto 0);
|
||||
-- O_IOB_OE_L : out std_logic;
|
||||
|
||||
ENA : in std_logic; -- clock enable for higher speed operation
|
||||
RESET_L : in std_logic;
|
||||
CLK : in std_logic -- note 6 Mhz
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of YM2149 is
|
||||
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
|
||||
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
|
||||
|
||||
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
|
||||
|
||||
signal noise_div : std_logic := '0';
|
||||
signal ena_div : std_logic := '0';
|
||||
signal ena_div_noise : std_logic := '0';
|
||||
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
|
||||
|
||||
-- registers
|
||||
signal addr : std_logic_vector(7 downto 0);
|
||||
signal busctrl_addr : std_logic;
|
||||
signal busctrl_we : std_logic;
|
||||
signal busctrl_re : std_logic;
|
||||
|
||||
signal reg : array_16x8 := (others => (others => '0'));
|
||||
signal env_reset : std_logic := '1';
|
||||
-- signal ioa_inreg : std_logic_vector(7 downto 0) := (others => '0');
|
||||
-- signal iob_inreg : std_logic_vector(7 downto 0) := (others => '0');
|
||||
|
||||
signal noise_gen_cnt : std_logic_vector(4 downto 0) := (others => '0');
|
||||
signal noise_gen_op : std_logic;
|
||||
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
|
||||
signal tone_gen_op : std_logic_vector(3 downto 1) := (others => '0');
|
||||
|
||||
signal env_gen_cnt : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal env_ena : std_logic := '0';
|
||||
signal env_hold : std_logic := '0';
|
||||
signal env_inc : std_logic := '0';
|
||||
signal env_vol : std_logic_vector(4 downto 0) := (others => '0');
|
||||
|
||||
signal tone_ena_l : std_logic;
|
||||
signal tone_src : std_logic;
|
||||
signal noise_ena_l : std_logic;
|
||||
signal chan_vol : std_logic_vector(4 downto 0);
|
||||
|
||||
signal dac_amp : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal audio_mix : std_logic_vector(9 downto 0) := (others => '0');
|
||||
signal audio_final : std_logic_vector(9 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
-- cpu i/f
|
||||
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
|
||||
variable cs : std_logic;
|
||||
variable sel : std_logic_vector(2 downto 0);
|
||||
begin
|
||||
-- BDIR BC2 BC1 MODE
|
||||
-- 0 0 0 inactive
|
||||
-- 0 0 1 address
|
||||
-- 0 1 0 inactive
|
||||
-- 0 1 1 read
|
||||
-- 1 0 0 address
|
||||
-- 1 0 1 inactive
|
||||
-- 1 1 0 write
|
||||
-- 1 1 1 read
|
||||
busctrl_addr <= '0';
|
||||
busctrl_we <= '0';
|
||||
busctrl_re <= '0';
|
||||
|
||||
cs := '0';
|
||||
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
|
||||
cs := '1';
|
||||
end if;
|
||||
|
||||
sel := (I_BDIR & I_BC2 & I_BC1);
|
||||
case sel is
|
||||
when "000" => null;
|
||||
when "001" => busctrl_addr <= '1';
|
||||
when "010" => null;
|
||||
when "011" => busctrl_re <= cs;
|
||||
when "100" => busctrl_addr <= '1';
|
||||
when "101" => null;
|
||||
when "110" => busctrl_we <= cs;
|
||||
when "111" => busctrl_addr <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
p_oe : process(busctrl_re)
|
||||
begin
|
||||
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
|
||||
O_DA_OE_L <= not (busctrl_re);
|
||||
end process;
|
||||
|
||||
--
|
||||
-- CLOCKED
|
||||
--
|
||||
p_waddr : process(RESET_L, CLK)
|
||||
begin
|
||||
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
|
||||
if (RESET_L = '0') then
|
||||
addr <= (others => '0');
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA = '1') then
|
||||
if (busctrl_addr = '1') then
|
||||
addr <= I_DA;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_wdata : process(RESET_L, CLK)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
reg <= (others => (others => '0'));
|
||||
env_reset <= '1';
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA = '1') then
|
||||
env_reset <= '0';
|
||||
if (busctrl_we = '1') then
|
||||
case addr(3 downto 0) is
|
||||
when x"0" => reg(0) <= I_DA;
|
||||
when x"1" => reg(1) <= I_DA;
|
||||
when x"2" => reg(2) <= I_DA;
|
||||
when x"3" => reg(3) <= I_DA;
|
||||
when x"4" => reg(4) <= I_DA;
|
||||
when x"5" => reg(5) <= I_DA;
|
||||
when x"6" => reg(6) <= I_DA;
|
||||
when x"7" => reg(7) <= I_DA;
|
||||
when x"8" => reg(8) <= I_DA;
|
||||
when x"9" => reg(9) <= I_DA;
|
||||
when x"A" => reg(10) <= I_DA;
|
||||
when x"B" => reg(11) <= I_DA;
|
||||
when x"C" => reg(12) <= I_DA;
|
||||
when x"D" => reg(13) <= I_DA; env_reset <= '1';
|
||||
when x"E" => reg(14) <= I_DA;
|
||||
when x"F" => reg(15) <= I_DA;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_rdata : process(busctrl_re, addr, reg) --, ioa_inreg, iob_inreg)
|
||||
begin
|
||||
O_DA <= (others => '0'); -- 'X'
|
||||
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
|
||||
case addr(3 downto 0) is
|
||||
when x"0" => O_DA <= reg(0) ;
|
||||
when x"1" => O_DA <= reg(1);
|
||||
when x"2" => O_DA <= reg(2);
|
||||
when x"3" => O_DA <= reg(3);
|
||||
when x"4" => O_DA <= reg(4);
|
||||
when x"5" => O_DA <= reg(5);
|
||||
when x"6" => O_DA <= reg(6);
|
||||
when x"7" => O_DA <= reg(7);
|
||||
when x"8" => O_DA <= reg(8);
|
||||
when x"9" => O_DA <= reg(9);
|
||||
when x"A" => O_DA <= reg(10);
|
||||
when x"B" => O_DA <= reg(11);
|
||||
when x"C" => O_DA <= reg(12);
|
||||
when x"D" => O_DA <= reg(13);
|
||||
when x"E" =>
|
||||
if (reg(7)(6) = '0') then -- input
|
||||
O_DA <= x"00"; --ioa_inreg;
|
||||
else
|
||||
O_DA <= reg(14); -- read output reg
|
||||
end if;
|
||||
when x"F" =>
|
||||
if (Reg(7)(7) = '0') then
|
||||
O_DA <= x"00"; --iob_inreg;
|
||||
else
|
||||
O_DA <= reg(15);
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
p_divider : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
-- / 8 when SEL is high and /16 when SEL is low
|
||||
if (ENA = '1') then
|
||||
ena_div <= '0';
|
||||
ena_div_noise <= '0';
|
||||
if (cnt_div = "0000") then
|
||||
cnt_div <= (not I_SEL_L) & "111";
|
||||
ena_div <= '1';
|
||||
|
||||
noise_div <= not noise_div;
|
||||
if (noise_div = '1') then
|
||||
ena_div_noise <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt_div <= cnt_div - "1";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_noise_gen : process
|
||||
variable noise_gen_comp : std_logic_vector(4 downto 0);
|
||||
variable poly17_zero : std_logic;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
if (reg(6)(4 downto 0) = "00000") then
|
||||
noise_gen_comp := (others => '0');
|
||||
else
|
||||
noise_gen_comp := (reg(6)(4 downto 0) - "1");
|
||||
end if;
|
||||
|
||||
poly17_zero := '0';
|
||||
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
|
||||
|
||||
if (ENA = '1') then
|
||||
|
||||
if (ena_div_noise = '1') then -- divider ena
|
||||
|
||||
if (noise_gen_cnt >= noise_gen_comp) then
|
||||
noise_gen_cnt <= (others => '0');
|
||||
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
|
||||
else
|
||||
noise_gen_cnt <= (noise_gen_cnt + "1");
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
noise_gen_op <= poly17(0);
|
||||
|
||||
p_tone_gens : process
|
||||
variable tone_gen_freq : array_3x12;
|
||||
variable tone_gen_comp : array_3x12;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
-- looks like real chips count up - we need to get the Exact behaviour ..
|
||||
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
|
||||
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
|
||||
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
|
||||
-- period 0 = period 1
|
||||
for i in 1 to 3 loop
|
||||
if (tone_gen_freq(i) = x"000") then
|
||||
tone_gen_comp(i) := (others => '0');
|
||||
else
|
||||
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
if (ENA = '1') then
|
||||
for i in 1 to 3 loop
|
||||
if (ena_div = '1') then -- divider ena
|
||||
|
||||
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
|
||||
tone_gen_cnt(i) <= (others => '0');
|
||||
tone_gen_op(i) <= not tone_gen_op(i);
|
||||
else
|
||||
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_envelope_freq : process
|
||||
variable env_gen_freq : std_logic_vector(15 downto 0);
|
||||
variable env_gen_comp : std_logic_vector(15 downto 0);
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
env_gen_freq := reg(12) & reg(11);
|
||||
-- envelope freqs 1 and 0 are the same.
|
||||
if (env_gen_freq = x"0000") then
|
||||
env_gen_comp := (others => '0');
|
||||
else
|
||||
env_gen_comp := (env_gen_freq - "1");
|
||||
end if;
|
||||
|
||||
if (ENA = '1') then
|
||||
env_ena <= '0';
|
||||
if (ena_div = '1') then -- divider ena
|
||||
if (env_gen_cnt >= env_gen_comp) then
|
||||
env_gen_cnt <= (others => '0');
|
||||
env_ena <= '1';
|
||||
else
|
||||
env_gen_cnt <= (env_gen_cnt + "1");
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_envelope_shape : process
|
||||
variable is_bot : boolean;
|
||||
variable is_bot_p1 : boolean;
|
||||
variable is_top_m1 : boolean;
|
||||
variable is_top : boolean;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
-- envelope shapes
|
||||
-- C AtAlH
|
||||
-- 0 0 x x \___
|
||||
--
|
||||
-- 0 1 x x /___
|
||||
--
|
||||
-- 1 0 0 0 \\\\
|
||||
--
|
||||
-- 1 0 0 1 \___
|
||||
--
|
||||
-- 1 0 1 0 \/\/
|
||||
-- ___
|
||||
-- 1 0 1 1 \
|
||||
--
|
||||
-- 1 1 0 0 ////
|
||||
-- ___
|
||||
-- 1 1 0 1 /
|
||||
--
|
||||
-- 1 1 1 0 /\/\
|
||||
--
|
||||
-- 1 1 1 1 /___
|
||||
|
||||
-- synchronous reset to avoid latch warning
|
||||
if (env_reset = '1') then
|
||||
-- load initial state
|
||||
if (reg(13)(2) = '0') then -- attack
|
||||
env_vol <= (others => '1');
|
||||
env_inc <= '0'; -- -1
|
||||
else
|
||||
env_vol <= (others => '0');
|
||||
env_inc <= '1'; -- +1
|
||||
end if;
|
||||
|
||||
env_hold <= '0';
|
||||
|
||||
else
|
||||
|
||||
is_bot := (env_vol = "00000");
|
||||
is_bot_p1 := (env_vol = "00001");
|
||||
is_top_m1 := (env_vol = "11110");
|
||||
is_top := (env_vol = "11111");
|
||||
|
||||
if (ENA = '1') then
|
||||
if (env_ena = '1') then
|
||||
if (env_hold = '0') then
|
||||
if (env_inc = '1') then
|
||||
env_vol <= (env_vol + "00001");
|
||||
else
|
||||
env_vol <= (env_vol + "11111");
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- envelope shape control.
|
||||
if (reg(13)(3) = '0') then
|
||||
if (env_inc = '0') then -- down
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_top then env_hold <= '1'; end if;
|
||||
end if;
|
||||
else
|
||||
if (reg(13)(0) = '1') then -- hold = 1
|
||||
if (env_inc = '0') then -- down
|
||||
if (reg(13)(1) = '1') then -- alt
|
||||
if is_bot then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
end if;
|
||||
else
|
||||
if (reg(13)(1) = '1') then -- alt
|
||||
if is_top then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_top_m1 then env_hold <= '1'; end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
elsif (reg(13)(1) = '1') then -- alternate
|
||||
if (env_inc = '0') then -- down
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
|
||||
else
|
||||
if is_top_m1 then env_hold <= '1'; end if;
|
||||
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
|
||||
begin
|
||||
tone_ena_l <= '1';
|
||||
tone_src <= '1';
|
||||
noise_ena_l <= '1';
|
||||
chan_vol <= "00000";
|
||||
case cnt_div(1 downto 0) is
|
||||
when "00" =>
|
||||
tone_ena_l <= reg(7)(0);
|
||||
tone_src <= tone_gen_op(1);
|
||||
chan_vol <= reg(8)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(3);
|
||||
when "01" =>
|
||||
tone_ena_l <= reg(7)(1);
|
||||
tone_src <= tone_gen_op(2);
|
||||
chan_vol <= reg(9)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(4);
|
||||
when "10" =>
|
||||
tone_ena_l <= reg(7)(2);
|
||||
tone_src <= tone_gen_op(3);
|
||||
chan_vol <= reg(10)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(5);
|
||||
when "11" => null; -- tone gen outputs become valid on this clock
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
p_op_mixer : process
|
||||
variable chan_mixed : std_logic;
|
||||
variable chan_amp : std_logic_vector(4 downto 0);
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA = '1') then
|
||||
|
||||
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
|
||||
|
||||
chan_amp := (others => '0');
|
||||
if (chan_mixed = '1') then
|
||||
if (chan_vol(4) = '0') then
|
||||
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
|
||||
chan_amp := (others => '0');
|
||||
else
|
||||
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
|
||||
end if;
|
||||
else
|
||||
chan_amp := env_vol(4 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
dac_amp <= (others => '0');
|
||||
case chan_amp is
|
||||
when "11111" => dac_amp <= x"FF";
|
||||
when "11110" => dac_amp <= x"D9";
|
||||
when "11101" => dac_amp <= x"BA";
|
||||
when "11100" => dac_amp <= x"9F";
|
||||
when "11011" => dac_amp <= x"88";
|
||||
when "11010" => dac_amp <= x"74";
|
||||
when "11001" => dac_amp <= x"63";
|
||||
when "11000" => dac_amp <= x"54";
|
||||
when "10111" => dac_amp <= x"48";
|
||||
when "10110" => dac_amp <= x"3D";
|
||||
when "10101" => dac_amp <= x"34";
|
||||
when "10100" => dac_amp <= x"2C";
|
||||
when "10011" => dac_amp <= x"25";
|
||||
when "10010" => dac_amp <= x"1F";
|
||||
when "10001" => dac_amp <= x"1A";
|
||||
when "10000" => dac_amp <= x"16";
|
||||
when "01111" => dac_amp <= x"13";
|
||||
when "01110" => dac_amp <= x"10";
|
||||
when "01101" => dac_amp <= x"0D";
|
||||
when "01100" => dac_amp <= x"0B";
|
||||
when "01011" => dac_amp <= x"09";
|
||||
when "01010" => dac_amp <= x"08";
|
||||
when "01001" => dac_amp <= x"07";
|
||||
when "01000" => dac_amp <= x"06";
|
||||
when "00111" => dac_amp <= x"05";
|
||||
when "00110" => dac_amp <= x"04";
|
||||
when "00101" => dac_amp <= x"03";
|
||||
when "00100" => dac_amp <= x"03";
|
||||
when "00011" => dac_amp <= x"02";
|
||||
when "00010" => dac_amp <= x"02";
|
||||
when "00001" => dac_amp <= x"01";
|
||||
when "00000" => dac_amp <= x"00";
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
if (cnt_div(1 downto 0) = "10") then
|
||||
audio_mix <= (others => '0');
|
||||
audio_final <= audio_mix;
|
||||
else
|
||||
audio_mix <= audio_mix + ("00" & dac_amp);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_audio_output : process(RESET_L, CLK)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
O_AUDIO <= (others => '0');
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA = '1') then
|
||||
O_AUDIO <= audio_final(9 downto 2);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- p_io_ports : process(reg)
|
||||
-- begin
|
||||
-- O_IOA <= reg(14);
|
||||
|
||||
-- O_IOA_OE_L <= not reg(7)(6);
|
||||
-- O_IOB <= reg(15);
|
||||
-- O_IOB_OE_L <= not reg(7)(7);
|
||||
-- end process;
|
||||
|
||||
-- p_io_ports_inreg : process
|
||||
-- begin
|
||||
-- wait until rising_edge(CLK);
|
||||
-- if (ENA = '1') then -- resync
|
||||
-- ioa_inreg <= I_IOA;
|
||||
-- iob_inreg <= I_IOB;
|
||||
-- end if;
|
||||
-- end process;
|
||||
end architecture RTL;
|
||||
@@ -1,87 +0,0 @@
|
||||
--
|
||||
-- addmenux.vhd
|
||||
--
|
||||
-- Manage bus address multiplexer
|
||||
--
|
||||
-- Copyright (C)2001 - 2005 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: addmenux.vhd, v0.10 2009/06/25 00:00:00 SEILEBOST $
|
||||
-- MODIFICATION :
|
||||
-- v0.01 : 200X/??/??
|
||||
-- v0.10 : 2009/06/25 : Intégration de la partie multiplexage de l'accès ram
|
||||
-- TODO :
|
||||
--
|
||||
-- TODO :
|
||||
-- Remark :
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_STD.all;
|
||||
--use IEEE.std_logic_unsigned.all;
|
||||
|
||||
entity addmemux is
|
||||
port ( RESETn : in std_logic;
|
||||
VAP1 : in std_logic_vector(15 downto 0);-- Video address phase 1
|
||||
VAP2 : in std_logic_vector(15 downto 0);-- Video address phase 2
|
||||
BAP : in std_logic_vector(15 downto 0);-- Bus address processor (A15-A0)
|
||||
VA1L : in std_logic; -- Video address phase 1 LATCH
|
||||
VA1R : in std_logic; -- Video address phase 1 ROW
|
||||
VA1C : in std_logic; -- Video address phase 1 COLUMN
|
||||
VA2L : in std_logic; -- Video address phase 2 LATCH
|
||||
VA2R : in std_logic; -- Video address phase 2 ROW
|
||||
VA2C : in std_logic; -- Video address phase 2 COLUMN
|
||||
BAC : in std_logic; -- Bus address COLUMN
|
||||
BAL : in std_logic; -- Bus address LATCH
|
||||
AD_DYN : out std_logic_vector(15 downto 0) -- Address Bus dynamic
|
||||
);
|
||||
end entity addmemux;
|
||||
|
||||
architecture addmemux_arch of addmemux is
|
||||
|
||||
signal lVAP1 : std_logic_vector(15 downto 0);
|
||||
signal lVAP2 : std_logic_vector(15 downto 0);
|
||||
signal lBAP : std_logic_vector(15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Latch VAP1
|
||||
u_VAP1 : PROCESS ( VAP1, VA1L,resetn )
|
||||
begin
|
||||
if (resetn = '0') then
|
||||
lVAP1 <= (OTHERS => '0');
|
||||
elsif rising_edge(VA1L) then
|
||||
lVAP1 <= VAP1;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Latch VAP2
|
||||
u_VAP2 : PROCESS ( VAP2, VA2L, resetn )
|
||||
begin
|
||||
if (resetn = '0') then
|
||||
lVAP2 <= (OTHERS => '0');
|
||||
elsif rising_edge(VA2L) then
|
||||
lVAP2 <= VAP2;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Latch BAP
|
||||
u_BAP: PROCESS ( BAP, BAL, resetn )
|
||||
begin
|
||||
if (resetn = '0') then
|
||||
lBAP<= (OTHERS => '0');
|
||||
elsif rising_edge(BAL) then
|
||||
lBAP<= BAP;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Assignation
|
||||
|
||||
AD_DYN <= lVAP1(15 downto 0) when VA1R = '1' else
|
||||
-- lVAP1(7 downto 0) when VA1C = '1' else
|
||||
lVAP2(15 downto 0) when VA2R = '1' else
|
||||
-- lVAP2(7 downto 0) when VA2C = '1' else
|
||||
-- lBAP when BAL = '1' else
|
||||
-- (OTHERS => 'Z');
|
||||
lBAP;
|
||||
end architecture addmemux_arch;
|
||||
@@ -1,435 +0,0 @@
|
||||
--
|
||||
-- A simulation model of PSG hardware
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: passionoric.free.fr
|
||||
--
|
||||
-- Email seilebost@free.fr
|
||||
--
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- v0.42 2002/01/03 : It seems ok
|
||||
-- v0.43 2009/01/21 : bus bidirectionnel => bus unidirectionnel
|
||||
-- v0.44 2009/10/11 : Reset asynchrone pour le process U_TRAIT
|
||||
-- v0.45 2010/01/03 : Ajout d'une horloge pour le DAC
|
||||
-- v0.46 2010/01/06 : Modification du générateur de fréquence
|
||||
-- pour ajouter la division par 16 et par 256
|
||||
-- v0.50 2010/01/19 : Reorganisation du code
|
||||
--
|
||||
-- AY3819X.vhd
|
||||
--
|
||||
-- Top entity of AY3819X.
|
||||
--
|
||||
-- Copyright (C)2001-2010 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: AY3819.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- TODO :
|
||||
-- Many verification !!
|
||||
-- Remark :
|
||||
|
||||
library IEEE;
|
||||
library UNISIM;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_STD.all;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--use UNISIM.Vcomponents.ALL; -- for IOBUF and OBUF
|
||||
|
||||
entity AY3819X is
|
||||
Port ( DATA_IN : in std_logic_vector(7 downto 0);
|
||||
DATA_OUT : out std_logic_vector(7 downto 0);
|
||||
O_DATA_OE_L : out std_logic;
|
||||
RESET : in std_logic;
|
||||
CLOCK : in std_logic;
|
||||
CLOCK_DAC : in std_logic; -- 24 MHz pour le DAC
|
||||
BDIR : in std_logic;
|
||||
BC1 : in std_logic;
|
||||
BC2 : in std_logic;
|
||||
IOA : inout std_logic_vector(7 downto 0);
|
||||
IOB : inout std_logic_vector(7 downto 0);
|
||||
AnalogA : out std_logic;
|
||||
AnalogB : out std_logic;
|
||||
AnalogC : out std_logic );
|
||||
end AY3819X;
|
||||
|
||||
|
||||
architecture Behavioral of AY3819X is
|
||||
|
||||
SIGNAL BUS_CS : std_logic_vector(15 downto 0); -- Select the different module when Read / Write Register
|
||||
|
||||
-- Create register
|
||||
SIGNAL R0 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel A
|
||||
SIGNAL R1 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel A
|
||||
SIGNAL R2 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel B
|
||||
SIGNAL R3 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel B
|
||||
SIGNAL R4 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel C
|
||||
SIGNAL R5 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel B
|
||||
SIGNAL R6 : std_logic_vector(7 downto 0); -- Noise generator frequency
|
||||
SIGNAL R7 : std_logic_vector(7 downto 0); -- Mixer Control I/O Enable
|
||||
SIGNAL R8 : std_logic_vector(7 downto 0); -- Amplitude control channel A
|
||||
SIGNAL R9 : std_logic_vector(7 downto 0); -- Amplitude control channel B
|
||||
SIGNAL R10 : std_logic_vector(7 downto 0); -- Amplitude control channel C
|
||||
SIGNAL R11 : std_logic_vector(7 downto 0); -- Envelope period control fine tune
|
||||
SIGNAL R12 : std_logic_vector(7 downto 0); -- Envelope period control coarse tune
|
||||
SIGNAL R13 : std_logic_vector(7 downto 0); -- Envelope shape/cycle control
|
||||
|
||||
SIGNAL REG_ADDR : std_logic_vector(3 downto 0); -- Keep the number of register addressed
|
||||
|
||||
SIGNAL WR : std_logic; -- WRITE (FLAG)
|
||||
|
||||
SIGNAL CLK_A : std_logic; -- CLOCK TONE VOICE A
|
||||
SIGNAL CLK_B : std_logic; -- CLOCK TONE VOICE B
|
||||
SIGNAL CLK_C : std_logic; -- CLOCK TONE VOICE C
|
||||
SIGNAL CLK_TONE_A : std_logic; -- CLOCK TONE VOICE A +/- CLOCK NOISE
|
||||
SIGNAL CLK_TONE_B : std_logic; -- CLOCK TONE VOICE B +/- CLOCK NOISE
|
||||
SIGNAL CLK_TONE_C : std_logic; -- CLOCK TONE VOICE C +/- CLOCK NOISE
|
||||
SIGNAL CLK_E : std_logic; -- CLOCK Envelope Generator
|
||||
SIGNAL CLK_N : std_logic; -- CLOCK FROM NOISE GENERATOR
|
||||
SIGNAL CLK_16 : std_logic; -- CLOCK (=1 MHz) / 16 pour le "tone"
|
||||
SIGNAL CLK_256 : std_logic; -- CLOCK (=1 MHz) / 256 pour l'enveloppe
|
||||
|
||||
SIGNAL OUT_AMPL_E : std_logic_vector(3 downto 0); -- Amplitude of signal from Envelope generator
|
||||
|
||||
SIGNAL IAnalogA : std_logic; -- FOR IOPAD, exit from DAC VOICE A
|
||||
SIGNAL IAnalogB : std_logic; -- FOR IOPAD, exit from DAC VOICE B
|
||||
SIGNAL IAnalogC : std_logic; -- FOR IOPAD, exit from DAC VOICE C
|
||||
|
||||
SIGNAL RST_ENV : std_logic; -- FOR RESET THE VALUE OF ENVELOPPE
|
||||
|
||||
COMPONENT TONE_GENERATOR PORT ( CLK : in std_logic;
|
||||
--CLK_TONE : in std_logic;
|
||||
RST : in std_logic;
|
||||
WR : in std_logic;
|
||||
--CS_COARSE : in std_logic;
|
||||
--CS_FINE : in std_logic;
|
||||
DATA_COARSE : in std_logic_vector(7 downto 0);
|
||||
DATA_FINE : in std_logic_vector(7 downto 0);
|
||||
OUT_TONE : inout std_logic );
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT NOISE_GENERATOR PORT ( CLK : in std_logic;
|
||||
RST : in std_logic;
|
||||
--WR : in std_logic;
|
||||
--CS : in std_logic;
|
||||
DATA : in std_logic_vector(4 downto 0);
|
||||
CLK_N : out std_logic );
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT GEN_CLK PORT ( CLK : in std_logic;
|
||||
RST : in std_logic;
|
||||
CLK_16 : out std_logic;
|
||||
CLK_256 : out std_logic);
|
||||
END COMPONENT;
|
||||
|
||||
-- COMPONENT MIXER PORT ( CLK : in std_logic;
|
||||
-- CS : in std_logic;
|
||||
-- RST : in std_logic;
|
||||
-- WR : in std_logic;
|
||||
-- IN_A : in std_logic;
|
||||
-- IN_B : in std_logic;
|
||||
-- IN_C : in std_logic;
|
||||
-- IN_NOISE : in std_logic;
|
||||
-- DATA : in std_logic_vector(5 downto 0);
|
||||
-- OUT_A : out std_logic;
|
||||
-- OUT_B : out std_logic;
|
||||
-- OUT_C : out std_logic );
|
||||
--END COMPONENT;
|
||||
|
||||
COMPONENT GEN_ENV PORT ( CLK_ENV : in std_logic;
|
||||
DATA : in std_logic_vector(3 downto 0);
|
||||
RST_ENV : in std_logic;
|
||||
WR : in std_logic;
|
||||
--CS : in std_logic;
|
||||
OUT_DATA : inout std_logic_vector(3 downto 0));
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT MANAGE_AMPLITUDE PORT ( CLK : in std_logic;
|
||||
CLK_DAC : in std_logic;
|
||||
CLK_TONE : in std_logic;
|
||||
CLK_NOISE : in std_logic;
|
||||
RST : in std_logic;
|
||||
CLK_TONE_ENA : in std_logic;
|
||||
CLK_NOISE_ENA : in std_logic;
|
||||
AMPLITUDE : in std_logic_vector(4 downto 0);
|
||||
AMPLITUDE_E : in std_logic_vector(3 downto 0);
|
||||
OUT_DAC : out std_logic );
|
||||
END COMPONENT;
|
||||
|
||||
--COMPONENT IOBUF_F_12 port ( O : out std_logic;
|
||||
-- IO : inout std_logic;
|
||||
-- I : in std_logic;
|
||||
-- T : in std_logic );
|
||||
--END COMPONENT;
|
||||
|
||||
--COMPONENT OBUF_F_12 port ( O : out std_logic;
|
||||
-- IO : inout std_logic;
|
||||
-- I : in std_logic;
|
||||
-- T : in std_logic );
|
||||
--END COMPONENT;
|
||||
|
||||
--component OBUF_F_24
|
||||
--port (
|
||||
-- I : in std_logic;
|
||||
-- O : out std_logic );
|
||||
--end component;
|
||||
|
||||
BEGIN
|
||||
|
||||
U_TRAIT : PROCESS(CLOCK, RESET, BC1, BC2, BDIR, REG_ADDR, DATA_IN)
|
||||
BEGIN
|
||||
|
||||
if (RESET = '1') then
|
||||
WR <= '0';
|
||||
R0 <= "00000000";
|
||||
R1 <= "00000000";
|
||||
R2 <= "00000000";
|
||||
R3 <= "00000000";
|
||||
R4 <= "00000000";
|
||||
R5 <= "00000000";
|
||||
R6 <= "00000000";
|
||||
R7 <= "00000000";
|
||||
R8 <= "00000000";
|
||||
R9 <= "00000000";
|
||||
R10 <= "00000000";
|
||||
R11 <= "00000000";
|
||||
R12 <= "00000000";
|
||||
R13 <= "00000000";
|
||||
IOA <= "00000000";
|
||||
IOB <= "00000000";
|
||||
DATA_OUT <= "00000000";
|
||||
RST_ENV <= '1';
|
||||
else
|
||||
if rising_edge(CLOCK) then -- edge clock
|
||||
-- READ FROM REGISTER
|
||||
RST_ENV <= '0';
|
||||
if ((BDIR = '0') and (BC2 = '1') and (BC1 = '1')) then
|
||||
CASE REG_ADDR is
|
||||
WHEN "0000" => DATA_OUT <= R0;
|
||||
WHEN "0001" => DATA_OUT <= R1;
|
||||
WHEN "0010" => DATA_OUT <= R2;
|
||||
WHEN "0011" => DATA_OUT <= R3;
|
||||
WHEN "0100" => DATA_OUT <= R4;
|
||||
WHEN "0101" => DATA_OUT <= R5;
|
||||
WHEN "0110" => DATA_OUT <= R6;
|
||||
WHEN "0111" => DATA_OUT <= R7;
|
||||
WHEN "1000" => DATA_OUT <= R8;
|
||||
WHEN "1001" => DATA_OUT <= R9;
|
||||
WHEN "1010" => DATA_OUT <= R10;
|
||||
WHEN "1011" => DATA_OUT <= R11;
|
||||
WHEN "1100" => DATA_OUT <= R12;
|
||||
WHEN "1101" => DATA_OUT <= R13;
|
||||
WHEN "1110" => DATA_OUT <= IOA;
|
||||
WHEN "1111" => DATA_OUT <= IOB;
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
WR <= '0';
|
||||
else
|
||||
DATA_OUT <= "00000000";
|
||||
WR <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- LATCH WHAT REGISTER
|
||||
if ((BDIR = '1') and (BC2 = '1') and (BC1 = '1')) then
|
||||
REG_ADDR <= DATA_IN(3 downto 0);
|
||||
WR <= '0';
|
||||
end if;
|
||||
|
||||
-- WRITE TO REGISTER OR IOA/IOB
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0')) then WR <= '1'; end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0000") ) then R0 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0001") ) then R1 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0010") ) then R2 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0011") ) then R3 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0100") ) then R4 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0101") ) then R5 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0110") ) then R6 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0111") ) then R7 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1000") ) then R8 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1001") ) then R9 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1010") ) then R10 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1011") ) then R11 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1100") ) then R12 <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1101") ) then R13 <= DATA_IN; RST_ENV <= '1'; end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1110") ) then IOA <= DATA_IN;end if;
|
||||
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1111") ) then IOB <= DATA_IN;end if;
|
||||
|
||||
end PROCESS;
|
||||
|
||||
URA: PROCESS(REG_ADDR, RESET)
|
||||
BEGIN
|
||||
if (RESET = '1') then
|
||||
BUS_CS <= "0000000000000000";
|
||||
else
|
||||
case REG_ADDR is
|
||||
when "0000" => BUS_CS <= "0000000000000001";
|
||||
when "0001" => BUS_CS <= "0000000000000010";
|
||||
when "0010" => BUS_CS <= "0000000000000100";
|
||||
when "0011" => BUS_CS <= "0000000000001000";
|
||||
when "0100" => BUS_CS <= "0000000000010000";
|
||||
when "0101" => BUS_CS <= "0000000000100000";
|
||||
when "0110" => BUS_CS <= "0000000001000000";
|
||||
when "0111" => BUS_CS <= "0000000010000000";
|
||||
when "1000" => BUS_CS <= "0000000100000000";
|
||||
when "1001" => BUS_CS <= "0000001000000000";
|
||||
when "1010" => BUS_CS <= "0000010000000000";
|
||||
when "1011" => BUS_CS <= "0000100000000000";
|
||||
when "1100" => BUS_CS <= "0001000000000000";
|
||||
when "1101" => BUS_CS <= "0010000000000000";
|
||||
when "1110" => BUS_CS <= "0100000000000000";
|
||||
when "1111" => BUS_CS <= "1000000000000000";
|
||||
when others => NULL;
|
||||
end case;
|
||||
end if;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
-- Instantiation of sub_level modules
|
||||
UCLK : GEN_CLK PORT MAP( CLK => CLOCK,
|
||||
RST => RESET,
|
||||
CLK_16 => CLK_16,
|
||||
CLK_256 => CLK_256
|
||||
);
|
||||
|
||||
UTONE_A : TONE_GENERATOR PORT MAP( CLK => CLOCK,
|
||||
--CLK_TONE => CLK_16,
|
||||
RST => RESET,
|
||||
WR => WR,
|
||||
--CS_COARSE => BUS_CS(1),
|
||||
--CS_FINE => BUS_CS(0),
|
||||
DATA_COARSE => R1,
|
||||
DATA_FINE => R0,
|
||||
OUT_TONE => CLK_A);
|
||||
|
||||
UTONE_B : TONE_GENERATOR PORT MAP( CLK => CLOCK,
|
||||
--CLK_TONE => CLK_16,
|
||||
RST => RESET,
|
||||
WR => WR,
|
||||
--CS_COARSE => BUS_CS(3),
|
||||
--CS_FINE => BUS_CS(2),
|
||||
DATA_COARSE => R3,
|
||||
DATA_FINE => R2,
|
||||
OUT_TONE => CLK_B);
|
||||
|
||||
UTONE_C : TONE_GENERATOR PORT MAP( CLK => CLOCK,
|
||||
--CLK_TONE => CLK_16,
|
||||
RST => RESET,
|
||||
WR => WR,
|
||||
--CS_COARSE => BUS_CS(5),
|
||||
--CS_FINE => BUS_CS(4),
|
||||
DATA_COARSE => R5,
|
||||
DATA_FINE => R4,
|
||||
OUT_TONE => CLK_C);
|
||||
|
||||
UTONE_NOISE : NOISE_GENERATOR PORT MAP( CLK => CLK_16,
|
||||
RST => RESET,
|
||||
--WR => WR,
|
||||
--CS => BUS_CS(6),
|
||||
DATA => R6(4 downto 0),
|
||||
CLK_N => CLK_N);
|
||||
|
||||
UTONE_ENV : TONE_GENERATOR PORT MAP( CLK => CLK_16,
|
||||
--CLK => CLOCK,
|
||||
--CLK_TONE => CLK_256,
|
||||
RST => RESET,
|
||||
WR => WR,
|
||||
--CS_COARSE => BUS_CS(12),
|
||||
--CS_FINE => BUS_CS(11),
|
||||
DATA_COARSE => R12,
|
||||
DATA_FINE => R11,
|
||||
OUT_TONE => CLK_E);
|
||||
|
||||
--UMIXER : MIXER PORT MAP ( CLK => CLOCK,
|
||||
-- CS => BUS_CS(7),
|
||||
-- RST => RESET,
|
||||
-- WR => WR,
|
||||
-- IN_A => CLK_A,
|
||||
-- IN_B => CLK_B,
|
||||
-- IN_C => CLK_C,
|
||||
-- IN_NOISE => CLK_N,
|
||||
-- DATA => R7(5 downto 0),
|
||||
-- OUT_A => CLK_TONE_A,
|
||||
-- OUT_B => CLK_TONE_B,
|
||||
-- OUT_C => CLK_TONE_C);
|
||||
|
||||
UGenEnv : GEN_ENV PORT MAP( CLK_ENV => CLK_E,
|
||||
--CS => BUS_CS(13),
|
||||
DATA => R13(3 downto 0),
|
||||
RST_ENV => RST_ENV,
|
||||
WR => WR,
|
||||
OUT_DATA => OUT_AMPL_E);
|
||||
|
||||
UManAmpA : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
|
||||
CLK_DAC => CLOCK_DAC,
|
||||
CLK_TONE => CLK_A, --CLK_TONE_A,
|
||||
CLK_NOISE => CLK_N,
|
||||
RST => RESET,
|
||||
CLK_TONE_ENA => R7(0),
|
||||
CLK_NOISE_ENA => R7(3),
|
||||
AMPLITUDE => R8(4 downto 0),
|
||||
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
|
||||
OUT_DAC => IAnalogA );
|
||||
|
||||
UManAmpB : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
|
||||
CLK_DAC => CLOCK_DAC,
|
||||
CLK_TONE => CLK_B, --CLK_TONE_B,
|
||||
CLK_NOISE => CLK_N,
|
||||
RST => RESET,
|
||||
CLK_TONE_ENA => R7(1),
|
||||
CLK_NOISE_ENA => R7(4),
|
||||
AMPLITUDE => R9(4 downto 0),
|
||||
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
|
||||
OUT_DAC => IAnalogB );
|
||||
|
||||
UManAmpC : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
|
||||
CLK_DAC => CLOCK_DAC,
|
||||
CLK_TONE => CLK_C, --CLK_TONE_C,
|
||||
CLK_NOISE => CLK_N,
|
||||
RST => RESET,
|
||||
CLK_TONE_ENA => R7(2),
|
||||
CLK_NOISE_ENA => R7(5),
|
||||
AMPLITUDE => R10(4 downto 0),
|
||||
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
|
||||
OUT_DAC => IAnalogC );
|
||||
|
||||
|
||||
--PAD_ANALOGA : OBUF_F_24 port map( I => IAnalogA, O => AnalogA);
|
||||
--PAD_ANALOGB : OBUF_F_24 port map( I => IAnalogB, O => AnalogB);
|
||||
--PAD_ANALOGC : OBUF_F_24 port map( I => IAnalogC, O => AnalogC);
|
||||
AnalogA <= IAnalogA;
|
||||
AnalogB <= IAnalogB;
|
||||
AnalogC <= IAnalogC;
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,35 +0,0 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
@@ -1,2 +0,0 @@
|
||||
`define BUILD_DATE "180624"
|
||||
`define BUILD_TIME "130024"
|
||||
@@ -1,321 +0,0 @@
|
||||
--
|
||||
-- ctrlseq.vhd
|
||||
--
|
||||
-- Manage internal register
|
||||
--
|
||||
-- Copyright (C)2001 - 2005 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: ctrlseq.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- TODO :
|
||||
-- Remark :
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_arith.all;
|
||||
--use IEEE.numeric_std.all;
|
||||
|
||||
entity ctrlseq is
|
||||
port ( RESETn : in std_logic; -- RESET
|
||||
CLK_24 : in std_logic; -- 2 x CLOCK SYSTEM
|
||||
TXTHIR_DEC : in std_logic; -- TeXT HIRes DECode signal
|
||||
isAttrib : in std_logic; -- Is a attribute byte
|
||||
iRW : in std_logic; -- Read/Write signal from CPU
|
||||
CSRAMn : in std_logic; -- SELECT RAM (Active low)
|
||||
-- OUTPUTS
|
||||
CLK_1_CPU : out std_logic; -- CLK for CPU
|
||||
CLK_4 : out std_logic; -- CLK internal for VIA
|
||||
CLK_6 : out std_logic; -- CLK internal for video generation
|
||||
VA1L : out std_logic; -- VIDEO ADDRESS PHASE1 LATCH
|
||||
VA1R : out std_logic; -- VIDEO ADDRESS PHASE1 ROW
|
||||
VA1C : out std_logic; -- VIDEO ADDRESS PHASE1 COLUMN
|
||||
VA2L : out std_logic; -- VIDEO ADDRESS PHASE2 LATCH
|
||||
VA2R : out std_logic; -- VIDEO ADDRESS PHASE2 ROW
|
||||
VA2C : out std_logic; -- VIDEO ADDRESS PHASE2 COLUMN
|
||||
BAC : out std_logic; -- BUS ADDRESS COLUMN
|
||||
BAL : out std_logic; -- BUS ADDRESS LATCH
|
||||
RAS : out std_logic; -- RAS FOR DYNAMIC RAM
|
||||
CAS : out std_logic; -- CAS FOR DYNAMIC RAM
|
||||
MUX : out std_logic; -- MUX
|
||||
oRW : out std_logic; -- Output Read/Write
|
||||
ATTRIB_DEC : out std_logic; -- Decode attribute
|
||||
LD_REG_0 : out std_logic; -- Initialization of video register
|
||||
LD_REG : out std_logic; -- Load data into video register
|
||||
LDFROMBUS : out std_logic; -- Load data from data bus
|
||||
DATABUS_EN : out std_logic; -- Enable data bus
|
||||
-- ajout du 09/02/09
|
||||
BAOE : out std_logic; -- Output enable for ram/rom
|
||||
-- ajout du 03/04/09
|
||||
SRAM_CE : out std_logic; -- Chip select enable for SRAM
|
||||
SRAM_OE : out std_logic; -- Ouput enable for SRAM
|
||||
SRAM_WE : out std_logic; -- Write enable for SRAM =1 for a read cycle
|
||||
LATCH_SRAM : out std_logic; -- Latch data from SRAM for cpu
|
||||
-- FOR DEBUG/TESTBENCH
|
||||
c0_out : out std_logic;
|
||||
c1_out : out std_logic;
|
||||
c2_out : out std_logic;
|
||||
c3_out : out std_logic;
|
||||
c4_out : out std_logic;
|
||||
c5_out : out std_logic;
|
||||
c6_out : out std_logic;
|
||||
c7_out : out std_logic;
|
||||
CLK_12 : out std_logic;
|
||||
TB_CPT : out std_logic_vector(4 downto 0)
|
||||
);
|
||||
end entity ctrlseq;
|
||||
|
||||
architecture ctrlseq_arch of ctrlseq is
|
||||
|
||||
signal lCPT_GEN : std_logic_vector(4 downto 0); -- counter
|
||||
signal lstate : std_logic_vector(23 downto 0); -- states
|
||||
signal lreload : std_logic; -- to reload null value to lCPT_GEN
|
||||
signal lld_reg_p : std_logic; -- to load value into register for VIDEO
|
||||
|
||||
signal c_ras : std_logic; -- RAS
|
||||
signal c_cas : std_logic; -- CAS
|
||||
signal c_mux : std_logic; -- MUX
|
||||
signal c_clk_cpu : std_logic; -- CLK_CPU
|
||||
|
||||
-- Phase P0
|
||||
signal c_0 : std_logic; -- state number 0
|
||||
signal c_1 : std_logic; -- state number 1
|
||||
signal c_2 : std_logic; -- state number 2
|
||||
signal c_3 : std_logic; -- state number 3
|
||||
signal c_4 : std_logic; -- state number 4
|
||||
signal c_5 : std_logic; -- state number 5
|
||||
signal c_6 : std_logic; -- state number 6
|
||||
signal c_7 : std_logic; -- state number 7
|
||||
-- Phase P1
|
||||
signal c_8 : std_logic; -- state number 8
|
||||
signal c_9 : std_logic; -- state number 9
|
||||
signal c_10 : std_logic; -- state number 10
|
||||
signal c_11 : std_logic; -- state number 11
|
||||
signal c_12 : std_logic; -- state number 12
|
||||
signal c_13 : std_logic; -- state number 13
|
||||
signal c_14 : std_logic; -- state number 14
|
||||
signal c_15 : std_logic; -- state number 15
|
||||
-- Phase P2
|
||||
signal c_16 : std_logic; -- state number 16
|
||||
signal c_17 : std_logic; -- state number 17
|
||||
signal c_18 : std_logic; -- state number 18
|
||||
signal c_19 : std_logic; -- state number 19
|
||||
signal c_20 : std_logic; -- state number 20
|
||||
signal c_21 : std_logic; -- state number 21
|
||||
signal c_22 : std_logic; -- state number 22
|
||||
signal c_23 : std_logic; -- state number 23
|
||||
|
||||
signal p_0 : std_logic; -- phase number 0
|
||||
signal p_1 : std_logic; -- phase number 1
|
||||
signal p_2 : std_logic; -- phase number 2
|
||||
|
||||
-- Constants for states
|
||||
-- Phase P0
|
||||
constant cd_step_0 : integer :=0;
|
||||
constant cd_step_1 : integer :=1;
|
||||
constant cd_step_2 : integer :=2;
|
||||
constant cd_step_3 : integer :=3;
|
||||
constant cd_step_4 : integer :=4;
|
||||
constant cd_step_5 : integer :=5;
|
||||
constant cd_step_6 : integer :=6;
|
||||
constant cd_step_7 : integer :=7;
|
||||
-- Phase P1
|
||||
constant cd_step_8 : integer :=8;
|
||||
constant cd_step_9 : integer :=9;
|
||||
constant cd_step_10: integer :=10;
|
||||
constant cd_step_11: integer :=11;
|
||||
constant cd_step_12: integer :=12;
|
||||
constant cd_step_13: integer :=13;
|
||||
constant cd_step_14: integer :=14;
|
||||
constant cd_step_15: integer :=15;
|
||||
-- Phase P2
|
||||
constant cd_step_16: integer :=16;
|
||||
constant cd_step_17: integer :=17;
|
||||
constant cd_step_18: integer :=18;
|
||||
constant cd_step_19: integer :=19;
|
||||
constant cd_step_20: integer :=20;
|
||||
constant cd_step_21: integer :=21;
|
||||
constant cd_step_22: integer :=22;
|
||||
constant cd_step_23: integer :=23;
|
||||
|
||||
begin
|
||||
|
||||
-- Increment counter
|
||||
U_TB_CPT: PROCESS (RESETn, CLK_24)
|
||||
BEGIN
|
||||
if (RESETn = '0') then
|
||||
lCPT_GEN <= "00000";
|
||||
elsif falling_edge(clk_24) then
|
||||
if (lreload = '1') then
|
||||
lCPT_GEN <= "00000";
|
||||
else
|
||||
lCPT_GEN <= lCPT_GEN + "00001";
|
||||
end if;
|
||||
end if;
|
||||
END PROCESS;
|
||||
lreload <= '1' when lCPT_GEN = "10111" else '0';
|
||||
|
||||
-- Manage states
|
||||
U_SM_GEST: PROCESS(lCPT_GEN)
|
||||
BEGIN
|
||||
lstate <= "000000000000000000000000";
|
||||
case lCPT_GEN(4 downto 0) is
|
||||
-- Phase P0
|
||||
when "00000" => lstate(cd_step_0) <= '1';
|
||||
when "00001" => lstate(cd_step_1) <= '1';
|
||||
when "00010" => lstate(cd_step_2) <= '1';
|
||||
when "00011" => lstate(cd_step_3) <= '1';
|
||||
when "00100" => lstate(cd_step_4) <= '1';
|
||||
when "00101" => lstate(cd_step_5) <= '1';
|
||||
when "00110" => lstate(cd_step_6) <= '1';
|
||||
when "00111" => lstate(cd_step_7) <= '1';
|
||||
-- Phase P1
|
||||
when "01000" => lstate(cd_step_8) <= '1';
|
||||
when "01001" => lstate(cd_step_9) <= '1';
|
||||
when "01010" => lstate(cd_step_10) <= '1';
|
||||
when "01011" => lstate(cd_step_11) <= '1';
|
||||
when "01100" => lstate(cd_step_12) <= '1';
|
||||
when "01101" => lstate(cd_step_13) <= '1';
|
||||
when "01110" => lstate(cd_step_14) <= '1';
|
||||
when "01111" => lstate(cd_step_15) <= '1';
|
||||
-- Phase P2
|
||||
when "10000" => lstate(cd_step_16) <= '1';
|
||||
when "10001" => lstate(cd_step_17) <= '1';
|
||||
when "10010" => lstate(cd_step_18) <= '1';
|
||||
when "10011" => lstate(cd_step_19) <= '1';
|
||||
when "10100" => lstate(cd_step_20) <= '1';
|
||||
when "10101" => lstate(cd_step_21) <= '1';
|
||||
when "10110" => lstate(cd_step_22) <= '1';
|
||||
when "10111" => lstate(cd_step_23) <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
END PROCESS;
|
||||
|
||||
-- Assign states
|
||||
-- Phase P0
|
||||
c_0 <= lstate(cd_step_0);
|
||||
c_1 <= lstate(cd_step_1);
|
||||
c_2 <= lstate(cd_step_2);
|
||||
c_3 <= lstate(cd_step_3);
|
||||
c_4 <= lstate(cd_step_4);
|
||||
c_5 <= lstate(cd_step_5);
|
||||
c_6 <= lstate(cd_step_6);
|
||||
c_7 <= lstate(cd_step_7);
|
||||
-- Phase P1
|
||||
c_8 <= lstate(cd_step_8);
|
||||
c_9 <= lstate(cd_step_9);
|
||||
c_10 <= lstate(cd_step_10);
|
||||
c_11 <= lstate(cd_step_11);
|
||||
c_12 <= lstate(cd_step_12);
|
||||
c_13 <= lstate(cd_step_13);
|
||||
c_14 <= lstate(cd_step_14);
|
||||
c_15 <= lstate(cd_step_15);
|
||||
-- Phase P2
|
||||
c_16 <= lstate(cd_step_16);
|
||||
c_17 <= lstate(cd_step_17);
|
||||
c_18 <= lstate(cd_step_18);
|
||||
c_19 <= lstate(cd_step_19);
|
||||
c_20 <= lstate(cd_step_20);
|
||||
c_21 <= lstate(cd_step_21);
|
||||
c_22 <= lstate(cd_step_22);
|
||||
c_23 <= lstate(cd_step_23);
|
||||
|
||||
-- Three phases
|
||||
p_0 <= NOT lCPT_GEN(4) and NOT lCPT_GEN(3); -- 00
|
||||
p_1 <= NOT lCPT_GEN(4) and lCPT_GEN(3); -- 01
|
||||
p_2 <= lCPT_GEN(4) and NOT lCPT_GEN(3); -- 10
|
||||
|
||||
--------------------------------
|
||||
-- GENERATION DE LA CLOCK CPU --
|
||||
--------------------------------
|
||||
CLK_1_CPU <= p_2;
|
||||
|
||||
---------------------------------
|
||||
-- GESTION DE LA RAM DYNAMIQUE --
|
||||
---------------------------------
|
||||
ras <= c_2 or c_3 or c_4 or c_5 or c_10 or c_11 or c_12 or c_13 or c_18 or c_19 or c_20 or c_20;
|
||||
cas <= not (c_2 or c_3) and not (c_10 or c_11) and not (c_18 or c_19);
|
||||
-- Mux permet de slectionner soit l'adresse haute d'une adresse cpu
|
||||
-- soit l'adresse haute d'une adresse ula
|
||||
mux <= '1' when ((c_1 = '1' or c_2 = '1') and p_2 = '1') else '0';
|
||||
oRW <= iRW and p_2;
|
||||
|
||||
---------------------------------
|
||||
-- GESTION DE LA RAM STATIQUE --
|
||||
---------------------------------
|
||||
SRAM_OE <= not (c_2 or c_3) and not (c_10 or c_11) and not iRW ;
|
||||
SRAM_CE <= not (c_1 or c_2 or c_3 or c_4) and not (c_9 or c_10 or c_11 or c_12) AND (CSRAMn or not (c_19 or c_20));
|
||||
SRAM_WE <= CSRAMn or not (c_19 or c_20) or irW;
|
||||
LATCH_SRAM <= not c_4 and not c_12 and not c_20; -- le 19/12/2011 : Ajout not c_4 and c_12 à not c_20
|
||||
|
||||
---------------------
|
||||
-- GESTION INTERNE --
|
||||
---------------------
|
||||
|
||||
--Generation pour la gestion de l'adresse video 1
|
||||
VA1L <= '1' when (c_1='1') ELSE '0';
|
||||
--VA1R <= '1' when (c_1='1' or c_2='1') ELSE '0';
|
||||
VA1R <= '1' when (p_0='1') ELSE '0';
|
||||
VA1C <= '1' when (c_3='1' or c_4='1' or c_5='1') ELSE '0';
|
||||
|
||||
--Generation pour la gestion de l'adresse video 2
|
||||
VA2L <= '1' when (c_8='1') ELSE '0';
|
||||
--VA2R <= '1' when (c_8='1' or c_9='1') ELSE '0';
|
||||
VA2R <= '1' when (p_1='1') ELSE '0';
|
||||
VA2C <= '1' when (c_10='1' or c_11='1' or c_12='1') ELSE '0';
|
||||
|
||||
--Generation pour la gestion de l'adresse CPU
|
||||
BAL <= '1' when (c_17='1' or c_18='1' or c_19='1' or c_20='1' or c_21='1' or c_22='1' or c_23='1') ELSE '0';
|
||||
--Modif. du 22/02/09 BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1' and CSRAMn='0') ELSE '0';
|
||||
BAC <= '1' when (c_19='1' or c_20='1' or c_21='1') ELSE '0';
|
||||
-- Ajout du 09/02/09 : output enable pour la rom/ram lors de l'adressage par le CPU
|
||||
BAOE <= '1' when (c_18='1') ELSE '0';
|
||||
|
||||
--Pour la partie video
|
||||
-- 27/07/09 lld_reg_p <= NOT isAttrib and c_7 and NOT TXTHIR_DEC;
|
||||
-- 27/07/09 c_7 aurait du tre c_15 en ram dynamique
|
||||
-- 27/07/09 en ram statique :
|
||||
-- 11/11/09 Modif c_10 en c_11
|
||||
lld_reg_p <= not isAttrib and c_11 and NOT TXTHIR_DEC; -- Partie texte
|
||||
|
||||
-- 04/12/09 ATTRIB_DEC <= '1' when (isAttrib='1' and c_10='1') ELSE '0';
|
||||
--ATTRIB_DEC <= '1' when (c_4='1') ELSE '0';
|
||||
-- 04/12/09 LD_REG_0 <= '1' when (isAttrib='1' and c_15='1') ELSE '0';
|
||||
--LD_REG_0 <= '1' when (isAttrib='1' and c_11='1' and TXTHIR_DEC = '0') ELSE '0';
|
||||
-- 05/12/09 LD_REG <= '1' when (lld_reg_p='1' or c_4='1') ELSE '0';
|
||||
--LD_REG <= '1' when (lld_reg_p='1' or (c_4='1' and TXTHIR_DEC = '0')) ELSE '0';
|
||||
--DATABUS_EN <= '1' when (lld_reg_p='1' or c_3='1') ELSE '0';
|
||||
--LDFROMBUS <= '1' when (c_16='1') ELSE '0';
|
||||
|
||||
-- 15/12/2009 :
|
||||
ATTRIB_DEC <= '1' when (c_4='1') ELSE '0';
|
||||
DATABUS_EN <= '1' when (c_11='1' or c_3='1') ELSE '0';
|
||||
LD_REG_0 <= '1' when (isAttrib='1' and c_5='1') ELSE '0';
|
||||
LDFROMBUS <= '1' when ( (isAttrib='0' and c_12='1' and TXTHIR_DEC='0')
|
||||
or (isAttrib='0' and c_5 ='1' and TXTHIR_DEC='1')
|
||||
) ELSE '0';
|
||||
LD_REG <= '1' when (c_15='1') ELSE '0';
|
||||
|
||||
-- for TEST BENCH
|
||||
c0_OUT <= lstate(cd_step_0);
|
||||
c1_OUT <= lstate(cd_step_1);
|
||||
c2_OUT <= lstate(cd_step_2);
|
||||
c3_OUT <= lstate(cd_step_3);
|
||||
c4_OUT <= lstate(cd_step_4);
|
||||
c5_OUT <= lstate(cd_step_5);
|
||||
c6_OUT <= lstate(cd_step_6);
|
||||
c7_OUT <= lstate(cd_step_7);
|
||||
TB_CPT <= lCPT_GEN;
|
||||
CLK_12 <= lCPT_GEN(0);
|
||||
|
||||
-- for VIA 6522
|
||||
CLK_4 <= c_0 or c_1 or c_2
|
||||
or c_6 or c_7 or c_8
|
||||
or c_12 or c_13 or c_14
|
||||
or c_18 or c_19 or c_20;
|
||||
|
||||
-- for Video Generation
|
||||
CLK_6 <= c_0 or c_1 or c_4 or c_5 or c_8 or c_9 or c_12 or c_13 or c_16 or c_17 or c_20 or c_21;
|
||||
end architecture ctrlseq_arch;
|
||||
@@ -1,207 +0,0 @@
|
||||
--
|
||||
-- ctrlseq.vhd
|
||||
--
|
||||
-- Manage internal register
|
||||
--
|
||||
-- Copyright (C)2001 - 2005 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: ctrlseq.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- TODO :
|
||||
-- Remark :
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_arith.all;
|
||||
--use IEEE.numeric_std.all;
|
||||
|
||||
entity ctrlseq is
|
||||
port ( RESETn : in std_logic; -- RESET
|
||||
CLK_24 : in std_logic; -- 2 x CLOCK SYSTEM
|
||||
TXTHIR_DEC : in std_logic; -- TeXT HIRes DECode signal
|
||||
isAttrib : in std_logic; -- Is a attribute byte
|
||||
iRW : in std_logic; -- Read/Write signal from CPU
|
||||
CSRAMn : in std_logic; -- SELECT RAM (Active low)
|
||||
-- OUTPUTS
|
||||
CLK_1_CPU : out std_logic; -- CLK for CPU
|
||||
CLK_4 : out std_logic; -- CLK interne for ram statique
|
||||
VA1L : out std_logic; -- VIDEO ADDRESS PHASE1 LATCH
|
||||
VA1R : out std_logic; -- VIDEO ADDRESS PHASE1 ROW
|
||||
VA1C : out std_logic; -- VIDEO ADDRESS PHASE1 COLUMN
|
||||
VA2L : out std_logic; -- VIDEO ADDRESS PHASE2 LATCH
|
||||
VA2R : out std_logic; -- VIDEO ADDRESS PHASE2 ROW
|
||||
VA2C : out std_logic; -- VIDEO ADDRESS PHASE2 COLUMN
|
||||
BAC : out std_logic; -- BUS ADDRESS COLUMN
|
||||
BAL : out std_logic; -- BUS ADDRESS LATCH
|
||||
RAS : out std_logic; -- RAS FOR DYNAMIC RAM
|
||||
CAS : out std_logic; -- CAS FOR DYNAMIC RAM
|
||||
MUX : out std_logic; -- MUX
|
||||
oRW : out std_logic; -- Output Read/Write
|
||||
ATTRIB_DEC : out std_logic; -- Decode attribute
|
||||
LD_REG_0 : out std_logic; -- Initialization of video register
|
||||
LD_REG : out std_logic; -- Load data into video register
|
||||
LDFROMBUS : out std_logic; -- Load data from data bus
|
||||
DATABUS_EN : out std_logic; -- Enable data bus
|
||||
-- ajout du 09/02/09
|
||||
BAOE : out std_logic; -- Output enable for ram/rom
|
||||
-- FOR DEBUG/TESTBENCH
|
||||
c0_out : out std_logic;
|
||||
c1_out : out std_logic;
|
||||
c2_out : out std_logic;
|
||||
c3_out : out std_logic;
|
||||
c4_out : out std_logic;
|
||||
c5_out : out std_logic;
|
||||
c6_out : out std_logic;
|
||||
c7_out : out std_logic;
|
||||
CLK_12 : out std_logic;
|
||||
TB_CPT : out std_logic_vector(4 downto 0)
|
||||
);
|
||||
end entity ctrlseq;
|
||||
|
||||
architecture ctrlseq_arch of ctrlseq is
|
||||
|
||||
signal lCPT_GEN : std_logic_vector(4 downto 0); -- counter
|
||||
signal lstate : std_logic_vector(7 downto 0); -- states
|
||||
signal lreload : std_logic; -- to reload null value to lCPT_GEN
|
||||
signal lld_reg_p : std_logic; -- to load value into register for VIDEO
|
||||
|
||||
signal c_ras : std_logic; -- RAS
|
||||
signal c_cas : std_logic; -- CAS
|
||||
signal c_mux : std_logic; -- MUX
|
||||
signal c_clk_cpu : std_logic; -- CLK_CPU
|
||||
|
||||
signal c_0 : std_logic; -- state number 0
|
||||
signal c_1 : std_logic; -- state number 1
|
||||
signal c_2 : std_logic; -- state number 2
|
||||
signal c_3 : std_logic; -- state number 3
|
||||
signal c_4 : std_logic; -- state number 4
|
||||
signal c_5 : std_logic; -- state number 5
|
||||
signal c_6 : std_logic; -- state number 6
|
||||
signal c_7 : std_logic; -- state number 7
|
||||
|
||||
signal p_0 : std_logic; -- phase number 0
|
||||
signal p_1 : std_logic; -- phase number 1
|
||||
signal p_2 : std_logic; -- phase number 2
|
||||
|
||||
-- Constants for states
|
||||
constant cd_step_0 : integer :=0;
|
||||
constant cd_step_1 : integer :=1;
|
||||
constant cd_step_2 : integer :=2;
|
||||
constant cd_step_3 : integer :=3;
|
||||
constant cd_step_4 : integer :=4;
|
||||
constant cd_step_5 : integer :=5;
|
||||
constant cd_step_6 : integer :=6;
|
||||
constant cd_step_7 : integer :=7;
|
||||
|
||||
begin
|
||||
|
||||
-- Increment counter
|
||||
U_TB_CPT: PROCESS (RESETn, CLK_24)
|
||||
BEGIN
|
||||
if (RESETn = '0') then
|
||||
lCPT_GEN <= "00000";
|
||||
elsif falling_edge(clk_24) then
|
||||
if (lreload = '1') then
|
||||
lCPT_GEN <= "00000";
|
||||
else
|
||||
lCPT_GEN <= lCPT_GEN + "00001";
|
||||
end if;
|
||||
end if;
|
||||
END PROCESS;
|
||||
lreload <= '1' when lCPT_GEN = "10111" else '0';
|
||||
|
||||
-- Manage states
|
||||
U_SM_GEST: PROCESS(lCPT_GEN)
|
||||
BEGIN
|
||||
lstate <= "00000000";
|
||||
case lCPT_GEN(2 downto 0) is
|
||||
when "000" => lstate(cd_step_0) <= '1';
|
||||
when "001" => lstate(cd_step_1) <= '1';
|
||||
when "010" => lstate(cd_step_2) <= '1';
|
||||
when "011" => lstate(cd_step_3) <= '1';
|
||||
when "100" => lstate(cd_step_4) <= '1';
|
||||
when "101" => lstate(cd_step_5) <= '1';
|
||||
when "110" => lstate(cd_step_6) <= '1';
|
||||
when "111" => lstate(cd_step_7) <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
END PROCESS;
|
||||
|
||||
-- Assign states
|
||||
c_0 <= lstate(cd_step_0);
|
||||
c_1 <= lstate(cd_step_1);
|
||||
c_2 <= lstate(cd_step_2);
|
||||
c_3 <= lstate(cd_step_3);
|
||||
c_4 <= lstate(cd_step_4);
|
||||
c_5 <= lstate(cd_step_5);
|
||||
c_6 <= lstate(cd_step_6);
|
||||
c_7 <= lstate(cd_step_7);
|
||||
|
||||
-- Three phases
|
||||
p_0 <= NOT lCPT_GEN(4) and NOT lCPT_GEN(3); -- 00
|
||||
p_1 <= NOT lCPT_GEN(4) and lCPT_GEN(3); -- 01
|
||||
p_2 <= lCPT_GEN(4) and NOT lCPT_GEN(3); -- 10
|
||||
|
||||
--------------------------------
|
||||
-- GENERATION DE LA CLOCK CPU --
|
||||
--------------------------------
|
||||
CLK_1_CPU <= p_2;
|
||||
|
||||
---------------------------------
|
||||
-- GESTION DE LA RAM DYNAMIQUE --
|
||||
---------------------------------
|
||||
ras <= c_2 or c_3 or c_4 or c_5;
|
||||
cas <= not (c_2 or c_3) and (not p_2 or CSRAMn);
|
||||
-- Mux permet de sélectionner soit l'adresse haute d'une adresse cpu
|
||||
-- soit l'adresse haute d'une adresse ula
|
||||
mux <= '1' when ((c_1 = '1' or c_2 = '1') and p_2 = '1') else '0';
|
||||
oRW <= iRW and p_2;
|
||||
|
||||
---------------------
|
||||
-- GESTION INTERNE --
|
||||
---------------------
|
||||
|
||||
--Generation pour la gestion de l'adresse video 1
|
||||
VA1L <= '1' when (c_1='1' and p_0='1') ELSE '0';
|
||||
VA1R <= '1' when ((c_1='1' or c_2='1') and p_0='1') ELSE '0';
|
||||
VA1C <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_0='1') ELSE '0';
|
||||
|
||||
--Generation pour la gestion de l'adresse video 2
|
||||
VA2L <= '1' when (c_1='1' and p_1='1') ELSE '0';
|
||||
VA2R <= '1' when ((c_1='1' or c_2='1') and p_1='1') ELSE '0';
|
||||
VA2C <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_1='1') ELSE '0';
|
||||
|
||||
--Generation pour la gestion de l'adresse CPU
|
||||
BAL <= '1' when (c_1='1' and p_2='1') ELSE '0';
|
||||
--Modif. du 22/02/09 BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1' and CSRAMn='0') ELSE '0';
|
||||
BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1') ELSE '0';
|
||||
-- Ajout du 09/02/09 : output enable pour la rom/ram lors de l'adressage par le CPU
|
||||
BAOE <= '1' when (not(c_0='1' or c_1 ='1') and p_2='1') ELSE '0';
|
||||
|
||||
--Pour la partie video
|
||||
lld_reg_p <= NOT isAttrib and (c_7 and p_1) and NOT TXTHIR_DEC;
|
||||
|
||||
ATTRIB_DEC <= '1' when (isAttrib='1' and c_2='1' and p_1='1') ELSE '0';
|
||||
LD_REG_0 <= '1' when (isAttrib='1' and c_7='1' and p_1='1') ELSE '0';
|
||||
LD_REG <= '1' when (lld_reg_p='1' or (c_7='1' and p_0='1')) ELSE '0';
|
||||
DATABUS_EN <= '1' when (lld_reg_p='1' or (c_7='1' and p_0='1')) ELSE '0';
|
||||
LDFROMBUS <= '1' when (c_0='1' and p_2='1') ELSE '0';
|
||||
|
||||
-- for TEST BENCH
|
||||
c0_OUT <= lstate(cd_step_0);
|
||||
c1_OUT <= lstate(cd_step_1);
|
||||
c2_OUT <= lstate(cd_step_2);
|
||||
c3_OUT <= lstate(cd_step_3);
|
||||
c4_OUT <= lstate(cd_step_4);
|
||||
c5_OUT <= lstate(cd_step_5);
|
||||
c6_OUT <= lstate(cd_step_6);
|
||||
c7_OUT <= lstate(cd_step_7);
|
||||
TB_CPT <= lCPT_GEN;
|
||||
CLK_12 <= lCPT_GEN(0);
|
||||
|
||||
-- for ram statique
|
||||
CLK_4 <= c_6 or c_7;
|
||||
|
||||
end architecture ctrlseq_arch;
|
||||
@@ -1,65 +0,0 @@
|
||||
--
|
||||
-- DAC.vhd
|
||||
--
|
||||
-- Digital to analog convertor.
|
||||
--
|
||||
-- Copyright (C)2001 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: DAC.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- from XAPP154.pdf & XAPP154.ZIP (XILINX APPLICATION)
|
||||
--
|
||||
-- DAC 8 Bits ( method : sigma delta)
|
||||
-- 2^N clock to convert with N = width of input
|
||||
-- Ex : Bus 8 bits => 256 CLOCK master to convert an value.
|
||||
-- Theorem Shannon : 2 x Fmax x 256 =< 16 MHz => Fmax = 31250 Hz
|
||||
-- band of sound : 0 -> 20000 Hz : Ok !!
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity DAC is
|
||||
Port ( CLK_DAC : in std_logic;
|
||||
RST : in std_logic;
|
||||
IN_DAC : in std_logic_vector(7 downto 0);
|
||||
OUT_DAC : out std_logic );
|
||||
end DAC;
|
||||
|
||||
architecture Behavioral of DAC is
|
||||
|
||||
signal DeltaAdder : std_logic_vector(9 downto 0);
|
||||
signal SigmaAdder : std_logic_vector(9 downto 0);
|
||||
signal SigmaLatch : std_logic_vector(9 downto 0);
|
||||
signal DeltaB : std_logic_vector(9 downto 0);
|
||||
|
||||
begin
|
||||
PROCESS(SigmaLatch, DeltaB)
|
||||
BEGIN
|
||||
DeltaB <= TRANSPORT ( SigmaLatch(9) & SigmaLatch(9) & "00000000");
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(IN_DAC, DeltaB, DeltaAdder)
|
||||
BEGIN
|
||||
DeltaAdder <= IN_DAC + DeltaB;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(DeltaAdder, SigmaLatch)
|
||||
BEGIN
|
||||
SigmaAdder <= DeltaAdder + SigmaLatch;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(CLK_DAC, RST)
|
||||
BEGIN
|
||||
if (RST = '1') then
|
||||
SigmaLatch <= "0100000000";
|
||||
OUT_DAC <= '1';
|
||||
elsif (CLK_DAC'event and CLK_DAC = '1') then
|
||||
SigmaLatch <= SigmaAdder;
|
||||
OUT_DAC <= SigmaLatch(9);
|
||||
end if;
|
||||
END PROCESS;
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,44 +0,0 @@
|
||||
--
|
||||
-- GEN_CLK.vhd
|
||||
--
|
||||
-- GENERATOR of CLOCK.
|
||||
--
|
||||
-- Copyright (C)2001 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: GEN_CLK.vhd, v0.42 2002/01/03 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- Generate secondary CLK from CLK_MASTER
|
||||
-- CLK : Clock Master, 16 MHz
|
||||
-- CLK_16 : for the tone generator,
|
||||
-- CLK_256 : for the envelope generator
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity GEN_CLK is
|
||||
Port ( CLK : in std_logic;
|
||||
RST : in std_logic;
|
||||
CLK_16 : out std_logic;
|
||||
CLK_256 : out std_logic
|
||||
);
|
||||
end GEN_CLK;
|
||||
|
||||
architecture Behavioral of GEN_CLK is
|
||||
|
||||
SIGNAL COUNT : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
|
||||
PROCESS(CLK, RST)
|
||||
BEGIN
|
||||
if (RST = '1') then
|
||||
COUNT <= (OTHERS => '0');
|
||||
elsif (CLK'event and CLK = '1') then
|
||||
COUNT <= COUNT + 1;
|
||||
CLK_16 <= COUNT(3);
|
||||
CLK_256 <= COUNT(7);
|
||||
end if;
|
||||
END PROCESS;
|
||||
end Behavioral;
|
||||
@@ -1,111 +0,0 @@
|
||||
--
|
||||
-- GEN_ENV.vhd
|
||||
--
|
||||
-- GENERATOR of ENVELOPE.
|
||||
--
|
||||
-- Copyright (C)2001-2010 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: GEN_ENV.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- NO BUGS
|
||||
-- NEARLY TESTED
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- v0.4 2001/11/21 : Modification
|
||||
-- v0.46 2010/01/06 : Modification du générateur d'enveloppe
|
||||
-- et de fréquence
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity gen_env is
|
||||
Port ( CLK_ENV : in std_logic;
|
||||
DATA : in std_logic_vector(3 downto 0);
|
||||
RST_ENV : in std_logic;
|
||||
WR : in std_logic;
|
||||
--CS : in std_logic;
|
||||
OUT_DATA : inout std_logic_vector(3 downto 0) );
|
||||
end gen_env;
|
||||
|
||||
architecture Behavioral of gen_env is
|
||||
|
||||
SIGNAL DIR : std_logic; -- direction
|
||||
SIGNAL HOLD : std_logic; -- continue the sound
|
||||
|
||||
begin
|
||||
|
||||
PROCESS(CLK_ENV, RST_ENV, DATA, WR)
|
||||
variable isMin : boolean;
|
||||
variable isNearlyMin : boolean;
|
||||
variable isNearlyMax : boolean;
|
||||
variable isMax : boolean;
|
||||
BEGIN
|
||||
if (RST_ENV = '1') then -- Reset : to load the good value to generate enveloppe
|
||||
if (DATA(2) = '0') then -- front initial : 0 = descendant et 1 = montant
|
||||
OUT_DATA <= "1111";
|
||||
DIR <= '0';
|
||||
else
|
||||
OUT_DATA <= "0000";
|
||||
DIR <= '1';
|
||||
end if;
|
||||
HOLD <= '0';
|
||||
elsif (CLK_ENV'event and CLK_ENV = '1') then -- edge clock
|
||||
-- To simply the written code !
|
||||
isMin := (OUT_DATA = "00000");
|
||||
isNearlyMin := (OUT_DATA = "00001");
|
||||
isNearlyMax := (OUT_DATA = "11110");
|
||||
isMax := (OUT_DATA = "11111");
|
||||
|
||||
-- To manage the next value
|
||||
if (HOLD = '0') then
|
||||
if (DIR = '0') then
|
||||
OUT_DATA <= OUT_DATA - 1;
|
||||
else
|
||||
OUT_DATA <= OUT_DATA + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- To generate the shape of envelope
|
||||
if (DATA(3) = '0') then
|
||||
if (DIR = '0') then
|
||||
if (isNearlyMin) then
|
||||
HOLD <= '1';
|
||||
end if;
|
||||
else
|
||||
if (isMax) then
|
||||
HOLD <= '1'; -- Astuce : il faut que OUT_DATE = "0000" au prochain tick donc comparaison de la sortie sur "1111" car incrementation automatique
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
if (DATA(0) = '1') then -- hold = 1
|
||||
if (DIR = '0') then -- down
|
||||
if (DATA(1) = '1') then -- alt
|
||||
if isMin then HOLD <= '1'; end if;
|
||||
else
|
||||
if isNearlyMin then HOLD <= '1'; end if;
|
||||
end if;
|
||||
else
|
||||
if (DATA(1) = '1') then -- alt
|
||||
if isMax then HOLD <= '1'; end if;
|
||||
else
|
||||
if isNearlyMax then HOLD <= '1'; end if;
|
||||
end if;
|
||||
end if;
|
||||
elsif (DATA(1) = '1') then -- alternate
|
||||
if (DIR = '0') then -- down
|
||||
if isNearlyMin then HOLD <= '1'; end if;
|
||||
if isMin then HOLD <= '0'; DIR <= '1'; end if;
|
||||
else
|
||||
if isNearlyMax then HOLD <= '1'; end if;
|
||||
if isMax then HOLD <= '0'; DIR <= '0'; end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if; -- fin elsif
|
||||
END PROCESS;
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,29 +0,0 @@
|
||||
ADDRESS_ACLR_B=NONE
|
||||
ADDRESS_REG_B=CLOCK0
|
||||
CLOCK_ENABLE_INPUT_A=NORMAL
|
||||
CLOCK_ENABLE_INPUT_B=NORMAL
|
||||
CLOCK_ENABLE_OUTPUT_B=NORMAL
|
||||
INTENDED_DEVICE_FAMILY="Cyclone III"
|
||||
LPM_TYPE=altsyncram
|
||||
NUMWORDS_A=8
|
||||
NUMWORDS_B=8
|
||||
OPERATION_MODE=DUAL_PORT
|
||||
OUTDATA_ACLR_B=NONE
|
||||
OUTDATA_REG_B=CLOCK0
|
||||
POWER_UP_UNINITIALIZED=FALSE
|
||||
RDCONTROL_REG_B=CLOCK0
|
||||
READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
|
||||
WIDTHAD_A=3
|
||||
WIDTHAD_B=3
|
||||
WIDTH_A=1
|
||||
WIDTH_B=1
|
||||
WIDTH_BYTEENA_A=1
|
||||
DEVICE_FAMILY="Cyclone III"
|
||||
address_a
|
||||
address_b
|
||||
clock0
|
||||
clocken0
|
||||
data_a
|
||||
rden_b
|
||||
wren_a
|
||||
q_b
|
||||
@@ -1,454 +0,0 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2012-2013 Ludvig Strigeus
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
|
||||
`define BITS_TO_FIT(N) ( \
|
||||
N <= 2 ? 0 : \
|
||||
N <= 4 ? 1 : \
|
||||
N <= 8 ? 2 : \
|
||||
N <= 16 ? 3 : \
|
||||
N <= 32 ? 4 : \
|
||||
N <= 64 ? 5 : \
|
||||
N <= 128 ? 6 : \
|
||||
N <= 256 ? 7 : \
|
||||
N <= 512 ? 8 : \
|
||||
N <=1024 ? 9 : 10 )
|
||||
|
||||
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
wire [DWIDTH:0] out[2];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input [1:0] rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input [1:0] wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
|
||||
wire [DWIDTH:0] out[4];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
|
||||
(
|
||||
input clock,
|
||||
input [DWIDTH:0] data,
|
||||
input [AWIDTH:0] rdaddress,
|
||||
input [AWIDTH:0] wraddress,
|
||||
input wren,
|
||||
output [DWIDTH:0] q
|
||||
);
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (wraddress),
|
||||
.clock0 (clock),
|
||||
.data_a (data),
|
||||
.wren_a (wren),
|
||||
.address_b (rdaddress),
|
||||
.q_b(q),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_b ({(DWIDTH+1){1'b1}}),
|
||||
.eccstatus (),
|
||||
.q_a (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_b = "NONE",
|
||||
altsyncram_component.address_reg_b = "CLOCK0",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = NUMWORDS,
|
||||
altsyncram_component.numwords_b = NUMWORDS,
|
||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
||||
altsyncram_component.widthad_a = AWIDTH+1,
|
||||
altsyncram_component.widthad_b = AWIDTH+1,
|
||||
altsyncram_component.width_a = DWIDTH+1,
|
||||
altsyncram_component.width_b = DWIDTH+1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
endmodule
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module DiffCheck
|
||||
(
|
||||
input [17:0] rgb1,
|
||||
input [17:0] rgb2,
|
||||
output result
|
||||
);
|
||||
|
||||
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
|
||||
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
|
||||
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
|
||||
wire [6:0] t = $signed(r) + $signed(b);
|
||||
wire [6:0] gx = {g[5], g};
|
||||
wire [7:0] y = $signed(t) + $signed(gx);
|
||||
wire [6:0] u = $signed(r) - $signed(b);
|
||||
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
|
||||
|
||||
// if y is inside (-24..24)
|
||||
wire y_inside = (y < 8'h18 || y >= 8'he8);
|
||||
|
||||
// if u is inside (-4, 4)
|
||||
wire u_inside = (u < 7'h4 || u >= 7'h7c);
|
||||
|
||||
// if v is inside (-6, 6)
|
||||
wire v_inside = (v < 8'h6 || v >= 8'hfA);
|
||||
assign result = !(y_inside && u_inside && v_inside);
|
||||
endmodule
|
||||
|
||||
module InnerBlend
|
||||
(
|
||||
input [8:0] Op,
|
||||
input [5:0] A,
|
||||
input [5:0] B,
|
||||
input [5:0] C,
|
||||
output [5:0] O
|
||||
);
|
||||
|
||||
function [8:0] mul6x3;
|
||||
input [5:0] op1;
|
||||
input [2:0] op2;
|
||||
begin
|
||||
mul6x3 = 9'd0;
|
||||
if(op2[0]) mul6x3 = mul6x3 + op1;
|
||||
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
|
||||
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire OpOnes = Op[4];
|
||||
wire [8:0] Amul = mul6x3(A, Op[7:5]);
|
||||
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
|
||||
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
|
||||
wire [8:0] At = Amul;
|
||||
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
|
||||
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
|
||||
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
|
||||
assign O = Op[8] ? A : Res[9:4];
|
||||
endmodule
|
||||
|
||||
module Blend
|
||||
(
|
||||
input [5:0] rule,
|
||||
input disable_hq2x,
|
||||
input [17:0] E,
|
||||
input [17:0] A,
|
||||
input [17:0] B,
|
||||
input [17:0] D,
|
||||
input [17:0] F,
|
||||
input [17:0] H,
|
||||
output [17:0] Result
|
||||
);
|
||||
|
||||
reg [1:0] input_ctrl;
|
||||
reg [8:0] op;
|
||||
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
|
||||
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
|
||||
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
|
||||
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
|
||||
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
|
||||
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
|
||||
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
|
||||
localparam AB = 2'b00;
|
||||
localparam AD = 2'b01;
|
||||
localparam DB = 2'b10;
|
||||
localparam BD = 2'b11;
|
||||
wire is_diff;
|
||||
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
|
||||
|
||||
always @* begin
|
||||
case({!is_diff, rule[5:2]})
|
||||
1,17: {op, input_ctrl} = {BLEND1, AB};
|
||||
2,18: {op, input_ctrl} = {BLEND1, DB};
|
||||
3,19: {op, input_ctrl} = {BLEND1, BD};
|
||||
4,20: {op, input_ctrl} = {BLEND2, DB};
|
||||
5,21: {op, input_ctrl} = {BLEND2, AB};
|
||||
6,22: {op, input_ctrl} = {BLEND2, AD};
|
||||
|
||||
8: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
9: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
10: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
11: {op, input_ctrl} = {BLEND1, AB};
|
||||
12: {op, input_ctrl} = {BLEND1, AB};
|
||||
13: {op, input_ctrl} = {BLEND1, AB};
|
||||
14: {op, input_ctrl} = {BLEND1, DB};
|
||||
15: {op, input_ctrl} = {BLEND1, BD};
|
||||
|
||||
24: {op, input_ctrl} = {BLEND2, DB};
|
||||
25: {op, input_ctrl} = {BLEND5, DB};
|
||||
26: {op, input_ctrl} = {BLEND6, DB};
|
||||
27: {op, input_ctrl} = {BLEND2, DB};
|
||||
28: {op, input_ctrl} = {BLEND4, DB};
|
||||
29: {op, input_ctrl} = {BLEND5, DB};
|
||||
30: {op, input_ctrl} = {BLEND3, BD};
|
||||
31: {op, input_ctrl} = {BLEND3, DB};
|
||||
default: {op, input_ctrl} = 11'bx;
|
||||
endcase
|
||||
|
||||
// Setting op[8] effectively disables HQ2X because blend will always return E.
|
||||
if (disable_hq2x) op[8] = 1;
|
||||
end
|
||||
|
||||
// Generate inputs to the inner blender. Valid combinations.
|
||||
// 00: E A B
|
||||
// 01: E A D
|
||||
// 10: E D B
|
||||
// 11: E B D
|
||||
wire [17:0] Input1 = E;
|
||||
wire [17:0] Input2 = !input_ctrl[1] ? A :
|
||||
!input_ctrl[0] ? D : B;
|
||||
|
||||
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
|
||||
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
|
||||
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
|
||||
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
|
||||
endmodule
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
input clk,
|
||||
input ce_x4,
|
||||
input [DWIDTH:0] inputpixel,
|
||||
input mono,
|
||||
input disable_hq2x,
|
||||
input reset_frame,
|
||||
input reset_line,
|
||||
input [1:0] read_y,
|
||||
input [AWIDTH+1:0] read_x,
|
||||
output [DWIDTH:0] outpixel
|
||||
);
|
||||
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
|
||||
|
||||
wire [5:0] hqTable[256] = '{
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
|
||||
};
|
||||
|
||||
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
|
||||
reg [17:0] A, B, D, F, G, H;
|
||||
reg [7:0] pattern, nextpatt;
|
||||
reg [1:0] i;
|
||||
reg [7:0] y;
|
||||
|
||||
wire curbuf = y[0];
|
||||
reg prevbuf = 0;
|
||||
wire iobuf = !curbuf;
|
||||
|
||||
wire diff0, diff1;
|
||||
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
|
||||
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
|
||||
|
||||
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
|
||||
|
||||
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
|
||||
wire [17:0] blend_result;
|
||||
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
|
||||
|
||||
reg Curr2_addr1;
|
||||
reg [AWIDTH:0] Curr2_addr2;
|
||||
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
|
||||
wire [DWIDTH:0] Curr2tmp;
|
||||
|
||||
reg [AWIDTH:0] wrin_addr2;
|
||||
reg [DWIDTH:0] wrpix;
|
||||
reg wrin_en;
|
||||
|
||||
function [17:0] h2rgb;
|
||||
input [8:0] v;
|
||||
begin
|
||||
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [8:0] rgb2h;
|
||||
input [17:0] v;
|
||||
begin
|
||||
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(Curr2_addr2),
|
||||
.rdbuf(Curr2_addr1),
|
||||
.q(Curr2tmp),
|
||||
|
||||
.wraddr(wrin_addr2),
|
||||
.wrbuf(iobuf),
|
||||
.data(wrpix),
|
||||
.wren(wrin_en)
|
||||
);
|
||||
|
||||
reg [1:0] wrout_addr1;
|
||||
reg [AWIDTH+1:0] wrout_addr2;
|
||||
reg wrout_en;
|
||||
reg [DWIDTH:0] wrdata;
|
||||
|
||||
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(read_x),
|
||||
.rdbuf(read_y),
|
||||
.q(outpixel),
|
||||
|
||||
.wraddr(wrout_addr2),
|
||||
.wrbuf(wrout_addr1),
|
||||
.data(wrdata),
|
||||
.wren(wrout_en)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [AWIDTH:0] offs;
|
||||
reg old_reset_line;
|
||||
reg old_reset_frame;
|
||||
|
||||
wrout_en <= 0;
|
||||
wrin_en <= 0;
|
||||
|
||||
if(ce_x4) begin
|
||||
|
||||
pattern <= new_pattern;
|
||||
|
||||
if(~&offs) begin
|
||||
if (i == 0) begin
|
||||
Curr2_addr1 <= prevbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 1) begin
|
||||
Prev2 <= Curr2;
|
||||
Curr2_addr1 <= curbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 2) begin
|
||||
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
|
||||
wrpix <= inputpixel;
|
||||
wrin_addr2 <= offs;
|
||||
wrin_en <= 1;
|
||||
end
|
||||
if (i == 3) begin
|
||||
offs <= offs + 1'd1;
|
||||
end
|
||||
|
||||
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
|
||||
else wrdata <= blend_result;
|
||||
|
||||
wrout_addr1 <= {curbuf, i[1]};
|
||||
wrout_addr2 <= {offs, i[1]^i[0]};
|
||||
wrout_en <= 1;
|
||||
end
|
||||
|
||||
if(i==3) begin
|
||||
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
|
||||
{A, G} <= {Prev0, Next0};
|
||||
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
|
||||
{Prev0, Prev1} <= {Prev1, Prev2};
|
||||
{Curr0, Curr1} <= {Curr1, Curr2};
|
||||
{Next0, Next1} <= {Next1, Next2};
|
||||
end else begin
|
||||
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
|
||||
{B, F, H, D} <= {F, H, D, B};
|
||||
end
|
||||
|
||||
i <= i + 1'b1;
|
||||
if(old_reset_line && ~reset_line) begin
|
||||
old_reset_frame <= reset_frame;
|
||||
offs <= 0;
|
||||
i <= 0;
|
||||
y <= y + 1'd1;
|
||||
prevbuf <= curbuf;
|
||||
if(old_reset_frame & ~reset_frame) begin
|
||||
y <= 0;
|
||||
prevbuf <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
old_reset_line <= reset_line;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // Hq2x
|
||||
@@ -1,112 +0,0 @@
|
||||
--
|
||||
-- iodecode.vhd
|
||||
--
|
||||
-- Manage access for I/O, Ram and Rom
|
||||
--
|
||||
-- Copyright (C)2001 - 2005 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: iodecode.vhd, v0.10 2009/06/25 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- TODO :
|
||||
-- Remark :
|
||||
-- 08/03/09 : Retour en arrière
|
||||
Library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_STD.all;
|
||||
--use IEEE.std_logic_unsigned.all;
|
||||
|
||||
entity iodecode is
|
||||
port ( RESETn : in std_logic;
|
||||
CLK_1 : in std_logic;
|
||||
ADDR : in std_logic_vector(15 downto 0);
|
||||
ADDR_LE : in std_logic;
|
||||
MAPn : in std_logic;
|
||||
CSROMn : out std_logic;
|
||||
CSRAMn : out std_logic;
|
||||
CSIOn : out std_logic
|
||||
);
|
||||
end entity iodecode;
|
||||
|
||||
architecture iodecode_arch of iodecode is
|
||||
|
||||
signal lCSROMn : std_logic;
|
||||
signal lCSRAMn : std_logic;
|
||||
signal lCSIOn : std_logic;
|
||||
signal lADDR : std_logic_vector(15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Latch BAP
|
||||
u_laddr: PROCESS ( ADDR_LE, resetn )
|
||||
begin
|
||||
if (resetn = '0') then
|
||||
lADDR<= (OTHERS => '0');
|
||||
elsif rising_edge(ADDR_LE) then
|
||||
lAddr<= Addr;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- PAGE I/O : 0x300-0x3FF
|
||||
-- lCSIOn <= '0' WHEN (lADDR(7 downto 0) = "00000011") AND (CLK_1 = '1') ELSE '1';
|
||||
lCSIOn <= '0' WHEN (ADDR(15 downto 8) = "00000011") AND (ADDR_LE = '1') ELSE '1';
|
||||
--p_CSION : process(CLK_1)
|
||||
--begin
|
||||
-- lCSIOn <= '1';
|
||||
-- if (rising_edge(CLK_1)) then
|
||||
-- if (lADDR(7 downto 0) = "00000011") then
|
||||
-- lCSION <= '0';
|
||||
-- end if;
|
||||
-- end if;
|
||||
--end process;
|
||||
|
||||
-- PAGE ROM : 0xC000-0xFFFF
|
||||
-- lCSROMn <= '0' WHEN (lADDR(7 downto 6) = "11" AND MAPn = '1' AND CLK_1 = '1') ELSE '1'; p_CSION : process(CLK_1)
|
||||
lCSROMn <= '0' WHEN (ADDR(15 downto 14) = "11" AND MAPn = '1' AND ADDR_LE = '1') ELSE '1';
|
||||
--p_CSROMN : process(CLK_1)
|
||||
--begin
|
||||
-- lCSROMn <= '1';
|
||||
-- if (rising_edge(CLK_1)) then
|
||||
-- if (lADDR(7 downto 6) = "11" AND MAPn = '1') then
|
||||
-- lCSROMn <= '0';
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
-- PAGR RAM : le reste ...
|
||||
-- lCSRAMn <= '0' WHEN -- Partie Ram shadow
|
||||
-- (lADDR(7 downto 6) = "11" AND MAPn = '0' AND CLK_1 = '1')
|
||||
-- OR
|
||||
-- -- Partie Ram normale
|
||||
-- ( (lADDR(7 downto 0) /= "00000011" and lADDR(7 downto 6) /= "11")
|
||||
-- AND MAPn = '1' AND CLK_1 = '1')
|
||||
-- ELSE '1';
|
||||
lCSRAMn <= '0' WHEN -- Partie Ram shadow
|
||||
(ADDR(15 downto 14) = "11" AND MAPn = '0' AND ADDR_LE = '1')
|
||||
OR
|
||||
-- Partie Ram normale
|
||||
(((ADDR(15 downto 8) /= "00000011") AND (ADDR(15 downto 14) /= "11")) AND MAPn = '1' AND ADDR_LE = '1')
|
||||
ELSE '1';
|
||||
|
||||
--p_CSRAMN : process(CLK_1)
|
||||
--begin
|
||||
-- lCSRAMn <= '1';
|
||||
-- if (rising_edge(CLK_1)) then
|
||||
-- if ((lADDR(7 downto 6) = "11" AND MAPn = '0')
|
||||
-- OR ((lADDR(7 downto 0) /= "00000011" and lADDR(7 downto 6) /= "11")
|
||||
-- AND MAPn = '1')) then
|
||||
-- lCSRAMn <= '0';
|
||||
-- end if;
|
||||
-- end if;
|
||||
--end process;
|
||||
|
||||
-- Assign output signal
|
||||
CSROMn <= lCSROMn;
|
||||
CSRAMn <= lCSRAMn;
|
||||
CSIOn <= lCSIOn;
|
||||
|
||||
end architecture iodecode_arch;
|
||||
|
||||
|
||||
|
||||
@@ -1,109 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity keyboard is
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
RESET : in std_logic;
|
||||
|
||||
PS2CLK : in std_logic;
|
||||
PS2DATA : in std_logic;
|
||||
|
||||
COL : in std_logic_vector(2 downto 0);
|
||||
ROWbit : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end keyboard;
|
||||
|
||||
architecture arch of keyboard is
|
||||
|
||||
-- Gestion du protocole sur PS/2
|
||||
component ps2key is
|
||||
generic (
|
||||
FREQ : integer := 24
|
||||
);
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
RESET : in std_logic;
|
||||
|
||||
PS2CLK : in std_logic;
|
||||
PS2DATA : in std_logic;
|
||||
|
||||
BREAK : out std_logic;
|
||||
EXTENDED : out std_logic;
|
||||
CODE : out std_logic_vector(6 downto 0);
|
||||
LATCH : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
-- La matrice du clavier
|
||||
component keymatrix is
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
wROW : in std_logic_vector(2 downto 0);
|
||||
wCOL : in std_logic_vector(2 downto 0);
|
||||
wVAL : in std_logic;
|
||||
wEN : in std_logic;
|
||||
WE : in std_logic;
|
||||
|
||||
rCOL : in std_logic_vector(2 downto 0);
|
||||
rROWbit : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal MAT_wROW : std_logic_vector(2 downto 0);
|
||||
signal MAT_wCOL : std_logic_vector(2 downto 0);
|
||||
signal MAT_wVAL : std_logic;
|
||||
signal MAT_WE : std_logic;
|
||||
signal MAT_wEN : std_logic;
|
||||
|
||||
signal ROM_A : std_logic_vector(7 downto 0);
|
||||
|
||||
signal DISPLAY : std_logic_vector(15 downto 0);
|
||||
|
||||
|
||||
begin
|
||||
|
||||
PS2 : ps2key port map(
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
|
||||
PS2CLK => PS2CLK,
|
||||
PS2DATA => PS2DATA,
|
||||
|
||||
BREAK => MAT_wVAL,
|
||||
EXTENDED => ROM_A(7),
|
||||
CODE(0) => ROM_A(0),
|
||||
CODE(1) => ROM_A(1),
|
||||
CODE(2) => ROM_A(2),
|
||||
CODE(3) => ROM_A(3),
|
||||
CODE(4) => ROM_A(4),
|
||||
CODE(5) => ROM_A(5),
|
||||
CODE(6) => ROM_A(6),
|
||||
|
||||
LATCH => MAT_WE
|
||||
);
|
||||
|
||||
ROM : entity work.keymap port map(
|
||||
A => ROM_A,
|
||||
ROW => MAT_wROW,
|
||||
COL => MAT_wCOL,
|
||||
clk_sys => CLK,
|
||||
EN => MAT_wEN
|
||||
);
|
||||
|
||||
MAT : keymatrix port map(
|
||||
CLK => CLK,
|
||||
wROW => MAT_wROW,
|
||||
wCOL => MAT_wCOL,
|
||||
wVAL => MAT_wVAL,
|
||||
wEN => MAT_wEN,
|
||||
WE => MAT_WE,
|
||||
|
||||
rCOL => COL,
|
||||
rROWbit => ROWbit
|
||||
);
|
||||
|
||||
end arch;
|
||||
@@ -1,30 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity keyboardX is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
RESET : in std_logic;
|
||||
PS2CLK : in std_logic;
|
||||
PS2DATA : in std_logic_vector( 7 downto 0);
|
||||
COL : in std_logic_vector(2 downto 0);
|
||||
ROWbit : out std_logic_vector( 7 downto 0)
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of keyboardX is
|
||||
|
||||
begin
|
||||
|
||||
CLKp: PROCESS ( CLK )
|
||||
begin
|
||||
if (RESET = '0') then
|
||||
COL<= (OTHERS => '0');
|
||||
ROWbit<= (OTHERS => '0');
|
||||
elsif rising_edge(CLK) then
|
||||
---
|
||||
end if;
|
||||
end process;
|
||||
end RTL;
|
||||
@@ -1,180 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity keymap is
|
||||
port(
|
||||
A : in std_logic_vector(7 downto 0);
|
||||
clk_sys: in std_logic;
|
||||
ROW : out std_logic_vector(2 downto 0);
|
||||
COL : out std_logic_vector(2 downto 0);
|
||||
EN : out std_logic
|
||||
);
|
||||
end keymap;
|
||||
|
||||
architecture arch of keymap is
|
||||
begin
|
||||
|
||||
ROM256X1_ROW2 : entity work.sprom
|
||||
generic map
|
||||
(
|
||||
init_file => "roms/key1.hex",
|
||||
widthad_a => 8,
|
||||
width_a => 1
|
||||
)
|
||||
port map
|
||||
(
|
||||
clock => clk_sys,
|
||||
address => A,
|
||||
q(0) => ROW(2)
|
||||
);
|
||||
|
||||
-- ROWS
|
||||
|
||||
-- ROM256X1_ROW2 : ROM256X1
|
||||
-- generic map (
|
||||
-- INIT => X"00140800000000000000000000000000004000402E3400000000004E7C760000")
|
||||
-- port map (
|
||||
-- q => ROW(2), -- ROM output
|
||||
-- address => A
|
||||
-- );
|
||||
|
||||
ROM256X1_ROW1 : entity work.sprom
|
||||
generic map
|
||||
(
|
||||
init_file => "roms/key2.hex",
|
||||
widthad_a => 8,
|
||||
width_a => 1
|
||||
)
|
||||
port map
|
||||
(
|
||||
clock => clk_sys,
|
||||
address => A,
|
||||
q(0) => ROW(1)
|
||||
);
|
||||
|
||||
-- ROM256X1_ROW1 : ROM256X1
|
||||
-- generic map (
|
||||
-- INIT => X"00340000000000000000000000000000000000002834763000146C7E68200000")
|
||||
-- port map (
|
||||
-- q => ROW(1), -- ROM output
|
||||
-- address => A
|
||||
-- );
|
||||
|
||||
ROM256X1_ROW0 : entity work.sprom
|
||||
generic map
|
||||
(
|
||||
init_file => "roms/key3.hex",
|
||||
widthad_a => 8,
|
||||
width_a => 1
|
||||
)
|
||||
port map
|
||||
(
|
||||
clock => clk_sys,
|
||||
address => A,
|
||||
q(0) => ROW(0)
|
||||
);
|
||||
|
||||
-- ROM256X1_ROW0 : ROM256X1
|
||||
-- generic map (
|
||||
-- INIT => X"003008000000000000000000000000000040004004346C4A004A1C7A34400000")
|
||||
-- port map (
|
||||
-- q => ROW(0), -- ROM output
|
||||
-- address => A -- ROM address
|
||||
-- );
|
||||
|
||||
-- COLUMNS
|
||||
|
||||
ROM256X1_COL2 : entity work.sprom
|
||||
generic map
|
||||
(
|
||||
init_file => "roms/key4.hex",
|
||||
widthad_a => 8,
|
||||
width_a => 1
|
||||
)
|
||||
port map
|
||||
(
|
||||
clock => clk_sys,
|
||||
address => A,
|
||||
q(0) => COL(2)
|
||||
);
|
||||
|
||||
-- ROM256X1_COL2 : ROM256X1
|
||||
-- generic map (
|
||||
-- INIT => X"00340800000000000000000000000000000000400E302E3A5038021038060000")
|
||||
-- port map (
|
||||
-- q => COL(2), -- ROM output
|
||||
-- address => A -- ROM address[7]
|
||||
-- );
|
||||
|
||||
ROM256X1_COL1 : entity work.sprom
|
||||
generic map
|
||||
(
|
||||
init_file => "roms/key5.hex",
|
||||
widthad_a => 8,
|
||||
width_a => 1
|
||||
)
|
||||
port map
|
||||
(
|
||||
clock => clk_sys,
|
||||
address => A,
|
||||
q(0) => COL(1)
|
||||
);
|
||||
|
||||
-- ROM256X1_COL1 : ROM256X1
|
||||
-- generic map (
|
||||
-- INIT => X"000000000000000000000000000000000000000026245C64447C00327C100000")
|
||||
-- port map (
|
||||
-- q => COL(1), -- ROM output
|
||||
-- address => A -- ROM address[7]
|
||||
-- );
|
||||
|
||||
ROM256X1_COL0 : entity work.sprom
|
||||
generic map
|
||||
(
|
||||
init_file => "roms/key6.hex",
|
||||
widthad_a => 8,
|
||||
width_a => 1
|
||||
)
|
||||
port map
|
||||
(
|
||||
clock => clk_sys,
|
||||
address => A,
|
||||
q(0) => COL(0)
|
||||
);
|
||||
|
||||
-- ROM256X1_COL0 : ROM256X1
|
||||
-- generic map (
|
||||
-- INIT => X"00000000000000000000000000000000004000402E347C7C5800380800220000")
|
||||
-- port map (
|
||||
-- q => COL(0), -- ROM output
|
||||
-- address => A -- ROM address[7]
|
||||
-- );
|
||||
|
||||
-- ENABLE
|
||||
|
||||
ROM256X1_EN : entity work.sprom
|
||||
generic map
|
||||
(
|
||||
init_file => "roms/key7.hex",
|
||||
widthad_a => 8,
|
||||
width_a => 1
|
||||
)
|
||||
port map
|
||||
(
|
||||
clock => clk_sys,
|
||||
address => A,
|
||||
q(0) => EN
|
||||
);
|
||||
|
||||
-- ROM256X1_EN : ROM256X1
|
||||
-- generic map (
|
||||
-- INIT => X"00340800000000000000000000000000004000402E347E7E7C7E7E7E7C760000")
|
||||
-- port map (
|
||||
-- q => EN, -- ROM output
|
||||
-- address => A -- ROM address[7]
|
||||
-- );
|
||||
|
||||
end arch;
|
||||
|
||||
@@ -1,102 +0,0 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity keymatrix is
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
wROW : in std_logic_vector(2 downto 0);
|
||||
wCOL : in std_logic_vector(2 downto 0);
|
||||
wVAL : in std_logic;
|
||||
wEN : in std_logic;
|
||||
WE : in std_logic;
|
||||
|
||||
rCOL : in std_logic_vector(2 downto 0);
|
||||
rROWbit : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end keymatrix;
|
||||
|
||||
architecture arch of keymatrix is
|
||||
signal WEi : std_logic_vector(7 downto 0);
|
||||
|
||||
-- inutilise
|
||||
signal SPOi : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
WEi(0) <= WE when wEN = '1' and wROW = "000" else '0';
|
||||
WEi(1) <= WE when wEN = '1' and wROW = "001" else '0';
|
||||
WEi(2) <= WE when wEN = '1' and wROW = "010" else '0';
|
||||
WEi(3) <= WE when wEN = '1' and wROW = "011" else '0';
|
||||
WEi(4) <= WE when wEN = '1' and wROW = "100" else '0';
|
||||
WEi(5) <= WE when wEN = '1' and wROW = "101" else '0';
|
||||
WEi(6) <= WE when wEN = '1' and wROW = "110" else '0';
|
||||
WEi(7) <= WE when wEN = '1' and wROW = "111" else '0';
|
||||
|
||||
|
||||
--ROWBit : for i in 0 to 7 generate
|
||||
-- RAM16X1D_ROWBit : RAM16X1D
|
||||
-- generic map (
|
||||
-- INIT => X"FFFF")
|
||||
-- port map (
|
||||
|
||||
-- D => wVAL, -- Write 1-bit data input---------------------------data
|
||||
|
||||
-- SPO => SPOi(i), -- R/W 1-bit data output for A0-A3
|
||||
|
||||
-- A0 => wCOL(0), -- R/W address[0] input bit--------------------------waddress
|
||||
-- A1 => wCOL(1), -- R/W address[1] input bit
|
||||
-- A2 => wCOL(2), -- R/W address[2] input bit
|
||||
-- A3 => '0', -- R/W ddress[3] input bit
|
||||
|
||||
|
||||
-- DPO => rROWBit(i), -- Read-only 1-bit data output for DPRA--------------q
|
||||
|
||||
|
||||
-- DPRA0 => rCOL(0), -- Read-only address[0] input bit--------------------------raddress
|
||||
-- DPRA1 => rCOL(1), -- Read-only address[1] input bit
|
||||
-- DPRA2 => rCOL(2), -- Read-only address[2] input bit
|
||||
-- DPRA3 => '0', -- Read-only address[3] input bit
|
||||
|
||||
|
||||
|
||||
-- WCLK => CLK, -- Write clock input-----------------------------------clock
|
||||
-- WE => WEi(i) -- Write enable input----------------------------------wren
|
||||
-- );
|
||||
--end generate;
|
||||
|
||||
ROWBit : for i in 0 to 7 generate
|
||||
RAM16X1D_ROWBit : entity work.RAM8X1D
|
||||
-- generic map (
|
||||
-- INIT => X"FFFF")
|
||||
port map (
|
||||
|
||||
data(0) => wVAL, -- Write 1-bit data input---------------------------data
|
||||
|
||||
enable => SPOi(i), -- R/W 1-bit data output for A0-A3
|
||||
wraddress => wCOL,
|
||||
-- A0 => wCOL(0), -- R/W address[0] input bit--------------------------waddress
|
||||
-- A1 => wCOL(1), -- R/W address[1] input bit
|
||||
-- A2 => wCOL(2), -- R/W address[2] input bit
|
||||
-- A3 => '0', -- R/W ddress[3] input bit
|
||||
|
||||
|
||||
-- rden => rROWBit(i), -- Read-only 1-bit data output for DPRA--------------q
|
||||
|
||||
rdaddress => rCOL,
|
||||
-- DPRA0 => rCOL(0), -- Read-only address[0] input bit--------------------------raddress
|
||||
-- DPRA1 => rCOL(1), -- Read-only address[1] input bit
|
||||
-- DPRA2 => rCOL(2), -- Read-only address[2] input bit
|
||||
-- DPRA3 => '0', -- Read-only address[3] input bit
|
||||
|
||||
|
||||
clock => CLK,
|
||||
-- WCLK => CLK, -- Write clock input-----------------------------------clock
|
||||
wren => WEi(i) -- Write enable input----------------------------------wren
|
||||
);
|
||||
end generate;
|
||||
|
||||
|
||||
end arch;
|
||||
|
||||
@@ -1,886 +0,0 @@
|
||||
--
|
||||
-- A simulation model of VIC20 hardware
|
||||
-- Copyright (c) MikeJ - March 2003
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email vic20@fpgaarcade.com
|
||||
--
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 002 fix from Mark McDougall, untested
|
||||
-- version 001 initial release
|
||||
-- not very sure about the shift register, documentation is a bit light.
|
||||
|
||||
library ieee ;
|
||||
use ieee.std_logic_1164.all ;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity M6522 is
|
||||
port (
|
||||
|
||||
I_RS : in std_logic_vector(3 downto 0);
|
||||
I_DATA : in std_logic_vector(7 downto 0);
|
||||
O_DATA : out std_logic_vector(7 downto 0);
|
||||
O_DATA_OE_L : out std_logic;
|
||||
|
||||
I_RW_L : in std_logic;
|
||||
I_CS1 : in std_logic;
|
||||
I_CS2_L : in std_logic;
|
||||
|
||||
O_IRQ_L : out std_logic; -- note, not open drain
|
||||
-- port a
|
||||
I_CA1 : in std_logic;
|
||||
I_CA2 : in std_logic;
|
||||
O_CA2 : out std_logic;
|
||||
O_CA2_OE_L : out std_logic;
|
||||
|
||||
I_PA : in std_logic_vector(7 downto 0);
|
||||
O_PA : out std_logic_vector(7 downto 0);
|
||||
O_PA_OE_L : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- port b
|
||||
I_CB1 : in std_logic;
|
||||
O_CB1 : out std_logic;
|
||||
O_CB1_OE_L : out std_logic;
|
||||
|
||||
I_CB2 : in std_logic;
|
||||
O_CB2 : out std_logic;
|
||||
O_CB2_OE_L : out std_logic;
|
||||
|
||||
I_PB : in std_logic_vector(7 downto 0);
|
||||
O_PB : out std_logic_vector(7 downto 0);
|
||||
O_PB_OE_L : out std_logic_vector(7 downto 0);
|
||||
|
||||
I_P2_H : in std_logic; -- high for phase 2 clock ____----__
|
||||
RESET_L : in std_logic;
|
||||
ENA_4 : in std_logic; -- clk enable
|
||||
CLK : in std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of M6522 is
|
||||
|
||||
signal phase : std_logic_vector(1 downto 0);
|
||||
signal p2_h_t1 : std_logic;
|
||||
signal cs : std_logic;
|
||||
|
||||
-- registers
|
||||
signal r_ddra : std_logic_vector(7 downto 0);
|
||||
signal r_ora : std_logic_vector(7 downto 0);
|
||||
signal r_ira : std_logic_vector(7 downto 0);
|
||||
|
||||
signal r_ddrb : std_logic_vector(7 downto 0);
|
||||
signal r_orb : std_logic_vector(7 downto 0);
|
||||
signal r_irb : std_logic_vector(7 downto 0);
|
||||
|
||||
signal r_t1l_l : std_logic_vector(7 downto 0);
|
||||
signal r_t1l_h : std_logic_vector(7 downto 0);
|
||||
signal r_t2l_l : std_logic_vector(7 downto 0);
|
||||
signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip
|
||||
signal r_sr : std_logic_vector(7 downto 0);
|
||||
signal r_acr : std_logic_vector(7 downto 0);
|
||||
signal r_pcr : std_logic_vector(7 downto 0);
|
||||
signal r_ifr : std_logic_vector(7 downto 0);
|
||||
signal r_ier : std_logic_vector(6 downto 0);
|
||||
|
||||
signal sr_write_ena : boolean;
|
||||
signal sr_read_ena : boolean;
|
||||
signal ifr_write_ena : boolean;
|
||||
signal ier_write_ena : boolean;
|
||||
signal clear_irq : std_logic_vector(7 downto 0);
|
||||
signal load_data : std_logic_vector(7 downto 0);
|
||||
|
||||
-- timer 1
|
||||
signal t1c : std_logic_vector(15 downto 0);
|
||||
signal t1c_active : boolean;
|
||||
signal t1c_done : boolean;
|
||||
signal t1_w_reset_int : boolean;
|
||||
signal t1_r_reset_int : boolean;
|
||||
signal t1_load_counter : boolean;
|
||||
signal t1_reload_counter : boolean;
|
||||
signal t1_toggle : std_logic;
|
||||
signal t1_irq : std_logic := '0';
|
||||
|
||||
-- timer 2
|
||||
signal t2c : std_logic_vector(15 downto 0);
|
||||
signal t2c_active : boolean;
|
||||
signal t2c_done : boolean;
|
||||
signal t2_pb6 : std_logic;
|
||||
signal t2_pb6_t1 : std_logic;
|
||||
signal t2_w_reset_int : boolean;
|
||||
signal t2_r_reset_int : boolean;
|
||||
signal t2_load_counter : boolean;
|
||||
signal t2_reload_counter : boolean;
|
||||
signal t2_irq : std_logic := '0';
|
||||
signal t2_sr_ena : boolean;
|
||||
|
||||
-- shift reg
|
||||
signal sr_cnt : std_logic_vector(3 downto 0);
|
||||
signal sr_cb1_oe_l : std_logic;
|
||||
signal sr_cb1_out : std_logic;
|
||||
signal sr_drive_cb2 : std_logic;
|
||||
signal sr_strobe : std_logic;
|
||||
signal sr_strobe_t1 : std_logic;
|
||||
signal sr_strobe_falling : boolean;
|
||||
signal sr_strobe_rising : boolean;
|
||||
signal sr_irq : std_logic;
|
||||
signal sr_out : std_logic;
|
||||
signal sr_off_delay : std_logic;
|
||||
|
||||
-- io
|
||||
signal w_orb_hs : std_logic;
|
||||
signal w_ora_hs : std_logic;
|
||||
signal r_irb_hs : std_logic;
|
||||
signal r_ira_hs : std_logic;
|
||||
|
||||
signal ca_hs_sr : std_logic;
|
||||
signal ca_hs_pulse : std_logic;
|
||||
signal cb_hs_sr : std_logic;
|
||||
signal cb_hs_pulse : std_logic;
|
||||
|
||||
signal cb1_in_mux : std_logic;
|
||||
signal ca1_ip_reg : std_logic;
|
||||
signal cb1_ip_reg : std_logic;
|
||||
signal ca1_int : boolean;
|
||||
signal cb1_int : boolean;
|
||||
signal ca1_irq : std_logic;
|
||||
signal cb1_irq : std_logic;
|
||||
|
||||
signal ca2_ip_reg : std_logic;
|
||||
signal cb2_ip_reg : std_logic;
|
||||
signal ca2_int : boolean;
|
||||
signal cb2_int : boolean;
|
||||
signal ca2_irq : std_logic;
|
||||
signal cb2_irq : std_logic;
|
||||
|
||||
signal final_irq : std_logic;
|
||||
begin
|
||||
|
||||
p_phase : process
|
||||
begin
|
||||
-- internal clock phase
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_4 = '1') then
|
||||
p2_h_t1 <= I_P2_H;
|
||||
if (p2_h_t1 = '0') and (I_P2_H = '1') then
|
||||
phase <= "11";
|
||||
else
|
||||
phase <= phase + "1";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_cs : process(I_CS1, I_CS2_L, I_P2_H)
|
||||
begin
|
||||
cs <= '0';
|
||||
if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then
|
||||
cs <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- peripheral control reg (pcr)
|
||||
-- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge)
|
||||
-- 3..1 ca2 operation
|
||||
-- 000 input -ve edge
|
||||
-- 001 independend interrupt input -ve edge
|
||||
-- 010 input +ve edge
|
||||
-- 011 independend interrupt input +ve edge
|
||||
-- 100 handshake output
|
||||
-- 101 pulse output
|
||||
-- 110 low output
|
||||
-- 111 high output
|
||||
-- 7..4 as 3..0 for cb1,cb2
|
||||
|
||||
-- auxiliary control reg (acr)
|
||||
-- 0 input latch PA (0 disable, 1 enable)
|
||||
-- 1 input latch PB (0 disable, 1 enable)
|
||||
-- 4..2 shift reg control
|
||||
-- 000 disable
|
||||
-- 001 shift in using t2
|
||||
-- 010 shift in using o2
|
||||
-- 011 shift in using ext clk
|
||||
-- 100 shift out free running t2 rate
|
||||
-- 101 shift out using t2
|
||||
-- 101 shift out using o2
|
||||
-- 101 shift out using ext clk
|
||||
-- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6)
|
||||
-- 7..6 t1 timer control
|
||||
-- 00 timed interrupt each time t1 is loaded pb7 disable
|
||||
-- 01 continuous interrupts pb7 disable
|
||||
-- 00 timed interrupt each time t1 is loaded pb7 one shot output
|
||||
-- 01 continuous interrupts pb7 square wave output
|
||||
--
|
||||
|
||||
p_write_reg_reset : process(RESET_L, CLK)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
r_ora <= x"00"; r_orb <= x"00";
|
||||
r_ddra <= x"00"; r_ddrb <= x"00";
|
||||
r_acr <= x"00"; r_pcr <= x"00";
|
||||
|
||||
w_orb_hs <= '0';
|
||||
w_ora_hs <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA_4 = '1') then
|
||||
w_orb_hs <= '0';
|
||||
w_ora_hs <= '0';
|
||||
if (cs = '1') and (I_RW_L = '0') then
|
||||
case I_RS is
|
||||
when x"0" => r_orb <= I_DATA; w_orb_hs <= '1';
|
||||
when x"1" => r_ora <= I_DATA; w_ora_hs <= '1';
|
||||
when x"2" => r_ddrb <= I_DATA;
|
||||
when x"3" => r_ddra <= I_DATA;
|
||||
|
||||
when x"B" => r_acr <= I_DATA;
|
||||
when x"C" => r_pcr <= I_DATA;
|
||||
when x"F" => r_ora <= I_DATA;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
if (r_acr(7) = '1') and (t1_toggle = '1') then
|
||||
r_orb(7) <= not r_orb(7); -- toggle
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_write_reg : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_4 = '1') then
|
||||
t1_w_reset_int <= false;
|
||||
t1_load_counter <= false;
|
||||
|
||||
t2_w_reset_int <= false;
|
||||
t2_load_counter <= false;
|
||||
|
||||
load_data <= x"00";
|
||||
sr_write_ena <= false;
|
||||
ifr_write_ena <= false;
|
||||
ier_write_ena <= false;
|
||||
|
||||
if (cs = '1') and (I_RW_L = '0') then
|
||||
load_data <= I_DATA;
|
||||
case I_RS is
|
||||
when x"4" => r_t1l_l <= I_DATA;
|
||||
when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
|
||||
t1_load_counter <= true;
|
||||
|
||||
when x"6" => r_t1l_l <= I_DATA;
|
||||
when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true;
|
||||
|
||||
when x"8" => r_t2l_l <= I_DATA;
|
||||
when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true;
|
||||
t2_load_counter <= true;
|
||||
|
||||
when x"A" => sr_write_ena <= true;
|
||||
when x"D" => ifr_write_ena <= true;
|
||||
when x"E" => ier_write_ena <= true;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_oe : process(cs, I_RW_L)
|
||||
begin
|
||||
O_DATA_OE_L <= '1';
|
||||
if (cs = '1') and (I_RW_L = '1') then
|
||||
O_DATA_OE_L <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l,
|
||||
r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb)
|
||||
begin
|
||||
t1_r_reset_int <= false;
|
||||
t2_r_reset_int <= false;
|
||||
sr_read_ena <= false;
|
||||
r_irb_hs <= '0';
|
||||
r_ira_hs <= '0';
|
||||
O_DATA <= x"00"; -- default
|
||||
if (cs = '1') and (I_RW_L = '1') then
|
||||
case I_RS is
|
||||
--when x"0" => O_DATA <= r_irb; r_irb_hs <= '1';
|
||||
-- fix from Mark McDougall, untested
|
||||
when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1';
|
||||
when x"1" => O_DATA <= r_ira; r_ira_hs <= '1';
|
||||
when x"2" => O_DATA <= r_ddrb;
|
||||
when x"3" => O_DATA <= r_ddra;
|
||||
when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true;
|
||||
when x"5" => O_DATA <= t1c(15 downto 8);
|
||||
when x"6" => O_DATA <= r_t1l_l;
|
||||
when x"7" => O_DATA <= r_t1l_h;
|
||||
when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true;
|
||||
when x"9" => O_DATA <= t2c(15 downto 8);
|
||||
when x"A" => O_DATA <= r_sr; sr_read_ena <= true;
|
||||
when x"B" => O_DATA <= r_acr;
|
||||
when x"C" => O_DATA <= r_pcr;
|
||||
when x"D" => O_DATA <= r_ifr;
|
||||
when x"E" => O_DATA <= ('0' & r_ier);
|
||||
when x"F" => O_DATA <= r_ira;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
--
|
||||
-- IO
|
||||
--
|
||||
p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1)
|
||||
begin
|
||||
-- if the shift register is enabled, cb1 may be an output
|
||||
-- in this case, we should listen to the CB1_OUT for the interrupt
|
||||
if (sr_cb1_oe_l = '1') then
|
||||
cb1_in_mux <= I_CB1;
|
||||
else
|
||||
cb1_in_mux <= sr_cb1_out;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux)
|
||||
begin
|
||||
if (r_pcr(0) = '0') then -- ca1 control
|
||||
-- negative edge
|
||||
ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0');
|
||||
else
|
||||
-- positive edge
|
||||
ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1');
|
||||
end if;
|
||||
|
||||
if (r_pcr(4) = '0') then -- cb1 control
|
||||
-- negative edge
|
||||
cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0');
|
||||
else
|
||||
-- positive edge
|
||||
cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1');
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2)
|
||||
begin
|
||||
ca2_int <= false;
|
||||
if (r_pcr(3) = '0') then -- ca2 input
|
||||
if (r_pcr(2) = '0') then -- ca2 edge
|
||||
-- negative edge
|
||||
ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0');
|
||||
else
|
||||
-- positive edge
|
||||
ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1');
|
||||
end if;
|
||||
end if;
|
||||
|
||||
cb2_int <= false;
|
||||
if (r_pcr(7) = '0') then -- cb2 input
|
||||
if (r_pcr(6) = '0') then -- cb2 edge
|
||||
-- negative edge
|
||||
cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0');
|
||||
else
|
||||
-- positive edge
|
||||
cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_ca2_cb2 : process(RESET_L, CLK)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
O_CA2 <= '0';
|
||||
O_CA2_OE_L <= '1';
|
||||
O_CB2 <= '0';
|
||||
O_CB2_OE_L <= '1';
|
||||
|
||||
ca_hs_sr <= '0';
|
||||
ca_hs_pulse <= '0';
|
||||
cb_hs_sr <= '0';
|
||||
cb_hs_pulse <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA_4 = '1') then
|
||||
-- ca
|
||||
if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then
|
||||
ca_hs_sr <= '1';
|
||||
elsif ca1_int then
|
||||
ca_hs_sr <= '0';
|
||||
end if;
|
||||
|
||||
if (phase = "00") then
|
||||
ca_hs_pulse <= w_ora_hs or r_ira_hs;
|
||||
end if;
|
||||
|
||||
O_CA2_OE_L <= not r_pcr(3); -- ca2 output
|
||||
case r_pcr(3 downto 1) is
|
||||
when "000" => O_CA2 <= '0'; -- input
|
||||
when "001" => O_CA2 <= '0'; -- input
|
||||
when "010" => O_CA2 <= '0'; -- input
|
||||
when "011" => O_CA2 <= '0'; -- input
|
||||
when "100" => O_CA2 <= not (ca_hs_sr); -- handshake
|
||||
when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse
|
||||
when "110" => O_CA2 <= '0'; -- low
|
||||
when "111" => O_CA2 <= '1'; -- high
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
-- cb
|
||||
if (phase = "00") and (w_orb_hs = '1') then
|
||||
cb_hs_sr <= '1';
|
||||
elsif cb1_int then
|
||||
cb_hs_sr <= '0';
|
||||
end if;
|
||||
|
||||
if (phase = "00") then
|
||||
cb_hs_pulse <= w_orb_hs;
|
||||
end if;
|
||||
|
||||
O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial
|
||||
if (sr_drive_cb2 = '1') then -- serial output
|
||||
O_CB2 <= sr_out;
|
||||
else
|
||||
case r_pcr(7 downto 5) is
|
||||
when "000" => O_CB2 <= '0'; -- input
|
||||
when "001" => O_CB2 <= '0'; -- input
|
||||
when "010" => O_CB2 <= '0'; -- input
|
||||
when "011" => O_CB2 <= '0'; -- input
|
||||
when "100" => O_CB2 <= not (cb_hs_sr); -- handshake
|
||||
when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse
|
||||
when "110" => O_CB2 <= '0'; -- low
|
||||
when "111" => O_CB2 <= '1'; -- high
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
O_CB1 <= sr_cb1_out;
|
||||
O_CB1_OE_L <= sr_cb1_oe_l;
|
||||
|
||||
p_ca_cb_irq : process(RESET_L, CLK)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
ca1_irq <= '0';
|
||||
ca2_irq <= '0';
|
||||
cb1_irq <= '0';
|
||||
cb2_irq <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA_4 = '1') then
|
||||
-- not pretty
|
||||
if ca1_int then
|
||||
ca1_irq <= '1';
|
||||
elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then
|
||||
ca1_irq <= '0';
|
||||
end if;
|
||||
|
||||
if ca2_int then
|
||||
ca2_irq <= '1';
|
||||
else
|
||||
if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or
|
||||
(clear_irq(0) = '1') then
|
||||
ca2_irq <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if cb1_int then
|
||||
cb1_irq <= '1';
|
||||
elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then
|
||||
cb1_irq <= '0';
|
||||
end if;
|
||||
|
||||
if cb2_int then
|
||||
cb2_irq <= '1';
|
||||
else
|
||||
if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or
|
||||
(clear_irq(3) = '1') then
|
||||
cb2_irq <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_input_reg : process(RESET_L, CLK)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
ca1_ip_reg <= '0';
|
||||
cb1_ip_reg <= '0';
|
||||
|
||||
ca2_ip_reg <= '0';
|
||||
cb2_ip_reg <= '0';
|
||||
|
||||
r_ira <= x"00";
|
||||
r_irb <= x"00";
|
||||
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA_4 = '1') then
|
||||
-- we have a fast clock, so we can have input registers
|
||||
ca1_ip_reg <= I_CA1;
|
||||
cb1_ip_reg <= cb1_in_mux;
|
||||
|
||||
ca2_ip_reg <= I_CA2;
|
||||
cb2_ip_reg <= I_CB2;
|
||||
|
||||
if (r_acr(0) = '0') then
|
||||
r_ira <= I_PA;
|
||||
else -- enable latching
|
||||
if ca1_int then
|
||||
r_ira <= I_PA;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if (r_acr(1) = '0') then
|
||||
r_irb <= I_PB;
|
||||
else -- enable latching
|
||||
if cb1_int then
|
||||
r_irb <= I_PB;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb)
|
||||
begin
|
||||
-- data direction reg (ddr) 0 = input, 1 = output
|
||||
O_PA <= r_ora;
|
||||
O_PA_OE_L <= not r_ddra;
|
||||
|
||||
if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well
|
||||
O_PB_OE_L(7) <= '0'; -- an output if under t1 control
|
||||
else
|
||||
O_PB_OE_L(7) <= not (r_ddrb(7));
|
||||
end if;
|
||||
|
||||
O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0);
|
||||
O_PB <= r_orb;
|
||||
|
||||
end process;
|
||||
--
|
||||
-- Timer 1
|
||||
--
|
||||
p_timer1_done : process
|
||||
variable done : boolean;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_4 = '1') then
|
||||
done := (t1c = x"0000");
|
||||
t1c_done <= done and (phase = "11");
|
||||
if (phase = "11") then
|
||||
t1_reload_counter <= done and (r_acr(6) = '1');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_timer1 : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_4 = '1') then
|
||||
if t1_load_counter or (t1_reload_counter and phase = "11") then
|
||||
t1c( 7 downto 0) <= r_t1l_l;
|
||||
t1c(15 downto 8) <= r_t1l_h;
|
||||
elsif (phase="11") then
|
||||
t1c <= t1c - "1";
|
||||
end if;
|
||||
|
||||
if t1_load_counter or t1_reload_counter then
|
||||
t1c_active <= true;
|
||||
elsif t1c_done then
|
||||
t1c_active <= false;
|
||||
end if;
|
||||
|
||||
t1_toggle <= '0';
|
||||
if t1c_active and t1c_done then
|
||||
t1_toggle <= '1';
|
||||
t1_irq <= '1';
|
||||
elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then
|
||||
t1_irq <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
-- Timer2
|
||||
--
|
||||
p_timer2_pb6_input : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_4 = '1') then
|
||||
if (phase = "01") then -- leading edge p2_h
|
||||
t2_pb6 <= I_PB(6);
|
||||
t2_pb6_t1 <= t2_pb6;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_timer2_done : process
|
||||
variable done : boolean;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_4 = '1') then
|
||||
done := (t2c = x"0000");
|
||||
t2c_done <= done and (phase = "11");
|
||||
if (phase = "11") then
|
||||
t2_reload_counter <= done;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_timer2 : process
|
||||
variable ena : boolean;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_4 = '1') then
|
||||
if (r_acr(5) = '0') then
|
||||
ena := true;
|
||||
else
|
||||
ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge
|
||||
end if;
|
||||
|
||||
if t2_load_counter or (t2_reload_counter and phase = "11") then
|
||||
-- not sure if t2c_reload should be here. Does timer2 just continue to
|
||||
-- count down, or is it reloaded ? Reloaded makes more sense if using
|
||||
-- it to generate a clock for the shift register.
|
||||
t2c( 7 downto 0) <= r_t2l_l;
|
||||
t2c(15 downto 8) <= r_t2l_h;
|
||||
else
|
||||
if (phase="11") and ena then -- or count mode
|
||||
t2c <= t2c - "1";
|
||||
end if;
|
||||
end if;
|
||||
|
||||
t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11");
|
||||
|
||||
if t2_load_counter then
|
||||
t2c_active <= true;
|
||||
elsif t2c_done then
|
||||
t2c_active <= false;
|
||||
end if;
|
||||
|
||||
|
||||
if t2c_active and t2c_done then
|
||||
t2_irq <= '1';
|
||||
elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then
|
||||
t2_irq <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
-- Shift Register
|
||||
--
|
||||
p_sr : process(RESET_L, CLK)
|
||||
variable dir_out : std_logic;
|
||||
variable ena : std_logic;
|
||||
variable cb1_op : std_logic;
|
||||
variable cb1_ip : std_logic;
|
||||
variable use_t2 : std_logic;
|
||||
variable free_run : std_logic;
|
||||
variable sr_count_ena : boolean;
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
r_sr <= x"00";
|
||||
sr_drive_cb2 <= '0';
|
||||
sr_cb1_oe_l <= '1';
|
||||
sr_cb1_out <= '0';
|
||||
sr_strobe <= '1';
|
||||
sr_cnt <= "0000";
|
||||
sr_irq <= '0';
|
||||
sr_out <= '1';
|
||||
sr_off_delay <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA_4 = '1') then
|
||||
-- decode mode
|
||||
dir_out := r_acr(4); -- output on cb2
|
||||
cb1_op := '0';
|
||||
cb1_ip := '0';
|
||||
use_t2 := '0';
|
||||
free_run := '0';
|
||||
|
||||
case r_acr(4 downto 2) is
|
||||
when "000" => ena := '0';
|
||||
when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1';
|
||||
when "010" => ena := '1'; cb1_op := '1';
|
||||
when "011" => ena := '1'; cb1_ip := '1';
|
||||
when "100" => ena := '1'; use_t2 := '1'; free_run := '1';
|
||||
when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1';
|
||||
when "110" => ena := '1';
|
||||
when "111" => ena := '1'; cb1_ip := '1';
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
-- clock select
|
||||
if (ena = '0') then
|
||||
sr_strobe <= '1';
|
||||
else
|
||||
if (cb1_ip = '1') then
|
||||
sr_strobe <= I_CB1;
|
||||
else
|
||||
if (sr_cnt(3) = '0') and (free_run = '0') then
|
||||
sr_strobe <= '1';
|
||||
else
|
||||
if ((use_t2 = '1') and t2_sr_ena) or
|
||||
((use_t2 = '0') and (phase = "00")) then
|
||||
sr_strobe <= not sr_strobe;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- latch on rising edge, shift on falling edge
|
||||
if sr_write_ena then
|
||||
r_sr <= load_data;
|
||||
elsif (ena = '1') then -- use shift reg
|
||||
|
||||
if (dir_out = '0') then
|
||||
-- input
|
||||
if (sr_cnt(3) = '1') or (cb1_ip = '1') then
|
||||
if sr_strobe_rising then
|
||||
r_sr(0) <= I_CB2;
|
||||
elsif sr_strobe_falling then
|
||||
r_sr(7 downto 1) <= r_sr(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
sr_out <= '1';
|
||||
else
|
||||
-- output
|
||||
if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then
|
||||
if sr_strobe_falling then
|
||||
r_sr(7 downto 1) <= r_sr(6 downto 0);
|
||||
r_sr(0) <= r_sr(7);
|
||||
sr_out <= r_sr(7);
|
||||
end if;
|
||||
else
|
||||
sr_out <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
sr_count_ena := sr_strobe_rising;
|
||||
|
||||
if sr_write_ena or sr_read_ena then
|
||||
-- some documentation says sr bit in IFR must be set as well ?
|
||||
sr_cnt <= "1000";
|
||||
elsif sr_count_ena and (sr_cnt(3) = '1') then
|
||||
sr_cnt <= sr_cnt + "1";
|
||||
end if;
|
||||
|
||||
if (phase = "00") then
|
||||
sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out
|
||||
end if;
|
||||
|
||||
if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then
|
||||
sr_irq <= '1';
|
||||
elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then
|
||||
sr_irq <= '0';
|
||||
end if;
|
||||
|
||||
-- assign ops
|
||||
sr_drive_cb2 <= dir_out;
|
||||
sr_cb1_oe_l <= not cb1_op;
|
||||
sr_cb1_out <= sr_strobe;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_sr_strobe_rise_fall : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA_4 = '1') then
|
||||
sr_strobe_t1 <= sr_strobe;
|
||||
sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1');
|
||||
sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0');
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
-- Interrupts
|
||||
--
|
||||
p_ier : process(RESET_L, CLK)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
r_ier <= "0000000";
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA_4 = '1') then
|
||||
if ier_write_ena then
|
||||
if (load_data(7) = '1') then
|
||||
-- set
|
||||
r_ier <= r_ier or load_data(6 downto 0);
|
||||
else
|
||||
-- clear
|
||||
r_ier <= r_ier and not load_data(6 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq,
|
||||
cb1_irq, cb2_irq)
|
||||
begin
|
||||
r_ifr(7) <= final_irq;
|
||||
r_ifr(6) <= t1_irq;
|
||||
r_ifr(5) <= t2_irq;
|
||||
r_ifr(4) <= cb1_irq;
|
||||
r_ifr(3) <= cb2_irq;
|
||||
r_ifr(2) <= sr_irq;
|
||||
r_ifr(1) <= ca1_irq;
|
||||
r_ifr(0) <= ca2_irq;
|
||||
|
||||
O_IRQ_L <= not final_irq;
|
||||
end process;
|
||||
|
||||
p_irq : process(RESET_L, CLK)
|
||||
begin
|
||||
if (RESET_L = '0') then
|
||||
final_irq <= '0';
|
||||
elsif rising_edge(CLK) then
|
||||
if (ENA_4 = '1') then
|
||||
if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then
|
||||
final_irq <= '0'; -- no interrupts
|
||||
else
|
||||
final_irq <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_clear_irq : process(ifr_write_ena, load_data)
|
||||
begin
|
||||
clear_irq <= x"00";
|
||||
if ifr_write_ena then
|
||||
clear_irq <= load_data;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture RTL;
|
||||
@@ -1,95 +0,0 @@
|
||||
--
|
||||
-- MANAGE_AMPLITUDE.vhd
|
||||
--
|
||||
-- Manage the amplitude for each tone.
|
||||
--
|
||||
-- Copyright (C)2001-2010 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: MANAGE_AMPLITUDE.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity MANAGE_AMPLITUDE is
|
||||
Port ( CLK : in std_logic; -- the system clock
|
||||
CLK_DAC : in std_logic; -- the clok of DAC
|
||||
CLK_TONE : in std_logic; -- the frequency of sound
|
||||
CLK_NOISE : in std_logic; -- the noise
|
||||
RST : in std_logic; -- reset
|
||||
CLK_TONE_ENA : in std_logic; -- enable tone
|
||||
CLK_NOISE_ENA : in std_logic; -- enable noise
|
||||
AMPLITUDE : in std_logic_vector(4 downto 0); -- value from register
|
||||
AMPLITUDE_E : in std_logic_vector(3 downto 0); -- value from envelope
|
||||
OUT_DAC : out std_logic );
|
||||
end MANAGE_AMPLITUDE;
|
||||
|
||||
architecture Behavioral of MANAGE_AMPLITUDE is
|
||||
|
||||
signal AMPLITUDE_TMP : std_logic_vector(3 downto 0);
|
||||
signal IN_DATA : std_logic_vector(7 downto 0);
|
||||
|
||||
COMPONENT DAC is Port ( CLK_DAC : in std_logic;
|
||||
RST : in std_logic;
|
||||
IN_DAC : in std_logic_vector(7 downto 0);
|
||||
OUT_DAC : out std_logic );
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- Convertisseur numérique analogique : méthode sigma delta
|
||||
U_DAC : DAC PORT MAP ( CLK_DAC => CLK_DAC,
|
||||
RST => RST,
|
||||
IN_DAC => IN_DATA,
|
||||
OUT_DAC => OUT_DAC);
|
||||
|
||||
-- Calcule de l'amplitude à générer par le DAC
|
||||
PROCESS(CLK, RST, AMPLITUDE_TMP, AMPLITUDE_E)
|
||||
variable mix_tone_noise : std_logic;
|
||||
BEGIN
|
||||
if (RST = '1') then -- reset
|
||||
AMPLITUDE_TMP <= "0000";
|
||||
IN_DATA <= "00000000";
|
||||
elsif (CLK'event and CLK = '1') then -- edge clock
|
||||
-- Note that this means that if both tone and noise are disabled, the output */
|
||||
-- is 1, not 0, and can be modulated changing the volume. */
|
||||
mix_tone_noise := (CLK_TONE or CLK_TONE_ENA) AND (CLK_NOISE or CLK_NOISE_ENA);
|
||||
if (mix_tone_noise = '1') then
|
||||
if (AMPLITUDE(4) = '0') then -- Utilisation de la valeur du registre
|
||||
AMPLITUDE_TMP <= AMPLITUDE(3 downto 0);
|
||||
else -- Utilisation de la valeur de l'enveloppe
|
||||
AMPLITUDE_TMP <= AMPLITUDE_E;
|
||||
end if;
|
||||
else
|
||||
AMPLITUDE_TMP <= "0000";
|
||||
end if;
|
||||
|
||||
-- Each amplitude has an 1.5 db step from previous amplitude
|
||||
CASE AMPLITUDE_TMP IS
|
||||
when "0000" => IN_DATA <= "00000000"; -- 0
|
||||
when "0001" => IN_DATA <= "00010110"; -- 22
|
||||
when "0010" => IN_DATA <= "00011010"; -- 26
|
||||
when "0011" => IN_DATA <= "00011111"; -- 31
|
||||
when "0100" => IN_DATA <= "00100101"; -- 37
|
||||
when "0101" => IN_DATA <= "00101100"; -- 44
|
||||
when "0110" => IN_DATA <= "00110100"; -- 52
|
||||
when "0111" => IN_DATA <= "00111110"; -- 62
|
||||
when "1000" => IN_DATA <= "01001010"; -- 74
|
||||
when "1001" => IN_DATA <= "01011000"; -- 88
|
||||
when "1010" => IN_DATA <= "01101001"; -- 105
|
||||
when "1011" => IN_DATA <= "01110101"; -- 125
|
||||
when "1100" => IN_DATA <= "10011001"; -- 149
|
||||
when "1101" => IN_DATA <= "10110001"; -- 177
|
||||
when "1110" => IN_DATA <= "11010010"; -- 210
|
||||
when "1111" => IN_DATA <= "11111111"; -- 255
|
||||
when OTHERS => NULL;
|
||||
END CASE;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,78 +0,0 @@
|
||||
--
|
||||
-- memmap.vhd
|
||||
--
|
||||
-- Manage offset for read ula
|
||||
--
|
||||
-- Copyright (C)2001 - 2005 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: memmap.vhd, v0.02 2005/01/01 00:00:00 SEILEBOST $
|
||||
--
|
||||
-- TODO :
|
||||
-- Remark :
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.std_logic_unsigned.all;
|
||||
--use IEEE.std_logic_arith.all;
|
||||
--use IEEE.numeric_std.all;
|
||||
|
||||
entity memmap is
|
||||
port ( TXTHIR_SEL : in std_logic;
|
||||
DBLHGT_SEL : in std_logic;
|
||||
FORCETXT : in std_logic;
|
||||
CPT_H : in std_logic_vector(6 downto 0);
|
||||
CPT_V : in std_logic_vector(8 downto 0);
|
||||
VAP1 : out std_logic_vector(15 downto 0);
|
||||
CHROWCNT : out std_logic_vector(2 downto 0);
|
||||
TXTHIR_DEC : out std_logic
|
||||
);
|
||||
end entity memmap;
|
||||
|
||||
architecture memmap_arch of memmap is
|
||||
|
||||
signal lDBLHGT_EN : std_logic; -- ENABLE DOUBLE HEIGT
|
||||
signal lTXTHIR_DEC : std_logic; -- MODE TEXT / HIRES
|
||||
signal lCPT_V_TMP : std_logic_vector(8 downto 0); -- VERTICAL COUNTER
|
||||
signal lCPT_V_8_TMP : std_logic_vector(8 downto 0); -- VERTICAL COUNTER DIVIDE OR NOT BY 8
|
||||
signal lVAP1 : std_logic_vector(12 downto 0); -- VIDEO ADDRESS PHASE 1
|
||||
signal lOFFSCR : std_logic_vector(15 downto 0); -- OFFSET SCREEN
|
||||
signal ltmpBy10 : std_logic_vector(12 downto 0); -- Using to mult by 10
|
||||
|
||||
|
||||
begin
|
||||
-- local signal
|
||||
lTXTHIR_DEC <= (TXTHIR_SEL and FORCETXT);
|
||||
lDBLHGT_EN <= (DBLHGT_SEL and lTXTHIR_DEC);
|
||||
|
||||
-- Compute video adress phase 1
|
||||
lCPT_V_TMP <= '0'&CPT_V(8 downto 1) when lDBLHGT_EN = '1' else CPT_V(8 downto 0);
|
||||
|
||||
-- divide by 8 if necessary : erreur sur la manière de diviser par 8? 03/02/2010
|
||||
--lCPT_V_8_TMP <= lCPT_V_TMP when lTXTHIR_DEC = '1' else lCPT_V_TMP(8 downto 3) & "000";
|
||||
|
||||
lCPT_V_8_TMP <= lCPT_V_TMP when lTXTHIR_DEC = '1' else "000" & lCPT_V_TMP(8 downto 3) ;
|
||||
|
||||
-- 03/02/2010 : Le bonne blague : après la phase de synthese, le 'bench' ne
|
||||
-- fonctionnait plus. Le synthetiseur de XILINX avait utilisé un multiplieur 18x18
|
||||
-- pour générer la multiplication par 10 et la simulation a repris cela. Or le
|
||||
-- multiplier a une latence de 1 µs (latence de l'horloge PHI2) d'où les problèmes
|
||||
-- durant les simulations (génération de 2 fois de suite de l'adresse vidéo)
|
||||
-- On revient à la bonne vieille méthode Bx10 = Bx8 + Bx2 !!
|
||||
--lVAP1 <= ("0000000" & CPT_H) + (lCPT_V_8_TMP * "1010");
|
||||
ltmpBy10 <= ("0" & lCPT_V_8_TMP & "000") + ("000" & lCPT_V_8_TMP & "0");
|
||||
-- le décalage en Y : il faut multiplier par 40 donc 4 * ltmpBy10
|
||||
lVAP1 <= ("00000" & CPT_H) + (ltmpBy10(10 downto 0) & "00");
|
||||
lOFFSCR <= X"A000" when lTXTHIR_DEC = '1' else X"BB80";
|
||||
VAP1 <= ("000" & lVAP1) + lOFFSCR;
|
||||
|
||||
-- Compute character row counter
|
||||
CHROWCNT <= CPT_V(2 downto 0) when lDBLHGT_EN = '1' else CPT_V(3 downto 1);
|
||||
|
||||
-- Output signal for texte/hires mode decode
|
||||
TXTHIR_DEC <= lTXTHIR_DEC;
|
||||
|
||||
end architecture memmap_arch;
|
||||
|
||||
|
||||
|
||||
@@ -1,491 +0,0 @@
|
||||
//
|
||||
// mist_io.v
|
||||
//
|
||||
// mist_io for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
|
||||
// (Sorgelig)
|
||||
//
|
||||
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
|
||||
// clk_ps2 = clk_sys/(PS2DIV*2)
|
||||
//
|
||||
|
||||
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
(
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
|
||||
// Global clock. It should be around 100MHz (higher is better).
|
||||
input clk_sys,
|
||||
|
||||
// Global SPI clock from ARM. 24MHz
|
||||
input SPI_SCK,
|
||||
|
||||
input CONF_DATA0,
|
||||
input SPI_SS2,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
output scandoubler_disable,
|
||||
output ypbpr,
|
||||
|
||||
output reg [31:0] status,
|
||||
|
||||
// SD config
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output img_mounted, // signaling that new image has been mounted
|
||||
output reg [31:0] img_size, // size of image in bytes
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba,
|
||||
input sd_rd,
|
||||
input sd_wr,
|
||||
output reg sd_ack,
|
||||
output reg sd_ack_conf,
|
||||
|
||||
// SD byte level access. Signals for 2-PORT altsyncram.
|
||||
output reg [8:0] sd_buff_addr,
|
||||
output reg [7:0] sd_buff_dout,
|
||||
input [7:0] sd_buff_din,
|
||||
output reg sd_buff_wr,
|
||||
|
||||
// ps2 keyboard emulation
|
||||
output ps2_kbd_clk,
|
||||
output reg ps2_kbd_data,
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
input ps2_caps_led,
|
||||
|
||||
// ARM -> FPGA download
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg [7:0] ioctl_index, // menu index used to upload the file
|
||||
output ioctl_wr,
|
||||
output reg [24:0] ioctl_addr,
|
||||
output reg [7:0] ioctl_dout
|
||||
);
|
||||
|
||||
reg [7:0] b_data;
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
reg [7:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
reg mount_strobe = 0;
|
||||
assign img_mounted = mount_strobe;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign scandoubler_disable = but_sw[4];
|
||||
assign ypbpr = but_sw[5];
|
||||
|
||||
wire [7:0] spi_dout = { sbuf, SPI_DI};
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
|
||||
|
||||
reg spi_do;
|
||||
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
|
||||
|
||||
wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
|
||||
|
||||
// drive MISO only when transmitting core id
|
||||
always@(negedge SPI_SCK) begin
|
||||
if(!CONF_DATA0) begin
|
||||
// first byte returned is always core type, further bytes are
|
||||
// command dependent
|
||||
if(byte_cnt == 0) begin
|
||||
spi_do <= core_type[~bit_cnt];
|
||||
|
||||
end else begin
|
||||
case(cmd)
|
||||
// reading config string
|
||||
8'h14: begin
|
||||
// returning a byte from string
|
||||
if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
|
||||
else spi_do <= 0;
|
||||
end
|
||||
|
||||
// reading sd card status
|
||||
8'h16: begin
|
||||
if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
|
||||
else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
|
||||
else spi_do <= 0;
|
||||
end
|
||||
|
||||
// reading sd card write data
|
||||
8'h18:
|
||||
spi_do <= b_data[~bit_cnt];
|
||||
|
||||
// reading keyboard LED status
|
||||
8'h1f:
|
||||
spi_do <= kbd_led[~bit_cnt];
|
||||
|
||||
default:
|
||||
spi_do <= 0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg b_wr2,b_wr3;
|
||||
always @(negedge clk_sys) begin
|
||||
b_wr3 <= b_wr2;
|
||||
sd_buff_wr <= b_wr3;
|
||||
end
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
|
||||
|
||||
if(CONF_DATA0) begin
|
||||
b_wr2 <= 0;
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= 0;
|
||||
sd_ack <= 0;
|
||||
sd_ack_conf <= 0;
|
||||
end else begin
|
||||
b_wr2 <= 0;
|
||||
|
||||
sbuf <= spi_dout[6:0];
|
||||
bit_cnt <= bit_cnt + 1'd1;
|
||||
if(bit_cnt == 5) begin
|
||||
if (byte_cnt == 0) sd_buff_addr <= 0;
|
||||
if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
|
||||
end
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
|
||||
if(byte_cnt == 0) begin
|
||||
cmd <= spi_dout;
|
||||
|
||||
if(spi_dout == 8'h19) begin
|
||||
sd_ack_conf <= 1;
|
||||
sd_buff_addr <= 0;
|
||||
end
|
||||
if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
|
||||
sd_ack <= 1;
|
||||
sd_buff_addr <= 0;
|
||||
end
|
||||
if(spi_dout == 8'h18) b_data <= sd_buff_din;
|
||||
|
||||
mount_strobe <= 0;
|
||||
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
// buttons and switches
|
||||
8'h01: but_sw <= spi_dout;
|
||||
8'h02: joystick_0 <= spi_dout;
|
||||
8'h03: joystick_1 <= spi_dout;
|
||||
|
||||
// store incoming ps2 mouse bytes
|
||||
8'h04: begin
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
8'h05: begin
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
|
||||
end
|
||||
|
||||
8'h15: status[7:0] <= spi_dout;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
8'h19,
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
8'h17: begin
|
||||
sd_buff_dout <= spi_dout;
|
||||
b_wr2 <= 1;
|
||||
end
|
||||
|
||||
8'h18: b_data <= sd_buff_din;
|
||||
|
||||
// joystick analog
|
||||
8'h1a: begin
|
||||
// first byte is joystick index
|
||||
if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
|
||||
else if(byte_cnt == 2) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
|
||||
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
|
||||
end else if(byte_cnt == 3) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
|
||||
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
|
||||
end
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
8'h1c: mount_strobe <= 1;
|
||||
|
||||
// send image info
|
||||
8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
|
||||
|
||||
// status, 32bit version
|
||||
8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// PS2 ///////////////////////////////
|
||||
// 8 byte fifos to store ps2 bytes
|
||||
localparam PS2_FIFO_BITS = 3;
|
||||
|
||||
reg clk_ps2;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt == PS2DIV) begin
|
||||
clk_ps2 <= ~clk_ps2;
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// keyboard
|
||||
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_kbd_tx_state;
|
||||
reg [7:0] ps2_kbd_tx_byte;
|
||||
reg ps2_kbd_parity;
|
||||
|
||||
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_kbd_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_kbd_r_inc <= 0;
|
||||
|
||||
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_kbd_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
|
||||
ps2_kbd_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_kbd_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_kbd_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_kbd_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
|
||||
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
|
||||
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
|
||||
if(ps2_kbd_tx_byte[0])
|
||||
ps2_kbd_parity <= !ps2_kbd_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
|
||||
else ps2_kbd_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// mouse
|
||||
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_mouse_tx_state;
|
||||
reg [7:0] ps2_mouse_tx_byte;
|
||||
reg ps2_mouse_parity;
|
||||
|
||||
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_mouse_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_mouse_r_inc <= 0;
|
||||
|
||||
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_mouse_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
|
||||
ps2_mouse_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_mouse_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_mouse_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_mouse_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
|
||||
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
|
||||
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
|
||||
if(ps2_mouse_tx_byte[0])
|
||||
ps2_mouse_parity <= !ps2_mouse_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
|
||||
else ps2_mouse_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// DOWNLOADING ///////////////////////////////
|
||||
|
||||
reg [7:0] data_w;
|
||||
reg [24:0] addr_w;
|
||||
reg rclk = 0;
|
||||
|
||||
localparam UIO_FILE_TX = 8'h53;
|
||||
localparam UIO_FILE_TX_DAT = 8'h54;
|
||||
localparam UIO_FILE_INDEX = 8'h55;
|
||||
|
||||
// data_io has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg [24:0] addr;
|
||||
|
||||
if(SPI_SS2) cnt <= 0;
|
||||
else begin
|
||||
rclk <= 0;
|
||||
|
||||
// don't shift in last bit. It is evaluated directly
|
||||
// when writing to ram
|
||||
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
|
||||
|
||||
// increase target address after write
|
||||
if(rclk) addr <= addr + 1'd1;
|
||||
|
||||
// count 0-7 8-15 8-15 ...
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
// finished command byte
|
||||
if(cnt == 7) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
// prepare/end transmission
|
||||
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
|
||||
// prepare
|
||||
if(SPI_DI) begin
|
||||
addr <= 0;
|
||||
ioctl_download <= 1;
|
||||
end else begin
|
||||
addr_w <= addr;
|
||||
ioctl_download <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// command 0x54: UIO_FILE_TX
|
||||
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
|
||||
addr_w <= addr;
|
||||
data_w <= {sbuf, SPI_DI};
|
||||
rclk <= 1;
|
||||
end
|
||||
|
||||
// expose file (menu) index
|
||||
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
|
||||
end
|
||||
end
|
||||
|
||||
assign ioctl_wr = |ioctl_wrd;
|
||||
reg [1:0] ioctl_wrd;
|
||||
|
||||
always@(negedge clk_sys) begin
|
||||
reg rclkD, rclkD2;
|
||||
|
||||
rclkD <= rclk;
|
||||
rclkD2 <= rclkD;
|
||||
ioctl_wrd<= {ioctl_wrd[0],1'b0};
|
||||
|
||||
if(rclkD & ~rclkD2) begin
|
||||
ioctl_dout <= data_w;
|
||||
ioctl_addr <= addr_w;
|
||||
ioctl_wrd <= 2'b11;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,80 +0,0 @@
|
||||
--
|
||||
-- NOISE_GENERATOR.vhd
|
||||
--
|
||||
-- Generator a noise tone.
|
||||
--
|
||||
-- Copyright (C)2001 SEILEBOST
|
||||
-- All rights reserved.
|
||||
--
|
||||
-- $Id: NOISE_GENERATOR.vhd, v0.41 2002/01/03 00:00:00 SEILEBOST $
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity noise_generator is
|
||||
Port ( CLK : in std_logic;
|
||||
RST : in std_logic;
|
||||
--WR : in std_logic;
|
||||
--CS : in std_logic;
|
||||
DATA : in std_logic_vector(4 downto 0);
|
||||
CLK_N : out std_logic -- pseudo clock
|
||||
);
|
||||
end noise_generator;
|
||||
|
||||
architecture Behavioral of noise_generator is
|
||||
|
||||
SIGNAL COUNT : std_logic_vector(4 downto 0);
|
||||
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
|
||||
--SIGNAL ShiftEn : std_logic;
|
||||
--SIGNAL FillSel : std_logic;
|
||||
--SIGNAL DataIn : std_logic;
|
||||
--SIGNAL lData : std_logic_vector(4 downto 0);
|
||||
|
||||
--COMPONENT i_pn_gen port (clk, ShiftEn, FillSel, DataIn_i, RESET : in std_logic;
|
||||
-- pn_out_i : out std_logic);
|
||||
--END COMPONENT;
|
||||
|
||||
begin
|
||||
|
||||
--U_IPNG : I_PN_GEN PORT MAP ( CLK => CLK,
|
||||
-- ShiftEn => ShiftEn,
|
||||
-- FillSel => FillSel,
|
||||
-- RESET => RST,
|
||||
-- DataIn_i => DataIn,
|
||||
-- pn_out_i => CLK_N);
|
||||
|
||||
-- The noise generator
|
||||
PROCESS(CLK,RST)
|
||||
variable COUNT_MAX : std_logic_vector(4 downto 0);
|
||||
variable poly17_zero : std_logic;
|
||||
BEGIN
|
||||
if (RST = '1') then
|
||||
poly17 <= (others => '0');
|
||||
elsif ( CLK'event and CLK = '1') then
|
||||
if (DATA = "00000") then
|
||||
COUNT_MAX := "00000";
|
||||
else
|
||||
COUNT_MAX := (DATA - "1");
|
||||
end if;
|
||||
|
||||
-- Manage the polynome = 0 to regenerate another sequence
|
||||
poly17_zero := '0';
|
||||
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
|
||||
|
||||
if (COUNT >= COUNT_MAX) then
|
||||
COUNT <= "00000";
|
||||
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero)
|
||||
& poly17(16 downto 1);
|
||||
else
|
||||
COUNT <= (COUNT + "1");
|
||||
end if;
|
||||
end if;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
CLK_N <= poly17(0);
|
||||
|
||||
end Behavioral;
|
||||
@@ -1,398 +0,0 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity oricatmos is
|
||||
port (
|
||||
CLOCK_27 : in std_logic;
|
||||
LED : out std_logic;
|
||||
VGA_R : out std_logic_vector(5 downto 0);
|
||||
VGA_G : out std_logic_vector(5 downto 0);
|
||||
VGA_B : out std_logic_vector(5 downto 0);
|
||||
VGA_HS : out std_logic;
|
||||
VGA_VS : out std_logic;
|
||||
SPI_SCK : in std_logic;
|
||||
SPI_DI : in std_logic;
|
||||
SPI_DO : out std_logic;
|
||||
SPI_SS3 : in std_logic;
|
||||
CONF_DATA0 : in std_logic;
|
||||
AUDIO_L : out std_logic;
|
||||
AUDIO_R : out std_logic
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of oricatmos is
|
||||
signal VGA_R_O : std_logic_vector(3 downto 0);
|
||||
signal VGA_G_O : std_logic_vector(3 downto 0);
|
||||
signal VGA_B_O : std_logic_vector(3 downto 0);
|
||||
signal hsync : std_logic;
|
||||
signal vsync : std_logic;
|
||||
signal hq2x : std_logic;
|
||||
signal buttons : std_logic_vector(1 downto 0);
|
||||
signal switches : std_logic_vector(1 downto 0);
|
||||
signal status : std_logic_vector(31 downto 0);
|
||||
signal scandoubler_disable : std_logic;
|
||||
signal scanlines : std_logic_vector(1 downto 0);
|
||||
signal ypbpr : std_logic;
|
||||
signal ps2Clk : std_logic;
|
||||
signal ps2Data : std_logic;
|
||||
signal loc_reset_n : std_logic; --active low
|
||||
signal reset : std_logic := '1';
|
||||
signal clk24 : std_logic := '0';
|
||||
signal clk12 : std_logic := '0';
|
||||
signal clk6 : std_logic := '0';
|
||||
signal pll_locked : std_logic := '0';
|
||||
signal CPU_ADDR : std_logic_vector(23 downto 0);
|
||||
signal CPU_DI : std_logic_vector( 7 downto 0);
|
||||
signal CPU_DO : std_logic_vector( 7 downto 0);
|
||||
signal cpu_rw : std_logic;
|
||||
signal cpu_irq : std_logic;
|
||||
signal ad : std_logic_vector(15 downto 0);
|
||||
signal via_pa_out_oe : std_logic_vector( 7 downto 0);
|
||||
signal via_pa_in : std_logic_vector( 7 downto 0);
|
||||
signal via_pa_out : std_logic_vector( 7 downto 0);
|
||||
signal via_cb1_out : std_logic;
|
||||
signal via_cb1_oe_l : std_logic;
|
||||
signal via_cb2_out : std_logic;
|
||||
signal via_cb2_oe_l : std_logic;
|
||||
signal via_in : std_logic_vector( 7 downto 0);
|
||||
signal via_out : std_logic_vector( 7 downto 0);
|
||||
signal via_oe_l : std_logic_vector( 7 downto 0);
|
||||
signal VIA_DO : std_logic_vector( 7 downto 0);
|
||||
signal KEY_ROW : std_logic_vector( 7 downto 0);
|
||||
signal psg_bdir : std_logic;
|
||||
signal PSG_OUT : std_logic_vector( 7 downto 0);
|
||||
signal ula_phi2 : std_logic;
|
||||
signal ula_CSIOn : std_logic;
|
||||
signal ula_CSIO : std_logic;
|
||||
signal ula_CSROMn : std_logic;
|
||||
signal SRAM_DO : std_logic_vector( 7 downto 0);
|
||||
signal ula_AD_SRAM : std_logic_vector(15 downto 0);
|
||||
signal ula_CE_SRAM : std_logic;
|
||||
signal ula_OE_SRAM : std_logic;
|
||||
signal ula_WE_SRAM : std_logic;
|
||||
signal ula_LE_SRAM : std_logic;
|
||||
signal ula_CLK_4 : std_logic;
|
||||
signal ula_IOCONTROL : std_logic;
|
||||
signal ula_VIDEO_R : std_logic;
|
||||
signal ula_VIDEO_G : std_logic;
|
||||
signal ula_VIDEO_B : std_logic;
|
||||
signal ula_SYNC : std_logic;
|
||||
signal ROM_DO : std_logic_vector( 7 downto 0);
|
||||
signal hs_int : std_logic;
|
||||
signal vs_int : std_logic;
|
||||
signal dummy : std_logic_vector( 3 downto 0) := (others => '0');
|
||||
signal s_cmpblk_n_out : std_logic;
|
||||
|
||||
|
||||
constant CONF_STR : string :=
|
||||
"ORIC;;O89,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T6,Reset;";
|
||||
|
||||
function to_slv(s: string) return std_logic_vector is
|
||||
constant ss: string(1 to s'length) := s;
|
||||
variable rval: std_logic_vector(1 to 8 * s'length);
|
||||
variable p: integer;
|
||||
variable c: integer;
|
||||
begin
|
||||
for i in ss'range loop
|
||||
p := 8 * i;
|
||||
c := character'pos(ss(i));
|
||||
rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
|
||||
end loop;
|
||||
return rval;
|
||||
end function;
|
||||
|
||||
component mist_io
|
||||
generic ( STRLEN : integer := 0 );
|
||||
port (
|
||||
clk_sys :in std_logic;
|
||||
SPI_SCK, CONF_DATA0, SPI_DI :in std_logic;
|
||||
SPI_DO : out std_logic;
|
||||
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
|
||||
buttons : out std_logic_vector(1 downto 0);
|
||||
switches : out std_logic_vector(1 downto 0);
|
||||
joystick_0 : out std_logic_vector(7 downto 0);
|
||||
joystick_1 : out std_logic_vector(7 downto 0);
|
||||
status : out std_logic_vector(31 downto 0);
|
||||
scandoubler_disable, ypbpr : out std_logic;
|
||||
ps2_kbd_clk : out std_logic;
|
||||
ps2_kbd_data : out std_logic
|
||||
);
|
||||
end component mist_io;
|
||||
|
||||
component video_mixer
|
||||
generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 );
|
||||
port (
|
||||
clk_sys, ce_pix, ce_pix_actual : in std_logic;
|
||||
SPI_SCK, SPI_SS3, SPI_DI : in std_logic;
|
||||
|
||||
scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic;
|
||||
scanlines : in std_logic_vector(1 downto 0);
|
||||
R, G, B : in std_logic_vector(2 downto 0);
|
||||
HSync, VSync, line_start, mono : in std_logic;
|
||||
|
||||
VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0);
|
||||
VGA_VS, VGA_HS : out std_logic
|
||||
);
|
||||
end component video_mixer;
|
||||
|
||||
begin
|
||||
inst_pll : entity work.pll
|
||||
port map (
|
||||
areset => open,
|
||||
inclk0 => CLOCK_27,
|
||||
c0 => clk24,
|
||||
c1 => clk12,
|
||||
c2 => clk6,
|
||||
locked => pll_locked
|
||||
);
|
||||
|
||||
loc_reset_n <= pll_locked;
|
||||
--reset <= not status(0) or status(6) or buttons(1);
|
||||
inst_cpu : entity work.T65
|
||||
port map (
|
||||
Mode => "00",
|
||||
Res_n => loc_reset_n,
|
||||
Enable => '1',
|
||||
Clk => ula_phi2,
|
||||
Rdy => '1',
|
||||
Abort_n => '1',
|
||||
IRQ_n => cpu_irq,
|
||||
NMI_n => '1',
|
||||
SO_n => '1',
|
||||
R_W_n => cpu_rw,
|
||||
Sync => open,
|
||||
EF => open,
|
||||
MF => open,
|
||||
XF => open,
|
||||
ML_n => open,
|
||||
VP_n => open,
|
||||
VDA => open,
|
||||
VPA => open,
|
||||
A => CPU_ADDR,
|
||||
DI => CPU_DI,
|
||||
DO => CPU_DO
|
||||
);
|
||||
-- place Rom in LE and we can use 48kb Memory
|
||||
-- inst_rom : entity work.rom
|
||||
-- port map (
|
||||
-- clk => clk24,
|
||||
-- ADDR => CPU_ADDR(13 downto 0),
|
||||
-- DATA => ROM_DO
|
||||
-- );
|
||||
-- place in BRAM and reduce Memory to 16kb see file ram48k
|
||||
inst_rom : entity work.rrom
|
||||
port map (
|
||||
clock => clk24,
|
||||
address => CPU_ADDR(13 downto 0),
|
||||
q => ROM_DO
|
||||
);
|
||||
|
||||
ad(15 downto 0) <= ula_AD_SRAM when ula_phi2 = '0' else CPU_ADDR(15 downto 0);
|
||||
|
||||
inst_ram : entity work.ram48k
|
||||
port map(
|
||||
clk => clk24,
|
||||
cs => ula_CE_SRAM,
|
||||
oe => ula_OE_SRAM,
|
||||
we => ula_WE_SRAM,
|
||||
addr => ad,
|
||||
di => CPU_DO,
|
||||
do => SRAM_DO
|
||||
);
|
||||
|
||||
inst_ula : entity work.ULA
|
||||
port map (
|
||||
RESETn => loc_reset_n,
|
||||
CLK => clk24,
|
||||
CLK_4 => ula_CLK_4,
|
||||
RW => cpu_rw,
|
||||
ADDR => CPU_ADDR(15 downto 0),
|
||||
MAPn => '1',
|
||||
DB => SRAM_DO,
|
||||
CSROMn => ula_CSROMn,
|
||||
CSIOn => ula_CSIOn,
|
||||
SRAM_AD => ula_AD_SRAM,
|
||||
SRAM_OE => ula_OE_SRAM,
|
||||
SRAM_CE => ula_CE_SRAM,
|
||||
SRAM_WE => ula_WE_SRAM,
|
||||
LATCH_SRAM => ula_LE_SRAM,
|
||||
PHI2 => ula_PHI2,
|
||||
R => ULA_VIDEO_R,
|
||||
G => ULA_VIDEO_G,
|
||||
B => ULA_VIDEO_B,
|
||||
SYNC => ULA_SYNC,
|
||||
HSYNC => hs_int,
|
||||
VSYNC => vs_int
|
||||
);
|
||||
|
||||
vmixer : video_mixer
|
||||
generic map(
|
||||
HALF_DEPTH => 1,
|
||||
LINE_LENGTH => 480
|
||||
)
|
||||
|
||||
port map (
|
||||
clk_sys => clk24,
|
||||
ce_pix => clk6,
|
||||
ce_pix_actual => clk6,
|
||||
SPI_SCK => SPI_SCK,
|
||||
SPI_SS3 => SPI_SS3,
|
||||
SPI_DI => SPI_DI,
|
||||
hq2x => hq2x,
|
||||
ypbpr => ypbpr,
|
||||
ypbpr_full => '1',
|
||||
scanlines => scanlines,
|
||||
scandoubler_disable => scandoubler_disable,
|
||||
R => ULA_VIDEO_R & ULA_VIDEO_R & ULA_VIDEO_R,
|
||||
G => ULA_VIDEO_G & ULA_VIDEO_G & ULA_VIDEO_G,
|
||||
B => ULA_VIDEO_B & ULA_VIDEO_B & ULA_VIDEO_B,
|
||||
HSync => hs_int,
|
||||
VSync => vs_int,
|
||||
line_start => '0',
|
||||
mono => '0',
|
||||
VGA_R => VGA_R,
|
||||
VGA_G => VGA_G,
|
||||
VGA_B => VGA_B,
|
||||
VGA_VS => VGA_VS,
|
||||
VGA_HS => VGA_HS
|
||||
);
|
||||
|
||||
scanlines(1) <= '1' when status(9 downto 8) = "11" and scandoubler_disable = '0' else '0';
|
||||
scanlines(0) <= '1' when status(9 downto 8) = "10" and scandoubler_disable = '0' else '0';
|
||||
hq2x <= '1' when status(9 downto 8) = "01" else '0';
|
||||
|
||||
mist_io_inst : mist_io
|
||||
generic map (STRLEN => CONF_STR'length)
|
||||
port map (
|
||||
clk_sys => clk24,
|
||||
SPI_SCK => SPI_SCK,
|
||||
CONF_DATA0 => CONF_DATA0,
|
||||
SPI_DI => SPI_DI,
|
||||
SPI_DO => SPI_DO,
|
||||
conf_str => to_slv(CONF_STR),
|
||||
buttons => buttons,
|
||||
switches => switches,
|
||||
scandoubler_disable => scandoubler_disable,
|
||||
ypbpr => ypbpr,
|
||||
status => status,
|
||||
ps2_kbd_clk => ps2Clk,
|
||||
ps2_kbd_data => ps2Data
|
||||
);
|
||||
|
||||
ula_CSIO <= not ula_CSIOn;
|
||||
|
||||
inst_via : entity work.M6522
|
||||
port map (
|
||||
I_RS => CPU_ADDR(3 downto 0),
|
||||
I_DATA => CPU_DO(7 downto 0),
|
||||
O_DATA => VIA_DO,
|
||||
O_DATA_OE_L => open,
|
||||
I_RW_L => cpu_rw,
|
||||
I_CS1 => ula_CSIO,
|
||||
I_CS2_L => ula_IOCONTROL,
|
||||
O_IRQ_L => cpu_irq, -- note, not open drain
|
||||
I_CA1 => '1', -- PRT_ACK
|
||||
I_CA2 => '1', -- psg_bdir
|
||||
O_CA2 => psg_bdir, -- via_ca2_out
|
||||
O_CA2_OE_L => open,
|
||||
I_PA => via_pa_in,
|
||||
O_PA => via_pa_out,
|
||||
O_PA_OE_L => via_pa_out_oe,
|
||||
-- I_CB1 => K7_TAPEIN,
|
||||
I_CB1 => '0',
|
||||
O_CB1 => via_cb1_out,
|
||||
O_CB1_OE_L => via_cb1_oe_l,
|
||||
I_CB2 => '1',
|
||||
O_CB2 => via_cb2_out,
|
||||
O_CB2_OE_L => via_cb2_oe_l,
|
||||
I_PB => via_in,
|
||||
O_PB => via_out,
|
||||
O_PB_OE_L => via_oe_l,
|
||||
RESET_L => loc_reset_n,
|
||||
I_P2_H => ula_phi2,
|
||||
ENA_4 => '1',
|
||||
CLK => ula_CLK_4
|
||||
);
|
||||
|
||||
inst_key : entity work.keyboard
|
||||
port map(
|
||||
CLK => clk24,
|
||||
RESET => '0', -- active high reset
|
||||
PS2CLK => ps2Clk,
|
||||
PS2DATA => ps2Data,
|
||||
COL => via_out(2 downto 0),
|
||||
ROWbit => KEY_ROW
|
||||
);
|
||||
|
||||
via_in <= x"F7" when (KEY_ROW or VIA_PA_OUT) = x"FF" else x"FF";
|
||||
|
||||
inst_psg : entity work.YM2149
|
||||
port map (
|
||||
I_DA => via_pa_out,
|
||||
O_DA => via_pa_in,
|
||||
O_DA_OE_L => open,
|
||||
I_A9_L => '0',
|
||||
I_A8 => '1',
|
||||
I_BDIR => via_cb2_out,
|
||||
I_BC2 => '1',
|
||||
I_BC1 => psg_bdir,
|
||||
I_SEL_L => '1',
|
||||
O_AUDIO => PSG_OUT,
|
||||
RESET_L => loc_reset_n,
|
||||
ENA => '1',
|
||||
CLK => ula_PHI2
|
||||
);
|
||||
|
||||
inst_dacl : entity work.DAC
|
||||
port map (
|
||||
CLK_DAC => clk24,
|
||||
RST => loc_reset_n,
|
||||
IN_DAC => PSG_OUT,
|
||||
OUT_DAC => AUDIO_L
|
||||
);
|
||||
|
||||
inst_dacr : entity work.DAC
|
||||
port map (
|
||||
CLK_DAC => clk24,
|
||||
RST => loc_reset_n,
|
||||
IN_DAC => PSG_OUT,
|
||||
OUT_DAC => AUDIO_R
|
||||
);
|
||||
|
||||
ula_IOCONTROL <= '0';
|
||||
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(clk24);
|
||||
-- expansion port
|
||||
if cpu_rw = '1' and ula_IOCONTROL = '1' and ula_CSIOn = '0' then
|
||||
CPU_DI <= SRAM_DO;
|
||||
-- Via
|
||||
elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSIOn = '0' and ula_LE_SRAM = '0' then
|
||||
CPU_DI <= VIA_DO;
|
||||
-- ROM
|
||||
elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSROMn = '0' then
|
||||
CPU_DI <= ROM_DO;
|
||||
-- Read data
|
||||
elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_phi2 = '1' and ula_LE_SRAM = '0' then
|
||||
cpu_di <= SRAM_DO;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- K7 PORT
|
||||
------------------------------------------------------------
|
||||
-- K7_TAPEOUT <= via_out(7);
|
||||
-- K7_REMOTE <= via_out(6);
|
||||
-- K7_AUDIOOUT <= AUDIO_OUT;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- PRINTER PORT
|
||||
------------------------------------------------------------
|
||||
-- PRT_DATA <= via_pa_out;
|
||||
-- PRT_STR <= via_out(4);
|
||||
LED <= '1';
|
||||
end RTL;
|
||||
@@ -1,179 +0,0 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd (
|
||||
// OSDs pixel clock, should be synchronous to cores pixel clock to
|
||||
// avoid jitter.
|
||||
input clk_sys,
|
||||
|
||||
// SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] R_in,
|
||||
input [5:0] G_in,
|
||||
input [5:0] B_in,
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] R_out,
|
||||
output [5:0] G_out,
|
||||
output [5:0] B_out
|
||||
);
|
||||
|
||||
parameter OSD_X_OFFSET = 10'd0;
|
||||
parameter OSD_Y_OFFSET = 10'd0;
|
||||
parameter OSD_COLOR = 3'd0;
|
||||
|
||||
localparam OSD_WIDTH = 10'd256;
|
||||
localparam OSD_HEIGHT = 10'd128;
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg osd_enable;
|
||||
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
|
||||
|
||||
// the OSD has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS3) begin
|
||||
reg [4:0] cnt;
|
||||
reg [10:0] bcnt;
|
||||
reg [7:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
|
||||
if(SPI_SS3) begin
|
||||
cnt <= 0;
|
||||
bcnt <= 0;
|
||||
end else begin
|
||||
sbuf <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// 0:7 is command, rest payload
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
|
||||
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
|
||||
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
|
||||
bcnt <= bcnt + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// *********************************************************************************
|
||||
// video timing and sync polarity anaylsis
|
||||
// *********************************************************************************
|
||||
|
||||
// horizontal counter
|
||||
reg [9:0] h_cnt;
|
||||
reg [9:0] hs_low, hs_high;
|
||||
wire hs_pol = hs_high < hs_low;
|
||||
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
|
||||
|
||||
// vertical counter
|
||||
reg [9:0] v_cnt;
|
||||
reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
|
||||
|
||||
wire doublescan = (dsp_height>350);
|
||||
|
||||
reg ce_pix;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt = 0;
|
||||
integer pixsz, pixcnt;
|
||||
reg hs;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
hs <= HSync;
|
||||
|
||||
pixcnt <= pixcnt + 1;
|
||||
if(pixcnt == pixsz) pixcnt <= 0;
|
||||
ce_pix <= !pixcnt;
|
||||
|
||||
if(hs && ~HSync) begin
|
||||
cnt <= 0;
|
||||
pixsz <= (cnt >> 9) - 1;
|
||||
pixcnt <= 0;
|
||||
ce_pix <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg hsD, hsD2;
|
||||
reg vsD, vsD2;
|
||||
|
||||
if(ce_pix) begin
|
||||
// bring hsync into local clock domain
|
||||
hsD <= HSync;
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of HSync
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of HSync
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_low <= h_cnt;
|
||||
v_cnt <= v_cnt + 1'd1;
|
||||
end else begin
|
||||
h_cnt <= h_cnt + 1'd1;
|
||||
end
|
||||
|
||||
vsD <= VSync;
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of VSync
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of VSync
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// area in which OSD is being displayed
|
||||
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
|
||||
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
|
||||
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
|
||||
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
|
||||
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
|
||||
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
|
||||
wire osd_de = osd_enable &&
|
||||
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
|
||||
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
|
||||
|
||||
reg [7:0] osd_byte;
|
||||
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
|
||||
|
||||
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
|
||||
|
||||
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
|
||||
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
|
||||
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
|
||||
|
||||
endmodule
|
||||
@@ -1,270 +0,0 @@
|
||||
--
|
||||
-- A simulation model of ORIC hardware
|
||||
-- Copyright (c) seilebost - January 2009
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email seilebost@free.fr
|
||||
--
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 001 initial release
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
package pkg_oric is
|
||||
component T65
|
||||
port(
|
||||
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
|
||||
Res_n : in std_logic;
|
||||
Enable : in std_logic;
|
||||
Clk : in std_logic;
|
||||
Rdy : in std_logic;
|
||||
Abort_n : in std_logic;
|
||||
IRQ_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
SO_n : in std_logic;
|
||||
R_W_n : out std_logic;
|
||||
Sync : out std_logic;
|
||||
EF : out std_logic;
|
||||
MF : out std_logic;
|
||||
XF : out std_logic;
|
||||
ML_n : out std_logic;
|
||||
VP_n : out std_logic;
|
||||
VDA : out std_logic;
|
||||
VPA : out std_logic;
|
||||
A : out std_logic_vector(23 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component ULA
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
PHI2 : out std_logic;
|
||||
CLK_4 : out std_logic;
|
||||
RW : in std_logic;
|
||||
RESETn : in std_logic;
|
||||
MAPn : in std_logic;
|
||||
DB : in std_logic_vector(7 downto 0);
|
||||
AD : in std_logic_vector(15 downto 0);
|
||||
AD_RAM : out std_logic_vector(7 downto 0);
|
||||
AD_SRAM : out std_logic_vector(15 downto 0);
|
||||
OE_SRAM : out std_logic;
|
||||
CE_SRAM : out std_logic;
|
||||
WE_SRAM : out std_logic;
|
||||
LATCH_SRAM : out std_logic;
|
||||
RASn : out std_logic;
|
||||
CASn : out std_logic;
|
||||
MUX : out std_logic;
|
||||
RW_RAM : out std_logic;
|
||||
CSIOn : out std_logic;
|
||||
CSROMn : out std_logic;
|
||||
CSRAMn : out std_logic;
|
||||
R : out std_logic;
|
||||
G : out std_logic;
|
||||
B : out std_logic;
|
||||
SYNC : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component M6522 is
|
||||
port (
|
||||
RS : in std_logic_vector(3 downto 0);
|
||||
DATA_IN : in std_logic_vector(7 downto 0);
|
||||
DATA_OUT : out std_logic_vector(7 downto 0);
|
||||
DATA_OUT_OE_L : out std_logic;
|
||||
|
||||
RW_L : in std_logic;
|
||||
CS1 : in std_logic;
|
||||
CS2_L : in std_logic;
|
||||
|
||||
IRQ_L : out std_logic; -- note, not open drain
|
||||
|
||||
CA1_IN : in std_logic;
|
||||
CA2_IN : in std_logic;
|
||||
CA2_OUT : out std_logic;
|
||||
CA2_OUT_OE_L : out std_logic;
|
||||
|
||||
PA_IN : in std_logic_vector(7 downto 0);
|
||||
PA_OUT : out std_logic_vector(7 downto 0);
|
||||
PA_OUT_OE_L : out std_logic_vector(7 downto 0);
|
||||
|
||||
-- port b
|
||||
CB1_IN : in std_logic;
|
||||
CB1_OUT : out std_logic;
|
||||
CB1_OUT_OE_L : out std_logic;
|
||||
|
||||
CB2_IN : in std_logic;
|
||||
CB2_OUT : out std_logic;
|
||||
CB2_OUT_OE_L : out std_logic;
|
||||
|
||||
PB_IN : in std_logic_vector(7 downto 0);
|
||||
PB_OUT : out std_logic_vector(7 downto 0);
|
||||
PB_OUT_OE_L : out std_logic_vector(7 downto 0);
|
||||
|
||||
RESET_L : in std_logic;
|
||||
P2_H : in std_logic; -- high for phase 2 clock ____----__
|
||||
CLK_4 : in std_logic -- 4x system clock (4HZ) _-_-_-_-_-
|
||||
);
|
||||
end component;
|
||||
|
||||
component AY3819X
|
||||
port (
|
||||
DATA_IN : in std_logic_vector(7 downto 0);
|
||||
DATA_OUT : out std_logic_vector(7 downto 0);
|
||||
O_DATA_OE_L : out std_logic;
|
||||
RESET : in std_logic;
|
||||
CLOCK : in std_logic;
|
||||
CLOCK_DAC : in std_logic;
|
||||
BDIR : in std_logic;
|
||||
BC1 : in std_logic;
|
||||
BC2 : in std_logic;
|
||||
IOA : inout std_logic_vector(7 downto 0);
|
||||
IOB : inout std_logic_vector(7 downto 0);
|
||||
AnalogA : out std_logic;
|
||||
AnalogB : out std_logic;
|
||||
AnalogC : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component ORIC_PS2_IF
|
||||
port (
|
||||
PS2_CLK : in std_logic;
|
||||
PS2_DATA : in std_logic;
|
||||
|
||||
COL_IN : in std_logic_vector(7 downto 0);
|
||||
ROW_IN : in std_logic_vector(7 downto 0);
|
||||
RESTORE : out std_logic;
|
||||
|
||||
RESET_L : in std_logic;
|
||||
ENA_1MHZ : in std_logic;
|
||||
P2_H : in std_logic; -- high for phase 2 clock ____----__
|
||||
CLK_4 : in std_logic -- 4x system clock (4HZ) _-_-_-_-_-
|
||||
);
|
||||
end component;
|
||||
|
||||
component ORIC_CHAR_ROM
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
ADDR : in std_logic_vector(11 downto 0);
|
||||
DATA : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component ORIC_BASIC_ROM
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
ADDR : in std_logic_vector(12 downto 0);
|
||||
DATA : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component ORIC_KERNAL_ROM
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
ADDR : in std_logic_vector(12 downto 0);
|
||||
DATA : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component ORIC_RAMS
|
||||
port (
|
||||
V_ADDR : in std_logic_vector(9 downto 0);
|
||||
DIN : in std_logic_vector(7 downto 0);
|
||||
DOUT : out std_logic_vector(7 downto 0);
|
||||
V_RW_L : in std_logic;
|
||||
CS_L : in std_logic; -- used for write enable gate only
|
||||
CLK : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component keyboard
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
RESET : in std_logic;
|
||||
PS2CLK : in std_logic;
|
||||
PS2DATA : in std_logic;
|
||||
COL : in std_logic_vector(2 downto 0);
|
||||
ROWbit : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component file_log
|
||||
generic (
|
||||
log_file: string := "res.log"
|
||||
);
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
RST : in std_logic;
|
||||
x1 : in std_logic_vector(7 downto 0);
|
||||
x2 : in std_logic_vector(7 downto 0);
|
||||
x3 : in std_logic_vector(15 downto 0);
|
||||
x4 : in std_logic_vector(2 downto 0);
|
||||
x5 : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component psg_log
|
||||
generic (
|
||||
log_psg: string := "psg.log"
|
||||
);
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
RST : in std_logic;
|
||||
x1 : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component ula_log
|
||||
generic (
|
||||
log_ula: string := "ula.log"
|
||||
);
|
||||
port(
|
||||
CLK : in std_logic;
|
||||
RST : in std_logic;
|
||||
x1 : in std_logic_vector(7 downto 0);
|
||||
x2 : in std_logic_vector(15 downto 0);
|
||||
x3 : in std_logic
|
||||
);
|
||||
end component;
|
||||
end pkg_oric;
|
||||
|
||||
package body pkg_ORIC is
|
||||
|
||||
end pkg_oric;
|
||||
@@ -1,117 +0,0 @@
|
||||
-- ****
|
||||
-- T65(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 Bugfixes by ehenciak added
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- 65xx compatible microprocessor core
|
||||
--
|
||||
-- Version : 0246
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t65/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package pack_t65 is
|
||||
|
||||
constant Flag_C : integer := 0;
|
||||
constant Flag_Z : integer := 1;
|
||||
constant Flag_I : integer := 2;
|
||||
constant Flag_D : integer := 3;
|
||||
constant Flag_B : integer := 4;
|
||||
constant Flag_1 : integer := 5;
|
||||
constant Flag_V : integer := 6;
|
||||
constant Flag_N : integer := 7;
|
||||
|
||||
component T65_MCode
|
||||
port(
|
||||
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
P : in std_logic_vector(7 downto 0);
|
||||
LCycle : out std_logic_vector(2 downto 0);
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
|
||||
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
|
||||
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
|
||||
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
|
||||
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
|
||||
BreakAtNA : out std_logic;
|
||||
ADAdd : out std_logic;
|
||||
AddY : out std_logic;
|
||||
PCAdd : out std_logic;
|
||||
Inc_S : out std_logic;
|
||||
Dec_S : out std_logic;
|
||||
LDA : out std_logic;
|
||||
LDP : out std_logic;
|
||||
LDX : out std_logic;
|
||||
LDY : out std_logic;
|
||||
LDS : out std_logic;
|
||||
LDDI : out std_logic;
|
||||
LDALU : out std_logic;
|
||||
LDAD : out std_logic;
|
||||
LDBAL : out std_logic;
|
||||
LDBAH : out std_logic;
|
||||
SaveP : out std_logic;
|
||||
Write : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T65_ALU
|
||||
port(
|
||||
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
|
||||
Op : in std_logic_vector(3 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
P_In : in std_logic_vector(7 downto 0);
|
||||
P_Out : out std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user