github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-18 17:06:57 +00:00
Code Issues Releases Wiki Activity

Midway MCR3: allow saving the work RAM

Browse Source
This commit is contained in:
Gyorgy Szombathelyi 2020-12-11 14:07:40 +01:00
parent 5b8795a621
commit 2c442684df
3 changed files with 31 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Arcade_MiST/Midway MCR 3/README.txt
View File

@ -71,6 +71,10 @@ Copy the ROM files to the root of the SD Card.
MRA utilty: https://github.com/sebdel/mra-tools-c
Some games are storing settings/high scores in a non-volatile RAM. It can be saved to
the SD Card with the "Save settings" option in the OSD menu. It'll be restored when
the core is loaded next time.
Based on Darfpga's work:
---------------------------------------------------------------------------------
-- DE10_lite Top level for Timber (Midway MCR) by Dar (darfpga@aol.fr) (22/11/2019)

19
Arcade_MiST/Midway MCR 3/rtl/MCR3_MiST.sv
View File

@ -54,12 +54,13 @@ module MCR3_MiST(
wire [6:0] core_mod;
localparam CONF_STR = {
`CORE_NAME,";ROM;",
`CORE_NAME,";;",
"O2,Rotate Controls,Off,On;",
"O5,Blend,Off,On;",
"O6,Swap Joystick,Off,On;",
"DIP;",
"O7,Service,Off,On;",
"R2048,Save settings;",
"T0,Reset;",
"V,v1.1.",`BUILD_DATE
};
@ -220,10 +221,12 @@ user_io(
);
wire ioctl_downl;
wire ioctl_upl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [7:0] ioctl_din;
/*
ROM structure:
@ -249,10 +252,12 @@ data_io #(.ROM_DIRECT_UPLOAD(1)) data_io(
.SPI_DI ( SPI_DI ),
.SPI_DO ( SPI_DO ),
.ioctl_download( ioctl_downl ),
.ioctl_upload ( ioctl_upl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
.ioctl_dout ( ioctl_dout ),
.ioctl_din ( ioctl_din )
);
wire [15:0] rom_addr;
@ -328,7 +333,7 @@ always @(posedge clk_sys) begin
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
if (~ioctl_wr_last && ioctl_wr && ioctl_index == 0) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
@ -397,9 +402,11 @@ mcr3 mcr3 (
.sp_addr ( sp_addr ),
.sp_graphx32_do ( sp_do ),
.dl_addr(ioctl_addr-gfx1_offset),
.dl_data(ioctl_dout),
.dl_wr(ioctl_wr)
.dl_addr ( ioctl_addr-(ioctl_index == 0 ? gfx1_offset : 0) ),
.dl_data ( ioctl_dout ),
.dl_wr ( ioctl_wr && ioctl_index == 0 ),
.up_data ( ioctl_din ),
.cmos_wr ( ioctl_wr && ioctl_index == 8'hff )
);
wire vs_out;

21
Arcade_MiST/Midway MCR 3/rtl/mcr3.vhd
View File

@ -174,7 +174,9 @@ port(
-- internal ROM download
dl_addr : in std_logic_vector(18 downto 0);
dl_data : in std_logic_vector(7 downto 0);
dl_wr : in std_logic
dl_wr : in std_logic;
up_data : out std_logic_vector(7 downto 0);
cmos_wr : in std_logic
);
end mcr3;
@ -741,14 +743,19 @@ begin
end process;
-- working RAM 0xE000-0xE7FF
wram : entity work.cmos_ram
wram : entity work.dpram
generic map( dWidth => 8, aWidth => 11)
port map(
clk => clock_vidn,
we => wram_we,
addr => cpu_addr(10 downto 0),
d => cpu_do,
q => wram_do
clk_a => clock_vidn,
addr_a => cpu_addr(10 downto 0),
d_a => cpu_do,
we_a => wram_we,
q_a => wram_do,
clk_b => clock_vid,
we_b => cmos_wr,
addr_b => dl_addr(10 downto 0),
d_b => dl_data,
q_b => up_data
);
-- video RAM 0xF000-0xF7FF