Repo Sync

Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/build_id.sv

@@ -0,0 +1,2 @@
+`define BUILD_DATE "190715"
+`define BUILD_TIME "162500"

Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.db_info

@@ -1,3 +0,0 @@
-Quartus_Version = Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-Version_Index = 318813696
-Creation_Time = Sun Mar 10 14:00:42 2019

Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/build_id.sv

@@ -1,2 +0,0 @@
-`define BUILD_DATE "190308"
-`define BUILD_TIME "223352"

Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.ppf

@@ -1,10 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE pinplan>
-<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
-<global>
-<pin name="inclk0" direction="input" scope="external" source="clock"  />
-<pin name="c0" direction="output" scope="external" source="clock"  />
-<pin name="locked" direction="output" scope="external"  />
-
-</global>
-</pinplan>

Arcade_MiST/Galaga Hardware/ReadMe.txt

@@ -0,0 +1,5 @@
+Games that should work on this Hardware
+
+Bosconian
+Dig Dug
+Xevious

Arcade_MiST/README.txt

@@ -24,12 +24,9 @@ Aviable Arcade Cores
 	Berzerk
 	Frenzy
 
-#Custom Hardware
-	Crazy Kong
-	Galaga
-
 #Crazy Climber Hardware
 	Crazy Climber
+	Crazy Kong
 	River Patrol
 	Silver Land
 
@@ -40,6 +37,9 @@ Aviable Arcade Cores
 #Dottori-Kun Hardware
 	Dottori Kun / Dottori-Man Jr / Mine Sweeper   (3in1Game)
 
+#Galaga Hardware
+	Galaga
+
 #Galaxian Hardware
 	Azurian Attack
 	Black Hole

Computer_MiST/Commodore - MAX_MiST/MAX.qpf

@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 16:51:32  December 14, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "16:51:32  December 14, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "MAX"

Computer_MiST/Commodore - MAX_MiST/MAX.qsf

@@ -1,172 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 16:51:32  December 14, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		MAX_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_90 -to SPI_SS4
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PIN_49 -to SDRAM_A[0]
-set_location_assignment PIN_44 -to SDRAM_A[1]
-set_location_assignment PIN_42 -to SDRAM_A[2]
-set_location_assignment PIN_39 -to SDRAM_A[3]
-set_location_assignment PIN_4 -to SDRAM_A[4]
-set_location_assignment PIN_6 -to SDRAM_A[5]
-set_location_assignment PIN_8 -to SDRAM_A[6]
-set_location_assignment PIN_10 -to SDRAM_A[7]
-set_location_assignment PIN_11 -to SDRAM_A[8]
-set_location_assignment PIN_28 -to SDRAM_A[9]
-set_location_assignment PIN_50 -to SDRAM_A[10]
-set_location_assignment PIN_30 -to SDRAM_A[11]
-set_location_assignment PIN_32 -to SDRAM_A[12]
-set_location_assignment PIN_83 -to SDRAM_DQ[0]
-set_location_assignment PIN_79 -to SDRAM_DQ[1]
-set_location_assignment PIN_77 -to SDRAM_DQ[2]
-set_location_assignment PIN_76 -to SDRAM_DQ[3]
-set_location_assignment PIN_72 -to SDRAM_DQ[4]
-set_location_assignment PIN_71 -to SDRAM_DQ[5]
-set_location_assignment PIN_69 -to SDRAM_DQ[6]
-set_location_assignment PIN_68 -to SDRAM_DQ[7]
-set_location_assignment PIN_86 -to SDRAM_DQ[8]
-set_location_assignment PIN_87 -to SDRAM_DQ[9]
-set_location_assignment PIN_98 -to SDRAM_DQ[10]
-set_location_assignment PIN_99 -to SDRAM_DQ[11]
-set_location_assignment PIN_100 -to SDRAM_DQ[12]
-set_location_assignment PIN_101 -to SDRAM_DQ[13]
-set_location_assignment PIN_103 -to SDRAM_DQ[14]
-set_location_assignment PIN_104 -to SDRAM_DQ[15]
-set_location_assignment PIN_58 -to SDRAM_BA[0]
-set_location_assignment PIN_51 -to SDRAM_BA[1]
-set_location_assignment PIN_85 -to SDRAM_DQMH
-set_location_assignment PIN_67 -to SDRAM_DQML
-set_location_assignment PIN_60 -to SDRAM_nRAS
-set_location_assignment PIN_64 -to SDRAM_nCAS
-set_location_assignment PIN_66 -to SDRAM_nWE
-set_location_assignment PIN_59 -to SDRAM_nCS
-set_location_assignment PIN_33 -to SDRAM_CKE
-set_location_assignment PIN_43 -to SDRAM_CLK
-set_location_assignment PIN_31 -to UART_RX
-set_location_assignment PIN_46 -to UART_TX
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name TOP_LEVEL_ENTITY MAX
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:51:32  DECEMBER 14, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VHDL_FILE rtl/sid_voice.vhd
-set_global_assignment -name VHDL_FILE rtl/sid_components.vhd
-set_global_assignment -name VHDL_FILE rtl/sid_6581.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/MAX.sv
-set_global_assignment -name QIP_FILE rtl/pll.qip
-set_global_assignment -name QIP_FILE rtl/COLRAM.qip
-set_global_assignment -name QIP_FILE rtl/MAINRAM.qip
-set_global_assignment -name VHDL_FILE rtl/cpu_6510.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu65xx_e.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu65xx_fast.vhd
-set_global_assignment -name VHDL_FILE rtl/fpga64_rgbcolor.vhd
-set_global_assignment -name VERILOG_FILE rtl/user_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/data_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VHDL_FILE rtl/cia_6526.vhd
-set_global_assignment -name VERILOG_FILE rtl/pla_6703.v
-set_global_assignment -name VHDL_FILE rtl/vic_656x_a.vhd
-set_global_assignment -name VHDL_FILE rtl/vic_656x_e.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cart.sv
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Computer_MiST/Commodore - MAX_MiST/clean.bat

@@ -1,13 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-del PLLJ_PLLSPE_INFO.txt
-del *.qws
-del *.ppf
-del *.qip
-pause

Computer_MiST/Commodore - MAX_MiST/rtl/COLRAM.qip

@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "COLRAM.v"]

Computer_MiST/Commodore - MAX_MiST/rtl/COLRAM.v

@@ -1,177 +0,0 @@
-// megafunction wizard: %RAM: 1-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram 
-
-// ============================================================
-// File Name: COLRAM.v
-// Megafunction Name(s):
-// 			altsyncram
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 13.1.0 Build 162 10/23/2013 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2013 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, Altera MegaCore Function License 
-//Agreement, or other applicable license agreement, including, 
-//without limitation, that your use is for the sole purpose of 
-//programming logic devices manufactured by Altera and sold by 
-//Altera or its authorized distributors.  Please refer to the 
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module COLRAM (
-	address,
-	clock,
-	data,
-	rden,
-	wren,
-	q);
-
-	input	[9:0]  address;
-	input	  clock;
-	input	[3:0]  data;
-	input	  rden;
-	input	  wren;
-	output	[3:0]  q;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri1	  clock;
-	tri1	  rden;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [3:0] sub_wire0;
-	wire [3:0] q = sub_wire0[3:0];
-
-	altsyncram	altsyncram_component (
-				.address_a (address),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.rden_a (rden),
-				.q_a (sub_wire0),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.address_b (1'b1),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b (1'b1),
-				.eccstatus (),
-				.q_b (),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_output_a = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = 1024,
-		altsyncram_component.operation_mode = "SINGLE_PORT",
-		altsyncram_component.outdata_aclr_a = "NONE",
-		altsyncram_component.outdata_reg_a = "CLOCK0",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
-		altsyncram_component.widthad_a = 10,
-		altsyncram_component.width_a = 4,
-		altsyncram_component.width_byteena_a = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-// Retrieval info: PRIVATE: AclrData NUMERIC "0"
-// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clken NUMERIC "0"
-// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING ""
-// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-// Retrieval info: PRIVATE: RegData NUMERIC "1"
-// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-// Retrieval info: PRIVATE: WidthData NUMERIC "4"
-// Retrieval info: PRIVATE: rden NUMERIC "1"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
-// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf

Computer_MiST/Commodore - MAX_MiST/rtl/MAINRAM.qip

@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "MAINRAM.v"]

Computer_MiST/Commodore - MAX_MiST/rtl/MAINRAM.v

@@ -1,177 +0,0 @@
-// megafunction wizard: %RAM: 1-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram 
-
-// ============================================================
-// File Name: MAINRAM.v
-// Megafunction Name(s):
-// 			altsyncram
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 13.1.0 Build 162 10/23/2013 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2013 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, Altera MegaCore Function License 
-//Agreement, or other applicable license agreement, including, 
-//without limitation, that your use is for the sole purpose of 
-//programming logic devices manufactured by Altera and sold by 
-//Altera or its authorized distributors.  Please refer to the 
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module MAINRAM (
-	address,
-	clock,
-	data,
-	rden,
-	wren,
-	q);
-
-	input	[10:0]  address;
-	input	  clock;
-	input	[7:0]  data;
-	input	  rden;
-	input	  wren;
-	output	[7:0]  q;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri1	  clock;
-	tri1	  rden;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [7:0] sub_wire0;
-	wire [7:0] q = sub_wire0[7:0];
-
-	altsyncram	altsyncram_component (
-				.address_a (address),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.rden_a (rden),
-				.q_a (sub_wire0),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.address_b (1'b1),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b (1'b1),
-				.eccstatus (),
-				.q_b (),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_output_a = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = 2048,
-		altsyncram_component.operation_mode = "SINGLE_PORT",
-		altsyncram_component.outdata_aclr_a = "NONE",
-		altsyncram_component.outdata_reg_a = "CLOCK0",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
-		altsyncram_component.widthad_a = 11,
-		altsyncram_component.width_a = 8,
-		altsyncram_component.width_byteena_a = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-// Retrieval info: PRIVATE: AclrData NUMERIC "0"
-// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clken NUMERIC "0"
-// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING ""
-// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-// Retrieval info: PRIVATE: RegData NUMERIC "1"
-// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-// Retrieval info: PRIVATE: WidthData NUMERIC "8"
-// Retrieval info: PRIVATE: rden NUMERIC "1"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf

Computer_MiST/Commodore - MAX_MiST/rtl/MAX.sv

@@ -1,331 +0,0 @@
-module MAX(
-	input         CLOCK_27,
-   output  [5:0] VGA_R,
-   output  [5:0] VGA_G,
-   output  [5:0] VGA_B,
-   output        VGA_HS,
-   output        VGA_VS,	 
-   output        LED,
-   output        AUDIO_L,
-   output        AUDIO_R,	
-   input         SPI_SCK,
-   output        SPI_DO,
-   input         SPI_DI,
-   input         SPI_SS2,
-   input         SPI_SS3,
-	input         SPI_SS4,
-   input         CONF_DATA0
-
-	);
-	
-`include "build_id.sv" 
-	 
-localparam CONF_STR = {
-		  "Commodore MAX;e0;",
-		  "O2,SID Filter,On,Off;",
-		  "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
-		  "T5,Reset;",
-		  "V,v0.0.",`BUILD_DATE
-		};	
-	
-wire clk_cpu, clk_sid, clk_ce, phi0_cpu;	
-wire locked;
-wire        scandoubler_disable;
-wire        ypbpr;
-wire        ps2_kbd_clk, ps2_kbd_data;
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-assign LED = 1;
-
-reg [7:0] reset_cnt;
-always @(posedge clk_cpu) begin
-	if(!locked || buttons[1] || status[0] || status[5])// | dio_download)
-		reset_cnt <= 8'h0;
-	else if(reset_cnt != 8'd255)
-		reset_cnt <= reset_cnt + 8'd1;
-end 
-
-wire reset = (reset_cnt != 8'd255);
-
-wire [15:0]ADDR_BUS;	
-wire [15:0]VIC_ADDR_BUS;	
-tri [7:0]DATA_BUS;	
-wire BA;
-wire RW;
-wire nRW_PLA;
-wire nRAM;
-wire nEXTRAM;
-wire nVIC;
-wire nSID;
-wire nCIA_PLA;
-wire nCIA;
-wire nROML;
-wire nROMH;
-wire nCOLRAM;
-wire nIRQ;
-wire nNMI;
-wire BUF;
-wire AEC;
-
-// Video
-wire hs, vs;
-wire [5:0]r, g, b;
-wire [17:0]audio;	
-//EXPANSIONS PORT
-wire SP;
-wire CNT;
-//Joystick
-wire [7:0]JoyA,JoyB;
-
-
-wire [7:0]CPU_DI;
-wire [7:0]CPU_DO;
-wire [7:0]cpuIO;
-//CIA 
-wire [7:0]CIA_DO;
-//VIC
-wire [7:0]VIC_DO;
-wire [3:0]VIC_ColIndex;
-//Main RAM
-wire [7:0]RAM_DO;
-//Color RAM
-wire [3:0]COL_DI;
-wire [3:0]COL_DO;
-//SID
-wire [7:0]SID_DO;
-//CARD
-wire [7:0]CART_DO;
-wire [7:0]cia_pai;
-wire [7:0]cia_pao;
-wire [7:0]cia_pbi;
-wire [7:0]cia_pbo;
-
-wire enableCPU, enableCIA, enableVIC = 1;
-wire enablePixel = 1;
-wire pulseRd;
-
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_cpu),//32
-	.c1(clk_sid),//1
-	.c2(clk_ce),//8
-	.c3(phi0_cpu),//todo
-	.locked(locked)
-	);	
-	
-mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
-(
-	.conf_str(CONF_STR),
-	.clk_sys(clk_cpu),
-	.SPI_SCK(SPI_SCK),
-	.CONF_DATA0(CONF_DATA0),
-	.SPI_SS2(SPI_SS2),
-	.SPI_DO(SPI_DO),
-	.SPI_DI(SPI_DI),
-	.buttons(buttons),
-	.switches(switches),
-	.scandoubler_disable(scandoubler_disable),
-	.ypbpr(ypbpr),
-	.status(status),
-	.ps2_kbd_clk(ps2_kbd_clk),
-	.ps2_kbd_data(ps2_kbd_data),
-	.joystick_0(JoyA),
-	.joystick_1(JoyB)
-);
-
-video_mixer #(.LINE_LENGTH(600), .HALF_DEPTH(0)) video_mixer
-(
-	.clk_sys(clk_cpu),
-	.ce_pix(clk_ce),
-	.ce_pix_actual(clk_ce),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
-	.scandoubler_disable(scandoubler_disable),
-	.hq2x(status[4:3]==1),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.R(r),
-	.G(g),
-	.B(b),
-	.mono(0),
-	.HSync(hs),
-	.VSync(vs),
-	.line_start(0),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS)
-);
-	
-sigma_delta_dac sigma_delta_dac
-(	
-	.DACout(AUDIO_L),
-	.DACin(audio),
-	.CLK(clk_cpu),
-	.RESET(0)
-);
-
-assign AUDIO_R = AUDIO_L;
-	
-//CPU MOS6510
-cpu_6510 U5 (
-	.clk(phi0_cpu),
-	.reset(reset),
-	.enable(enableCPU),
-	.nmi_n(nNMI),
-	.nmi_ack(),	
-	.irq_n(nIRQ),
-	.CPUdi(CPU_DI),
-	.CPUdo(CPU_DO),
-	.addr(ADDR_BUS),
-	.we(RW),
-	.doIO(cpuIO),
-	.diIO("00010111")
-	);
-
-//PLA	MOS6703
-pla_6703 pla_6703 (
-	.A(ADDR_BUS[15:10]),
-	.DI(CPU_DO),// Color Data
-	.DO(),//CPU_DI),// DataBUS
-	.CLK(clk_cpu),
-	.BA(BA),
-	.RW_IN(RW),
-	.RAM(nRAM), 						//invert
-	.EXRAM(nEXTRAM), 					//invert
-	.VIC(nVIC),  						//invert
-	.SID(nSID),  						//invert
-	.CIA(nCIA_PLA),					//invert
-	.COLRAM(nCOLRAM),  				//invert
-	.ROML(nROML),  					//invert
-	.ROMH(nROMH), 						//invert
-	.BUF(BUF),							//not invert
-	.RW_OUT(nRW_PLA)  				//invert
-	);	
-
-
-
-//COLRAM 1024x4
-COLRAM U11 (
-	.address(ADDR_BUS[9:0]),
-	.clock(clk_cpu),
-	.data(CPU_DO),
-	.rden(~nCOLRAM),
-	.wren(~nRW_PLA),
-	.q(COL_DO)
-	);
-
-//MAINRAM 2048x8
-MAINRAM U6 (
-	.address(ADDR_BUS[10:0]),
-	.clock(clk_cpu),
-	.data(CPU_DO),
-	.rden(~nRAM),
-	.wren(~nRW_PLA),
-	.q(CPU_DI)
-	);	
-
-
-//VIC MOS6566
-vic_656x vic_656x (
-	.clk(clk_cpu),
-	.phi(phi0_cpu),// phi = 0 is VIC cycle-- phi = 1 is CPU cycle (only used by VIC when BA is low)
-	.enaData(enablePixel),
-	.enaPixel(enableVIC),
-	.baSync(0),
-	.ba(BA),
-	.mode6569(0),// PAL 63 cycles and 312 lines
-	.mode6567old(1),// old NTSC 64 cycles and 262 line
-	.mode6567R8(0),// new NTSC 65 cycles and 263 line
-	.mode6572(0),// PAL-N 65 cycles and 312 lines
-	.reset(reset),
-	.cs(~nVIC),
-	.we(~nRW_PLA),
-	.rd(pulseRd),
-	.lp_n(),
-	.aRegisters(DATA_BUS[5:0]),
-	.diRegisters(CPU_DO),
-	.datai(CPU_DO),
-	.diColor(COL_DO),
-	.datao(VIC_DO),
-	.vicAddr(VIC_ADDR_BUS[13:0]),
-	.irq_n(nIRQ),
-	.hSync(hs),
-	.vSync(vs),
-	.colorIndex(VIC_ColIndex),
-	.debugX(),
-	.debugY(),
-	.vicRefresh(),
-	.addrValid()
-	);
-
-fpga64_rgbcolor fpga64_rgbcolor (
-	.index(VIC_ColIndex),
-	.r(r[5:0]),
-	.g(g[5:0]),
-	.b(b[5:0])
-	);
-
-//CIA MOS6526
-cia_6526 cia_6526 (
-	.clk(clk_cpu),
-	.todClk(vs),
-	.reset(reset),
-	.enable(enableCIA),
-	.cs(~nCIA),
-	.we(~RW),
-	.rd(pulseRd),
-	.addr(ADDR_BUS[3:0]),
-	.CIAdi(CPU_DO),
-	.CIAdo(CIA_DO),
-	.ppai(cia_pai),//Keyboard
-	.ppao(cia_pao),//Keyboard
-	.ppbi(cia_pbi),//Keyboard
-	.ppbo(cia_pbo),//Keyboard
-	.flag_n(1),
-	.sp(SP),
-	.cnt(CNT),
-	.irq_n(~nIRQ)
-	);
-	
-//SID MOS6581
-sid_6581 sid_6581 (
-	.clk32(clk_cpu),
-	.clk_1MHz(clk_sid),
-	.reset(reset),   	
-	.cs(~nSID),
-   .we(~RW),
-	.addr(ADDR_BUS[3:0]),
-   .data_i(CPU_DO),
-   .data_o(SID_DO),
-   .poti_x(~(cia_pao[7] & JoyA[5]) | (cia_pao[6] & JoyB[5])),//todo
-   .poti_y(~(cia_pao[7] & JoyA[6]) | (cia_pao[6] & JoyB[6])),//todo   
-   .audio_data(audio)
-	);
-	
-cart cart(
-	.clk0(clk_cpu),
-	.addr(ADDR_BUS),
-	.data_i(CPU_DO),
-	.data_o(CART_DO),
-	.nmi(nNMI),
-   .reset(reset),
-	.romL(nROML),
-	.romH(nROMH),
-	.rw_pla_n(nRW_PLA),
-	.ba(BA),
-	.cia_pla_n(nCIA_PLA),
-	.cia_n(nCIA),
-	.cnt(CNT),
-	.exram_n(nEXTRAM),
-	.sp(SP),
-	.rw_n(RW),
-	.irq_n(nIRQ)
-	);
-	
-endmodule 

Computer_MiST/Commodore - MAX_MiST/rtl/build_id.sv

@@ -1,2 +0,0 @@
-`define BUILD_DATE "180103"
-`define BUILD_TIME "021747"

Computer_MiST/Commodore - MAX_MiST/rtl/cart.sv

@@ -1,21 +0,0 @@
-module cart(
-   input         	clk0,
-	input [15:0]	addr,
-	input [7:0]		data_i,
-	output [7:0]	data_o,
-	output reg    	nmi,
-   input         	reset,	
-	input         	romL,						// romL signal in
-	input         	romH,
-	input				rw_pla_n,
-	input				ba,
-	input				cia_pla_n,
-	input				cia_n,
-	input				cnt,
-	input				exram_n,
-	input				sp,
-	input				rw_n,
-	input				irq_n
-);
-
-endmodule 

Computer_MiST/Commodore - MAX_MiST/rtl/cia_6526.vhd

@@ -1,783 +0,0 @@
--- -----------------------------------------------------------------------
---
---                                 FPGA 64
---
---     A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- 6526 Complex Interface Adapter
---
--- rev 1 - june17 / TOD alarms
--- -----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity cia_6526 is
-	generic (
-		todEnabled : std_logic := '0'
-	);
-	port (
-		clk: in std_logic;
-		todClk: in std_logic;
-		reset: in std_logic;
-		enable: in std_logic;
-		cs: in std_logic;
-		we: in std_logic; -- Write strobe
-		rd: in std_logic; -- Read strobe
-
-		addr: in unsigned(3 downto 0);
-		CIAdi: in unsigned(7 downto 0);
-		CIAdo: out unsigned(7 downto 0);
-
-		ppai: in unsigned(7 downto 0);
-		ppao: out unsigned(7 downto 0);
-		ppad: out unsigned(7 downto 0);
-
-		ppbi: in unsigned(7 downto 0);
-		ppbo: out unsigned(7 downto 0);
-		ppbd: out unsigned(7 downto 0);
-
-		flag_n: in std_logic;
-		sp: out std_logic;
-		cnt: out std_logic;
-		irq_n: out std_logic
-	);
-end cia_6526;
-
--- -----------------------------------------------------------------------
-
-architecture Behavioral of cia_6526 is
-	-- IO ports
-	signal pra: unsigned(7 downto 0);
-	signal prb: unsigned(7 downto 0);
-	signal ddra: unsigned(7 downto 0);
-	signal ddrb: unsigned(7 downto 0);
-	
-	-- Timer to IO ports
-	signal timerAPulse : std_logic;
-	signal timerAToggle : std_logic;
-	signal timerBPulse : std_logic;
-	signal timerBToggle : std_logic;
-
-	-- Timer A reload registers
-	signal talo: unsigned(7 downto 0) := (others => '1');
-	signal tahi: unsigned(7 downto 0) := (others => '1');
-
-	-- Timer B reload registers
-	signal tblo: unsigned(7 downto 0) := (others => '1');
-	signal tbhi: unsigned(7 downto 0) := (others => '1');
-
-	-- Timer A and B internal registers
-	signal timerA : unsigned(15 downto 0);
-	signal forceTimerA : std_logic;
-	signal loadTimerA : std_logic;
-	signal clkTimerA : std_logic; -- internal timer clock
-
-	signal timerB: unsigned(15 downto 0);
-	signal forceTimerB : std_logic;
-	signal loadTimerB : std_logic;
-	signal clkTimerB : std_logic; -- internal timer clock
-	
-	signal WR_Delay_offset : std_logic; -- adjustable WR signal delay - LCA jun17
-
-	-- Config register A
-	signal cra_start : std_logic;
-	signal cra_pbon : std_logic;
-	signal cra_outmode : std_logic;
-	signal cra_runmode : std_logic;
-	signal cra_runmode_reg : std_logic;
-	signal cra_inmode : std_logic;
-	signal cra_spmode : std_logic;
-	signal cra_todin : std_logic;
-	
-	-- Config register B
-	signal crb_start : std_logic;
-	signal crb_pbon : std_logic;
-	signal crb_outmode : std_logic;
-	signal crb_runmode : std_logic;
-	signal crb_runmode_reg : std_logic;
-	signal crb_inmode5 : std_logic;
-	signal crb_inmode6 : std_logic;
-	signal crb_alarm : std_logic;
-
-	-- TOD 50/60 hz clock
-	signal todTick : std_logic;
-	signal oldTodClk : std_logic;
-	signal tod_clkcnt: unsigned(2 downto 0);
-
-	-- TOD counters
-	signal tod_running: std_logic;
-	signal tod_10ths: unsigned(3 downto 0);
-	signal tod_secs: unsigned(6 downto 0);
-	signal tod_mins: unsigned(6 downto 0);
-	signal tod_hrs: unsigned(7 downto 0);
-	signal tod_pm: std_logic;
-	
-	-- TOD latches
-	signal tod_latched: std_logic;
-	signal tod_latch_10ths: unsigned(3 downto 0);
-	signal tod_latch_secs: unsigned(6 downto 0);
-	signal tod_latch_mins: unsigned(6 downto 0);
-	signal tod_latch_hrs: unsigned(7 downto 0);
-	constant tod_latch_pm: std_logic := '0';
-
-	-- TOD alarms - LCA
-	signal tod_10ths_alarm: unsigned(3 downto 0);
-	signal tod_secs_alarm: unsigned(6 downto 0);
-	signal tod_mins_alarm: unsigned(6 downto 0);
-	signal tod_hrs_alarm: unsigned(7 downto 0);
-	signal tod_pm_alarm: std_logic;
-	
-	-- Interrupt processing
-	signal resetIrq : boolean;
-	signal intr_flagn : std_logic;
-	signal intr_serial : std_logic;
-	signal intr_alarm : std_logic; -- LCA
-	signal intr_timerA : std_logic;
-	signal intr_timerB : std_logic;
-	signal mask_timerA : std_logic;
-	signal mask_timerB : std_logic;
-	signal mask_alarm : std_logic; -- LCA
-	signal mask_serial : std_logic;
-	signal mask_flagn : std_logic;
-	signal ir: std_logic;
-
-	signal prevFlag_n: std_logic;
-
-	signal myWr : std_logic;
-	signal myRd : std_logic;
-begin
--- -----------------------------------------------------------------------
--- chip-select signals
--- -----------------------------------------------------------------------
-	myWr <= cs and we;
-	myRd <= cs and rd;
-
--- -----------------------------------------------------------------------
--- I/O ports
--- -----------------------------------------------------------------------
-	-- Port A
-	process(pra, ddra)
-	begin
-		ppad <= ddra;
-		ppao <= pra or (not ddra);
-	end process;
-
-	-- Port B
-	process(prb, ddrb, cra_pbon, cra_outmode, crb_pbon, crb_outmode, timerAPulse, timerAToggle, timerBPulse, timerBToggle)
-	begin
-		ppbd <= ddrb;
-		ppbo <= prb or (not ddrb);
-		if cra_pbon = '1' then
-			ppbo(6) <= timerAPulse or (not ddrb(6));
-			if cra_outmode = '1' then
-				ppbo(6) <= timerAToggle or (not ddrb(6));
-			end if;
-		end if;
-		if crb_pbon = '1' then
-			ppbo(7) <= timerBPulse or (not ddrb(7));
-			if crb_outmode = '1' then
-				ppbo(7) <= timerBToggle or (not ddrb(7));
-			end if;
-		end if;
-	end process;
-	
-	-- I/O port registers
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if myWr = '1' then
-				case addr is
-				when X"0" => pra <= CIAdi;
-				when X"1" => prb <= CIAdi;
-				when X"2" => ddra <= CIAdi;
-				when X"3" => ddrb <= CIAdi;
-				when others => null;
-				end case;
-			end if;
-			if reset = '1' then
-				pra <= (others => '0');
-				prb <= (others => '0');
-				ddra <= (others => '0');
-				ddrb <= (others => '0');
-			end if;
-		end if;	
-	end process;
-
--- -----------------------------------------------------------------------
--- TOD - time of day
--- -----------------------------------------------------------------------
-	process(clk)
-	begin
-		-- Process rising edge on the todClk.
-		-- There is a prescaler of 5 or 6 to get 10ths of seconds from
-		-- 50 Hz or 60 Hz line frequency.
-		--
-		-- Output is a 'todTick' signal synchronished with enable signal (@ 1Mhz).
-		if rising_edge(clk) then			
-			if todEnabled = '1' then
-				if enable = '1' then
-					todTick <= '0';
-				end if;
-
-				if todClk = '1' and oldTodClk = '0' then
-					-- Divide by 5 or 6 dependng on 50/60 Hz flag.
-					if tod_clkcnt /= "000" then
-						tod_clkcnt <= tod_clkcnt - 1;
-					else
-						todTick <= tod_running;
-						tod_clkcnt <= "101"; -- 60 Hz
-						if cra_todin = '1' then
-							tod_clkcnt <= "100"; -- 50 Hz
-						end if;
-					end if;
-				end if;
-				oldTodClk <= todClk;
-			else
-				todTick <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(clk)
-		variable new_10ths : unsigned(3 downto 0);
-		variable new_secsL : unsigned(3 downto 0);
-		variable new_secsH : unsigned(2 downto 0);
-		variable new_minsL : unsigned(3 downto 0);
-		variable new_minsH : unsigned(2 downto 0);
-		variable new_hrsL : unsigned(3 downto 0);
-		variable new_hrsH : std_logic;
-		variable new_hrs_byte : unsigned(7 downto 0); -- LCA am/pm and hours
-	begin
-		if rising_edge(clk) then
-			new_10ths := tod_10ths;
-			new_secsL := tod_secs(3 downto 0);
-			new_secsH := tod_secs(6 downto 4);
-			new_minsL := tod_mins(3 downto 0);
-			new_minsH := tod_mins(6 downto 4);
---			new_hrsL := tod_hrs(3 downto 0);
---			new_hrsH := tod_hrs(4);
-			new_hrs_byte := tod_hrs (7 downto 0); -- LCA am/pm and hours
---			new_hrs_byte := new_hrsH & new_hrsL;
-			
-			if enable = '1'
-			and todTick = '1' then
-				if new_10ths /= "1001" then
-					new_10ths := new_10ths + 1;
-				else
-					new_10ths := "0000";
-					if new_secsL /= "1001" then
-						new_secsL := new_secsL + 1;
-					else
-						new_secsL := "0000";
-						if new_secsH /= "101" then
-							new_secsH := new_secsH + 1;
-						else
-							new_secsH := "000";
-							if new_minsL /= "1001" then
-								new_minsL := new_minsL + 1;
-							else
-								new_minsL := "0000";
-								if new_minsH /= "101" then
-									new_minsH := new_minsH + 1;
-								else
-									new_minsH := "000";
-									-- hrs were missing jun17 LCA
-									-- I mean completely absent from code :) !!!!!!
-									-- case to lookup then handles oddities in others
-									-- retarded am/pm flag flip madness handled at register load below (REG B)
-									
-									case tod_hrs is											-- case state to set hours and am/pm 
-										when "00010010" =>
-											new_hrs_byte := "00000001";					-- 1 am set
-										when "00000001" => 
-											new_hrs_byte := "00000010";
-										when "00000010" => 
-											new_hrs_byte := "00000011";
-										when "00000011" => 
-											new_hrs_byte := "00000100";
-										when "00000100" => 
-											new_hrs_byte := "00000101";
-										when "00000101" => 
-											new_hrs_byte := "00000110";
-										when "00000110" => 
-											new_hrs_byte := "00000111";
-										when "00000111" => 
-											new_hrs_byte := "00001000";
-										when "00001000" => 
-											new_hrs_byte := "00001001";
-										when "00001001" => 
-											new_hrs_byte := "00010000";
-										when "00010000" => 
-											new_hrs_byte := "00010001";					-- 11am set
-										when "00010001" => 
-											new_hrs_byte := "10010010";					-- 12pm set
-										when "10010010" => 
-											new_hrs_byte := "10000001";					-- 1 pm set
-										
-										when "10000001" => 
-											new_hrs_byte := "10000010";
-										when "10000010" => 
-											new_hrs_byte := "10000011";
-										when "10000011" => 
-											new_hrs_byte := "10000100";
-										when "10000100" => 
-											new_hrs_byte := "10000101";
-										when "10000101" => 
-											new_hrs_byte := "10000110";
-										when "10000110" => 
-											new_hrs_byte := "10000111";
-										when "10000111" => 
-											new_hrs_byte := "10001000";
-										when "10001000" => 
-											new_hrs_byte := "10001001";
-										when "10001001" => 
-											new_hrs_byte := "10010000";					-- 10pm set
-										when "10010000" => 
-											new_hrs_byte := "10010001";					-- 11pm set
-										when "10010001" => 
-											new_hrs_byte := "00010010";					-- 12am set (midnight)
-										when others =>
-											new_hrs_byte (3 downto 0) := new_hrs_byte (3 downto 0) + 1;
-											--null;
-									end case;
-										
-								end if;
-							end if;
-						end if;
-					end if;
-				end if;
-			end if;
-
-			if myWr = '1' then
-				if crb_alarm = '0' then
-					case addr is
-					when X"8" =>
-						new_10ths := CIAdi(3 downto 0);
-						tod_running <= '1';
-					when X"9" =>
-						new_secsL := CIAdi(3 downto 0);
-						new_secsH := CIAdi(6 downto 4);
-					when X"A" =>
-						new_minsL := CIAdi(3 downto 0);
-						new_minsH := CIAdi(6 downto 4);
-					when X"B" =>
-						new_hrs_byte := CIAdi(7) & "00" & CIAdi(4 downto 0); 			-- LCA
-						tod_running <= '0';
-						if CIAdi(7 downto 0) = "10010010" or CIAdi(7 downto 0) = "00010010" then  -- super bodge because cbm flips am/pm flag at 12 am or pm (its retarded!!!!!)
-							new_hrs_byte(7) := not new_hrs_byte(7);								  -- This P.O.S. now mimics real commodore 64 !!!!! LCA
-						end if;
-					when others =>
-						null;
-					end case;
-				else -- TOD ALARM UPDATE
-					case addr is
-					when X"8" =>
-						tod_10ths_alarm <= CIAdi(3 downto 0);
-					when X"9" =>
-						tod_secs_alarm <= CIAdi(6 downto 0);
-					when X"A" =>
-						tod_mins_alarm <= CIAdi(6 downto 0);
-					when X"B" =>
---						tod_hrs_alarm <= CIAdi(4 downto 0);
---						tod_pm_alarm <= CIAdi(7);
-						tod_hrs_alarm <= CIAdi(7) & "00" & CIAdi(4 downto 0); 		-- LCA
-						if CIAdi(7 downto 0) = "10010010" or CIAdi(7 downto 0) = "00010010" then  -- super bodge because cbm flips am/pm flag at 12 am or pm (its retarded!!!!!)
-							tod_hrs_alarm(7) <= not tod_hrs_alarm(7);								  -- This P.O.S. now mimics real commodore 64 !!!!! LCA
-						end if;
-					when others =>
-						null;
-					end case;
-				end if;
-			end if;
-			
-			-- Update state
-			tod_10ths <= new_10ths;
-			tod_secs <= new_secsH & new_secsL;
-			tod_mins <= new_minsH & new_minsL;
-			tod_hrs <= new_hrs_byte; 								-- LCA
-			
-			if tod_latched = '0' then
-				tod_latch_10ths <= new_10ths;
-				tod_latch_secs <= new_secsH & new_secsL;
-				tod_latch_mins <= new_minsH & new_minsL;
-				tod_latch_hrs <= new_hrs_byte;					-- LCA
-			end if;
-			
-			-- TOD ALARM test for match - LCA
-			if (tod_10ths = tod_10ths_alarm) and
-				(tod_secs = tod_secs_alarm) and
-				(tod_mins = tod_mins_alarm) and
-				(tod_hrs = tod_hrs_alarm) and
-				(crb_alarm = '1') then
-				intr_alarm <= '1' ;
-			end if;
-			
-			if reset = '1' then
-				tod_running <= '0';
-				tod_10ths_alarm <= "0000" ;
-				tod_secs_alarm <= "0000000" ;
-				tod_mins_alarm <= "0000000" ;
-				tod_hrs_alarm <= "00000000" ;
-				tod_pm_alarm <= '0' ;
-			end if;
-			
-			if resetIrq then 
-				intr_alarm <= '0' ;
-			end if;
-		end if;		
-	end process;
-	
-	-- Control TOD output latch
-	-- Reading the hours latches the output until
-	-- the 10ths of seconds are read. While latched the
-	-- clock continues to run in the bankground.
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if myRd = '1' then
-				case addr is
-				when X"8" => tod_latched <= '0';
-				when X"B" => tod_latched <= '1';
-				when others => null;
-				end case;
-			end if;
-		end if;		
-	end process;
-
-
--- -----------------------------------------------------------------------
--- Timer A and B
--- -----------------------------------------------------------------------
-
-
--- adjustable time delay jun17 - LCA
-
--- -----------------------------------------------------------------------
--- -----------------------------------------------------------------------
-
-	process(clk)
-		variable WR_delay : unsigned(15 downto 0);
-	begin
-		if rising_edge(clk) then
-			if (myWr = '0' or reset =  '1') then
-				WR_delay := "0000000000000000";
-				WR_Delay_offset <= '0';
---			end if;
-			elsif (myWr = '1' and (WR_delay < 31)) then
-				WR_delay := WR_delay + 1;
---			end if;
-			elsif (WR_delay > 8) then               -- adds a (1/32mhz * value) qualifier to WR signal in timers - LCA jun17
-				WR_Delay_offset <= '1';
-				else
-				WR_Delay_offset <= '0';
-			end if;
-		end if;		
-	end process;
-	
--- -----------------------------------------------------------------------
-
-	process(clk)
-		variable newTimerA : unsigned(15 downto 0);
-		variable nextClkTimerA : std_logic;
-		variable timerBInput : std_logic;
-		variable newTimerB : unsigned(15 downto 0);
-		variable nextClkTimerB : std_logic;
-		variable new_cra_runmode : std_logic;
-		variable new_crb_runmode : std_logic;
-	begin		
-		if rising_edge(clk) then
-			loadTimerA <= '0';
-			loadTimerB <= '0';
-			new_cra_runmode := cra_runmode;
-			new_crb_runmode := crb_runmode;
-			
-			if resetIrq then
-				intr_timerA <= '0';
-				intr_timerB <= '0';
-			end if;
-
-			if myWr = '1' then
---			if (myWr = '1' and WR_Delay_offset = '1') then         -- x/32mhz offset to qualify WR signal LCA jun17
-				case addr is
-				when X"4" =>
-					talo <= CIAdi;
-				when X"5" =>
-					tahi <= CIAdi;
-					if cra_start = '0' then
-						loadTimerA <= '1';
-					end if;
-				when X"6" =>
-					tblo <= CIAdi;
-				when X"7" =>
-					tbhi <= CIAdi;
-					if crb_start = '0' then
-						loadTimerB <= '1';
-					end if;
-				when X"E" =>
-					if cra_start = '0' then
-						-- Only set on rising edge
-						timerAToggle <= timerAToggle or CIAdi(0);
-					end if;
-					cra_start <= CIAdi(0);
-					new_cra_runmode := CIAdi(3);
-				when X"F" =>
-					if crb_start = '0' then
-						-- Only set on rising edge
-						timerBToggle <= timerBToggle or CIAdi(0);
-					end if;
-					crb_start <= CIAdi(0);
-					new_crb_runmode := CIAdi(3);
-				when others => null;
-				end case;
-			end if;
-			
-			if reset = '1' then
-				new_cra_runmode := '0';
-				new_crb_runmode := '0';
-			end if;
-			
-			cra_runmode <= new_cra_runmode;
-			crb_runmode <= new_crb_runmode;
-
-			if enable = '1' then
-				--
-				-- process timer A
-				--
-				timerAPulse <= '0';
-				newTimerA := timerA;
-				
-				-- CNT is not emulated so don't count when inmode = 1
-				nextClkTimerA := cra_start and (not cra_inmode);
-				if clkTimerA = '1' then
-					newTimerA := newTimerA - 1;
-				end if;
-				if nextClkTimerA = '1'
-				and newTimerA = 0 then
-					intr_timerA <= '1';
-					loadTimerA <= '1';
-					timerAPulse <= '1';
-					timerAToggle <= not timerAToggle;
-					if (new_cra_runmode or cra_runmode) = '1' then
-						cra_start <= '0';
-					end if;
-				end if;
-				if forceTimerA = '1' then
-					loadTimerA <= '1';
-				end if;
-				clkTimerA <= nextClkTimerA;
-				timerA <= newTimerA;
-					
-				--
-				-- process timer B
-				--
-				timerBPulse <= '0';
-				newTimerB := timerB;
-
-				if crb_inmode6 = '1' then
-					-- count timerA underflows
-					timerBInput := timerAPulse;
-				elsif crb_inmode5 = '0' then
-					-- count clock pulses
-					timerBInput := '1'; 
-				else
-					-- CNT is not emulated so don't count
-					timerBInput := '0';
-				end if;
-				nextClkTimerB := timerBInput and crb_start;
-				if clkTimerB = '1' then
-					newTimerB := newTimerB - 1;
-				end if;				
-				if nextClkTimerB = '1'
-				and newTimerB = 0 then
-					intr_timerB <= '1';
-					loadTimerB <= '1';
-					timerBPulse <= '1';
-					timerBToggle <= not timerBToggle;
-					if (new_crb_runmode or crb_runmode) = '1' then
-						crb_start <= '0';
-					end if;
-				end if;
-				if forceTimerB = '1' then
-					loadTimerB <= '1';
-				end if;
-				clkTimerB <= nextClkTimerB;
-				timerB <= newTimerB;
-			end if;
-
-			if loadTimerA = '1' then
-				timerA <= tahi & talo;
-				clkTimerA <= '0';
-			end if;
-
-			if loadTimerB = '1' then
-				timerB <= tbhi & tblo;
-				clkTimerB <= '0';
-			end if;
-		end if;
-	end process;
-
-
--- -----------------------------------------------------------------------
--- Interrupts
--- -----------------------------------------------------------------------
-	resetIrq <= ((myRd = '1') and (addr = X"D")) or (reset = '1');
-	irq_n <= not(ir);
-	intr_serial <= '0';
-
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if enable = '1' then
-				ir <= ir
-				or (intr_timerA and mask_timerA)
-				or (intr_timerB and mask_timerB)
-				or (intr_alarm and mask_alarm)
-				or (intr_serial and mask_serial)
-				or (intr_flagn and mask_flagn);
-			end if;
-
-			if myWr = '1' then
-				case addr is
-				when X"D" =>
-					if CIAdi(7) ='0' then
-						mask_timerA <= mask_timerA and (not CIAdi(0));
-						mask_timerB <= mask_timerB and (not CIAdi(1));
-						mask_alarm <= mask_alarm and (not CIAdi(2)); -- LCA
-						mask_serial <= mask_serial and (not CIAdi(3));
-						mask_flagn <= mask_flagn and (not CIAdi(4));
-					else
-						mask_timerA <= mask_timerA or CIAdi(0);
-						mask_timerB <= mask_timerB or CIAdi(1);
-						mask_alarm <= mask_alarm or CIAdi(2); -- LCA
-						mask_serial <= mask_serial or CIAdi(3);
-						mask_flagn <= mask_flagn or CIAdi(4);
-					end if;
-				when others =>
-					null;
-				end case;
-			end if;
-
-			if resetIrq then
-				ir <= '0';
-			end if;
-
-			if reset = '1' then
-				mask_timerA <= '0';
-				mask_timerB <= '0';
-				mask_alarm <= '0' ;
-				mask_serial <= '0';
-				mask_flagn <= '0';
-			end if;
-		end if;
-	end process;
-
-
-
-
--- -----------------------------------------------------------------------
--- FLAG_N input
--- -----------------------------------------------------------------------
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			prevFlag_n <= flag_n;
-			if (flag_n = '0') and (prevFlag_n = '1') then
-				intr_flagn <= '1';
-			end if;
-			if resetIrq then
-				intr_flagn <= '0';
-			end if;
-		end if;
-	end process;
-
-
--- -----------------------------------------------------------------------
--- Write registers
--- -----------------------------------------------------------------------
-	process(clk)
-	begin
-		if rising_edge(clk) then
---			resetIrq <= '0';
-			if enable = '1' then
-				forceTimerA <= '0';
-				forceTimerB <= '0';
---				cra_runmode_reg <= cra_runmode;
---				crb_runmode_reg <= crb_runmode;
-			end if;
-			if myWr = '1' then
-				case addr is
-				when X"E" =>
-					cra_pbon <= CIAdi(1);
-					cra_outmode <= CIAdi(2);
---					cra_runmode <= CIAdi(3);
-					forceTimerA <= CIAdi(4);
-					cra_inmode <= CIAdi(5);
-					cra_spmode <= CIAdi(6);
-					cra_todin <= CIAdi(7);
-				when X"F" =>
-					crb_pbon <= CIAdi(1);
-					crb_outmode <= CIAdi(2);
---					crb_runmode <= CIAdi(3);
-					forceTimerB <= CIAdi(4);
-					crb_inmode5 <= CIAdi(5);
-					crb_inmode6 <= CIAdi(6);
-					crb_alarm <= CIAdi(7);
-				when others => null;
-				end case;
-			end if;
-			if reset = '1' then
-				cra_pbon <= '0';
-				cra_outmode <= '0';
---				cra_runmode <= '0';
-				cra_inmode <= '0';
-				cra_spmode <= '0';
-				cra_todin <= '0';
-				crb_pbon <= '0';
-				crb_outmode <= '0';
---				crb_runmode <= '0';
-				crb_inmode5 <= '0';
-				crb_inmode6 <= '0';
-				crb_alarm <= '0';
-			end if;
-		end if;
-	end process;
-
-
--- -----------------------------------------------------------------------
--- Read registers
--- -----------------------------------------------------------------------
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			case addr is
-			when X"0" => CIAdo <= ppai;
-			when X"1" => CIAdo <= ppbi;
-			when X"2" => CIAdo <= DDRA;
-			when X"3" => CIAdo <= DDRB;
-			when X"4" => CIAdo <= timera(7 downto 0);
-			when X"5" => CIAdo <= timera(15 downto 8);
-			when X"6" => CIAdo <= timerb(7 downto 0);
-			when X"7" => CIAdo <= timerb(15 downto 8);
-			when X"8" => CIAdo <= "0000" & tod_latch_10ths;
-			when X"9" => CIAdo <= "0" & tod_latch_secs;
-			when X"A" => CIAdo <= "0" & tod_latch_mins;
---			when X"B" => CIAdo <= tod_latch_pm & "00" & tod_latch_hrs;
-			when X"B" => CIAdo <= tod_latch_hrs; -- LCA
-			when X"C" => CIAdo <= (others => '0');
-			when X"D" => CIAdo <= ir & "00" & intr_flagn & intr_serial & intr_alarm & intr_timerB & intr_timerA;
-			when X"E" => CIAdo <= cra_todin & cra_spmode & cra_inmode & '0' & cra_runmode & cra_outmode & cra_pbon & cra_start;
-			when X"F" => CIAdo <= crb_alarm & crb_inmode6 & crb_inmode5 & '0' & crb_runmode & crb_outmode & crb_pbon & crb_start;
-			when others => CIAdo <= (others => '-');
-			end case;
-		end if;
-	end process;
-end Behavioral;

Computer_MiST/Commodore - MAX_MiST/rtl/cpu65xx_e.vhd

@@ -1,49 +0,0 @@
--- -----------------------------------------------------------------------
---
---                                 FPGA 64
---
---     A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- Interface to 6502/6510 core
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use ieee.std_logic_1164.ALL;
-use ieee.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity cpu65xx is
-	generic (
-		pipelineOpcode : boolean;
-		pipelineAluMux : boolean;
-		pipelineAluOut : boolean
-	);
-	port (
-		clk : in std_logic;
-		enable : in std_logic;
-		reset : in std_logic;
-		nmi_n : in std_logic;
-		nmi_ack : out std_logic;
-		irq_n : in std_logic;
-		so_n : in std_logic := '1';
-
-		di : in unsigned(7 downto 0);
-		do : out unsigned(7 downto 0);
-		addr : out unsigned(15 downto 0);
-		we : out std_logic;
-		
-		debugOpcode : out unsigned(7 downto 0);
-		debugPc : out unsigned(15 downto 0);
-		debugA : out unsigned(7 downto 0);
-		debugX : out unsigned(7 downto 0);
-		debugY : out unsigned(7 downto 0);
-		debugS : out unsigned(7 downto 0)
-	);
-end cpu65xx;

Computer_MiST/Commodore - MAX_MiST/rtl/cpu_6510.vhd

@@ -1,150 +0,0 @@
--- -----------------------------------------------------------------------
---
---                                 FPGA 64
---
---     A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- 6510 wrapper for 65xx core
--- Adds 8 bit I/O port mapped at addresses $0000 to $0001
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use ieee.std_logic_1164.ALL;
-use ieee.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity cpu_6510 is
-	generic (
-		pipelineOpcode : boolean:= false;
-		pipelineAluMux : boolean:= false;
-		pipelineAluOut : boolean:= false
-	);
-	port (
-		clk : in std_logic;
-		enable : in std_logic;
-		reset : in std_logic;
-		nmi_n : in std_logic;
-		nmi_ack : out std_logic;
-		irq_n : in std_logic;
-
-		CPUdi : in unsigned(7 downto 0);
-		CPUdo : out unsigned(7 downto 0);
-		addr : out unsigned(15 downto 0);
-		we : out std_logic;
-
-		diIO : in unsigned(7 downto 0);
-		doIO : out unsigned(7 downto 0);
-		
-		debugOpcode : out unsigned(7 downto 0);
-		debugPc : out unsigned(15 downto 0);
-		debugA : out unsigned(7 downto 0);
-		debugX : out unsigned(7 downto 0);
-		debugY : out unsigned(7 downto 0);
-		debugS : out unsigned(7 downto 0)
-	);
-end cpu_6510;
-
--- -----------------------------------------------------------------------
-
-architecture rtl of cpu_6510 is
-	signal localA : unsigned(15 downto 0);
-	signal localDi : unsigned(7 downto 0);
-	signal localDo : unsigned(7 downto 0);
-	signal localWe : std_logic;
-
-	signal currentIO : unsigned(7 downto 0);
-	signal ioDir : unsigned(7 downto 0);
-	signal ioData : unsigned(7 downto 0);
-	
-	signal accessIO : std_logic;
-begin
-	cpuInstance: entity work.cpu65xx(fast)
-		generic map (
-			pipelineOpcode => pipelineOpcode,
-			pipelineAluMux => pipelineAluMux,
-			pipelineAluOut => pipelineAluOut
-		)
-		port map (
-			clk => clk,
-			enable => enable,
-			reset => reset,
-			nmi_n => nmi_n,
-			nmi_ack => nmi_ack,
-			irq_n => irq_n,
-
-			di => localDi,
-			do => localDo,
-			addr => localA,
-			we => localWe,
-
-			debugOpcode => debugOpcode,
-			debugPc => debugPc,
-			debugA => debugA,
-			debugX => debugX,
-			debugY => debugY,
-			debugS => debugS
-		);
-		
-	process(localA)
-	begin
-		accessIO <= '0';
-		if localA(15 downto 1) = 0 then
-			accessIO <= '1';
-		end if;
-	end process;
-	
-	process(CPUdi, localA, ioDir, currentIO, accessIO)
-	begin
-		localDi <= CPUdi;
-		if accessIO = '1' then
-			if localA(0) = '0' then
-				localDi <= ioDir;
-			else
-				localDi <= currentIO;
-			end if;
-		end if;
-	end process;
-	
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if accessIO = '1' then
-				if localWe = '1'
-				and enable = '1' then
-					if localA(0) = '0' then
-						ioDir <= localDo;
-					else
-						ioData <= localDo;
-					end if;
-				end if;
-			end if;
-			if reset = '1' then
-				ioDir <= (others => '0');
-			end if;
-		end if;
-	end process;
-	
-	process(ioDir, ioData, diIO)
-	begin
-		for i in 0 to 7 loop
-			if ioDir(i) = '0' then
-				currentIO(i) <= diIO(i);
-			else
-				currentIO(i) <= ioData(i);
-			end if;
-		end loop;
-	end process;
-	
-	-- Cunnect zee wires
-	addr <= localA;
-	CPUdo <= localDo;
-	we <= localWe;
-	doIO <= currentIO;
-end architecture;

Computer_MiST/Commodore - MAX_MiST/rtl/data_io.v

@@ -1,126 +0,0 @@
-//
-// data_io.v
-//
-// io controller writable ram for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// ZX Spectrum adapted version
-//
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-module data_io (
-	// io controller spi interface
-	input         sck,
-	input         ss,
-	input         sdi,
-
-	output        downloading,   // signal indicating an active download
-   output reg [4:0]  index,     // menu index used to upload the file
-	 
-	// external ram interface
-	input 			   clk,
-	output reg        wr,
-	output reg [24:0] addr,
-	output reg [7:0]  data
-);
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// filter spi clock. the 8 bit gate delay is ~2.5ns in total
-wire [7:0] spi_sck_D = { spi_sck_D[6:0], sck } /* synthesis keep */;
-wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg [6:0]      sbuf;
-reg [7:0]      cmd;
-reg [4:0]      cnt;
-reg rclk;
-
-reg [24:0] laddr;
-reg [7:0] ldata;
-	
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-assign downloading = downloading_reg;
-reg downloading_reg = 1'b0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge spi_sck, posedge ss) begin
-	if(ss == 1'b1)
-		cnt <= 5'd0;
-	else begin
-		rclk <= 1'b0;
-
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15)
-			sbuf <= { sbuf[5:0], sdi};
-
-		// increase target address after write
-		if(rclk)
-			laddr <= laddr + 1;
-	 
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) 	cnt <= cnt + 4'd1;
-		else				cnt <= 4'd8;
-
-		// finished command byte
-      if(cnt == 7)
-			cmd <= {sbuf, sdi};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(sdi) begin
-				laddr <= 25'd0;
-				downloading_reg <= 1'b1; 
-			end else
-				downloading_reg <= 1'b0; 
-		end
-		
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			ldata <= {sbuf, sdi};
-			rclk <= 1'b1;
-		end
-		
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15))
-			index <= {sbuf[3:0], sdi};
-	end
-end
-
-reg rclkD, rclkD2;
-always@(posedge clk) begin
-	// bring all signals from spi clock domain into local clock domain
-	rclkD <= rclk;
-	rclkD2 <= rclkD;
-	wr <= 1'b0;
-	
-	if(rclkD && !rclkD2) begin
-		addr <= laddr;
-		data <= ldata;
-		wr <= 1'b1;
-	end
-end
-
-endmodule