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Gehstock 2018-01-22 11:32:25 +01:00
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# Auto detect text files and perform LF normalization
* text=auto

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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 20:08:26 November 23, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "20:08:26 November 23, 2017"
# Revisions
PROJECT_REVISION = "mz80k"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 20:08:26 November 23, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# mz80k_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY mz80k
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:08:26 NOVEMBER 23, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mz80k.sv
set_global_assignment -name VERILOG_FILE rtl/mycom.v
set_global_assignment -name QIP_FILE rtl/vram.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/vga.v
set_global_assignment -name VERILOG_FILE rtl/sound.v
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/ps2.v
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name QIP_FILE rtl/monrom.qip
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name VERILOG_FILE rtl/i8253.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VERILOG_FILE rtl/fz80.v
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name QIP_FILE rtl/cgrom.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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:1000000000000000000000001824427E424242002E
:100010007C22223C22227C001C22404040221C00E8
:1000200078242222222478007E40407840407E00BE
:100030007E404078404040001C22404E42221C003E
:100040004242427E424242001C08080808081C0046
:100050000E040404044438004244487048444200FA
:100060004040404040407E0042665A5A4242420070
:100070004262524A46424200182442424224180038
:100080007C42427C40404000182442424A241A00EC
:100090007C42427C484442003C42403C02423C009C
:1000A0003E080808080808004242424242423C001A
:1000B00042424224241818004242425A5A664200E0
:1000C00042422418244242002222221C080808002E
:1000D0007E02041820407E000C12103810103E00E2
:1000E000080808080F00000008080808F8000000C9
:1000F000080808080F08080808080808FF0000009A
:100100003C42465A62423C000818280808083E0053
:100110003C42020C30407E003C42023C02423C0029
:10012000040C14247E0404007E4078040244380049
:100130001C20407C42423C007E420408101010000B
:100140003C42423C42423C003C42423E02043800B7
:100150000000007E0000000000007E007E00000025
:1001600000000800000808100002040810204000E9
:10017000000000000018180000000000000808102F
:1001800000FF000000000000404040404040404070
:1001900080808080808080FF01010101010101FFDA
:1001A000000000FF000000001010101010101010D0
:1001B000FFFF000000000000C0C0C0C0C0C0C0C041
:1001C0000000000000FF0000040404040404040410
:1001D00000000000FFFFFFFF0F0F0F0F0F0F0F0FAB
:1001E00000000000000000FF010101010101010108
:1001F000000000000000FFFF0303030303030303E9
:100200000000000000000000081C3E7F7F1C3E0034
:10021000FF7F3F1F0F070301FFFFFFFFFFFFFFFFF0
:10022000081C3E7F3E1C0800000010207F201000AC
:10023000081C2A7F2A080800003C7E7E7E7E3C0047
:10024000003C424242423C003C42020C1000100082
:10025000FFC381818181C3FF0000000003040808FF
:1002600000000000C020101080C0E0F0F8FCFEFF8D
:100270000103070F1F3F7FFF000008000008000078
:1002800000081C2A080808000E18306030180E00FC
:100290003C20202020203C00367F7F7F3E1C080031
:1002A0003C04040404043C001C224A564C201E005A
:1002B000FFFEFCF8F0E0C08070180C060C1870000F
:1002C000000808082A1C080000402010080402004A
:1002D000000004027F020400F0F0F0F00F0F0F0F97
:1002E000000000000F08080800000000F8080808D7
:1002F00008080808F808080800000000FF080808B7
:100300000000013E5414140008080808000008000A
:10031000242424000000000024247E247E242400C1
:10032000081E281C0A1C08000062640810264600EB
:10033000304848304A443A000408100000000000E9
:1003400004081010100804002010080808102000ED
:100350000008083E08080000082A1C3E1C2A080065
:100360000F0F0F0FF0F0F0F0814224181824428193
:10037000101020C000000000080804030000000066
:10038000FF0000000000000080808080808080806E
:10039000FF80808080808080FF01010101010101D8
:1003A0000000FF000000000020202020202020204E
:1003B000010204081020408080402010080402013F
:1003C00000000000FF0000000808080808080808EE
:1003D000FFFFFFFF00000000F0F0F0F0F0F0F0F0A1
:1003E000000000000000FF000202020202020202FE
:1003F0000000000000FFFFFF0707070707070707C8
:100400000000000000000000000038043C443A00F6
:1004100040405C6242625C0000003C4240423C0062
:1004200002023A4642463A0000003C427E403C000E
:100430000C12107C1010100000003A46463A023CA4
:1004400040405C62424242000800180808081C0054
:1004500004000C04040444384040444850684400FC
:100460001808080808081C00000076494949490096
:1004700000005C624242420000003C4242423C00BA
:1004800000005C62625C404000003A46463A02026C
:1004900000005C624040400000003E403C027C00A6
:1004A00010107C1010120C000000424242423C002E
:1004B00000004242422418000000414949493600E8
:1004C000000044281028440000004242463A023C02
:1004D00000007E0418207E00240038043C443A00CA
:1004E0000000000102040810031C608000000000EE
:1004F000C038060100000000000000804020100805
:1005000000000000C0300C0300FF000000FF0000EE
:10051000444444444444444444FF444444FF444425
:1005200022448811224488118844221188442211CF
:10053000AA44AA11AA44AA1100000000030C30C06A
:10054000030C30C000000000C0300C0300000000AD
:100550003844444A42524C000022002222221C000D
:100560000022001C22221C004200424242423C0067
:10057000421824427E42420042182442422418007B
:1005800010202040404080800106182020404080FC
:10059000806018040402020108040402020201013E
:1005A00080804040402020108040402020180601DC
:1005B000010202040418608001010202020404081E
:1005C00010080402010000000000000080601C030D
:1005D00000000000010638C0081020408000000024
:1005E00022143E083E08080008080808FF0808080A
:1005F00024242424C381423C003C7AA9A97A3C00EB
:100600001C1C3E1C08003E00FFF7F7F7D5E3F7FF80
:10061000FFF7E3D5F7F7F7FFFFFFF7FB81FBF7FFE6
:10062000FFFFEFDF81DFEFFFBDBDBD81BDBDBDFFC2
:10063000E3DDBFBFBFDDE3FF18247EFF5A240000C7
:10064000E047427E4247E000223E2A0808497F41B7
:100650001C1C083E080814220011D2FCD211000014
:1006600000884B3F4B880000221408083E081C1CE1
:100670003C7EFFDBFF677E3C3C4281A58199423C8A
:10068000AA55AA55AA55AA550A050A050A050A0532
:10069000A050A050A050A050AA55AA55000000009C
:1006A00000000000AA55AA55AA54A850A0408000F6
:1006B000AA552A150A0502018040A050A854AA553F
:1006C000000102050A152A558080404020201010A4
:1006D0000808040402020101382838000000000064
:1006E00000542A542A542A00010102020404080872
:1006F000101020204040808000C0C8545455220073
:10070000000000000002FF020202020202020702D1
:10071000020202020202FF020000205088050200CD
:10072000000E1122C404020100FF00814242810038
:10073000007088442320408000C4A4948F94A4C4F3
:1007400000232549F14925238890A0C0C0A898B866
:10075000A8B0B8C0C0A09088804020101F20408062
:1007600000002424E724240008083E00003E080876
:10077000081020100804020455AA55AA55AA55AA23
:100780000000000000000000007070700000000019
:1007900000070707000000000077777700000000DF
:1007A0000000000000707070007070700070707059
:1007B000000707070070707000777777007070701F
:1007C00000000000000707070070707000070707AF
:1007D0000007070700070707007777770007070775
:1007E00000000000007777770070707000777777EF
:1007F00000070707007777770077777700777777B5
:00000001FF

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:10000000C34D00C3E607184200C31809C32009C343
:100010002609C33509C38109C39909C3BD08C33281
:100020000AC33604C37504C3D804C3F804C38805DF
:10003000C3C701C308030000C33810C35803C3E596
:1000400002C3FA02C3AB02C3BE02C30E0931F010F1
:10005000ED56CDC90F063C217011CDD80F2192036A
:100060003EC33238102239103E04329E113C329F7A
:10007000113EEF329211119E01CD150031F010CFDB
:100080003E3ECD1200CD3E00CD2D0721410106118F
:10009000BE232806232310F818EECD120011740198
:1000A000D55E2356EBE9CD2D07FE66C8CDF90338A2
:1000B000F55FC3D303F5DBFE0F38FBF1D3FF3E80C2
:1000C000D3FEDBFE0F30FB3E00D3FEC9CD3A08D88D
:1000D000CFCD2D07FE62280EFE63280AFE66C87784
:1000E00023CD960118EBCDD90D18E6CD3A08D8E509
:1000F000CD3A08D1C9CD2700D8CFDF11F1103E0D80
:10010000320111DFCF2A0411CD1602ED5B02111965
:100110002BCD16022A0611CD16023AF010CDC303DC
:10012000CF06682108117E23CD960110F9C9CF189A
:10013000CA46B7A5B09C200D4CB7A19CA6B097208D
:100140000D4CB20A56A80643540853F90C472D0E1D
:10015000482E0146A00645480859BF0A4D1C0D57B8
:100160009E0A58E40C44540D4B930D54CC002324A8
:100170000E167C0011B50138021EB9CFDFC37C001A
:10018000C5D5E51ABE200B052808FE0D280413234B
:1001900018F1E1D1C1C9CDB90BCD6D09AFC9162098
:1001A00020202020202053BDA49692B3204DB7B02C
:1001B000A696B79D0D4EB796204FA90D56929DA6B7
:1001C000AABDA6B097200DC5D5E53E0232A0110606
:1001D000011AFE0D2802FEC82830FECF281FFED7C8
:1001E0002824FE23217102200421890213CD1C0240
:1001F00038DFCDC8023816CDAB024118D43E0332E9
:10020000A01113C3D1013E0118F5CDC802F5CDBE32
:1002100002F1E1D1C1C9CDBA03C3E306C506081A8C
:10022000BE280923232310F83713C1C923D55E2321
:1002300056EB7CB728093AA0113D28032918FA2269
:10024000A1113E0232A011D1131A47E6F0FE302868
:10025000053A9F1118071378E60F329F114F0600D9
:1002600021A102094E3A9E1147AF8110FDC14FAF47
:10027000C943770744A70645ED0546980547FC04A2
:1002800041710442F503520000430C074447064500
:10029000980546480547B40441310442BB03520067
:1002A000000102030406080C1018202AA1117CB7D3
:1002B000280CD5EB2104E073723E01D118063E34C0
:1002C0003207E0AF3208E0C92100E036F9237EE6CC
:1002D00008200237C93A08E00F38FA3A08E00F3030
:1002E000FA10F2AFC9C5E5217104CDAE020632AFF6
:1002F000CD5B0710FAE1C1C3BE02F5C5E60F473E6C
:100300000890329E11C1F1C9F3C5D5E5329B113E6B
:10031000F0329C1121C0A8AFED52E523EB3E7432C0
:1003200007E03EB03207E02106E073722B360A3652
:10033000003E803207E0234E7EBA20FB79BB20F7D7
:100340002B0000003612367A23D14E7EBA20FB797C
:10035000BB20F7E1D1C1FBC9E53E803207E02106B1
:10036000E0F35E56FB7BB2CA7903AF21C0A8ED5221
:10037000DA8303EB3A9B11E1C911C0A83A9B11EE55
:1003800001E1C9F32106E07E2F5F7E2F57FB13C3E7
:100390007C03F5C5D5E53A9B11EE01329B113E80F9
:1003A0003207E02106E05E5621C0A8192B2BEB2175
:1003B00006E07372E1D1C1F1FBC97CCDC3037DCDF1
:1003C000C303C9F5E6F00F0F0F0FCDDA03CD3D09DA
:1003D000F1E60FCDDA03CD3D09C9D5E521E903E604
:1003E0000F5F1600197EE1D1C93031323334353612
:1003F000373839414243444546C5E501001021E9FB
:1004000003BE2003791806230C0520F537E1C1C986
:10041000D5CD1F04380767CD1F0438016FD1C9C57A
:100420001A13CDF903380D070707074F1A13CDF933
:10043000033801B1C1C9F3D5C5E516031ECC21F0BF
:1004400010018000CD3307CDB206DA63057BFECC08
:100450002011CD0900D5116C04CD150011F110CD7E
:100460001800D1CDB807CD8D04C36305579DA6965E
:10047000A6B097200DF3D5C5E516031E532A021129
:10048000E5C12A041178B1CAD404C34404D5C5E532
:1004900016013EF93200E07ECDA5073A01E0E608FC
:1004A000C2A70437C3D404230B78B1C297042A9798
:1004B000117CCDA5077DCDA507CD800715C2C4044D
:1004C000B7C3D4040600CD670705C2C604E1C1C5A1
:1004D000E5C39704E1C1D1C9F3D5C5E5160A1E28C5
:1004E00001800021F010CDB206DA8205CD5E06DA79
:1004F0008205CD1005C36305F3D5C5E5160A1E14A4
:100500002A0211E5C12A041178B1CA6305C3E604C1
:10051000D5C5E526020101E01102E0CD0106DA822F
:1005200005CD6007CD6007CD60071AE620CA1B0520
:1005300054210000229711E1C1C5E5CD2406DA82DD
:100540000577230B78B1C23B052A9711CD2406DA33
:1005500082055FCD2406DA8205BDC274057BBCC26C
:100560007405AFE1C1D1CD0007F53A9C11FEF02032
:1005700001FBF1C915CA7C0562C315053E0137C3ED
:1005800063053E0237C36305F3D5C5E52A0211E5CD
:10059000C12A0411160A1E1478B1CA6305CD3307A7
:1005A000CDB206DA8205CD5E06DA8205CDB205C38C
:1005B0006305D5C5E526010101E01102E0CD010684
:1005C000DA8205CD6007CD6007CD60071AE620CA44
:1005D000BD0554E1C1C5E5CD2406DA8205BEC27C65
:1005E00005230B78B1C2D7052A9911CD2406BCC2C8
:1005F0007C05CD2406BDC27C0515CA620562C3B761
:10060000053EF93200E0000AE608C20F0637C91AB3
:10061000E620C207060AE608C21D0637C91AE62008
:10062000CA1506C9C5D5E52100080101E01102E09F
:10063000CD0106DA5A06CD6007CD6007CD60071AF6
:10064000E620CA4F06E52A971123229711E1377D4C
:10065000176F25C23006CD01067DE1D1C1C9C5D5D0
:10066000E5636B2295110101E01102E02A9511CD9D
:100670000106382ACD6007CD6007CD60071AE62055
:1006800028EA2520EACD01063814CD6007CD6007A1
:10069000CD60071AE62020D42D20EACD010618BA35
:1006A0002100F07EB737C0E911BC01CDF500D8C3F9
:1006B0002D00C5D5E50E0A3A02E0E61020E03E0620
:1006C0003203E03C3203E00D20EDCF42111E07DF84
:1006D00078835FDF3A02E0E61020C3CD440A20F4BD
:1006E0003718BBAFC36D09CD0C00D9CDA600280EBD
:1006F0004BCDA6003728077907070707831CD9C900
:10070000F5C5D5060A3A02E0E6102004D1C1F1C9C8
:100710003E063203E03C3203E00520E918EE7F207C
:100720000D52929FB79D9C2B50B8A1BD0DCDB30922
:10073000C3CE0BC5D5E511000078B1200BEB229795
:1007400011229911E1D1C1C97EE5260807300113B4
:100750002520F9E1230BC339073E0E3DC25B07C9D3
:100760003E0D3DC26207C9F53E033203E0CD590795
:10077000CD59073E023203E0CD5907CD5907F1C9E3
:10078000F53E033203E0CD5907CD5907CD5907CDCA
:1007900059073E023203E0CD5907CD5907CD59071D
:1007A000CD6007F1C9C50608CD800707DC8007D4F6
:1007B000670705C2AB07C1C9C5D57B01F055112834
:1007C00028FECCCACC0701F82A111414CD67070BF8
:1007D00078B120F8CD80071520FACD67071D20FAE3
:1007E000CD8007D1C1C9F5C5E5D5219311AF77CD2E
:1007F000B30947E6F0FEC0C2A60878FECD285CFE2D
:10080000C92819FECA2815FECBCAB308FEC8281489
:10081000FEC728087EB7FA2708200678CDDC0D1819
:10082000CE3518033418F478CDA60DCDB50DFE6283
:1008300020BD7EE680EE807718B5CDE70637C86725
:10084000CDEA0637C83F6FC92120E07EFE3E37C0A3
:10085000E93E2EC9CD2100D8C324002A71115C16AF
:100860000021731119EB1AB70128002A7111C27AFD
:1008700008131AB7CA7D08C37B08250E502E00CD79
:10088000B40FD1D5C5CDA60DEDB0C1E1E5417ECD0A
:10089000CE0B772310F8360D2B7EFE2028F8CD06E0
:1008A00000D1E1C1F1C93A9311B7FA2708CA270864
:1008B000C32108E1E5361B23360DC39E08CDCA08C7
:1008C000FEF02002AFC9CDCE0BC9C5D5E5CD500A8B
:1008D000780738063EF0E1D1C1C907D2EC0806001E
:1008E0002108000911C90A197EC3D6083A7011B748
:1008F000C2FD08060021C90A097EC3D60879E6F0C0
:100900000F4779E60F80C6A06F2600C3E408AF3218
:1009100094113ECDCDDC0DC93A9411B7C8C3060081
:100920003E20CD3509C9CD0C003A9411B7C8D60A7E
:1009300038F420FAC9FE0DCA0E09CDA60DC54F47E1
:10094000CD460978C1C979CDB90B4FE6F0FEF0C8A4
:10095000FEC0792018FEC73014CDDC0DFEC328136D
:10096000FEC5CA6809FEC6C0AF329411C9CDE30FF7
:10097000CDB50D3A94113CFE503802D65032941148
:10098000C9F5C5D50605CDA60D1AFE0DCADF0F4F58
:10099000CD46091310F3C38409F5C5D50605CDA6C8
:1009A0000D1AFE0DCADF0FCDB90BCD6D091310F175
:1009B000C39C09C5D5E5CDB10FCDA60D7E328E11F4
:1009C000228F11AF3200E03291112F3200E021006E
:1009D00010CD1B00280E7E3D280B770630CDFF0979
:1009E00010FB18ED77CDFF09CDCA08FEF028F6F50B
:1009F000CDA60D3A8E112A8F1177F1E1D1C1C9F53B
:100A0000E53A02E00707DA250A3A91110FDA220ADD
:100A10003A92112A8F11CDA60D773A9111EE01323B
:100A20009111E1F1C93A91110FD2220A3A8E11C304
:100A3000130A3EF83200E0003A01E02FE621C244FA
:100A40000AC601C93EF93200E0003A01E0E608C9F1
:100A5000D5E506FA160005783200E0FEEF200442E4
:100A6000D1E1C9FEF828233A01E02FB728E85F7AE0
:100A7000F6805778E60F070707074F7BC50607077D
:100A8000380210FB78C1814F18CC3A01E02F5FE6A5
:100A90002128047AF640577BE6DE28BA18D0CD3AF2
:100AA00008D8CFCD16020608CDE706C8772310F880
:100AB00018F0CDBF0AD82A06117CFE123FD0E911EA
:100AC0003801CDF500D8C32A0021232527292A1D66
:100AD0001F61636567696A5D5F22242628201C1EEA
:100AE000D162646668605C5ED0110514150F2B310D
:100AF00033514554554F6B71731712190910303229
:100B0000D357525949507072D20104070A0C1B3551
:100B1000374144474A4C5B75771306080B2C343633
:100B2000D55346484B6C7476D41A03020D2EC9393E
:100B30003B5A43424D6ECA797B18160E2F2D383A18
:100B4000D758564E6F6D787AD6F0C7F0C3CDF03DCA
:100B50003FF0C8F0C4CDF07D7FC500C1F0F03C3E51
:100B6000DCC600C2CBF07C7ED8A1A3A5A7A9AA9D14
:100B70009FA2A4A6A8A09C9EDD918594958FABB161
:100B8000B39792998990B0B2DE8184878A8C9BB5A5
:100B9000B79386888BACB4B6D99A83828DAEC9B927
:100BA000BB98968EAFADB8BADAF0C7F0C3CDF0BD42
:100BB000BFC500C1F0F0BCBEDBD610D2C10B3EF009
:100BC000C9C5E521DD0B4F0600097EE1C1C9C5E5B8
:100BD00021DD0B01F000EDB1792FB718EEF0C1C2A5
:100BE000C3C4C5C6F0F0F0F0F0F0F0F0F0006162C0
:100BF000636465666768696B6A2F2A2E2D2021223F
:100C0000232425262728294F2C512B5749550102EB
:100C1000030405060708090A0B0C0D0E0F1011122C
:100C2000131415161718191A5259545045C7C8C924
:100C3000CACBCCCDCECFDFE7E8E9EAECEDD0D1D21C
:100C4000D3D4D5D6D7D8D9DADBDCDDDEC000BD9D64
:100C5000B1B5B9B49EB2B6BABE9FB3B7BBBFA38598
:100C6000A4A5A69487889C82988492908391819A67
:100C700097939589A1AF8B8696A2ABAA8A8EB0ADC9
:100C80008DA7A8A98F8CAEAC9BA099BCB8003B3AAD
:100C9000703C715A3D43563F1E4A1C5D3E5C1F5FCF
:100CA0005E377B7F367A7E334B4C1D6C5B784135EB
:100CB0003474303875394D6F6E3277767273477C85
:100CC00053314E6D48467D441B587942600603CD32
:100CD0003A08E5380810F8D1E1C1C5ED42DA7401EF
:100CE000E5C1E1C9CDCD0CE5ED52E1380403EDB02D
:100CF000C9EB09EB0903EDB8C9CF11F110CD030021
:100D00003E0D320111CDCD0C03ED43021122041131
:100D1000ED5306113E0132F010C35408CD3A08D805
:100D2000CFCD1602E516083A9D11B72802161042DB
:100D30007ECDC30323CDE30610F6CDE306E1427E6C
:100D4000CDB90BFEF0CC5108CD6D092310F1CD11BA
:100D50000EC818CCCDEB00D8ED52D823EBCFD5067A
:100D6000FF11A31104CDEA06DADD0C121320F5CF32
:100D7000CD830DCC160223D11B7AB3C8CD110EC87A
:100D8000D518ED11A311C5E51ABE2004132310F8E0
:100D9000E1C1C9CDEB00D8EBCDE70637C87723E535
:100DA000ED52E138F8C9F53A02E00730FA3A02E0CC
:100DB0000738FAF1C9F5C5D5E547CDB10F702A71ED
:100DC000117DFE2720105C1600217311197EB720BB
:100DD000052336012372C3900ECDB90BF5C5D5E5B9
:100DE000EEC0FE0DCCF40FCA8B0FFE0BD2DE0F212E
:100DF000F90D4704232310FCC3A100320E740E84A6
:100E00000E900EAE0EBF0EC50EF80E490FE10EEE9F
:100E10000ECD320AC8CD440AC0CDB309FE63CC243E
:100E20000E28F6C93A9D112F329D113FC9CD3A08BF
:100E3000D8E9CDA60DAF3203E001C0031100D021E7
:100E400028D0EDB0EB0628CDD80F011A0011731190
:100E500021731123EDB036003A7311B7C26A0ECD7B
:100E6000A60D3E013203E0C3DE0F2A711125227167
:100E700011C3390E2A71117CFE18CA320E24227158
:100E800011C3DE0F2A71117CB7CADE0F25C37E0E97
:100E90002A71117DFE27D29D0E2CC37E0E2E0024BA
:100EA0007CFE19DA7E0E2618227111C3320E2A71C9
:100EB000117DB728042DC37E0E2E2725F27E0E212C
:100EC0000000C37E0ECDA60D0E192100D00628CD40
:100ED000D80F0DC2CD0E217311061BCDD80FC3BF85
:100EE0000E3E053203E03E00327011C3DE0F3E04B9
:100EF0003203E03E01C3E80E2A71117CB5CADE0F51
:100F00007DB7C21D0F5C1600217311197EB7C21D7B
:100F10000FCDB10FCDA60D2B3600C3AE0E2A711129
:100F20005C1C1600217311197E47B73E2828023E2B
:100F3000502A7111954F0600CDB10FE5D11BCDA6FA
:100F40000DEDB02B3600C3AE0E2A71115C1C1600DD
:100F5000217311197EB70E002A71112E2728022441
:100F60000CCDB40F7EB7C2DE0FE52A71113E279576
:100F70004779B728043E288047D1D5E12BCDA60D6F
:100F80007E1236002B1B10F8C3DE0F2A71115C1C79
:100F90001600217311197EB72A7111CA9D0E2E00F9
:100FA0007CFE1728052424C37E0E24227111C3322F
:100FB0000E2A7111C5D5E5C111280021D8CF190518
:100FC000F2BE0F060009D1C1C92103E0368A3607F7
:100FD00036053E013203E0C9AF772310FCC9E1D1E9
:100FE000C1F1C9F53A9D11B72808F1F5CDCE0BCD69
:100FF000B500F1C93A9D11B7C83E0DCDB500AFC9D6
:00000001FF

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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`define BUILD_DATE "171123"
`define BUILD_TIME "223444"

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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cgrom.v"]

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// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cgrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cgrom (
address,
clock,
rden,
q);
input [10:0] address;
input clock;
input rden;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.rden_a (rden),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "../rtl/80KCG.rif"
`else
altsyncram_component.init_file = "../rtl/80KCG.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../rtl/80KCG.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../rtl/80KCG.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

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-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac is
generic (
C_bits : integer := 8
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(C_bits-1 downto 0);
dac_o : out std_logic
);
end dac;
architecture rtl of dac is
signal sig_in: unsigned(C_bits downto 0);
begin
seq: process(clk_i, res_n_i)
begin
if res_n_i = '0' then
sig_in <= to_unsigned(2**C_bits, sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
dac_o <= sig_in(C_bits);
end if;
end process seq;
end rtl;

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//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
wire [DWIDTH:0] out[2];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input [1:0] rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input [1:0] wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
wire [DWIDTH:0] out[4];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output [DWIDTH:0] q
);
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b(q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH+1){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUMWORDS,
altsyncram_component.numwords_b = NUMWORDS,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = AWIDTH+1,
altsyncram_component.widthad_b = AWIDTH+1,
altsyncram_component.width_a = DWIDTH+1,
altsyncram_component.width_b = DWIDTH+1,
altsyncram_component.width_byteena_a = 1;
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module DiffCheck
(
input [17:0] rgb1,
input [17:0] rgb2,
output result
);
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
wire [6:0] t = $signed(r) + $signed(b);
wire [6:0] gx = {g[5], g};
wire [7:0] y = $signed(t) + $signed(gx);
wire [6:0] u = $signed(r) - $signed(b);
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
// if y is inside (-24..24)
wire y_inside = (y < 8'h18 || y >= 8'he8);
// if u is inside (-4, 4)
wire u_inside = (u < 7'h4 || u >= 7'h7c);
// if v is inside (-6, 6)
wire v_inside = (v < 8'h6 || v >= 8'hfA);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [5:0] A,
input [5:0] B,
input [5:0] C,
output [5:0] O
);
function [8:0] mul6x3;
input [5:0] op1;
input [2:0] op2;
begin
mul6x3 = 9'd0;
if(op2[0]) mul6x3 = mul6x3 + op1;
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [8:0] Amul = mul6x3(A, Op[7:5]);
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
wire [8:0] At = Amul;
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[9:4];
endmodule
module Blend
(
input [5:0] rule,
input disable_hq2x,
input [17:0] E,
input [17:0] A,
input [17:0] B,
input [17:0] D,
input [17:0] F,
input [17:0] H,
output [17:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = 11'bx;
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [17:0] Input1 = E;
wire [17:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input [AWIDTH+1:0] read_x,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
reg [17:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] i;
reg [7:0] y;
wire curbuf = y[0];
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
wire [17:0] blend_result;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
reg Curr2_addr1;
reg [AWIDTH:0] Curr2_addr2;
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
wire [DWIDTH:0] Curr2tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [17:0] h2rgb;
input [8:0] v;
begin
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
end
endfunction
function [8:0] rgb2h;
input [17:0] v;
begin
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(Curr2_addr2),
.rdbuf(Curr2_addr1),
.q(Curr2tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [1:0] wrout_addr1;
reg [AWIDTH+1:0] wrout_addr2;
reg wrout_en;
reg [DWIDTH:0] wrdata;
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
(
.clk(clk),
.rdaddr(read_x),
.rdbuf(read_y),
.q(outpixel),
.wraddr(wrout_addr2),
.wrbuf(wrout_addr1),
.data(wrdata),
.wren(wrout_en)
);
always @(posedge clk) begin
reg [AWIDTH:0] offs;
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(~&offs) begin
if (i == 0) begin
Curr2_addr1 <= prevbuf;
Curr2_addr2 <= offs;
end
if (i == 1) begin
Prev2 <= Curr2;
Curr2_addr1 <= curbuf;
Curr2_addr2 <= offs;
end
if (i == 2) begin
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
if (i == 3) begin
offs <= offs + 1'd1;
end
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
else wrdata <= blend_result;
wrout_addr1 <= {curbuf, i[1]};
wrout_addr2 <= {offs, i[1]^i[0]};
wrout_en <= 1;
end
if(i==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
{B, F, H, D} <= {F, H, D, B};
end
i <= i + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
i <= 0;
y <= y + 1'd1;
prevbuf <= curbuf;
if(old_reset_frame & ~reset_frame) begin
y <= 0;
prevbuf <= 0;
end
end
old_reset_line <= reset_line;
end
end
endmodule // Hq2x

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:58:45 02/25/2008
// Design Name:
// Module Name: i8253
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module i8253(reset, clk, addr, data_out, data_in, cs, rd, wr, clk0, clk1, clk2, out0, out1, out2);
input reset;
input clk;
input [1:0] addr;
output[7:0] data_out;
input [7:0] data_in;
input cs, rd, wr;
input clk0, clk1, clk2;
output out0, out1, out2;
wire [1:0] addr;
wire [7:0] data_out, data_in;
wire cs, rd, wr;
wire clk0, clk1, clk2;
wire out0, out1, out2;
reg [7:0] mode0, mode1, mode2;
reg [15:0] max0, max1, max2;
reg [15:0] count0 = 0, count1 = 0, count2 = 0;
reg signal0 = 0, signal1 = 0, signal2 = 0;
reg read_hl0, read_hl1, read_hl2;
reg write_hl0, write_hl1, write_hl2;
reg [7:0] data;
always @(posedge clk or posedge reset) begin
if ( reset ) begin
mode0 <= 8'h00;
mode1 <= 8'h00;
mode2 <= 8'h00;
max0 <= 16'd1;
max1 <= 16'd1;
max2 <= 16'd1;
write_hl0 <= 1'b0;
write_hl1 <= 1'b0;
write_hl2 <= 1'b0;
read_hl0 <= 1'b0;
read_hl1 <= 1'b0;
read_hl2 <= 1'b0;
end else if ( cs ) begin
if ( addr == 2'd0 & wr ) begin
write_hl0 <= ( mode0[5:4] == 2'b00 | mode0[5:4] == 2'b11 ) ? ~write_hl0: write_hl0;
if ( ((mode0[5:4] == 2'b00 | mode0[5:4] == 2'b11) & write_hl0) | mode0[5:4] == 2'b10 )
max0[15:8] <= data_in;
else
max0[7:0] <= data_in;
end else if ( addr == 2'd1 & wr ) begin
write_hl1 <= ( mode1[5:4] == 2'b00 | mode1[5:4] == 2'b11 ) ? ~write_hl1: write_hl1;
if ( ((mode1[5:4] == 2'b00 | mode1[5:4] == 2'b11) & write_hl1) | mode1[5:4] == 2'b10 )
max1[15:8] <= data_in;
else
max1[7:0] <= data_in;
end else if ( addr == 2'd2 & wr ) begin
write_hl2 <= ( mode2[5:4] == 2'b00 | mode2[5:4] == 2'b11 ) ? ~write_hl2: write_hl2;
if ( ((mode2[5:4] == 2'b00 | mode2[5:4] == 2'b11) & write_hl2) | mode2[5:4] == 2'b10 )
max2[15:8] <= data_in;
else
max2[7:0] <= data_in;
end else if ( addr == 2'd3 & wr ) begin
if ( data_in[7:6] == 2'd0 ) begin
mode0 <= data_in;
read_hl0 <= data_in[5:4] == 2'b10 ? 1 : 0;
write_hl0 <= data_in[5:4] == 2'b10 ? 1 : 0;
end else if ( data_in[7:6] == 2'd1 ) begin
mode1 <= data_in;
read_hl1 <= data_in[5:4] == 2'b10 ? 1 : 0;
write_hl1 <= data_in[5:4] == 2'b10 ? 1 : 0;
end else if ( data_in[7:6] == 2'd2 ) begin
mode2 <= data_in;
read_hl2 <= data_in[5:4] == 2'b10 ? 1 : 0;
write_hl2 <= data_in[5:4] == 2'b10 ? 1 : 0;
end
end else if ( addr == 2'd0 & rd ) begin
read_hl0 <= ( mode0[5:4] == 2'b00 | mode0[5:4] == 2'b11 ) ? ~read_hl0: read_hl0;
data <= ~( ((mode0[5:4] == 2'b00 | mode0[5:4] == 2'b11 ) & read_hl0) | mode0[5:4] == 2'b10 ) ? count0[15:8] : count0[7:0];
end else if ( addr == 2'd1 & rd ) begin
read_hl1 <= ( mode1[5:4] == 2'b00 | mode1[5:4] == 2'b11 ) ? ~read_hl1: read_hl1;
data <= ~( ((mode1[5:4] == 2'b00 | mode1[5:4] == 2'b11 ) & read_hl1) | mode1[5:4] == 2'b10 ) ? count1[15:8] : count1[7:0];
end else if ( addr == 2'd2 & rd ) begin
read_hl2 <= ( mode2[5:4] == 2'b00 | mode2[5:4] == 2'b11 ) ? ~read_hl2: read_hl2;
data <= ~( ((mode2[5:4] == 2'b00 | mode2[5:4] == 2'b11 ) & read_hl2) | mode2[5:4] == 2'b10 ) ? count2[15:8] : count2[7:0];
end
end
end
always @(posedge clk0) begin
if ( count0 != 0 ) begin
count0 <= ( count0 <= max0 ) ? count0 - 1: max0;
if ( mode0[3:1] == 3'b000 | mode0[3:1] == 3'b001 ) // MODE0
signal0 <= 0;
end else begin
if ( mode0[3:1] == 3'b000 | mode0[3:1] == 3'b001 ) begin // MODE0
count0 <= max0;
signal0 <= 1;
end else begin
count0 <= max0;
signal0 <= ~signal0;
end
end
end
always @(posedge clk1) begin
if ( count1 != 0 ) begin
count1 <= ( count1 <= max1 ) ? count1 - 1: max1;
if ( mode1[3:1] == 3'b000 | mode1[3:1] == 3'b001 ) // MODE0/1
signal1 <= 0;
end else begin
if ( mode1[3:1] == 3'b000 | mode1[3:1] == 3'b001 ) begin // MODE0/1
count1 <= max1;
signal1 <= 1;
end else begin
count1 <= max1;
signal1 <= ~signal1;
end
end
end
always @(posedge clk2) begin
if ( count2 != 0 ) begin
count2 <= ( count2 <= max2 ) ? count2 - 1: max2;
if ( mode2[3:1] == 3'b000 | mode2[3:1] == 3'b001 ) // MODE0/1
signal2 <= 0;
end else begin
if ( mode2[3:1] == 3'b000 | mode2[3:1] == 3'b001 ) begin // MODE0/1
count2 <= max2;
signal2 <= 1;
end else begin
count2 <= max2;
signal2 <= ~signal2;
end
end
end
assign out0 = signal0;
assign out1 = signal1;
assign out2 = signal2;
assign data_out = data;
endmodule

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module keyboard
(
input clk,
input reset,
input ps2_kbd_clk,
input ps2_kbd_data,
output reg[7:0] joystick
);
reg [11:0] shift_reg = 12'hFFF;
wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
wire [7:0] kcode = kdata[9:2];
reg release_btn = 0;
reg [7:0] code;
reg input_strobe = 0;
always @(negedge clk) begin
reg old_reset = 0;
old_reset <= reset;
if(~old_reset & reset)begin
joystick <= 0;
end
if(input_strobe) begin
case(code)
'h16: joystick[1] <= ~release_btn; // 1
'h1E: joystick[2] <= ~release_btn; // 2
'h75: joystick[4] <= ~release_btn; // arrow up
'h72: joystick[5] <= ~release_btn; // arrow down
'h6B: joystick[6] <= ~release_btn; // arrow left
'h74: joystick[7] <= ~release_btn; // arrow right
'h29: joystick[0] <= ~release_btn; // Space
// 'h11: joystick[1] <= ~release_btn; // Left Alt
// 'h0d: joystick[2] <= ~release_btn; // Tab
'h76: joystick[3] <= ~release_btn; // Escape
endcase
end
end
always @(posedge clk) begin
reg [3:0] prev_clk = 0;
reg old_reset = 0;
reg action = 0;
old_reset <= reset;
input_strobe <= 0;
if(~old_reset & reset)begin
prev_clk <= 0;
shift_reg <= 12'hFFF;
end else begin
prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
if(prev_clk == 1) begin
if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
shift_reg <= 12'hFFF;
if (kcode == 8'he0) ;
// Extended key code follows
else if (kcode == 8'hf0)
// Release code follows
action <= 1;
else begin
// Cancel extended/release flags for next time
action <= 0;
release_btn <= action;
code <= kcode;
input_strobe <= 1;
end
end else begin
shift_reg <= kdata;
end
end
end
end
endmodule

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//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
input ps2_caps_led,
// ARM -> FPGA download
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output ioctl_wr,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] b_data;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
wire [7:0] spi_dout = { sbuf, SPI_DI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
// drive MISO only when transmitting core id
always@(negedge SPI_SCK) begin
if(!CONF_DATA0) begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
spi_do <= core_type[~bit_cnt];
end else begin
case(cmd)
// reading config string
8'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else spi_do <= 0;
end
// reading sd card status
8'h16: begin
if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else spi_do <= 0;
end
// reading sd card write data
8'h18:
spi_do <= b_data[~bit_cnt];
// reading keyboard LED status
8'h1f:
spi_do <= kbd_led[~bit_cnt];
default:
spi_do <= 0;
endcase
end
end
end
reg b_wr2,b_wr3;
always @(negedge clk_sys) begin
b_wr3 <= b_wr2;
sd_buff_wr <= b_wr3;
end
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
if(CONF_DATA0) begin
b_wr2 <= 0;
bit_cnt <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
end else begin
b_wr2 <= 0;
sbuf <= spi_dout[6:0];
bit_cnt <= bit_cnt + 1'd1;
if(bit_cnt == 5) begin
if (byte_cnt == 0) sd_buff_addr <= 0;
if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
end
// finished reading command byte
if(bit_cnt == 7) begin
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
if(byte_cnt == 0) begin
cmd <= spi_dout;
if(spi_dout == 8'h19) begin
sd_ack_conf <= 1;
sd_buff_addr <= 0;
end
if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
sd_ack <= 1;
sd_buff_addr <= 0;
end
if(spi_dout == 8'h18) b_data <= sd_buff_din;
mount_strobe <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_dout;
8'h02: joystick_0 <= spi_dout;
8'h03: joystick_1 <= spi_dout;
// store incoming ps2 mouse bytes
8'h04: begin
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_dout;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_dout;
b_wr2 <= 1;
end
8'h18: b_data <= sd_buff_din;
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
end
end
// notify image selection
8'h1c: mount_strobe <= 1;
// send image info
8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
// status, 32bit version
8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
default: ;
endcase
end
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// increase target address after write
if(rclk) addr <= addr + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
ioctl_download <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
rclk <= 1;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
assign ioctl_wr = |ioctl_wrd;
reg [1:0] ioctl_wrd;
always@(negedge clk_sys) begin
reg rclkD, rclkD2;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wrd<= {ioctl_wrd[0],1'b0};
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wrd <= 2'b11;
end
end
endmodule

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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "monrom.v"]

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// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: monrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module monrom (
address,
clock,
data,
rden,
wren,
q);
input [14:0] address;
input clock;
input [7:0] data;
input rden;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.rden_a (rden),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "80ktc.rif"
`else
altsyncram_component.init_file = "80ktc.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "80ktc.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "80ktc.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL monrom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL monrom_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

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module mycom(CLK_50MHZ, BTN_NORTH,BTN_EAST,BTN_SOUTH, BTN_WEST,
VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC, Pix_ce,
PS2_CLK, PS2_DATA, Turbo,
SW,LED,TP1);
input CLK_50MHZ;
input BTN_NORTH,BTN_EAST,BTN_SOUTH,BTN_WEST;
input PS2_CLK, PS2_DATA;
input Turbo;
output VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;
output Pix_ce;
input [3:0] SW;
output [7:0] LED;
output TP1;
// <EFBFBD>N<EFBFBD><EFBFBD><EFBFBD>b<EFBFBD>N<EFBFBD>̐<EFBFBD><EFBFBD><EFBFBD>
wire CLK_CPU;
reg CLK_2M = 0, CLK_31250 = 0;
reg [4:0] count_2M = 0;
reg [10:0] count_31250 = 0;
reg [32:0] clk_count = 0;
always @(posedge CLK_50MHZ) begin
clk_count <= clk_count + 1;
end
always @(posedge CLK_50MHZ) begin
count_2M <= count_2M >= 13 ? 0 : count_2M + 1;
count_31250 <= count_31250 >= 800 ? 0 : count_31250 + 1;
CLK_2M <= count_2M == 0 ? ~CLK_2M : CLK_2M;
CLK_31250 <= count_31250 == 0 ? ~CLK_31250 : CLK_31250;
end
assign CLK_CPU = Turbo ? clk_count[2] : clk_count[3];
// assign CLK_CPU = clk_count[2]; // 6MHZ
// assign CLK_CPU = clk_count[3]; // 3MHZ
// reset<EFBFBD><EFBFBD><EFBFBD>H
wire reset;
reg reset1 = 1, reset2 = 1;
always @( posedge CLK_CPU ) begin
reset1 <= BTN_EAST;
reset2 <= reset1;
end
assign reset = reset1 | reset2;
// Z80<EFBFBD><EFBFBD>WIRE<EFBFBD><EFBFBD><EFBFBD>`
wire [15:0] cpu_addr;
wire [7:0] cpu_data_in, cpu_data_out;
wire mreq, iorq, rd, wr, busreq, busack, intack;
wire start, waitreq;
// I/O<EFBFBD>̎<EFBFBD><EFBFBD>
wire [15:0]io_led,io_e000,io_e001,io_e002,io_8253,io_e008;
assign io_led = (cpu_addr[15:0] == 16'he300) & mreq;
assign io_e000 = (cpu_addr[15:0] == 16'he000) & mreq;
assign io_e001 = (cpu_addr[15:0] == 16'he001) & mreq;
assign io_e002 = (cpu_addr[15:0] == 16'he002) & mreq;
assign io_8253 = (cpu_addr[15:2] == 14'b11100000000001) & mreq;
assign io_e008 = (cpu_addr[15:0] == 16'he008) & mreq;
wire [7:0] io_switch = {BTN_NORTH,BTN_EAST,BTN_SOUTH,
BTN_WEST,SW[3:0]};
reg [7:0] led_buf;
reg [7:0] sound_buf;
reg [3:0] key_no;
reg speaker_enable;
always @(posedge CLK_CPU or posedge reset) begin
if (reset) begin
led_buf <= 0;
sound_buf <= 0;
key_no <= 0;
speaker_enable <= 0;
end else begin
if ( io_led & wr ) begin
led_buf <= cpu_data_out;
end else if (io_e000 & wr ) begin
key_no <= cpu_data_out[3:0];
end else if (io_e008 & wr ) begin
speaker_enable <= cpu_data_out[0];
end
end
end
assign LED = led_buf;
// Z80<EFBFBD>̎<EFBFBD><EFBFBD>
assign waitreq = start;
wire out0, out1, out2;
fz80 z80(.data_in(cpu_data_in), .data_out(cpu_data_out),
.reset_in(reset), .clk(CLK_CPU),
.mreq(mreq), .iorq(iorq), .rd(rd), .wr(wr),
.adr(cpu_addr), .waitreq(waitreq),
.nmireq(0), .intreq(out2 & 0), .busreq(busreq), .busack_out(busack),
.start(start));
// 8253<EFBFBD>̎<EFBFBD><EFBFBD> (CLK0=2M CLK1=31.25K CLK2=OUT1)
wire [7:0] i8253_data_out;
i8253 i8253_1(.reset(reset), .clk(CLK_CPU), .addr(cpu_addr[1:0]), .data_out(i8253_data_out), .data_in(cpu_data_out),
.cs(io_8253 & ~start), .rd(rd), .wr(wr),
.clk0(CLK_2M), .clk1(CLK_31250), .clk2(out1),
.out0(out0), .out1(out1), .out2(out2) );
// KEYBOARD<EFBFBD>̎<EFBFBD><EFBFBD>
wire [7:0] ps2_data;
ps2 ps2_1(.clk(CLK_50MHZ), .reset(reset), .ps2_clk(PS2_CLK), .ps2_data(PS2_DATA), .cs(io_e001 & rd), .rd(rd), .addr(key_no), .data(ps2_data));
// MAIN RAM<EFBFBD>̎<EFBFBD><EFBFBD>
wire ram_select = (( cpu_addr[15:15] == 1'b0 || cpu_addr[15:12] == 4'b1000) & mreq) & ~busack;
wire ram_en, ram_we;
wire [7:0] ram_data_out, ram_data_in;
monrom monrom(.address(cpu_addr),.clock(CLK_50MHZ),.data(ram_data_in),
.q(ram_data_out),.rden(ram_en),.wren(ram_we));
assign ram_en = ram_select;
assign ram_we = wr;
assign ram_data_in = cpu_data_out;
// VRAM<EFBFBD>̎<EFBFBD><EFBFBD>
wire vram_select = ((cpu_addr[15:11] == 5'b11010) & mreq) | busack;
wire [11:0] vram_addr;
wire vram_rd, vram_wr;
wire [7:0] vram_data, vram_data_in;
vram vram(.address(vram_addr),.clock(CLK_50MHZ),
.data(vram_data_in),.q(vram_data),.rden(vram_select),.wren(vram_wr));
assign vram_data_in = (vram_select & wr) ? cpu_data_out : 8'hzz;
// VGA<EFBFBD>̎<EFBFBD><EFBFBD>
wire [11:0] vga_addr;
vga vga1(.CLK_50MHZ(CLK_50MHZ), .VGA_RED(VGA_RED), .VGA_GREEN(VGA_GREEN), .VGA_BLUE(VGA_BLUE),
.VGA_HSYNC(VGA_HSYNC), .VGA_VSYNC(VGA_VSYNC), .Pix_ce(Pix_ce),
.VGA_ADDR(vga_addr), .VGA_DATA(vram_data), .BUS_REQ(busreq), .BUS_ACK(busack));
assign vram_addr[11:0] = busack ? vga_addr[11:0] : cpu_addr[11:0];
assign vram_rd = busack | rd;
assign vram_wr = busack ? 1'b0 : wr;
// Memory<EFBFBD>A<EFBFBD>N<EFBFBD>Z<EFBFBD>X
assign cpu_data_in = ( io_led & rd ) ? io_switch :
( io_e001 & rd ) ? ps2_data :
( io_e002 & rd ) ? {VGA_VSYNC, clk_count[24], 6'b0000000} :
( io_8253 & rd ) ? i8253_data_out :
( io_e008 & rd ) ? {7'b0000000, clk_count[19]} : // MUSIC<EFBFBD><EFBFBD><EFBFBD>Ȃǂ<EFBFBD>WAIT<EFBFBD>ŏd<EFBFBD>v
(vram_select & rd) ? vram_data :
(ram_select & rd) ? ram_data_out: 8'hzz;
assign TP1 = speaker_enable & out0;
endmodule

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module mz80k
(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"MZ80K;;",
"O2,CPU CLOCK ,6MHZ,3MHZ;",
"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"T6,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire clk_sys;
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] kbjoy;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoubler_disable;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
wire [7:0] audio;
//assign LED = 1;
wire hblank, vblank;
wire ce_vid;
wire hs, vs;
wire r,g,b;
pll pll
(
.inclk0(CLOCK_27),
.c0(clk_sys)
);
video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
(
.clk_sys(clk_sys),
.ce_pix(ce_vid),
.ce_pix_actual(ce_vid),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R({r,r,r}),
.G({g,g,g}),
.B({b,b,b}),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.scandoubler_disable(1),//scandoubler_disable),
.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
.hq2x(status[4:3]==1),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable(scandoubler_disable),
.ypbpr (ypbpr ),
.ps2_kbd_clk (ps2_kbd_clk ),
.ps2_kbd_data (ps2_kbd_data ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
mycom mycom
(
.CLK_50MHZ(clk_sys),
.BTN_NORTH(),
.BTN_EAST((status[0] | status[6] | buttons[1])),//reset
.BTN_SOUTH(),
.BTN_WEST(),
.VGA_RED(r),
.VGA_GREEN(g),
.VGA_BLUE(b),
.VGA_HSYNC(hs),
.VGA_VSYNC(vs),
.Turbo(status[2]),
.Pix_ce(ce_vid),
.PS2_CLK(ps2_kbd_clk),
.PS2_DATA(ps2_kbd_data),
.SW(),
.LED(LED),
.TP1(audio)
);
dac dac
(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
assign AUDIO_R = AUDIO_L;
endmodule

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// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
cnt <= cnt + 1;
hs <= HSync;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end
end
always @(posedge clk_sys) begin
reg hsD, hsD2;
reg vsD, vsD2;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [7:0] osd_byte;
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 50,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

283
Sharp -MZ-80K_MiST/rtl/ps2.v Normal file
View File

@ -0,0 +1,283 @@
module ps2(clk, reset,
ps2_clk, ps2_data,
cs, rd, addr, data);
input clk,reset;
input ps2_clk, ps2_data;
input cs, rd;
input [7:0] addr;
output [7:0] data;
wire clk, reset;
wire ps2_clk, ps2_data;
wire cs, rd;
wire [7:0] addr;
reg [7:0] data;
reg [7:0]key_tbl0 = 8'b11111111,
key_tbl1 = 8'b11111111,
key_tbl2 = 8'b11111111,
key_tbl3 = 8'b11111111,
key_tbl4 = 8'b11111111,
key_tbl5 = 8'b11111111,
key_tbl6 = 8'b11111111,
key_tbl7 = 8'b11111111,
key_tbl8 = 8'b11111111,
key_tbl9 = 8'b11111111,
key_tbla = 8'b11111111,
key_tblb = 8'b11111111,
key_tblc = 8'b11111111,
key_tbld = 8'b11111111,
key_tble = 8'b11111111;
reg key_f0 = 1'b0;
reg key_e0 = 1'b0;
//
// I/O(0-9) read
//
always @(posedge clk ) begin
if ( cs & rd ) begin
begin
case (addr[3:0])
4'h0: data <= key_tbl0;
4'h1: data <= key_tbl1;
4'h2: data <= key_tbl2;
4'h3: data <= key_tbl3;
4'h4: data <= key_tbl4;
4'h5: data <= key_tbl5;
4'h6: data <= key_tbl6;
4'h7: data <= key_tbl7;
4'h8: data <= key_tbl8;
4'h9: data <= key_tbl9;
4'ha: data <= key_tbla;
4'hb: data <= key_tblb;
4'hc: data <= key_tblc;
4'hd: data <= key_tbld;
4'he: data <= key_tble;
default: data <= 8'hzz;
endcase
end
end
end
//
// PS/2<EFBFBD><EFBFBD><EFBFBD>͏<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//
wire dten;
wire [7:0] kdata;
ps2_recieve ps2_recieve1(.clk(clk), .reset(reset),
.ps2_clk(ps2_clk), .ps2_data(ps2_data),
.dten(dten), .kdata(kdata));
//
//
//
always @(posedge clk or posedge reset) begin
if( reset ) begin
key_e0 <= 1'b0;
key_f0 <= 1'b0;
key_tbl0 <= 8'b11111111;
key_tbl1 <= 8'b11111111;
key_tbl2 <= 8'b11111111;
key_tbl3 <= 8'b11111111;
key_tbl4 <= 8'b11111111;
key_tbl5 <= 8'b11111111;
key_tbl6 <= 8'b11111111;
key_tbl7 <= 8'b11111111;
key_tbl8 <= 8'b11111111;
key_tbl9 <= 8'b11111111;
end else if ( dten ) begin
case ( kdata )
8'h70: begin
if ( key_e0 ) begin
key_tbl8[1] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // INS (E0)
end else begin
key_tbl1[4] <= key_f0; key_f0 <= 1'b0; // 0
end
end
8'h69: begin
if ( key_e0 ) begin
key_f0 <= 1'b0; key_e0 <= 1'b0; // END (E0)
end else begin
key_tbl0[0] <= key_f0; key_f0 <= 1'b0; // 1
end
end
8'h72: begin
if ( key_e0 ) begin
key_tbl9[2] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // DOWN (E0)
end else begin
key_tbl1[0] <= key_f0; key_f0 <= 1'b0; // 2
end
end
8'h7A: begin
if ( key_e0 ) begin
key_tble[0] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // PGDN (E0)
end else begin
key_tbl0[1] <= key_f0; key_f0 <= 1'b0; // 3
end
end
8'h6B: begin
if ( key_e0 ) begin
key_tbl8[3] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // LEFT (E0)
end else begin
key_tbl1[1] <= key_f0; key_f0 <= 1'b0; // 4
end
end
8'h73: begin key_tbl0[2] <= key_f0; key_f0 <= 1'b0; end // 5
8'h74: begin
if ( key_e0 ) begin
key_tbl8[3] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // RIGHT (E0)
end else begin
key_tbl1[2] <= key_f0; key_f0 <= 1'b0; // 6
end
end
8'h6C: begin
if ( key_e0 ) begin
key_tbl8[0] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // HOME (E0)
end else begin
key_tbl0[3] <= key_f0; key_f0 <= 1'b0; // 7
end
end
8'h75: begin
if ( key_e0 ) begin
key_tbl9[2] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // UP (E0)
end else begin
key_tbl1[3] <= key_f0; key_f0 <= 1'b0; // 8
end
end
8'h7D: begin
if ( key_e0 ) begin
key_tble[0] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // PGUP (E0)
end else begin
key_tbl0[4] <= key_f0; key_f0 <= 1'b0; // 9
end
end
8'h7C: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // *
8'h79: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // +
8'h7B: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // =
8'h7C: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // ,
8'h71: begin
if ( key_e0 ) begin
key_tbl8[1] <= key_f0; key_tblc[7] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // DEL (E0)
end else begin
key_tble[0] <= key_f0; key_f0 <= 1'b0; // .
end
end
8'h71: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // .
8'h5A: begin key_tbl8[4] <= key_f0; key_f0 <= 1'b0; end // RET E0
8'h54: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // @
8'h1C: begin key_tbl4[0] <= key_f0; key_f0 <= 1'b0; end // A
8'h32: begin key_tbl6[2] <= key_f0; key_f0 <= 1'b0; end // B
8'h21: begin key_tbl6[1] <= key_f0; key_f0 <= 1'b0; end // C
8'h23: begin key_tbl4[1] <= key_f0; key_f0 <= 1'b0; end // D
8'h24: begin key_tbl2[1] <= key_f0; key_f0 <= 1'b0; end // E
8'h2B: begin key_tbl5[1] <= key_f0; key_f0 <= 1'b0; end // F
8'h34: begin key_tbl4[2] <= key_f0; key_f0 <= 1'b0; end // G
8'h33: begin key_tbl5[2] <= key_f0; key_f0 <= 1'b0; end // H
8'h43: begin key_tbl3[3] <= key_f0; key_f0 <= 1'b0; end // I
8'h3B: begin key_tbl4[3] <= key_f0; key_f0 <= 1'b0; end // J
8'h42: begin key_tbl5[3] <= key_f0; key_f0 <= 1'b0; end // K
8'h4B: begin key_tbl4[4] <= key_f0; key_f0 <= 1'b0; end // L
8'h3A: begin key_tbl6[3] <= key_f0; key_f0 <= 1'b0; end // M
8'h31: begin key_tbl7[2] <= key_f0; key_f0 <= 1'b0; end // N
8'h44: begin key_tbl2[4] <= key_f0; key_f0 <= 1'b0; end // O
8'h4D: begin key_tbl3[4] <= key_f0; key_f0 <= 1'b0; end // P
8'h15: begin key_tbl2[0] <= key_f0; key_f0 <= 1'b0; end // Q
8'h2D: begin key_tbl3[1] <= key_f0; key_f0 <= 1'b0; end // R
8'h1B: begin key_tbl5[0] <= key_f0; key_f0 <= 1'b0; end // S
8'h2C: begin key_tbl2[2] <= key_f0; key_f0 <= 1'b0; end // T
8'h3C: begin key_tbl2[3] <= key_f0; key_f0 <= 1'b0; end // U
8'h2A: begin key_tbl7[1] <= key_f0; key_f0 <= 1'b0; end // V
8'h1D: begin key_tbl3[0] <= key_f0; key_f0 <= 1'b0; end // W
8'h22: begin key_tbl7[0] <= key_f0; key_f0 <= 1'b0; end // X
8'h35: begin key_tbl3[2] <= key_f0; key_f0 <= 1'b0; end // Y
8'h1A: begin key_tbl6[0] <= key_f0; key_f0 <= 1'b0; end // Z
8'h5B: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // [
8'h6A: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // \
8'h5D: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // ]
8'h55: begin key_tbl5[5] <= key_f0; key_f0 <= 1'b0; end // ^
8'h4E: begin key_tbl2[5] <= key_f0; key_f0 <= 1'b0; end // =
8'h45: begin key_tbl1[4] <= key_f0; key_f0 <= 1'b0; end // 0
8'h16: begin key_tbl0[0] <= key_f0; key_f0 <= 1'b0; end // 1
8'h1E: begin key_tbl1[0] <= key_f0; key_f0 <= 1'b0; end // 2
8'h26: begin key_tbl0[1] <= key_f0; key_f0 <= 1'b0; end // 3
8'h25: begin key_tbl1[1] <= key_f0; key_f0 <= 1'b0; end // 4
8'h2E: begin key_tbl0[2] <= key_f0; key_f0 <= 1'b0; end // 5
8'h36: begin key_tbl1[2] <= key_f0; key_f0 <= 1'b0; end // 6
8'h3D: begin key_tbl0[3] <= key_f0; key_f0 <= 1'b0; end // 7
8'h3E: begin key_tbl1[3] <= key_f0; key_f0 <= 1'b0; end // 8
8'h46: begin key_tbl0[4] <= key_f0; key_f0 <= 1'b0; end // 9
8'h52: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // :
8'h4C: begin key_tbl5[4] <= key_f0; key_f0 <= 1'b0; end // ;
8'h41: begin key_tbl7[3] <= key_f0; key_f0 <= 1'b0; end // < ,
8'h49: begin key_tbl6[4] <= key_f0; key_f0 <= 1'b0; end // > .
8'h4A: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // ?
8'h51: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // _
8'h11: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // GRPH
8'h13: begin key_tbl6[5] <= key_f0; key_f0 <= 1'b0; end // <EFBFBD>J<EFBFBD>i
8'h12: begin key_tbl8[0] <= ( key_f0 | key_e0 ) & (key_tbl8[0] | ~key_e0 ); key_f0 <= 1'b0; key_e0 <= 1'b0; end // SHIFT
8'h59: begin key_tbl8[5] <= ( key_f0 | key_e0 ) & (key_tbl8[5] | ~key_e0 ); key_f0 <= 1'b0; key_e0 <= 1'b0; end // SHIFT
8'h14: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // CTRL
8'h77: begin key_tbl9[3] <= key_f0; key_f0 <= 1'b0; end // STOP (E1)
8'h7E: begin key_tbl9[3] <= key_f0; key_f0 <= 1'b0; end // STOP (SCROLL KEY)
8'h05: begin key_tble[0] <= key_f0; key_tblc[0] <= key_f0; key_f0 <= 1'b0; end // F1
8'h06: begin key_tble[0] <= key_f0; key_tblc[1] <= key_f0; key_f0 <= 1'b0; end // F2
8'h04: begin key_tble[0] <= key_f0; key_tblc[2] <= key_f0; key_f0 <= 1'b0; end // F3
8'h0C: begin key_tble[0] <= key_f0; key_tblc[3] <= key_f0; key_f0 <= 1'b0; end // F4
8'h03: begin key_tble[0] <= key_f0; key_tblc[4] <= key_f0; key_f0 <= 1'b0; end // F5
8'h29: begin key_tbl9[1] <= key_f0; key_tbld[7] <= key_f0; key_f0 <= 1'b0; end // SPACE
8'h76: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // ESC
8'h0d: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // TAB
8'h58: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // CAPS
8'h66: begin key_tbl8[1] <= key_f0; key_f0 <= 1'b0; end // BS
8'h0b: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F6
8'h83: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F7
8'h0a: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F8
8'h01: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F9
8'h09: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F10
8'he0: key_e0 <= 1'b1;
8'hf0: key_f0 <= 1'b1;
default: begin key_e0 <= 1'b0; key_f0 <= 1'b0; end
endcase
end
end
endmodule
module ps2_recieve(clk, reset,
ps2_clk, ps2_data,
dten, kdata);
input clk,reset;
input ps2_clk, ps2_data;
output dten;
output [7:0] kdata;
wire clk, reset;
wire ps2_clk, ps2_data;
reg dten;
reg [7:0] kdata;
reg [10:0] key_data;
reg [3:0] clk_data;
always @(posedge clk or posedge reset) begin
if( reset ) begin
key_data <= 11'b11111111111;
dten <= 1'b0;
end else begin
clk_data <= {clk_data[2:0], ps2_clk};
if ( clk_data == 4'b0011 )
key_data <= {ps2_data, key_data[10:1]};
if ( !key_data[0] & key_data[10] ) begin
dten <= 1'b1;
kdata <= key_data[8:1];
key_data <= 11'b11111111111;
end else
dten <= 1'b0;
end
end
endmodule

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//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
input ce_pix_actual,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input line_start,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
assign vs_out = vs_in;
reg [2:0] phase;
reg [2:0] ce_div;
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
wire ls_in = hs_in | line_start;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x1 <= 0;
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
phase <= phase + 1'd1;
ce_x4 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
phase <= phase + 1'd1;
ce_cnt <= ce_cnt + 1'd1;
if(ce_pix_actual) begin
phase <= 0;
ce_div <= ce_cnt + 1'd1;
ce_cnt <= 0;
req_line_reset <= 0;
end
if(ls_in) req_line_reset <= 1;
end
end
reg ce_sd;
always @(*) begin
case(ce_div)
2: ce_sd = !phase[0];
4: ce_sd = !phase[1:0];
default: ce_sd <= 1;
endcase
end
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4 & ce_sd),
.inputpixel({b_in,g_in,r_in}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h_actual),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h_actual;
always @(*) begin
case(ce_div)
2: sd_h_actual = sd_h[10:1];
4: sd_h_actual = sd_h[10:2];
default: sd_h_actual = sd_h;
endcase
end
reg [10:0] sd_h;
reg [1:0] sd_line;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise,hs_ls;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg hs, hs2, vs, ls;
if(ce_x1) begin
hs <= hs_in;
ls <= ls_in;
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
if(sd_hcnt == hs_ls) sd_h <= 0;
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
end
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:54:34 02/19/2008
// Design Name:
// Module Name: clock_gen
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sound(CLK_50MHZ, SW, TP1);
input CLK_50MHZ;
input [7:0] SW;
output TP1;
reg [14:0] count = 0;
reg [14:0] count2 = 1;
reg CLK = 0;
wire TP1;
always @(posedge CLK_50MHZ)
begin
count <= count + 1;
end
always @(posedge count[12])
begin
if ( count2 >= SW )
begin
CLK <= SW != 0 ? ~CLK: CLK;
count2 <= 1;
end else
begin
count2 <= count2 + 1;
end
end
assign TP1 = CLK;
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:27:35 02/19/2008
// Design Name:
// Module Name: vga
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga(CLK_50MHZ, VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC, Pix_ce,
VGA_ADDR, VGA_DATA, BUS_REQ, BUS_ACK);
input CLK_50MHZ;
output VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;
output Pix_ce;
output [11:0] VGA_ADDR;
input [7:0] VGA_DATA;
output BUS_REQ;
input BUS_ACK;
reg [9:0] x = 0;
reg [9:0] y = 0;
reg [1:0] counter = 0;
wire display;
wire [9:0] gx, gy; // <EFBFBD>O<EFBFBD><EFBFBD><EFBFBD>t<EFBFBD>B<EFBFBD>b<EFBFBD>N<EFBFBD><EFBFBD>W(0,0)-(639,399)
always @(posedge CLK_50MHZ) begin
counter <= counter + 1;
end
assign Pix_ce = counter[0];
assign gx = x - 144; // (96+48)
assign gy = y - 71; // (2+29+40)
always @(posedge counter[0]) begin
if ( x < 800 )
begin
x <= x + 1;
end else begin
x <= 0;
if ( y < 521 )
y <= y + 1;
else
y <= 0;
end
end
// CGROM<EFBFBD>̎<EFBFBD><EFBFBD>
wire [7:0] cgrom_data;
wire [11:0] cgrom_addr;
cgrom cgrom(.address(cgrom_addr), .clock(CLK_50MHZ), .q(cgrom_data), .rden(1'b1));
wire [5:0] cx, cy; // <EFBFBD>L<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>N<EFBFBD>^<EFBFBD>[<EFBFBD><EFBFBD>W<EFBFBD>֕ϊ<EFBFBD>(0,0)-(79,24)
assign cx = gx >> 4; // <EFBFBD>P<EFBFBD>U<EFBFBD>Ŋ<EFBFBD><EFBFBD><EFBFBD>
assign cy = gy >> 4; // <EFBFBD>P<EFBFBD>U<EFBFBD>Ŋ<EFBFBD><EFBFBD><EFBFBD>
assign VGA_ADDR = (cy * 40) + cx;
assign cgrom_addr = {VGA_DATA, gy[3:1]};
// assign BUS_REQ = ( (96+48-8) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400));
assign BUS_REQ = ( (96+48-16) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400));
assign display =( (96+48) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400));
assign VGA_RED = 0; //display ? (cgrom_data[7-((gx>>1) & 7)]) : 0;
assign VGA_GREEN = display & (y[0] & 1) ? cgrom_data[7-(((gx+15)>>1) & 7)] : 0;
assign VGA_BLUE = 0; //display ? (cgrom_data[7-((gx>>1) & 7)]) : 0;
assign VGA_HSYNC = x < 96 ? 0 : 1;
assign VGA_VSYNC = y < 2 ? 0 : 1;
endmodule

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//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 3 bits per component
// For half depth 6 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0,
parameter OSD_COLOR = 3'd4,
parameter OSD_X_OFFSET = 10'd0,
parameter OSD_Y_OFFSET = 10'd0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
// Some systems have multiple resolutions.
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
input ce_pix_actual,
// OSD SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// 0 = HVSync 31KHz, 1 = CSync 15KHz
input scandoubler_disable,
// High quality 2x scaling
input hq2x,
// YPbPr always uses composite sync
input ypbpr,
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
input ypbpr_full,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// interlace sync. Positive pulses.
input HSync,
input VSync,
// Falling of this signal means start of informative part of line.
// It can be horizontal blank signal.
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
// before first informative pixel.
input line_start,
// MiST video output signals
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_VS,
output VGA_HS
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.r_in(R),
.g_in(G),
.b_in(B),
.hs_out(hs_sd),
.vs_out(vs_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
generate
if(HALF_DEPTH) begin
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [5:0] r = rt;
wire [5:0] g = gt;
wire [5:0] b = bt;
end
endgenerate
wire hs = (scandoubler_disable ? HSync : hs_sd);
wire vs = (scandoubler_disable ? VSync : vs_sd);
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire [5:0] r_out, g_out, b_out;
always @(*) begin
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
end
2: begin // reduce 50% = 1/2
r_out = {1'b0, r[5:1]};
g_out = {1'b0, g[5:1]};
b_out = {1'b0, b[5:1]};
end
3: begin // reduce 75% = 1/4
r_out = {2'b00, r[5:2]};
g_out = {2'b00, g[5:2]};
b_out = {2'b00, b[5:2]};
end
default: begin
r_out = r;
g_out = g;
b_out = b;
end
endcase
end
wire [5:0] red, green, blue;
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
(
.*,
.R_in(r_out),
.G_in(g_out),
.B_in(b_out),
.HSync(hs),
.VSync(vs),
.R_out(red),
.G_out(green),
.B_out(blue)
);
wire [5:0] yuv_full[225] = '{
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
6'd63
};
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
endmodule

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Sharp -MZ-80K_MiST/rtl/vram.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "vram.v"]

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Sharp -MZ-80K_MiST/rtl/vram.v Normal file
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// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: vram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vram (
address,
clock,
data,
rden,
wren,
q);
input [11:0] address;
input clock;
input [7:0] data;
input rden;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.rden_a (rden),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

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Sharp -MZ-80K_MiST/snapshot/mz80k.rbf Normal file
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