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Gehstock
2020-03-08 22:45:59 +01:00
parent 9316bde00d
commit 36e390aa9a
219 changed files with 55624 additions and 182 deletions
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14
Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf
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{ "" "" "" "Verilog HDL Declaration warning at tv80s.v(55): \"do\" is SystemVerilog-2005 keyword" { } { } 0 10463 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Unrecognized synthesis attribute \"dc_script_begin\" at rtl/TV80/tv80_reg.v(67)" { } { } 0 10335 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Net \"R\" at tv80_core.v(97) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL warning at tv80_core.v(97): object R used but never assigned" { } { } 0 10858 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Output port \"rfsh_n\" at tv80_core.v(59) has no driver" { } { } 0 10034 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10335 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10463 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10270 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 14284 "" 0 0 "Quartus II" 0 -1 0 ""}

30
Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
# Date created = 23:49:02 July 13, 2012
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "10.1"
DATE = "23:49:02 July 13, 2012"
# Revisions
PROJECT_REVISION = "LodeRunner_MiST"

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Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 21:06:00 February 29, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# LodeRunner_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/LodeRunner_MiST.sv
set_global_assignment -name VHDL_FILE rtl/target_top.vhd
set_global_assignment -name VHDL_FILE rtl/platform_variant_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/platform.vhd
set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/pace.vhd
set_global_assignment -name VHDL_FILE rtl/Graphics.VHD
set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/video_controller.vhd
set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
set_global_assignment -name VHDL_FILE rtl/spritereg.vhd
set_global_assignment -name VHDL_FILE rtl/spritectl.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd
set_global_assignment -name VHDL_FILE rtl/Inputs.VHD
set_global_assignment -name VHDL_FILE rtl/input_mapper.vhd
set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/clk_div.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name VHDL_FILE rtl/Sound_Board.vhd
set_global_assignment -name VHDL_FILE rtl/roms/ldrun/snd_prg.vhd
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name VHDL_FILE ../../../common/CPU/T80/Z80.vhd
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY LodeRunner_MiST
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SEARCH_PATH common/CPU/T80/ -tag from_archive
set_global_assignment -name SEARCH_PATH common/mist/ -tag from_archive
set_global_assignment -name SEARCH_PATH rtl/ -tag from_archive
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/mcr3.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -----------------------------
# start ENTITY(LodeRunner_MiST)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(LodeRunner_MiST)
# ---------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

15
Arcade_MiST/IremM62 Hardware/Kung_MiST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

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Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Graphics.VHD Normal file
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library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.sprite_pkg.all;
--use work.project_pkg.all;
use work.platform_pkg.all;
entity Graphics is
port
(
bitmap_ctl_i : in to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
bitmap_ctl_o : out from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
tilemap_ctl_i : in to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
tilemap_ctl_o : out from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
sprite_reg_i : in to_SPRITE_REG_t;
sprite_ctl_i : in to_SPRITE_CTL_t;
sprite_ctl_o : out from_SPRITE_CTL_t;
spr0_hit : out std_logic;
graphics_i : in to_GRAPHICS_t;
graphics_o : out from_GRAPHICS_t;
video_i : in from_VIDEO_t;
video_o : out to_VIDEO_t
);
end Graphics;
architecture SYN of Graphics is
alias clk : std_logic is video_i.clk;
signal from_video_ctl : from_VIDEO_CTL_t;
signal bitmap_ctl_o_s : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
signal tilemap_ctl_o_s : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
signal sprite_ctl_o_s : from_SPRITE_CTL_t;
signal sprite_pri : std_logic;
signal rgb_data : RGB_t;
-- before OSD is mixed in
signal video_o_s : to_VIDEO_t;
begin
-- dodgy OSD transparency...
video_o.clk <= video_o_s.clk;
video_o.rgb.r <= video_o_s.rgb.r;
video_o.rgb.g <= video_o_s.rgb.g;
video_o.rgb.b <= video_o_s.rgb.b;
video_o.hsync <= video_o_s.hsync;
video_o.vsync <= video_o_s.vsync;
video_o.hblank <= video_o_s.hblank;
video_o.vblank <= video_o_s.vblank;
graphics_o.y <= from_video_ctl.y;
-- should this be the 'real' vblank or the 'active' vblank?
-- - use the real for now
graphics_o.hblank <= video_o_s.hblank;
graphics_o.vblank <= video_o_s.vblank;
--graphics_o.vblank <= from_video_ctl.vblank;
pace_video_controller_inst : entity work.pace_video_controller
generic map
(
CONFIG => PACE_VIDEO_CONTROLLER_TYPE,
DELAY => PACE_VIDEO_PIPELINE_DELAY,
H_SIZE => PACE_VIDEO_H_SIZE,
V_SIZE => PACE_VIDEO_V_SIZE,
L_CROP => PACE_VIDEO_L_CROP,
R_CROP => PACE_VIDEO_R_CROP,
H_SCALE => PACE_VIDEO_H_SCALE,
V_SCALE => PACE_VIDEO_V_SCALE,
H_SYNC_POL => PACE_VIDEO_H_SYNC_POLARITY,
V_SYNC_POL => PACE_VIDEO_V_SYNC_POLARITY,
BORDER_RGB => PACE_VIDEO_BORDER_RGB
)
port map
(
-- clocking etc
video_i => video_i,
-- register interface
reg_i.h_scale => "000",
reg_i.v_scale => "000",
-- video data signals (in)
rgb_i => rgb_data,
-- video control signals (out)
video_ctl_o => from_video_ctl,
-- VGA signals (out)
video_o => video_o_s
);
pace_video_mixer_inst : entity work.pace_video_mixer
port map
(
bitmap_ctl_o => bitmap_ctl_o_s,
tilemap_ctl_o => tilemap_ctl_o_s,
sprite_rgb => sprite_ctl_o_s.rgb,
sprite_set => sprite_ctl_o_s.set,
sprite_pri => sprite_pri,
video_ctl_i => from_video_ctl,
graphics_i => graphics_i,
rgb_o => rgb_data
);
GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
--bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
end generate GEN_NO_BITMAPS;
GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
ctl_i => bitmap_ctl_i(1),
ctl_o => bitmap_ctl_o_s(1),
graphics_i => graphics_i
);
end generate GEN_BITMAP_1;
GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
ctl_i => bitmap_ctl_i(2),
ctl_o => bitmap_ctl_o_s(2),
graphics_i => graphics_i
);
end generate GEN_BITMAP_2;
GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate
forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
ctl_i => bitmap_ctl_i(3),
ctl_o => bitmap_ctl_o_s(3),
graphics_i => graphics_i
);
end generate GEN_BITMAP_3;
bitmap_ctl_o <= bitmap_ctl_o_s;
GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate
--tilemap_ctl_o_s(1) <= ((others => '0'), (others => '0'), (others => '0'),
-- (others => (others => '0')), '0');
end generate GEN_NO_TILEMAPS;
GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate
foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
ctl_i => tilemap_ctl_i(1),
ctl_o => tilemap_ctl_o_s(1),
graphics_i => graphics_i
);
end generate GEN_TILEMAP_1;
GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate
background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2)
generic map
(
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
video_ctl => from_video_ctl,
ctl_i => tilemap_ctl_i(2),
ctl_o => tilemap_ctl_o_s(2),
graphics_i => graphics_i
);
end generate GEN_TILEMAP_2;
tilemap_ctl_o <= tilemap_ctl_o_s;
GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
sprite_pri <= '0';
spr0_hit <= '0';
end generate GEN_NO_SPRITES;
GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
sprites_inst : sprite_array
generic map
(
N_SPRITES => PACE_VIDEO_NUM_SPRITES,
DELAY => PACE_VIDEO_PIPELINE_DELAY
)
port map
(
reset => video_i.reset,
-- register interface
reg_i => sprite_reg_i,
-- video control signals
video_ctl => from_video_ctl,
graphics_i => graphics_i,
row_a => sprite_ctl_o_s.a,
row_d => sprite_ctl_i.d,
rgb => sprite_ctl_o_s.rgb,
set => sprite_ctl_o_s.set,
pri => sprite_pri,
spr0_set => spr0_hit
);
end generate GEN_SPRITES;
sprite_ctl_o <= sprite_ctl_o_s;
end SYN;

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Library IEEE;
Use IEEE.std_logic_1164.all;
library work;
use work.pace_pkg.all;
entity inputs is
generic
(
NUM_DIPS : integer := 8;
NUM_INPUTS : integer := 2;
CLK_1US_DIV : natural := 30
);
port
(
clk : in std_logic;
reset : in std_logic;
jamma : in from_JAMMA_t;
dips : in std_logic_vector(NUM_DIPS-1 downto 0);
inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
);
end entity inputs;
architecture SYN of inputs is
signal reset_n : std_logic;
begin
reset_n <= not reset;
inputmapper_inst : entity work.inputmapper
generic map
(
NUM_DIPS => NUM_DIPS,
NUM_INPUTS => NUM_INPUTS
)
port map
(
clk => clk,
rst_n => reset_n,
jamma => jamma,
dips => dips,
inputs => inputs
);
end architecture SYN;

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module LodeRunner_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl/build_id.v"
localparam CONF_STR = {
"KUNGFUM;ROM;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"O6,Service,Off,On;",
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire service = status[6];
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_sd;
assign SDRAM_CKE = 1;
wire clk_sys, clk_aud, clk_sd, clk_vid;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys),
.c1(clk_vid),
.c2(clk_sd),
.c3(clk_aud),
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire [14:0] rom_addr;
wire [15:0] rom_do;
wire [13:0] snd_addr;
wire [15:0] snd_do;
wire [14:0] sp_addr;
wire [31:0] sp_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clk_sd ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h10000; //todo
reg port1_req, port2_req;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_sd ),
// port1 used for main + sound CPU
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]} ),
.cpu1_q ( rom_do ),
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h4000 + snd_addr[13:1]) ),
.cpu2_q ( snd_do ),
// port2 for sprite graphics
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( {sp_ioctl_addr[23:16], sp_ioctl_addr[13:0], sp_ioctl_addr[15]} ), // merge sprite roms to 32-bit wide words
.port2_ds ( {sp_ioctl_addr[14], ~sp_ioctl_addr[14]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.sp_addr ( ioctl_downl ? 15'h7fff : sp_addr ),
.sp_q ( sp_do )
);
// ROM download controller
always @(posedge clk_sd) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
// reset signal generation
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_sys) begin
reg ioctl_downlD;
reg [15:0] reset_count;
ioctl_downlD <= ioctl_downl;
if (status[0] | buttons[1] | ~rom_loaded) reset_count <= 16'hffff;
else if (reset_count != 0) reset_count <= reset_count - 1'd1;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= reset_count != 16'h0000;
end
wire [11:0] audio;
wire hs, vs;
wire blankn = 1'b1;//todo
wire [3:0] g,b,r;
target_top target_top(
.clock_sys(clk_sys),//4xclk_vid
.clock_vid(clk_vid),//11MHz
.clk_aud(clk_aud),//0.895MHz
.reset_in(reset),
.audio_out(audio),
.usr_coin1(m_coin1),
.usr_coin2(m_coin2),
.usr_service(service),
.usr_start1(m_one_player),
.usr_start2(m_two_players),
.p1_up(m_up),
.p1_dw(m_down),
.p1_lt(m_left),
.p1_rt(m_right),
.p1_f1(m_fireA),
.p1_f2(m_fireB),
.p2_up(m_up2),
.p2_dw(m_down2),
.p2_lt(m_left2),
.p2_rt(m_right2),
.p2_f1(m_fire2A),
.p2_f2(m_fire2B),
.VGA_VS(vs),
.VGA_HS(hs),
.VGA_R(r),
.VGA_G(g),
.VGA_B(b),
.cpu_rom_addr(rom_addr),
.cpu_rom_do( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.snd_rom_addr(snd_addr),
.snd_rom_do(snd_addr[0] ? snd_do[15:8] : snd_do[7:0])
);
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? b : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ( { 1'b1, rotate } ),
.ce_divider ( 1'b0 ),
.scandoubler_disable( scandoublerD ),
.scanlines ( scanlines ),
.blend ( blend ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
wire dac_o;
assign AUDIO_L = dac_o;
assign AUDIO_R = dac_o;
dac #(
.C_bits(12))
dac(
.clk_i(clk_aud),
.res_n_i(1),
.dac_i(audio),
.dac_o(dac_o)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( 2'b10 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

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---------------------------------------------------------------------------------
-- Moon patrol sound board by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- gen_ram.vhd
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
---------------------------------------------------------------------------------
-- cpu68 - Version 9th Jan 2004 0.8
-- 6800/01 compatible CPU core
-- GNU public license - December 2002 : John E. Kent
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- Version 0.0 -- 24/11/2017 --
-- initial version
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Sound_Board is
port(
clock_E : in std_logic; -- 3.58 Mhz/4
areset : in std_logic;
select_sound : in std_logic_vector(7 downto 0);
audio_out : out std_logic_vector(11 downto 0);
snd_rom_addr : out std_logic_vector(13 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end Sound_Board;
architecture struct of Sound_Board is
component YM2149
port (
CLK : in std_logic;
CE : in std_logic;
RESET : in std_logic;
A8 : in std_logic := '1';
A9_L : in std_logic := '0';
BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write)
BC : in std_logic; -- Bus control
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CHANNEL_A : out std_logic_vector(7 downto 0);
CHANNEL_B : out std_logic_vector(7 downto 0);
CHANNEL_C : out std_logic_vector(7 downto 0);
SEL : in std_logic;
MODE : in std_logic;
ACTIVE : out std_logic_vector(5 downto 0);
IOA_in : in std_logic_vector(7 downto 0);
IOA_out : out std_logic_vector(7 downto 0);
IOB_in : in std_logic_vector(7 downto 0);
IOB_out : out std_logic_vector(7 downto 0)
);
end component;
signal reset : std_logic := '1';
signal reset_cnt : integer range 0 to 1000000 := 1000000;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_rw : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal irqraz_cs : std_logic;
signal irqraz_we : std_logic;
signal wram_cs : std_logic;
signal wram_we : std_logic;
signal wram_do : std_logic_vector( 7 downto 0);
signal rom_cs : std_logic;
signal rom_do : std_logic_vector( 7 downto 0);
signal ay1_chan_a : std_logic_vector(7 downto 0);
signal ay1_chan_b : std_logic_vector(7 downto 0);
signal ay1_chan_c : std_logic_vector(7 downto 0);
signal ay1_do : std_logic_vector(7 downto 0);
signal ay1_audio : std_logic_vector(9 downto 0);
signal ay1_port_b_do : std_logic_vector(7 downto 0);
signal ay2_chan_a : std_logic_vector(7 downto 0);
signal ay2_chan_b : std_logic_vector(7 downto 0);
signal ay2_chan_c : std_logic_vector(7 downto 0);
signal ay2_do : std_logic_vector(7 downto 0);
signal ay2_audio : std_logic_vector(9 downto 0);
signal ports_cs : std_logic;
signal ports_we : std_logic;
signal port1_bus : std_logic_vector(7 downto 0);
signal port1_data : std_logic_vector(7 downto 0);
signal port1_ddr : std_logic_vector(7 downto 0);
signal port1_in : std_logic_vector(7 downto 0);
signal port2_bus : std_logic_vector(7 downto 0);
signal port2_data : std_logic_vector(7 downto 0);
signal port2_ddr : std_logic_vector(7 downto 0);
signal port2_in : std_logic_vector(7 downto 0);
signal adpcm_cs : std_logic;
signal adpcm_we : std_logic;
signal adpcm_0_di : std_logic_vector(3 downto 0);
signal select_sound_r : std_logic_vector(7 downto 0);
signal audio : std_logic_vector(12 downto 0);
type t_step_size is array(0 to 48) of integer range 0 to 1552;
constant step_size : t_step_size := (
16, 17, 19, 21, 23, 25, 28, 31,
34, 37, 41, 45, 50, 55, 60, 66,
73, 80, 88, 97, 107, 118, 130, 143,
157, 173, 190, 209, 230, 253, 279, 307,
337, 371, 408, 449, 494, 544, 598, 658,
724, 796, 876, 963, 1060, 1166, 1282, 1411, 1552);
type t_delta_step is array(0 to 7) of integer range -1 to 8;
constant delta_step : t_delta_step := (-1,-1,-1,-1,2,4,6,8);
signal adpcm_vclk : std_logic := '0';
signal adpcm_signal : integer range -16384 to 16383 := 0;
-- adpcm algorithm (4bits) [no pcm here]
--
-- val : input value 3bits (0 - 7 : b2b1b0)
-- sign : input value sign (4th bit : 0=>sign=1 ,1=>sign=-1)
--
-- step : internal data, init = 0
-- signal : output value, init = 0;
--
-- for each new val (and sign) :
-- |
-- | step_size = 16*1.1^(step)
-- | delta = sign * (step_size/8 + step_size/4*b0 + step_size/2*b1 + step_size*b2)
-- | signal = signal + delta
-- | step = step + delta_step(val)
-- |
-- | signal is then limited between -2048..2047
-- | step is then limited between 0..48
begin
dbg_cpu_addr <= cpu_addr;
-- cs
wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF
ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F
adpcm_cs <= '1' when cpu_addr(14 downto 11) = "0001" else '0'; -- 0800-0FFF / 8800-8FFF
irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001" else '0'; -- 1000-1FFF / 9000-9FFF
rom_cs <= '1' when cpu_addr(14 downto 12) = "111" else '0'; -- 7000-7FFF / F000-FFFF
-- write enables
wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0';
ports_we <= '1' when cpu_rw = '0' and ports_cs = '1' else '0';
adpcm_we <= '1' when cpu_rw = '0' and adpcm_cs = '1' else '0';
irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
-- mux cpu in data between roms/io/wram
cpu_di <=
wram_do when wram_cs = '1' else
port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
snd_rom_do when rom_cs = '1' else X"55";
process (clock_E)
begin
if rising_edge(clock_E) then
reset <= '0';
if reset_cnt /= 0 then
reset_cnt <= reset_cnt - 1;
reset <= '1';
end if;
if areset = '1' then
reset_cnt <= 1000000;
end if;
end if;
end process;
-- irq to cpu
process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '1';
elsif rising_edge(clock_E) then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then
cpu_irq <= '1';
end if;
if irqraz_we = '1' then
cpu_irq <= '0';
end if;
end if;
end process;
-- cpu nmi
cpu_nmi <= adpcm_vclk;
-- 6803 ports 1 and 2 (only)
process (reset, clock_E)
begin
if reset='1' then
port1_ddr <= (others=>'0'); -- port1 set as input
port1_data <= (others=>'0'); -- port1 data set to 0
port2_ddr <= ("11100000"); -- port2 bit 7 to 5 should always remain output to simulate mode data
port2_data <= ("01000000"); -- port2 data bit 7 to 5 set to 2 (for mode 2 at start up)
elsif rising_edge(clock_E) then
if ports_cs = '1' and ports_we = '1' then
if cpu_addr(3 downto 0) = X"0" then port1_ddr <= cpu_do; end if;
if cpu_addr(3 downto 0) = X"1" then port2_ddr <= cpu_do and "11100000"; end if;
if cpu_addr(3 downto 0) = X"2" then port1_data <= cpu_do; end if;
if cpu_addr(3 downto 0) = X"3" then port2_data <= cpu_do; end if;
end if;
end if;
end process;
port1_in <= (port1_bus and not(port1_ddr)) or (port1_data and port1_ddr);
port2_in <= (port2_bus and not(port2_ddr)) or (port2_data and port2_ddr);
-- port1 bus mux
port1_bus <= ay1_do when port2_data(4) = '0' else
ay2_do when port2_data(3) = '0' else X"FF";
-- port2 bus
port2_bus <= X"FF";
-- latch adpcm (msm5205) data in
process (reset, clock_E)
begin
if reset='1' then
adpcm_0_di <= (others=>'0');
elsif rising_edge(clock_E) then
if adpcm_cs = '1' and adpcm_we = '1' then
if cpu_addr(1) = '0' then adpcm_0_di <= cpu_do(3 downto 0); end if;
end if;
end if;
end process;
-- adcpm clocks and computation -- make 24kHz and vclk 8/6/4kHz
adpcm_clocks : process(clock_E, ay1_port_b_do)
variable clock_div_a : integer range 0 to 148 := 0;
variable clock_div_b : integer range 0 to 5 := 0;
variable step : integer range 0 to 48;
variable step_n : integer range -1 to 48+8;
variable sz : integer range 0 to 1552;
variable dn : integer range -32768 to 32767;
variable adpcm_signal_n : integer range -32768 to 32767;
begin
if rising_edge(clock_E) then
if clock_div_a = 37 then -- 24kHz
clock_div_a := 0;
case ay1_port_b_do(3 downto 2) is
when "00" => if clock_div_b = 5 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 4kHz
when "01" => if clock_div_b = 2 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 8kHz
when "10" => if clock_div_b = 3 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if; -- 6kHz
when others => null;
end case;
if clock_div_b = 0 then adpcm_vclk <= '1'; else adpcm_vclk <= '0'; end if;
else
clock_div_a := clock_div_a + 1;
end if;
if ay1_port_b_do(0) = '1' then
step := 0;
adpcm_signal <= 0;
else
if clock_div_b = 0 then
case clock_div_a is
when 0 => -- it's time to get new nibble (adpcm_0_di)
sz := step_size(step);
dn := sz/8;
if adpcm_0_di(0) = '1' then dn := dn + sz/4; end if;
if adpcm_0_di(1) = '1' then dn := dn + sz/2; end if;
if adpcm_0_di(2) = '1' then dn := dn + sz ; end if;
if adpcm_0_di(3) = '1' then
dn := -dn;
end if;
step_n := step + delta_step(to_integer(unsigned(adpcm_0_di(2 downto 0))));
when 4 =>
adpcm_signal_n := adpcm_signal + dn;
if step_n > 48 then step := 48; else step := step_n; end if;
if step_n < 0 then step := 0; else step := step_n; end if;
when 8 =>
if adpcm_signal_n > 2040 then adpcm_signal <= 2040; else adpcm_signal <= adpcm_signal_n; end if;
if adpcm_signal_n < -2040 then adpcm_signal <= -2040; else adpcm_signal <= adpcm_signal_n; end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
-- audio mux
audio <= ("000"&ay1_audio) + ("000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12)));
audio_out <= audio(12 downto 1);
-- microprocessor 6800/01/03
main_cpu : entity work.cpu68
port map(
clk => clock_E, -- E clock input (falling edge)
rst => reset, -- reset input (active high)
rw => cpu_rw, -- read not write output
vma => open, -- valid memory address (active high)
address => cpu_addr, -- address bus output
data_in => cpu_di, -- data bus input
data_out => cpu_do, -- data bus output
hold => '0', -- hold input (active high) extend bus cycle
halt => '0', -- halt input (active high) grants DMA
irq => cpu_irq, -- interrupt request input (active high)
nmi => cpu_nmi, -- non maskable interrupt request input (active high)
test_alu => open,
test_cc => open
);
snd_rom_addr <= cpu_addr(13 downto 0);
-- cpu wram
cpu_ram : entity work.spram
generic map( widthad_a => 7)
port map(
clock => clock_E,
wren => wram_we,
address => cpu_addr(6 downto 0),
data => cpu_do,
q => wram_do
);
ay83910_inst1: YM2149
port map (
CLK => clock_E,
CE => '1',
RESET => reset,
A8 => '1',
A9_L => port2_data(4),
BDIR => port2_data(0),
BC => port2_data(2),
DI => port1_data,
DO => ay1_do,
CHANNEL_A => ay1_chan_a,
CHANNEL_B => ay1_chan_b,
CHANNEL_C => ay1_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => select_sound_r,
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => ay1_port_b_do
);
ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c;
ay83910_inst2: YM2149
port map (
CLK => clock_E,
CE => '1',
RESET => reset,
A8 => '1',
A9_L => port2_data(3),
BDIR => port2_data(0),
BC => port2_data(2),
DI => port1_data,
DO => ay2_do,
CHANNEL_A => ay2_chan_a,
CHANNEL_B => ay2_chan_b,
CHANNEL_C => ay2_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => (others => '0'),
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => open
);
ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c;
end struct;

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//
// Copyright (c) MikeJ - Jan 2005
// Copyright (c) 2016-2018 Sorgelig
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// BDIR BC MODE
// 0 0 inactive
// 0 1 read value
// 1 0 write value
// 1 1 set address
//
module YM2149
(
input CLK, // Global clock
input CE, // PSG Clock enable
input RESET, // Chip RESET (set all Registers to '0', active hi)
input BDIR, // Bus Direction (0 - read , 1 - write)
input BC, // Bus control
input A8,
input A9_L,
input [7:0] DI, // Data In
output [7:0] DO, // Data Out
output [7:0] CHANNEL_A, // PSG Output channel A
output [7:0] CHANNEL_B, // PSG Output channel B
output [7:0] CHANNEL_C, // PSG Output channel C
input SEL,
input MODE,
output [5:0] ACTIVE,
input [7:0] IOA_in,
output [7:0] IOA_out,
input [7:0] IOB_in,
output [7:0] IOB_out
);
assign ACTIVE = ~ymreg[7][5:0];
assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff;
assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff;
reg [7:0] addr;
reg [7:0] ymreg[16];
wire cs = !A9_L & A8;
// Write to PSG
reg env_reset;
always @(posedge CLK) begin
if(RESET) begin
ymreg <= '{default:0};
ymreg[7] <= '1;
addr <= '0;
env_reset <= 0;
end else begin
env_reset <= 0;
if(cs & BDIR) begin
if(BC) addr <= DI;
else if(!addr[7:4]) begin
ymreg[addr[3:0]] <= DI;
env_reset <= (addr == 13);
end
end
end
end
// Read from PSG
assign DO = dout;
reg [7:0] dout;
always_comb begin
dout = 8'hFF;
if(cs & ~BDIR & BC & !addr[7:4]) begin
case(addr[3:0])
0: dout = ymreg[0];
1: dout = ymreg[1][3:0];
2: dout = ymreg[2];
3: dout = ymreg[3][3:0];
4: dout = ymreg[4];
5: dout = ymreg[5][3:0];
6: dout = ymreg[6][4:0];
7: dout = ymreg[7];
8: dout = ymreg[8][4:0];
9: dout = ymreg[9][4:0];
10: dout = ymreg[10][4:0];
11: dout = ymreg[11];
12: dout = ymreg[12];
13: dout = ymreg[13][3:0];
14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
endcase
end
end
reg ena_div;
reg ena_div_noise;
// p_divider
always @(posedge CLK) begin
reg [3:0] cnt_div;
reg noise_div;
if(CE) begin
ena_div <= 0;
ena_div_noise <= 0;
if(!cnt_div) begin
cnt_div <= {SEL, 3'b111};
ena_div <= 1;
noise_div <= (~noise_div);
if (noise_div) ena_div_noise <= 1;
end else begin
cnt_div <= cnt_div - 1'b1;
end
end
end
reg [2:0] noise_gen_op;
// p_noise_gen
always @(posedge CLK) begin
reg [16:0] poly17;
reg [4:0] noise_gen_cnt;
if(CE) begin
if (ena_div_noise) begin
if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
noise_gen_cnt <= 0;
poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
end else begin
noise_gen_cnt <= noise_gen_cnt + 1'd1;
end
noise_gen_op <= {3{poly17[0]}};
end
end
end
wire [11:0] tone_gen_freq[1:3];
assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
reg [3:1] tone_gen_op;
//p_tone_gens
always @(posedge CLK) begin
integer i;
reg [11:0] tone_gen_cnt[1:3];
if(CE) begin
// looks like real chips count up - we need to get the Exact behaviour ..
for (i = 1; i <= 3; i = i + 1) begin
if(ena_div) begin
if (tone_gen_freq[i]) begin
if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
tone_gen_cnt[i] <= 0;
tone_gen_op[i] <= ~tone_gen_op[i];
end else begin
tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
end
end else begin
tone_gen_op[i] <= ymreg[7][i];
tone_gen_cnt[i] <= 0;
end
end
end
end
end
reg env_ena;
wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
//p_envelope_freq
always @(posedge CLK) begin
reg [15:0] env_gen_cnt;
if(CE) begin
env_ena <= 0;
if(ena_div) begin
if (env_gen_cnt >= env_gen_comp) begin
env_gen_cnt <= 0;
env_ena <= 1;
end else begin
env_gen_cnt <= (env_gen_cnt + 1'd1);
end
end
end
end
reg [4:0] env_vol;
wire is_bot = (env_vol == 5'b00000);
wire is_bot_p1 = (env_vol == 5'b00001);
wire is_top_m1 = (env_vol == 5'b11110);
wire is_top = (env_vol == 5'b11111);
always @(posedge CLK) begin
reg env_hold;
reg env_inc;
// envelope shapes
// C AtAlH
// 0 0 x x \___
//
// 0 1 x x /___
//
// 1 0 0 0 \\\\
//
// 1 0 0 1 \___
//
// 1 0 1 0 \/\/
// ___
// 1 0 1 1 \
//
// 1 1 0 0 ////
// ___
// 1 1 0 1 /
//
// 1 1 1 0 /\/\
//
// 1 1 1 1 /___
if(env_reset | RESET) begin
// load initial state
if(!ymreg[13][2]) begin // attack
env_vol <= 5'b11111;
env_inc <= 0; // -1
end else begin
env_vol <= 5'b00000;
env_inc <= 1; // +1
end
env_hold <= 0;
end
else if(CE) begin
if (env_ena) begin
if (!env_hold) begin
if (env_inc) env_vol <= (env_vol + 5'b00001);
else env_vol <= (env_vol + 5'b11111);
end
// envelope shape control.
if(!ymreg[13][3]) begin
if(!env_inc) begin // down
if(is_bot_p1) env_hold <= 1;
end else if (is_top) env_hold <= 1;
end else if(ymreg[13][0]) begin // hold = 1
if(!env_inc) begin // down
if(ymreg[13][1]) begin // alt
if(is_bot) env_hold <= 1;
end else if(is_bot_p1) env_hold <= 1;
end else if(ymreg[13][1]) begin // alt
if(is_top) env_hold <= 1;
end else if(is_top_m1) env_hold <= 1;
end else if(ymreg[13][1]) begin // alternate
if(env_inc == 1'b0) begin // down
if(is_bot_p1) env_hold <= 1;
if(is_bot) begin
env_hold <= 0;
env_inc <= 1;
end
end else begin
if(is_top_m1) env_hold <= 1;
if(is_top) begin
env_hold <= 0;
env_inc <= 0;
end
end
end
end
end
end
reg [5:0] A,B,C;
always @(posedge CLK) begin
A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}};
B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}};
C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
end
wire [7:0] volTable[64] = '{
//YM2149
8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04,
8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13,
8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47,
8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
//AY8910
8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06,
8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22,
8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72,
8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff
};
assign CHANNEL_A = volTable[A];
assign CHANNEL_B = volTable[B];
assign CHANNEL_C = volTable[C];
endmodule

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Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/bitmapctl_e.vhd Normal file
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.platform_pkg.all;
--use work.project_pkg.all;
entity bitmapCtl is
generic
(
DELAY : integer
);
port
(
reset : in std_logic;
-- video control signals
video_ctl : in from_VIDEO_CTL_t;
-- bitmap controller signals
ctl_i : in to_BITMAP_CTL_t;
ctl_o : out from_BITMAP_CTL_t;
graphics_i : in to_GRAPHICS_t
);
end entity bitmapCtl;

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/clk_div.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
entity clk_div is
generic
(
DIVISOR : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
clk_en : out std_logic
);
end clk_div;
architecture SYN of clk_div is
begin
process (clk, reset)
variable count : integer range 0 to DIVISOR-1;
begin
if reset = '1' then
count := 0;
clk_en <= '0';
elsif rising_edge(clk) then
clk_en <= '0';
if count = DIVISOR-1 then
clk_en <= '1';
count := 0;
else
count := count + 1;
end if;
end if;
end process;
end SYN;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
--numwords_a : natural;
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dprom_2r IS
GENERIC
(
INIT_FILE : string := "";
--NUMWORDS_A : natural;
WIDTHAD_A : natural;
WIDTH_A : natural := 8;
--NUMWORDS_B : natural;
WIDTHAD_B : natural;
WIDTH_B : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : in std_logic_vector (WIDTHAD_A-1 downto 0);
address_b : in std_logic_vector (WIDTHAD_B-1 downto 0);
clock : in std_logic ;
q_a : out std_logic_vector (WIDTH_A-1 downto 0);
q_b : out std_logic_vector (WIDTH_B-1 downto 0)
);
END dprom_2r;
ARCHITECTURE SYN OF dprom_2r IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3_bv : BIT_VECTOR (WIDTH_A-1 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (WIDTH_B-1 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
init_file_layout : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
ram_block_type : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (WIDTHAD_A-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (WIDTHAD_B-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire2 <= '0';
sub_wire3_bv(WIDTH_A-1 DOWNTO 0) <= (others => '0');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
sub_wire4_bv(WIDTH_B-1 DOWNTO 0) <= (others => '0');
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
q_a <= sub_wire0(WIDTH_A-1 DOWNTO 0);
q_b <= sub_wire1(WIDTH_B-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => INIT_FILE,
init_file_layout => "PORT_A",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**WIDTHAD_A,
numwords_b => 2**WIDTHAD_B,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
widthad_a => WIDTHAD_A,
widthad_b => WIDTHAD_B,
width_a => WIDTH_A,
width_b => WIDTH_B,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
wren_a => sub_wire2,
wren_b => sub_wire2,
clock0 => clock,
address_a => address_a,
address_b => address_b,
data_a => sub_wire3,
data_b => sub_wire4,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.pace_pkg.all;
entity inputmapper is
generic
(
NUM_DIPS : integer := 8;
NUM_INPUTS : integer := 2
);
port
(
clk : in std_logic;
rst_n : in std_logic;
jamma : in from_JAMMA_t;
-- user outputs
dips : in std_logic_vector(NUM_DIPS-1 downto 0);
inputs : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
);
end inputmapper;
architecture SYN of inputmapper is
begin
process (clk, rst_n)
variable jamma_v : from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1);
begin
-- note: all inputs are active LOW
if rst_n = '0' then
for i in 0 to NUM_INPUTS-1 loop
jamma_v(i).d := (others =>'1');
end loop;
elsif rising_edge (clk) then
-- handle JAMMA inputs
jamma_v(0).d(0) := jamma.p(1).start;
jamma_v(0).d(1) := jamma.p(2).start;
jamma_v(0).d(2) := '1';--jamma.service;
jamma_v(0).d(3) := jamma.coin(1);
--unused
--unused
--unused
--unused
jamma_v(1).d(0) := jamma.p(1).right;
jamma_v(1).d(1) := jamma.p(1).left;
jamma_v(1).d(2) := jamma.p(1).down;
jamma_v(1).d(3) := jamma.p(1).up;
--unused
jamma_v(1).d(5) := jamma.p(1).button(2);
--unused
jamma_v(1).d(7) := jamma.p(1).button(1);
jamma_v(2).d(0) := jamma.p(2).right;
jamma_v(2).d(1) := jamma.p(2).left;
jamma_v(2).d(2) := jamma.p(2).down;
jamma_v(2).d(3) := jamma.p(2).up;
jamma_v(2).d(4) := jamma.coin(2);
jamma_v(2).d(5) := jamma.p(2).button(2);
--unused
jamma_v(2).d(7) := jamma.p(2).button(1);
end if; -- rising_edge (clk)
-- assign outputs
inputs(0).d <= jamma_v(0).d;
inputs(1).d <= jamma_v(1).d;
inputs(2).d <= jamma_v(2).d;
inputs(3).d <= "11111110"; -- 1C/1C, 10/30/50K, 3 lives
inputs(4).d <= jamma.service & "1111100";
-- PORT_START("DSW2")
-- PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:1")
-- PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
-- PORT_DIPSETTING( 0x00, DEF_STR( On ) )
-- PORT_DIPNAME( 0x02, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:2")
-- PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
-- PORT_DIPSETTING( 0x02, DEF_STR( Cocktail ) )
-- PORT_DIPNAME( 0x04, 0x04, "Coin Mode" ) PORT_DIPLOCATION("SW2:3")
-- PORT_DIPSETTING( 0x04, "Mode 1" )
-- PORT_DIPSETTING( 0x00, "Mode 2" )
-- /* Bits 4,5,6 are different in each game, see below */
-- PORT_DIPUNUSED_DIPLOC( 0x38, 0x38, "SW2:4,5,6" )
-- PORT_DIPNAME( 0x40, 0x40, "Invulnerability (Cheat)" ) PORT_DIPLOCATION("SW2:7")
-- PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
-- PORT_DIPSETTING( 0x00, DEF_STR( On ) )
-- PORT_SERVICE_DIPLOC( 0x80, IP_ACTIVE_LOW, "SW2:8" )
end process;
end architecture SYN;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.sprite_pkg.all;
use work.platform_pkg.all;
--use work.project_pkg.all;
entity PACE is
port
(
-- clocks and resets
clkrst_i : in from_CLKRST_t;
-- misc I/O
buttons_i : in from_BUTTONS_t;
switches_i : in from_SWITCHES_t;
leds_o : out to_LEDS_t;
-- controller inputs
inputs_i : in from_INPUTS_t;
-- video
video_i : in from_VIDEO_t;
video_o : out to_VIDEO_t;
sound_data_o : out std_logic_vector(7 downto 0);
-- custom i/o
-- project_i : in from_PROJECT_IO_t;
-- project_o : out to_PROJECT_IO_t;
platform_i : in from_PLATFORM_IO_t;
platform_o : out to_PLATFORM_IO_t;
cpu_rom_addr : out std_logic_vector(14 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0)
);
end entity PACE;
architecture SYN of PACE is
constant CLK_1US_COUNTS : integer :=
integer(27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY);
signal mapped_inputs : from_MAPPED_INPUTS_t(0 to PACE_INPUTS_NUM_BYTES-1);
signal to_tilemap_ctl : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
signal to_bitmap_ctl : to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
signal from_bitmap_ctl : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
signal to_sprite_reg : to_SPRITE_REG_t;
signal to_sprite_ctl : to_SPRITE_CTL_t;
signal from_sprite_ctl : from_SPRITE_CTL_t;
signal spr0_hit : std_logic;
signal to_graphics : to_GRAPHICS_t;
signal from_graphics : from_GRAPHICS_t;
begin
inputs_inst : entity work.inputs
generic map
(
NUM_DIPS => PACE_NUM_SWITCHES,
NUM_INPUTS => PACE_INPUTS_NUM_BYTES,
CLK_1US_DIV => CLK_1US_COUNTS
)
port map
(
clk => clkrst_i.clk(0),
reset => clkrst_i.rst(0),
jamma => inputs_i.jamma_n,
dips => switches_i,
inputs => mapped_inputs
);
platform_inst : entity work.platform
generic map
(
NUM_INPUT_BYTES => PACE_INPUTS_NUM_BYTES
)
port map
(
-- clocking and reset
clkrst_i => clkrst_i,
-- misc inputs and outputs
buttons_i => buttons_i,
switches_i => switches_i,
leds_o => leds_o,
sound_data_o => sound_data_o,
-- controller inputs
inputs_i => mapped_inputs,
-- graphics
bitmap_i => from_bitmap_ctl,
bitmap_o => to_bitmap_ctl,
tilemap_i => from_tilemap_ctl,
tilemap_o => to_tilemap_ctl,
sprite_reg_o => to_sprite_reg,
sprite_i => from_sprite_ctl,
sprite_o => to_sprite_ctl,
spr0_hit => spr0_hit,
graphics_i => from_graphics,
graphics_o => to_graphics,
-- custom i/o
-- project_i => project_i,
-- project_o => project_o,
platform_i => platform_i,
platform_o => platform_o,
cpu_rom_addr => cpu_rom_addr,
cpu_rom_do => cpu_rom_do
);
graphics_inst : entity work.Graphics
Port Map
(
bitmap_ctl_i => to_bitmap_ctl,
bitmap_ctl_o => from_bitmap_ctl,
tilemap_ctl_i => to_tilemap_ctl,
tilemap_ctl_o => from_tilemap_ctl,
sprite_reg_i => to_sprite_reg,
sprite_ctl_i => to_sprite_ctl,
sprite_ctl_o => from_sprite_ctl,
spr0_hit => spr0_hit,
graphics_i => to_graphics,
graphics_o => from_graphics,
-- video (incl. clk)
video_i => video_i,
video_o => video_o
);
end SYN;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
package pace_pkg is
--
-- PACE constants which *MUST* be defined
--
type PACETargetType is
(
PACE_TARGET_NANOBOARD_NB1,
PACE_TARGET_DE0,
PACE_TARGET_DE0_CV, -- 5CEBA4
PACE_TARGET_DE0_NANO, -- EP4CE22
PACE_TARGET_DE1,
PACE_TARGET_DE2,
PACE_TARGET_DE2_70, -- EP2C70
PACE_TARGET_DE2_115, -- EP4CE115
PACE_TARGET_P2, -- A02 build
PACE_TARGET_P2A, -- A04/A build (SRAM byte selects)
PACE_TARGET_P3M,
PACE_TARGET_S3A_700, -- Spartan 3A/N Starter Kit
PACE_TARGET_RC10,
PACE_TARGET_NX2_12,
PACE_TARGET_NEXYS_3, -- Digilent S6 board
PACE_TARGET_CYC3DEV,
PACE_TARGET_CYC5GXDEV,
PACE_TARGET_COCO3PLUS,
PACE_TARGET_S5A,
PACE_TARGET_CARTEBLANCHE_250,
PACE_TARGET_CARTEBLANCHE_500,
PACE_TARGET_BEMICRO,
PACE_TARGET_OPENEP3C16,
PACE_TARGET_MIST,
PACE_TARGET_CHAMELEON64,
PACE_TARGET_RETRORAMBLINGS_CYC3, -- Generic EP3C25 board with custom io boards
PACE_TARGET_S5A_R2_EP4C,
PACE_TARGET_S5A_R2_EP3SL,
PACE_TARGET_S5A_R2B0_EP4C,
PACE_TARGET_S5A_R2B0_EP3SL,
PACE_TARGET_S5A_R2C0_EP4C,
PACE_TARGET_S5A_R2C0_EP3SL,
PACE_TARGET_S5L_A0_EP4C,
PACE_TARGET_S5L_A0_EP3SL,
PACE_TARGET_NAVICO_ROCKY,
PACE_TARGET_NGPACE,
PACE_TARGET_S6M_A0
);
type PACEFpgaVendor_t is
(
PACE_FPGA_VENDOR_ALTERA,
PACE_FPGA_VENDOR_XILINX,
PACE_FPGA_VENDOR_LATTICE
);
type PACEFpgaFamily_t is
(
PACE_FPGA_FAMILY_CYCLONE1,
PACE_FPGA_FAMILY_CYCLONE2,
PACE_FPGA_FAMILY_CYCLONE3,
PACE_FPGA_FAMILY_CYCLONE4,
PACE_FPGA_FAMILY_CYCLONE5,
PACE_FPGA_FAMILY_CYCLONE6,
PACE_FPGA_FAMILY_STRATIX_III,
PACE_FPGA_FAMILY_SPARTAN3,
PACE_FPGA_FAMILY_SPARTAN3A,
PACE_FPGA_FAMILY_SPARTAN3E
);
type PACEJamma_t is
(
PACE_JAMMA_NONE,
PACE_JAMMA_MAPLE,
PACE_JAMMA_NGC,
PACE_JAMMA_PS2
);
-- Types
type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
type from_CLKRST_t is record
arst : std_logic;
arst_n : std_logic;
rst : std_logic_vector(0 to 3);
clk_ref : std_logic; --reference clock
clk : std_logic_vector(0 to 3);
end record;
-- maximums from the DE2 target
constant PACE_NUM_SWITCHES : natural := 18;
subtype from_SWITCHES_t is std_logic_vector(PACE_NUM_SWITCHES-1 downto 0);
constant PACE_NUM_BUTTONS : natural := 4;
subtype from_BUTTONS_t is std_logic_vector(PACE_NUM_BUTTONS-1 downto 0);
constant PACE_NUM_LEDS : natural := 18;
subtype to_LEDS_t is std_logic_vector(PACE_NUM_LEDS-1 downto 0);
--
-- JAMMA interface data structures
-- - note: all signals are active LOW
--
type from_JAMMA_player_t is record
start : std_logic;
up : std_logic;
down : std_logic;
left : std_logic;
right : std_logic;
button : std_logic_vector(1 to 5);
end record;
type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t;
type from_JAMMA_t is record
coin_cnt : std_logic_vector(1 to 2);
service : std_logic;
tilt : std_logic;
test : std_logic;
coin : std_logic_vector(1 to 2);
p : from_JAMMA_player_a(1 to 2);
end record;
--
-- INPUTS
--
subtype analogue_in_t is std_logic_vector(9 downto 0);
type analogue_in_a is array (natural range <>) of analogue_in_t;
type from_INPUTS_t is record
ps2_kclk : std_logic;
ps2_kdat : std_logic;
ps2_mclk : std_logic;
ps2_mdat : std_logic;
jamma_n : from_JAMMA_t;
-- up to 4 10-bit analgue inputs
analogue : analogue_in_a(1 to 4);
end record;
type in8_t is record
d : std_logic_vector(7 downto 0);
end record;
type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t;
--
-- SRAM interface data structure
--
type from_SRAM_t is record
d : std_logic_vector(31 downto 0);
end record;
type to_SRAM_t is record
a : std_logic_vector(23 downto 0);
d : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
cs : std_logic;
oe : std_logic;
we : std_logic;
end record;
function NULL_TO_SRAM return to_SRAM_t;
--
-- FLASH interface data structure
--
type from_FLASH_t is record
d : std_logic_vector(15 downto 0);
end record;
type to_FLASH_t is record
a : std_logic_vector(21 downto 0);
d : std_logic_vector(15 downto 0);
we : std_logic;
cs : std_logic;
oe : std_logic;
end record;
function NULL_TO_FLASH return to_FLASH_t;
type from_AUDIO_t is record
clk : std_logic;
end record;
type to_AUDIO_t is record
clk : std_logic;
ldata : std_logic_vector(15 downto 0);
rdata : std_logic_vector(15 downto 0);
end record;
function NULL_TO_AUDIO return to_AUDIO_t;
type from_SPI_t is record
din : std_logic;
end record;
type to_SPI_t is record
clk : std_logic;
mode : std_logic;
sel : std_logic;
ena : std_logic;
dout : std_logic;
end record;
function NULL_TO_SPI return to_SPI_t;
type to_SERIAL_t is record
txd : std_logic;
rts : std_logic;
end record;
function NULL_TO_SERIAL return to_SERIAL_t;
type from_SERIAL_t is record
dcd : std_logic;
rxd : std_logic;
cts : std_logic;
end record;
constant PACE_NUM_GPI : natural := 72;
subtype from_GP_t is std_logic_vector(PACE_NUM_GPI-1 downto 0);
constant PACE_NUM_GPO : natural := PACE_NUM_GPI;
type to_GP_t is record
d : std_logic_vector(PACE_NUM_GPO-1 downto 0);
oe : std_logic_vector(PACE_NUM_GPO-1 downto 0);
end record;
function NULL_TO_GP return to_GP_t;
subtype SND_A_t is std_logic_vector(7 downto 0);
subtype SND_D_t is std_logic_vector(7 downto 0);
type to_SOUND_t is record
a : SND_A_t;
d : SND_D_t;
rd : std_logic;
wr : std_logic;
end record;
type from_SOUND_t is record
d : SND_D_t;
end record;
function NULL_TO_SOUND return to_SOUND_t;
--
-- OSD interface data structure
--
type from_OSD_t is record
d : std_logic_vector(7 downto 0);
end record;
function NULL_FROM_OSD return from_OSD_t;
type to_OSD_t is record
en : std_logic;
a : std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
we : std_logic;
end record;
function NULL_TO_OSD return to_OSD_t;
-- create a constant that automatically determines
-- whether this is simulation or synthesis
constant IN_SIMULATION : BOOLEAN := false
-- synthesis translate_off
or true
-- synthesis translate_on
;
constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
end;

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library work;
package body pace_pkg is
function NULL_TO_FLASH return to_FLASH_t is
begin
return ((others => '0'), (others => '0'), '0', '0', '0');
end NULL_TO_FLASH;
function NULL_TO_SRAM return to_SRAM_t is
begin
return ((others => '0'), (others => '0'), (others => '0'), '0', '0', '0');
end NULL_TO_SRAM;
function NULL_TO_AUDIO return to_AUDIO_t is
begin
return ('0', (others => '0'), (others => '0'));
end NULL_TO_AUDIO;
function NULL_TO_SPI return to_SPI_t is
begin
return (others => '0');
end NULL_TO_SPI;
function NULL_TO_SERIAL return to_SERIAL_t is
begin
return (others => '0');
end NULL_TO_SERIAL;
function NULL_TO_SOUND return to_SOUND_t is
begin
return ((others => '0'), (others => '0'), '0', '0');
end NULL_TO_SOUND;
function NULL_FROM_OSD return from_OSD_t is
begin
return (others => (others => '0'));
end NULL_FROM_OSD;
function NULL_TO_OSD return to_OSD_t is
begin
return ('0', (others => '0'), (others => '0'), '0');
end NULL_TO_OSD;
function NULL_TO_GP return to_GP_t is
begin
return ((others => '0'), (others => '0'));
end NULL_TO_GP;
end package body pace_pkg;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.sprite_pkg.all;
use work.platform_pkg.all;
use work.platform_variant_pkg.all;
--use work.project_pkg.all;
entity platform is
generic
(
NUM_INPUT_BYTES : integer
);
port
(
-- clocking and reset
clkrst_i : in from_CLKRST_t;
-- misc I/O
buttons_i : in from_BUTTONS_t;
switches_i : in from_SWITCHES_t;
leds_o : out to_LEDS_t;
-- controller inputs
inputs_i : in from_MAPPED_INPUTS_t(0 to NUM_INPUT_BYTES-1);
-- graphics
bitmap_i : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
bitmap_o : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
tilemap_i : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
tilemap_o : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
sprite_reg_o : out to_SPRITE_REG_t;
sprite_i : in from_SPRITE_CTL_t;
sprite_o : out to_SPRITE_CTL_t;
spr0_hit : in std_logic;
-- various graphics information
graphics_i : in from_GRAPHICS_t;
graphics_o : out to_GRAPHICS_t;
sound_data_o : out std_logic_vector(7 downto 0);
-- custom i/o
-- project_i : in from_PROJECT_IO_t;
-- project_o : out to_PROJECT_IO_t;
platform_i : in from_PLATFORM_IO_t;
platform_o : out to_PLATFORM_IO_t;
cpu_rom_addr : out std_logic_vector(14 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0)
);
end platform;
architecture SYN of platform is
alias clk_sys : std_logic is clkrst_i.clk(0);
alias rst_sys : std_logic is clkrst_i.rst(0);
alias clk_video : std_logic is clkrst_i.clk(1);
-- cpu signals
signal clk_3M072_en : std_logic;
signal cpu_clk_en : std_logic;
signal cpu_a : std_logic_vector(15 downto 0);
signal cpu_d_i : std_logic_vector(7 downto 0);
signal cpu_d_o : std_logic_vector(7 downto 0);
signal cpu_mem_wr : std_logic;
signal cpu_io_rd : std_logic;
signal cpu_io_wr : std_logic;
signal cpu_irq : std_logic;
-- ROM signals
signal rom_cs : std_logic;
-- signal rom_d_o : std_logic_vector(7 downto 0);
-- keyboard signals
-- VRAM signals
signal vram_cs : std_logic;
signal vram_wr : std_logic;
signal vram_d_o : std_logic_vector(7 downto 0);
signal snd_cs : std_logic;
-- RAM signals
signal wram_cs : std_logic;
signal wram_wr : std_logic;
signal wram_d_o : std_logic_vector(7 downto 0);
-- CRAM/SPRITE signals
signal cram_cs : std_logic;
signal cram_wr : std_logic;
signal cram_d_o : std_logic_vector(7 downto 0);
signal sprite_cs : std_logic;
-- misc signals
signal in_cs : std_logic;
signal in_d_o : std_logic_vector(7 downto 0);
-- other signals
signal rst_platform : std_logic;
signal pause : std_logic;
signal rot_en : std_logic;
begin
-- handle special keys
process (clk_sys, rst_sys)
variable spec_keys_r : std_logic_vector(7 downto 0);
alias spec_keys : std_logic_vector(7 downto 0) is inputs_i(PACE_INPUTS_NUM_BYTES-1).d;
variable layer_en : std_logic_vector(4 downto 0);
begin
if rst_sys = '1' then
rst_platform <= '0';
pause <= '0';
rot_en <= '0'; -- to default later
spec_keys_r := (others => '0');
layer_en := "11111";
elsif rising_edge(clk_sys) then
rst_platform <= spec_keys(0);
if spec_keys_r(1) = '0' and spec_keys(1) = '1' then
pause <= not pause;
end if;
if spec_keys_r(2) = '0' and spec_keys(2) = '1' then
rot_en <= not rot_en;
if layer_en = "11111" then
layer_en := "00001";
elsif layer_en = "10000" then
layer_en := "11111";
else
layer_en := layer_en(3 downto 0) & layer_en(4);
end if;
end if;
spec_keys_r := spec_keys;
end if;
graphics_o.bit8(0)(4 downto 0) <= layer_en;
end process;
--graphics_o.bit8(0)(0) <= rot_en;
-- chip select logic
-- ROM $0000-$7FFF
rom_cs <= '1' when STD_MATCH(cpu_a, "0---------------") else '0';
-- SPRITE $C000-$C0FF
sprite_cs <= '1' when STD_MATCH(cpu_a, X"C0"& "--------") else '0';
-- VRAM/CRAM $D000-$DFFF
vram_cs <= '1' when PLATFORM_VARIANT = "kungfum" and
STD_MATCH(cpu_a, X"D"&"0-----------") else
'1' when PLATFORM_VARIANT /= "kungfum" and
STD_MATCH(cpu_a, X"D"&"-----------0") else
'0';
cram_cs <= '1' when PLATFORM_VARIANT = "kungfum" and
STD_MATCH(cpu_a, X"D"&"1-----------") else
'1' when PLATFORM_VARIANT /= "kungfum" and
STD_MATCH(cpu_a, X"D"&"-----------1") else
'0';
-- RAM $E000-$EFFF
wram_cs <= '1' when STD_MATCH(cpu_a, X"E"&"------------") else '0';
-- OUTPUT $DXX0
snd_cs <= '1' when STD_MATCH(cpu_a(7 downto 0), X"D") else '0';
-- INPUTS (I/O) $00-$04
in_cs <= '1' when STD_MATCH(cpu_a(7 downto 0), X"0"&"00--") else
'1' when STD_MATCH(cpu_a(7 downto 0), X"04") else
'0';
process (clk_sys, rst_sys) begin
if rst_sys = '1' then
sound_data_o <= X"00";
elsif rising_edge(clk_sys) then
if cpu_clk_en = '1' and cpu_mem_wr = '1' and snd_cs = '1' then
sound_data_o <= cpu_d_o;
end if;
end if;
end process;
-- memory read mux
cpu_d_i <= in_d_o when (cpu_io_rd = '1' and in_cs = '1') else
cpu_rom_do when rom_cs = '1' else
vram_d_o when vram_cs = '1' else
cram_d_o when cram_cs = '1' else
wram_d_o when wram_cs = '1' else
(others => '1');
-- memory block write signals
vram_wr <= vram_cs and cpu_mem_wr;
cram_wr <= cram_cs and cpu_mem_wr;
wram_wr <= wram_cs and cpu_mem_wr;
-- sprite registers
sprite_reg_o.clk <= clk_sys;
sprite_reg_o.clk_ena <= clk_3M072_en;
sprite_reg_o.a <= cpu_a(7 downto 0);
sprite_reg_o.d <= cpu_d_o;
sprite_reg_o.wr <= sprite_cs and cpu_mem_wr;
--
-- COMPONENT INSTANTIATION
--
BLK_CPU : block
signal cpu_rst : std_logic;
begin
-- generate CPU enable clock (3MHz from 27/30MHz)
clk_en_inst : entity work.clk_div
generic map
(
DIVISOR => M62_CPU_CLK_ENA_DIVIDE_BY
)
port map
(
clk => clk_sys,
reset => rst_sys,
clk_en => clk_3M072_en
);
-- gated CPU signals
cpu_clk_en <= clk_3M072_en and not pause;
cpu_rst <= rst_sys or rst_platform;
cpu_inst : entity work.Z80
port map
(
clk => clk_sys,
clk_en => cpu_clk_en,
reset => cpu_rst,
addr => cpu_a,
datai => cpu_d_i,
datao => cpu_d_o,
mem_rd => open,
mem_wr => cpu_mem_wr,
io_rd => cpu_io_rd,
io_wr => cpu_io_wr,
intreq => cpu_irq,
intvec => cpu_d_i,
intack => open,
nmi => '0'
);
end block BLK_CPU;
BLK_INTERRUPTS : block
signal vblank_int : std_logic;
begin
process (clk_sys, rst_sys)
variable vblank_r : std_logic_vector(3 downto 0);
alias vblank_prev : std_logic is vblank_r(vblank_r'left);
alias vblank_um : std_logic is vblank_r(vblank_r'left-1);
-- 1us duty for VBLANK_INT
variable count : integer range 0 to CLK0_FREQ_MHz * 100;
begin
if rst_sys = '1' then
vblank_int <= '0';
vblank_r := (others => '0');
count := count'high;
elsif rising_edge(clk_sys) then
-- rising edge vblank only
if vblank_prev = '0' and vblank_um = '1' then
count := 0;
end if;
if count /= count'high then
vblank_int <= '1';
count := count + 1;
else
vblank_int <= '0';
end if;
vblank_r := vblank_r(vblank_r'left-1 downto 0) & graphics_i.vblank;
end if; -- rising_edge(clk_sys)
end process;
-- generate INT
cpu_irq <= vblank_int;
end block BLK_INTERRUPTS;
BLK_INPUTS : block
begin
in_d_o <= inputs_i(0).d when cpu_a(2 downto 0) = "000" else
inputs_i(1).d when cpu_a(2 downto 0) = "001" else
inputs_i(2).d when cpu_a(2 downto 0) = "010" else
inputs_i(3).d when cpu_a(2 downto 0) = "011" else
inputs_i(4).d;
end block BLK_INPUTS;
BLK_SCROLL : block
signal m62_hscroll : std_logic_vector(15 downto 0);
begin
process (clk_sys, rst_sys)
begin
if rst_sys = '1' then
m62_hscroll <= (others => '0');
elsif rising_edge(clk_sys) then
if cpu_clk_en = '1' and cpu_mem_wr = '1' then
case cpu_a is
when X"A000" =>
if PLATFORM_VARIANT = "kungfum" then
m62_hscroll(7 downto 0) <= cpu_d_o;
end if;
when X"B000" =>
if PLATFORM_VARIANT = "kungfum" then
m62_hscroll(15 downto 8) <= cpu_d_o;
end if;
when others =>
null;
end case;
end if; -- cpu_wr
end if; -- rising_edge(clk_sys)
end process;
graphics_o.bit16(0) <= m62_hscroll;
end block BLK_SCROLL;
cpu_rom_addr <= cpu_a(14 downto 0);
BLK_GFX_ROMS : block
type gfx_rom_d_a is array(M62_CHAR_ROM'range) of std_logic_vector(7 downto 0);
signal chr_rom_d : gfx_rom_d_a;
type spr_rom_d_a is array(0 to 11) of std_logic_vector(7 downto 0);
signal spr_rom_left : spr_rom_d_a;
signal spr_rom_right : spr_rom_d_a;
begin
GEN_CHAR_ROMS : for i in M62_CHAR_ROM'range generate
char_rom_inst : entity work.sprom
generic map
(
init_file => "./roms/" &
M62_CHAR_ROM(i) & ".hex",
widthad_a => 13
)
port map
(
clock => clk_video,
address => tilemap_i(1).tile_a(12 downto 0),
q => chr_rom_d(i)
);
end generate GEN_CHAR_ROMS;
tilemap_o(1).tile_d(23 downto 0) <= chr_rom_d(0) & chr_rom_d(1) & chr_rom_d(2);
GEN_SPRITE_ROMS : for i in M62_SPRITE_ROM'range generate
sprite_rom_inst : entity work.dprom_2r
generic map
(
init_file => "./roms/" &
M62_SPRITE_ROM(i) & ".hex",
widthad_a => 13,
widthad_b => 13
)
port map
(
clock => clk_video,
address_a(12 downto 5) => sprite_i.a(12 downto 5),
address_a(4) => '0',
address_a(3 downto 0) => sprite_i.a(3 downto 0),
q_a => spr_rom_left(i),
address_b(12 downto 5) => sprite_i.a(12 downto 5),
address_b(4) => '1',
address_b(3 downto 0) => sprite_i.a(3 downto 0),
q_b => spr_rom_right(i)
);
end generate GEN_SPRITE_ROMS;
sprite_o.d(sprite_o.d'left downto 48) <= (others => '0');
sprite_o.d(47 downto 0) <= spr_rom_left(0) & spr_rom_right(0) &
spr_rom_left(1) & spr_rom_right(1) &
spr_rom_left(2) & spr_rom_right(2)
when sprite_i.a(14 downto 13) = "00" else
spr_rom_left(3) & spr_rom_right(3) &
spr_rom_left(4) & spr_rom_right(4) &
spr_rom_left(5) & spr_rom_right(5)
when sprite_i.a(14 downto 13) = "01" else
spr_rom_left(6) & spr_rom_right(6) &
spr_rom_left(7) & spr_rom_right(7) &
spr_rom_left(8) & spr_rom_right(8)
when sprite_i.a(14 downto 13) = "10" else
spr_rom_left(9) & spr_rom_right(9) &
spr_rom_left(10) & spr_rom_right(10) &
spr_rom_left(11) & spr_rom_right(11);
end block BLK_GFX_ROMS;
BLK_VRAM : block
signal vram_a : std_logic_vector(10 downto 0);
alias cram_a : std_logic_vector(10 downto 0) is vram_a;
begin
vram_a <= cpu_a(10 downto 0) when PLATFORM_VARIANT = "kungfum" else
cpu_a(11 downto 1);
vram_inst : entity work.dpram
generic map
(
init_file => "",
widthad_a => 11
)
port map
(
clock_b => clk_sys,
address_b => vram_a,
wren_b => vram_wr,
data_b => cpu_d_o,
q_b => vram_d_o,
clock_a => clk_video,
address_a => tilemap_i(1).map_a(10 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).map_d(7 downto 0)
);
tilemap_o(1).map_d(15 downto 8) <= (others => '0');
cram_inst : entity work.dpram
generic map
(
init_file => "",
widthad_a => 11
)
port map
(
clock_b => clk_sys,
address_b => cram_a,
wren_b => cram_wr,
data_b => cpu_d_o,
q_b => cram_d_o,
clock_a => clk_video,
address_a => tilemap_i(1).attr_a(10 downto 0),
wren_a => '0',
data_a => (others => 'X'),
q_a => tilemap_o(1).attr_d(7 downto 0)
);
tilemap_o(1).attr_d(15 downto 8) <= (others => '0');
end block BLK_VRAM;
wram_inst : entity work.spram
generic map
(
widthad_a => 12
)
port map
(
clock => clk_sys,
address => cpu_a(11 downto 0),
data => cpu_d_o,
wren => wram_wr,
q => wram_d_o
);
-- unused outputs
sprite_o.ld <= '0';
--graphics_o <= NULL_TO_GRAPHICS;
leds_o <= (others => '0');
end SYN;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.platform_variant_pkg.all;
use work.video_controller_pkg.all;
package platform_pkg is
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_PAL_576x288_50Hz;
constant PACE_CLK0_DIVIDE_BY : natural := 27;
constant PACE_CLK0_MULTIPLY_BY : natural := 44; -- 27*44/27 = 44MHz
constant PACE_CLK1_DIVIDE_BY : natural := 27;
constant PACE_CLK1_MULTIPLY_BY : natural := 11; -- 27*11/27 = 11MHz
constant PACE_VIDEO_H_SCALE : integer := 1;
constant PACE_VIDEO_V_SCALE : integer := 1;
constant PACE_ENABLE_ADV724 : std_logic := '1';
constant USE_VIDEO_VBLANK_INTERRUPT : boolean := false;
constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1';
constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_BLACK;
constant M62_VIDEO_H_SIZE : integer := 256;
constant M62_VIDEO_H_OFFSET : integer := (512-M62_VIDEO_H_SIZE)/2;
constant M62_VIDEO_V_SIZE : integer := 256;
constant PACE_VIDEO_NUM_BITMAPS : natural := 0;
constant PACE_VIDEO_NUM_TILEMAPS : natural := 1;
constant PACE_VIDEO_NUM_SPRITES : natural := 32;
constant PACE_VIDEO_H_SIZE : integer := M62_VIDEO_H_SIZE;
constant PACE_VIDEO_V_SIZE : integer := M62_VIDEO_V_SIZE;
constant PACE_VIDEO_L_CROP : integer := 0;
constant PACE_VIDEO_R_CROP : integer := PACE_VIDEO_L_CROP;
constant PACE_VIDEO_PIPELINE_DELAY : integer := 5;
constant PACE_INPUTS_NUM_BYTES : integer := 6;
constant CLK0_FREQ_MHz : natural :=
27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;
constant CPU_FREQ_MHz : natural := 3;
constant M62_CPU_CLK_ENA_DIVIDE_BY : natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
type from_PLATFORM_IO_t is record
not_used : std_logic;
end record;
type to_PLATFORM_IO_t is record
not_used : std_logic;
end record;
end;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.platform_pkg.all;
package platform_variant_pkg is
constant PLATFORM_VARIANT : string := "kungfum";
type rom_a is array (natural range <>) of string;
-- constant M62_ROM : rom_a(0 to 3) :=
-- (
-- 0 => "lr-a-4e",
-- 1 => "lr-a-4d",
-- 2 => "lr-a-4b",
-- 3 => "lr-a-4a"
-- );
-- constant M62_ROM_WIDTHAD : natural := 13;
constant M62_CHAR_ROM : rom_a(0 to 2) :=
(
0 => "g-4c-a",
1 => "g-4d-a",
2 => "g-4e-a"
);
constant M62_SPRITE_ROM : rom_a(0 to 11) :=
(
0 => "b-4k-.bin",
3 => "b-4f-.bin",
6 => "b-4l-.bin",
9 => "b-4h-.bin",
1 => "b-3n-.bin",
4 => "b-4n-.bin",
7 => "b-4m-.bin",
10 => "b-3m-.bin",
2 => "b-4c-.bin",
5 => "b-4e-.bin",
8 => "b-4d-.bin",
11 => "b-4a-.bin"
);
type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0);
type pal_a is array (natural range <>) of pal_rgb_t;
constant tile_pal : pal_a(0 to 255) :=
(
0 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
1 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
2 => (0=>"00000011", 1=>"11111111", 2=>"00000011"), -- 03FF03
3 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
4 => (0=>"00000011", 1=>"00000011", 2=>"11111111"), -- 0303FF
5 => (0=>"11111111", 1=>"00000011", 2=>"11111111"), -- FF03FF
6 => (0=>"00000011", 1=>"11111111", 2=>"11111111"), -- 03FFFF
8 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
9 => (0=>"11110000", 1=>"10110111", 2=>"10000100"), -- F0B784
10 => (0=>"11011100", 1=>"10100110", 2=>"01110000"), -- DCA670
11 => (0=>"11111111", 1=>"00000011", 2=>"00110001"), -- FF0331
12 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
13 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
14 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
15 => (0=>"11110000", 1=>"11110000", 2=>"11110000"), -- F0F0F0
16 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
18 => (0=>"10000100", 1=>"11001100", 2=>"10000100"), -- 84CC84
19 => (0=>"11001100", 1=>"11110000", 2=>"11001100"), -- CCF0CC
20 => (0=>"01100010", 1=>"01100010", 2=>"01100010"), -- 626262
21 => (0=>"11011100", 1=>"10010100", 2=>"01010000"), -- DC9450
22 => (0=>"10110111", 1=>"10010100", 2=>"01010000"), -- B79450
23 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
24 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
25 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
26 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
27 => (0=>"10100110", 1=>"11001100", 2=>"11111111"), -- A6CCFF
29 => (0=>"11001100", 1=>"10010100", 2=>"10000100"), -- CC9484
30 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
31 => (0=>"11111111", 1=>"11110000", 2=>"11001100"), -- FFF0CC
32 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
33 => (0=>"11001100", 1=>"00110001", 2=>"01000001"), -- CC3141
34 => (0=>"11111111", 1=>"10000100", 2=>"10000100"), -- FF8484
35 => (0=>"11111111", 1=>"10110111", 2=>"10110111"), -- FFB7B7
36 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
37 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
38 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
39 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
40 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
41 => (0=>"00000011", 1=>"11001100", 2=>"11001100"), -- 03CCCC
42 => (0=>"11011100", 1=>"11111111", 2=>"11111111"), -- DCFFFF
43 => (0=>"11011100", 1=>"10010100", 2=>"01110000"), -- DC9470
44 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
45 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
46 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
47 => (0=>"11111111", 1=>"11001100", 2=>"01110000"), -- FFCC70
48 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
49 => (0=>"11011100", 1=>"11111111", 2=>"11111111"), -- DCFFFF
50 => (0=>"00000011", 1=>"11110000", 2=>"11110000"), -- 03F0F0
51 => (0=>"11011100", 1=>"10010100", 2=>"01110000"), -- DC9470
52 => (0=>"11111111", 1=>"11001100", 2=>"01110000"), -- FFCC70
53 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
54 => (0=>"01110000", 1=>"01110000", 2=>"01110000"), -- 707070
55 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
56 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
57 => (0=>"00000011", 1=>"11111111", 2=>"00000011"), -- 03FF03
58 => (0=>"11111111", 1=>"11001100", 2=>"00000011"), -- FFCC03
59 => (0=>"11111111", 1=>"11011100", 2=>"00000011"), -- FFDC03
60 => (0=>"00000011", 1=>"11111111", 2=>"11111111"), -- 03FFFF
61 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
62 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
63 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
64 => (0=>"11111111", 1=>"00000011", 2=>"00110001"), -- FF0331
65 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
66 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
67 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
68 => (0=>"11011100", 1=>"10010100", 2=>"01110000"), -- DC9470
69 => (0=>"11111111", 1=>"11001100", 2=>"01110000"), -- FFCC70
70 => (0=>"00000011", 1=>"11110000", 2=>"11110000"), -- 03F0F0
71 => (0=>"11011100", 1=>"11111111", 2=>"11111111"), -- DCFFFF
72 => (0=>"10100110", 1=>"11001100", 2=>"11111111"), -- A6CCFF
73 => (0=>"11111111", 1=>"11001100", 2=>"01110000"), -- FFCC70
74 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
75 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
76 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
77 => (0=>"11110000", 1=>"11011100", 2=>"10100110"), -- F0DCA6
78 => (0=>"11110000", 1=>"11110000", 2=>"11110000"), -- F0F0F0
80 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
81 => (0=>"11111111", 1=>"11001100", 2=>"01110000"), -- FFCC70
82 => (0=>"11011100", 1=>"10010100", 2=>"01110000"), -- DC9470
83 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
84 => (0=>"11011100", 1=>"11111111", 2=>"11111111"), -- DCFFFF
85 => (0=>"00000011", 1=>"11110000", 2=>"11110000"), -- 03F0F0
86 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
87 => (0=>"01110000", 1=>"01110000", 2=>"01110000"), -- 707070
88 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
91 => (0=>"11111111", 1=>"00000011", 2=>"00110001"), -- FF0331
92 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
93 => (0=>"11001100", 1=>"00000011", 2=>"10000100"), -- CC0384
94 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
96 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
97 => (0=>"00000011", 1=>"10110111", 2=>"11001100"), -- 03B7CC
98 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
99 => (0=>"11111111", 1=>"11001100", 2=>"01110000"), -- FFCC70
100 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
101 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
102 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
103 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
105 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
106 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
107 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
108 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
109 => (0=>"10100110", 1=>"11001100", 2=>"11111111"), -- A6CCFF
110 => (0=>"00000011", 1=>"11011100", 2=>"00000011"), -- 03DC03
111 => (0=>"10110111", 1=>"11111111", 2=>"10110111"), -- B7FFB7
112 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
113 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
114 => (0=>"00000011", 1=>"11110000", 2=>"10100110"), -- 03F0A6
115 => (0=>"11111111", 1=>"11011100", 2=>"10010100"), -- FFDC94
116 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
117 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
118 => (0=>"00000011", 1=>"11011100", 2=>"00000011"), -- 03DC03
119 => (0=>"10110111", 1=>"11111111", 2=>"10110111"), -- B7FFB7
120 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
121 => (0=>"11111111", 1=>"10110111", 2=>"10110111"), -- FFB7B7
122 => (0=>"00000011", 1=>"11110000", 2=>"10100110"), -- 03F0A6
123 => (0=>"11111111", 1=>"11011100", 2=>"10010100"), -- FFDC94
125 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
126 => (0=>"11011100", 1=>"11011100", 2=>"11011100"), -- DCDCDC
127 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
128 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
129 => (0=>"11111111", 1=>"10110111", 2=>"10110111"), -- FFB7B7
130 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
131 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
132 => (0=>"00000011", 1=>"11011100", 2=>"00000011"), -- 03DC03
133 => (0=>"11011100", 1=>"11011100", 2=>"11011100"), -- DCDCDC
134 => (0=>"10110111", 1=>"11111111", 2=>"10110111"), -- B7FFB7
135 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
136 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
137 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
138 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
139 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
140 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
141 => (0=>"11111111", 1=>"11001100", 2=>"10110111"), -- FFCCB7
142 => (0=>"00000011", 1=>"11011100", 2=>"11011100"), -- 03DCDC
143 => (0=>"10110111", 1=>"10100110", 2=>"10000100"), -- B7A684
144 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
145 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
146 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
147 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
148 => (0=>"11001100", 1=>"10010100", 2=>"10000100"), -- CC9484
149 => (0=>"11111111", 1=>"11001100", 2=>"10110111"), -- FFCCB7
150 => (0=>"10100110", 1=>"11001100", 2=>"11111111"), -- A6CCFF
151 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
152 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
153 => (0=>"10100110", 1=>"10000100", 2=>"00000011"), -- A68403
154 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
155 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
156 => (0=>"11001100", 1=>"10010100", 2=>"10000100"), -- CC9484
157 => (0=>"11111111", 1=>"11001100", 2=>"10110111"), -- FFCCB7
158 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
159 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
160 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
162 => (0=>"11111111", 1=>"10010100", 2=>"01110000"), -- FF9470
163 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
164 => (0=>"11111111", 1=>"11111111", 2=>"11001100"), -- FFFFCC
165 => (0=>"11111111", 1=>"11111111", 2=>"10110111"), -- FFFFB7
166 => (0=>"11001100", 1=>"11001100", 2=>"00000011"), -- CCCC03
167 => (0=>"11110000", 1=>"11110000", 2=>"00000011"), -- F0F003
168 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
169 => (0=>"00000011", 1=>"11111111", 2=>"11111111"), -- 03FFFF
170 => (0=>"11111111", 1=>"00000011", 2=>"11111111"), -- FF03FF
171 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
173 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
174 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
175 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
176 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
177 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
178 => (0=>"11001100", 1=>"11111111", 2=>"11001100"), -- CCFFCC
179 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
180 => (0=>"00000011", 1=>"00000011", 2=>"11111111"), -- 0303FF
181 => (0=>"11110000", 1=>"10110111", 2=>"10010100"), -- F0B794
182 => (0=>"10110111", 1=>"11110000", 2=>"11110000"), -- B7F0F0
183 => (0=>"11001100", 1=>"10100110", 2=>"10000100"), -- CCA684
186 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
188 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
194 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
196 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
200 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
201 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
202 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
203 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
204 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
205 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
206 => (0=>"00000011", 1=>"00000011", 2=>"10100110"), -- 0303A6
208 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
209 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
210 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
212 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
213 => (0=>"11111111", 1=>"10010100", 2=>"10010100"), -- FF9494
214 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
216 => (0=>"11111111", 1=>"11110000", 2=>"11011100"), -- FFF0DC
217 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
218 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
219 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
220 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
221 => (0=>"11111111", 1=>"11001100", 2=>"10110111"), -- FFCCB7
222 => (0=>"11011100", 1=>"10110111", 2=>"10010100"), -- DCB794
223 => (0=>"11110000", 1=>"11001100", 2=>"10100110"), -- F0CCA6
224 => (0=>"01100010", 1=>"01100010", 2=>"01100010"), -- 626262
225 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
226 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
227 => (0=>"11011100", 1=>"00100010", 2=>"11001100"), -- DC22CC
228 => (0=>"11001100", 1=>"11110000", 2=>"11001100"), -- CCF0CC
229 => (0=>"10000100", 1=>"11001100", 2=>"10000100"), -- 84CC84
231 => (0=>"11110000", 1=>"11011100", 2=>"10100110"), -- F0DCA6
232 => (0=>"10100110", 1=>"10000100", 2=>"11011100"), -- A684DC
233 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
234 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
235 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
236 => (0=>"01100010", 1=>"01100010", 2=>"01100010"), -- 626262
237 => (0=>"11110000", 1=>"11011100", 2=>"10100110"), -- F0DCA6
238 => (0=>"11011100", 1=>"00100010", 2=>"11001100"), -- DC22CC
239 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
240 => (0=>"01100010", 1=>"01100010", 2=>"01100010"), -- 626262
241 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
242 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
243 => (0=>"11011100", 1=>"00100010", 2=>"11001100"), -- DC22CC
244 => (0=>"00000011", 1=>"10110111", 2=>"00000011"), -- 03B703
245 => (0=>"11110000", 1=>"11011100", 2=>"10100110"), -- F0DCA6
246 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
248 => (0=>"11111111", 1=>"11110000", 2=>"11011100"), -- FFF0DC
249 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
250 => (0=>"10010100", 1=>"10000100", 2=>"10110111"), -- 9484B7
251 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
252 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
253 => (0=>"10000100", 1=>"11001100", 2=>"10000100"), -- 84CC84
254 => (0=>"11011100", 1=>"11001100", 2=>"10110111"), -- DCCCB7
255 => (0=>"11110000", 1=>"11110000", 2=>"11001100"), -- F0F0CC
others => (others => (others => '1'))
);
constant sprite_pal : pal_a(0 to 255) :=
(
0 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
1 => (0=>"10100110", 1=>"01110000", 2=>"00000011"), -- A67003
2 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
3 => (0=>"11111111", 1=>"10110111", 2=>"10010100"), -- FFB794
4 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
5 => (0=>"11001100", 1=>"11111111", 2=>"11111111"), -- CCFFFF
6 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
8 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
9 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
10 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
11 => (0=>"11111111", 1=>"10110111", 2=>"10010100"), -- FFB794
12 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
13 => (0=>"10100110", 1=>"11011100", 2=>"11110000"), -- A6DCF0
14 => (0=>"11001100", 1=>"11111111", 2=>"11111111"), -- CCFFFF
16 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
17 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
18 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
19 => (0=>"11111111", 1=>"10110111", 2=>"10010100"), -- FFB794
20 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
21 => (0=>"10100110", 1=>"11011100", 2=>"11110000"), -- A6DCF0
22 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
24 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
25 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
26 => (0=>"11001100", 1=>"11111111", 2=>"11111111"), -- CCFFFF
27 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
28 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
29 => (0=>"10100110", 1=>"01110000", 2=>"00000011"), -- A67003
30 => (0=>"10110111", 1=>"10010100", 2=>"01110000"), -- B79470
31 => (0=>"11111111", 1=>"10110111", 2=>"10010100"), -- FFB794
32 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
33 => (0=>"10010100", 1=>"10010100", 2=>"11001100"), -- 9494CC
34 => (0=>"10110111", 1=>"10110111", 2=>"11011100"), -- B7B7DC
35 => (0=>"11001100", 1=>"11011100", 2=>"11111111"), -- CCDCFF
36 => (0=>"11011100", 1=>"00000011", 2=>"11011100"), -- DC03DC
37 => (0=>"11110000", 1=>"10100110", 2=>"11011100"), -- F0A6DC
38 => (0=>"11111111", 1=>"10110111", 2=>"10010100"), -- FFB794
39 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
40 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
41 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
42 => (0=>"10110111", 1=>"10110111", 2=>"11011100"), -- B7B7DC
43 => (0=>"11001100", 1=>"11011100", 2=>"11111111"), -- CCDCFF
44 => (0=>"11011100", 1=>"00000011", 2=>"11011100"), -- DC03DC
45 => (0=>"11110000", 1=>"10100110", 2=>"11011100"), -- F0A6DC
46 => (0=>"11111111", 1=>"10110111", 2=>"10010100"), -- FFB794
47 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
48 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
49 => (0=>"11001100", 1=>"11011100", 2=>"11111111"), -- CCDCFF
50 => (0=>"10100110", 1=>"10110111", 2=>"11001100"), -- A6B7CC
51 => (0=>"11110000", 1=>"11110000", 2=>"11110000"), -- F0F0F0
52 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
53 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
54 => (0=>"11111111", 1=>"11011100", 2=>"10110111"), -- FFDCB7
56 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
57 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
59 => (0=>"11110000", 1=>"10100110", 2=>"00000011"), -- F0A603
60 => (0=>"11111111", 1=>"11011100", 2=>"10110111"), -- FFDCB7
61 => (0=>"11110000", 1=>"11001100", 2=>"10100110"), -- F0CCA6
62 => (0=>"10100110", 1=>"10000100", 2=>"00000011"), -- A68403
63 => (0=>"10110111", 1=>"11111111", 2=>"10110111"), -- B7FFB7
64 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
65 => (0=>"11111111", 1=>"10110111", 2=>"10010100"), -- FFB794
66 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
67 => (0=>"11011100", 1=>"11110000", 2=>"11110000"), -- DCF0F0
68 => (0=>"11001100", 1=>"11011100", 2=>"11111111"), -- CCDCFF
69 => (0=>"10100110", 1=>"10010100", 2=>"01110000"), -- A69470
70 => (0=>"10000100", 1=>"10000100", 2=>"10000100"), -- 848484
71 => (0=>"10110111", 1=>"10110111", 2=>"11011100"), -- B7B7DC
72 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
73 => (0=>"11110000", 1=>"11110000", 2=>"10000100"), -- F0F084
74 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
75 => (0=>"11011100", 1=>"11110000", 2=>"11110000"), -- DCF0F0
76 => (0=>"11001100", 1=>"11011100", 2=>"11111111"), -- CCDCFF
77 => (0=>"10100110", 1=>"10010100", 2=>"01110000"), -- A69470
78 => (0=>"10000100", 1=>"10000100", 2=>"10000100"), -- 848484
80 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
81 => (0=>"11011100", 1=>"11001100", 2=>"10010100"), -- DCCC94
82 => (0=>"01110000", 1=>"10110111", 2=>"01110000"), -- 70B770
83 => (0=>"11110000", 1=>"11011100", 2=>"10010100"), -- F0DC94
84 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
86 => (0=>"01110000", 1=>"10010100", 2=>"01110000"), -- 709470
88 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
89 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
90 => (0=>"10000100", 1=>"11111111", 2=>"10000100"), -- 84FF84
91 => (0=>"11111111", 1=>"10110111", 2=>"01110000"), -- FFB770
92 => (0=>"01110000", 1=>"01110000", 2=>"10110111"), -- 7070B7
94 => (0=>"11001100", 1=>"10100110", 2=>"11111111"), -- CCA6FF
96 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
97 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
98 => (0=>"01110000", 1=>"11001100", 2=>"01110000"), -- 70CC70
99 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
100 => (0=>"01110000", 1=>"10100110", 2=>"01110000"), -- 70A670
101 => (0=>"11111111", 1=>"11001100", 2=>"01110000"), -- FFCC70
102 => (0=>"10110111", 1=>"11110000", 2=>"11110000"), -- B7F0F0
104 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
105 => (0=>"11011100", 1=>"00000011", 2=>"00000011"), -- DC0303
107 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
108 => (0=>"00000011", 1=>"00000011", 2=>"10110111"), -- 0303B7
109 => (0=>"11110000", 1=>"10100110", 2=>"01110000"), -- F0A670
110 => (0=>"10000100", 1=>"10000100", 2=>"11111111"), -- 8484FF
111 => (0=>"11111111", 1=>"11001100", 2=>"01110000"), -- FFCC70
112 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
113 => (0=>"11111111", 1=>"11001100", 2=>"00000011"), -- FFCC03
114 => (0=>"10110111", 1=>"10010100", 2=>"10000100"), -- B79484
115 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
116 => (0=>"10000100", 1=>"10000100", 2=>"10110111"), -- 8484B7
117 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
118 => (0=>"11011100", 1=>"10110111", 2=>"10010100"), -- DCB794
120 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
121 => (0=>"11111111", 1=>"11001100", 2=>"00000011"), -- FFCC03
122 => (0=>"10110111", 1=>"10010100", 2=>"10000100"), -- B79484
123 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
124 => (0=>"11111111", 1=>"10100110", 2=>"00000011"), -- FFA603
125 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
126 => (0=>"11011100", 1=>"10110111", 2=>"10010100"), -- DCB794
128 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
129 => (0=>"11111111", 1=>"11001100", 2=>"00000011"), -- FFCC03
130 => (0=>"10110111", 1=>"10010100", 2=>"10000100"), -- B79484
131 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
132 => (0=>"10000100", 1=>"10000100", 2=>"10110111"), -- 8484B7
133 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
134 => (0=>"11011100", 1=>"10110111", 2=>"10010100"), -- DCB794
136 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
137 => (0=>"11011100", 1=>"00000011", 2=>"00000011"), -- DC0303
138 => (0=>"10010100", 1=>"11111111", 2=>"10010100"), -- 94FF94
139 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
140 => (0=>"00000011", 1=>"11011100", 2=>"00000011"), -- 03DC03
141 => (0=>"11110000", 1=>"10010100", 2=>"10010100"), -- F09494
142 => (0=>"10110111", 1=>"10000100", 2=>"00000011"), -- B78403
143 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
144 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
145 => (0=>"11011100", 1=>"00000011", 2=>"00000011"), -- DC0303
146 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
148 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
149 => (0=>"11110000", 1=>"10010100", 2=>"10010100"), -- F09494
150 => (0=>"11011100", 1=>"11011100", 2=>"11011100"), -- DCDCDC
151 => (0=>"11111111", 1=>"11001100", 2=>"10100110"), -- FFCCA6
152 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
153 => (0=>"11011100", 1=>"10000100", 2=>"00000011"), -- DC8403
154 => (0=>"11111111", 1=>"11011100", 2=>"10110111"), -- FFDCB7
155 => (0=>"11110000", 1=>"11110000", 2=>"00000011"), -- F0F003
156 => (0=>"10100110", 1=>"11110000", 2=>"10100110"), -- A6F0A6
157 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
158 => (0=>"10110111", 1=>"11111111", 2=>"10110111"), -- B7FFB7
159 => (0=>"11110000", 1=>"11110000", 2=>"11110000"), -- F0F0F0
160 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
161 => (0=>"11011100", 1=>"10000100", 2=>"00000011"), -- DC8403
162 => (0=>"10000100", 1=>"11001100", 2=>"10000100"), -- 84CC84
163 => (0=>"11001100", 1=>"01110000", 2=>"00000011"), -- CC7003
164 => (0=>"10100110", 1=>"11110000", 2=>"10100110"), -- A6F0A6
165 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
166 => (0=>"10110111", 1=>"11111111", 2=>"10110111"), -- B7FFB7
167 => (0=>"11110000", 1=>"11110000", 2=>"11110000"), -- F0F0F0
168 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
169 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
170 => (0=>"01110000", 1=>"01110000", 2=>"01110000"), -- 707070
171 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
172 => (0=>"00000011", 1=>"00000011", 2=>"11110000"), -- 0303F0
174 => (0=>"11001100", 1=>"10010100", 2=>"11001100"), -- CC94CC
176 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
177 => (0=>"10100110", 1=>"10010100", 2=>"01110000"), -- A69470
178 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
179 => (0=>"11011100", 1=>"11001100", 2=>"10010100"), -- DCCC94
180 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
182 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
183 => (0=>"11110000", 1=>"11011100", 2=>"10100110"), -- F0DCA6
184 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
185 => (0=>"11011100", 1=>"10110111", 2=>"11001100"), -- DCB7CC
186 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
188 => (0=>"10010100", 1=>"10010100", 2=>"10010100"), -- 949494
189 => (0=>"11111111", 1=>"11011100", 2=>"11011100"), -- FFDCDC
190 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
191 => (0=>"11110000", 1=>"11011100", 2=>"10100110"), -- F0DCA6
192 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
193 => (0=>"11111111", 1=>"00000011", 2=>"00000011"), -- FF0303
194 => (0=>"11011100", 1=>"11011100", 2=>"11011100"), -- DCDCDC
195 => (0=>"11111111", 1=>"11111111", 2=>"00000011"), -- FFFF03
196 => (0=>"10110111", 1=>"10100110", 2=>"10000100"), -- B7A684
198 => (0=>"11011100", 1=>"10110111", 2=>"10010100"), -- DCB794
199 => (0=>"11110000", 1=>"11110000", 2=>"11110000"), -- F0F0F0
200 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
201 => (0=>"11111111", 1=>"10000100", 2=>"10000100"), -- FF8484
202 => (0=>"11001100", 1=>"10110111", 2=>"10000100"), -- CCB784
203 => (0=>"11111111", 1=>"11111111", 2=>"10010100"), -- FFFF94
204 => (0=>"10110111", 1=>"01110000", 2=>"10000100"), -- B77084
205 => (0=>"11110000", 1=>"10110111", 2=>"10010100"), -- F0B794
206 => (0=>"11110000", 1=>"11011100", 2=>"10110111"), -- F0DCB7
207 => (0=>"11011100", 1=>"11011100", 2=>"11011100"), -- DCDCDC
208 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
209 => (0=>"11111111", 1=>"10000100", 2=>"10000100"), -- FF8484
210 => (0=>"10100110", 1=>"10100110", 2=>"10100110"), -- A6A6A6
211 => (0=>"11111111", 1=>"11111111", 2=>"10010100"), -- FFFF94
212 => (0=>"10110111", 1=>"01110000", 2=>"10000100"), -- B77084
213 => (0=>"11110000", 1=>"10110111", 2=>"10010100"), -- F0B794
214 => (0=>"10110111", 1=>"10110111", 2=>"10110111"), -- B7B7B7
215 => (0=>"11011100", 1=>"11011100", 2=>"11011100"), -- DCDCDC
216 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
217 => (0=>"11111111", 1=>"00000011", 2=>"10010100"), -- FF0394
218 => (0=>"11011100", 1=>"11001100", 2=>"10010100"), -- DCCC94
219 => (0=>"11110000", 1=>"11011100", 2=>"10110111"), -- F0DCB7
220 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
221 => (0=>"11111111", 1=>"10010100", 2=>"00000011"), -- FF9403
222 => (0=>"10100110", 1=>"01110000", 2=>"10000100"), -- A67084
224 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
225 => (0=>"11111111", 1=>"00000011", 2=>"10010100"), -- FF0394
226 => (0=>"11011100", 1=>"11001100", 2=>"10010100"), -- DCCC94
227 => (0=>"11110000", 1=>"11011100", 2=>"10110111"), -- F0DCB7
228 => (0=>"11011100", 1=>"00000011", 2=>"00000011"), -- DC0303
229 => (0=>"11111111", 1=>"10010100", 2=>"00000011"), -- FF9403
230 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
232 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
234 => (0=>"11001100", 1=>"11001100", 2=>"00000011"), -- CCCC03
235 => (0=>"11011100", 1=>"11111111", 2=>"00000011"), -- DCFF03
236 => (0=>"11001100", 1=>"11001100", 2=>"11001100"), -- CCCCCC
240 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
248 => (0=>"00000011", 1=>"00000011", 2=>"00000011"), -- 030303
others => (others => (others => '1'))
);
-- table of sprite heights
type prom_a is array (natural range <>) of integer range 0 to 3;
constant sprite_prom : prom_a(0 to 31) :=
(
0 => 0,
1 => 0,
8 => 0,
9 => 0,
12 => 2,
13 => 2,
14 => 2,
15 => 2,
16 => 0,
23 => 0,
24 => 0,
27 => 0,
others => 1
);
end package platform_variant_pkg;

4
Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.qip Normal file
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@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]

461
Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.vhd Normal file
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@@ -0,0 +1,461 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_mist.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_mist IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll_mist;
ARCHITECTURE SYN OF pll_mist IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 44,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 11,
clk1_phase_shift => "0",
clk2_divide_by => 27,
clk2_duty_cycle => 50,
clk2_multiply_by => 88,
clk2_phase_shift => "0",
clk3_divide_by => 9000,
clk3_duty_cycle => 50,
clk3_multiply_by => 299,
clk3_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "44.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "88.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.897000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "44"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "88"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "44.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "88.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89700000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "44"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "88"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9000"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "299"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

37
Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/Roms.txt Normal file
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@@ -0,0 +1,37 @@
ROM_START( ldrun )
ROM_REGION( 0x10000, "maincpu", 0 )
ROM_LOAD( "lr-a-4e", 0x0000, 0x2000, CRC(5d7e2a4d) SHA1(fe8aeff360f6c3a8606d67a8b95148c3c2ef7267) )
ROM_LOAD( "lr-a-4d", 0x2000, 0x2000, CRC(96f20473) SHA1(e400c43f3f32e12f68ca204c60bcebdb2b3da55d) )
ROM_LOAD( "lr-a-4b", 0x4000, 0x2000, CRC(b041c4a9) SHA1(77768b03ea2497e25c3e47b68a0eb2fe3e9aea35) )
ROM_LOAD( "lr-a-4a", 0x6000, 0x2000, CRC(645e42aa) SHA1(c806ffce7ece418bad86854c987f78c70c13e492) )
ROM_REGION( 0x10000, "irem_audio:iremsound", 0 ) /* 64k for the audio CPU (6803) */
ROM_LOAD( "lr-a-3f", 0xc000, 0x2000, CRC(7a96accd) SHA1(e94815dbfaabbb562df8f3298060aa6bd7825904) )
ROM_LOAD( "lr-a-3h", 0xe000, 0x2000, CRC(3f7f3939) SHA1(7ee25a21e74995bfb36ac11b45d384b33a6d8515) )
ROM_REGION( 0x6000, "gfx1", 0 )
ROM_LOAD( "lr-e-2d", 0x0000, 0x2000, CRC(24f9b58d) SHA1(e33224b910d37aaa85713b954c8dd50996245a8c) ) /* characters */
ROM_LOAD( "lr-e-2j", 0x2000, 0x2000, CRC(43175e08) SHA1(9dbafb27d46cf7df35f343a8753e8d91ea706993) )
ROM_LOAD( "lr-e-2f", 0x4000, 0x2000, CRC(e0317124) SHA1(b766bd21e2da1673d2054148f62d61c33c95d38e) )
ROM_REGION( 0x6000, "gfx2", 0 )
ROM_LOAD( "lr-b-4k", 0x0000, 0x2000, CRC(8141403e) SHA1(65fa6bc872fb07c71aacbbcc35cee766b2877896) ) /* sprites */
ROM_LOAD( "lr-b-3n", 0x2000, 0x2000, CRC(55154154) SHA1(35304676e1ab55adccdabdc766a4e0e0901d3cd0) )
ROM_LOAD( "lr-b-4c", 0x4000, 0x2000, CRC(924e34d0) SHA1(6a841419797a129235fc7d0405a5be55e8d703da) )
ROM_REGION( 0x20, "spr_height_prom", 0 )
ROM_LOAD( "lr-b-5p", 0x00, 0x20, CRC(e01f69e2) SHA1(0d00ef348025ea4a9c274a7e3dbb006217d8449d) ) /* sprite height, one entry per 32 */
ROM_REGION( 0x300, "spr_color_proms", 0 )
ROM_LOAD( "lr-b-1m", 0x0000, 0x0100, CRC(4bae1c25) SHA1(17a9e2567d9d648dca69510bb201f8af0738b068) ) /* sprite palette red component */
ROM_LOAD( "lr-b-1n", 0x0100, 0x0100, CRC(9cd3db94) SHA1(bff95965f946df0e4af1f99db5b2468bf1d4403f) ) /* sprite palette green component */
ROM_LOAD( "lr-b-1l", 0x0200, 0x0100, CRC(08d8cf9a) SHA1(a46213e0dc04e44b0544401eb341fd49eef331dd) ) /* sprite palette blue component */
ROM_REGION( 0x300, "chr_color_proms", 0 )
ROM_LOAD( "lr-e-3m", 0x0000, 0x0100, CRC(53040416) SHA1(2c6915164d1c31afc60a21b557abdf023d5b3f46) ) /* character palette red component */
ROM_LOAD( "lr-e-3l", 0x0100, 0x0100, CRC(67786037) SHA1(cd40dfd94295afe57139733752643cf48b8566b1) ) /* character palette green component */
ROM_LOAD( "lr-e-3n", 0x0200, 0x0100, CRC(5b716837) SHA1(e3ea250891fec43a97e92ac1c3a4fbb5ee2d4a4d) ) /* character palette blue component */
ROM_REGION( 0x100, "timing", 0 )
ROM_LOAD( "lr-b-6f", 0x000, 0x100, CRC(34d88d3c) SHA1(727f4c5cfff33538886fa0a29fd119aa085d7008) ) /* video timing - common to the other games */
ROM_END

513
Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3e-.bin.hex Normal file
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copy /b a-4e-c.bin + a-4d-c.bin prog.bin
make_vhdl_prom.exe prog.bin prog.vhd
copy /b a-3e-.bin + a-3f-.bin + a-3h-.bin snd.bin
make_vhdl_prom.exe snd.bin snd_prg.vhd
copy /b prog.bin + snd.bin KUNGFUM.ROM
copy /b b-4k-.bin + b-4f-.bin + b-4l-.bin + b-4h-.bin spr1.bin
copy /b b-3n-.bin + b-4n-.bin + b-4m-.bin + b-3m-.bin spr2.bin
copy /b b-4c-.bin + b-4e-.bin + b-4d-.bin + b-4a-.bin spr3.bin
pause

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