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Interton VC4000_MiST

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Marcel
2022-07-02 08:48:11 +02:00
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15
Console_MiST/Interton VC4000_MiST/Readme.md Normal file
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# Interton VC4000 game console
## General description
This core implements a game console with Signetics 2650 CPU and 2636 Video controller.
This chipset was used in many game consoles such as :
- Interton VC4000
- Acetronic MPU-1000
- Occitane OC2000
The Interton console had the largest game library.

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Console_MiST/Interton VC4000_MiST/VC4000_MiST.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 17:44:51 March 04, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "17:44:51 March 04, 2019"
# Revisions
PROJECT_REVISION = "VC4000_MiST"

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Console_MiST/Interton VC4000_MiST/VC4000_MiST.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:36:26 March 08, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Galaga_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_46 -to UART_TX
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name TOP_LEVEL_ENTITY vc4000_mist
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# -------------------------
# start ENTITY(galaga_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(galaga_mist)
# -----------------------
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE rtl/vc4000_mist.sv
set_global_assignment -name VHDL_FILE rtl/vc4000_core.vhd
set_global_assignment -name VHDL_FILE rtl/sgs2650_pack.vhd
set_global_assignment -name VHDL_FILE rtl/sgs2650.vhd
set_global_assignment -name VHDL_FILE rtl/sgs2636.vhd
set_global_assignment -name VHDL_FILE rtl/base_pack.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Console_MiST/Interton VC4000_MiST/VC4000_MiST.sdc Normal file
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#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
#
#************************************************************
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}]
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1

15
Console_MiST/Interton VC4000_MiST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

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Console_MiST/Interton VC4000_MiST/rtl/base_pack.vhd Normal file
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--------------------------------------------------------------------------------
-- BASE
-- Definitions
--------------------------------------------------------------------------------
-- DO 3/2009
--------------------------------------------------------------------------------
-- Base
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE base_pack IS
--------------------------------------
SUBTYPE uv IS unsigned;
SUBTYPE sv IS signed;
SUBTYPE uv1_0 IS unsigned(1 DOWNTO 0);
SUBTYPE uv0_1 IS unsigned(0 TO 1);
SUBTYPE uv3_0 IS unsigned(3 DOWNTO 0);
SUBTYPE uv0_3 IS unsigned(0 TO 3);
SUBTYPE uv7_0 IS unsigned(7 DOWNTO 0);
SUBTYPE uv0_7 IS unsigned(0 TO 7);
SUBTYPE uv2 IS unsigned(1 DOWNTO 0);
SUBTYPE uv3 IS unsigned(2 DOWNTO 0);
SUBTYPE uv4 IS unsigned(3 DOWNTO 0);
SUBTYPE uv5 IS unsigned(4 DOWNTO 0);
SUBTYPE uv6 IS unsigned(5 DOWNTO 0);
SUBTYPE uv7 IS unsigned(6 DOWNTO 0);
SUBTYPE uv8 IS unsigned(7 DOWNTO 0);
SUBTYPE uv9 IS unsigned(8 DOWNTO 0);
SUBTYPE uv10 IS unsigned(9 DOWNTO 0);
SUBTYPE uv11 IS unsigned(10 DOWNTO 0);
SUBTYPE uv12 IS unsigned(11 DOWNTO 0);
SUBTYPE uv13 IS unsigned(12 DOWNTO 0);
SUBTYPE uv14 IS unsigned(13 DOWNTO 0);
SUBTYPE uv15 IS unsigned(14 DOWNTO 0);
SUBTYPE uv16 IS unsigned(15 DOWNTO 0);
SUBTYPE uv17 IS unsigned(16 DOWNTO 0);
SUBTYPE uv18 IS unsigned(17 DOWNTO 0);
SUBTYPE uv19 IS unsigned(18 DOWNTO 0);
SUBTYPE uv20 IS unsigned(19 DOWNTO 0);
SUBTYPE uv21 IS unsigned(20 DOWNTO 0);
SUBTYPE uv22 IS unsigned(21 DOWNTO 0);
SUBTYPE uv23 IS unsigned(22 DOWNTO 0);
SUBTYPE uv24 IS unsigned(23 DOWNTO 0);
SUBTYPE uv25 IS unsigned(24 DOWNTO 0);
SUBTYPE uv26 IS unsigned(25 DOWNTO 0);
SUBTYPE uv27 IS unsigned(26 DOWNTO 0);
SUBTYPE uv28 IS unsigned(27 DOWNTO 0);
SUBTYPE uv29 IS unsigned(28 DOWNTO 0);
SUBTYPE uv30 IS unsigned(29 DOWNTO 0);
SUBTYPE uv31 IS unsigned(30 DOWNTO 0);
SUBTYPE uv32 IS unsigned(31 DOWNTO 0);
SUBTYPE uv64 IS unsigned(63 DOWNTO 0);
SUBTYPE uv128 IS unsigned(127 DOWNTO 0);
SUBTYPE sv2 IS signed(1 DOWNTO 0);
SUBTYPE sv4 IS signed(3 DOWNTO 0);
SUBTYPE sv8 IS signed(7 DOWNTO 0);
SUBTYPE sv16 IS signed(15 DOWNTO 0);
SUBTYPE sv32 IS signed(31 DOWNTO 0);
SUBTYPE sv64 IS signed(63 DOWNTO 0);
SUBTYPE sv128 IS signed(127 DOWNTO 0);
TYPE arr_uv0_3 IS ARRAY(natural RANGE <>) OF uv0_3;
TYPE arr_uv0_7 IS ARRAY(natural RANGE <>) OF uv0_7;
TYPE arr_uv4 IS ARRAY(natural RANGE <>) OF uv4;
TYPE arr_uv8 IS ARRAY(natural RANGE <>) OF uv8;
TYPE arr_uv16 IS ARRAY(natural RANGE <>) OF uv16;
TYPE arr_uv32 IS ARRAY(natural RANGE <>) OF uv32;
TYPE arr_uv64 IS ARRAY(natural RANGE <>) OF uv64;
SUBTYPE uint1 IS natural RANGE 0 TO 1;
SUBTYPE uint2 IS natural RANGE 0 TO 3;
SUBTYPE uint3 IS natural RANGE 0 TO 7;
SUBTYPE uint4 IS natural RANGE 0 TO 15;
SUBTYPE uint5 IS natural RANGE 0 TO 31;
SUBTYPE uint6 IS natural RANGE 0 TO 63;
SUBTYPE uint7 IS natural RANGE 0 TO 127;
SUBTYPE uint8 IS natural RANGE 0 TO 255;
SUBTYPE uint9 IS natural RANGE 0 TO 511;
SUBTYPE uint10 IS natural RANGE 0 TO 1023;
SUBTYPE uint11 IS natural RANGE 0 TO 2047;
SUBTYPE uint12 IS natural RANGE 0 TO 4095;
SUBTYPE uint13 IS natural RANGE 0 TO 8191;
SUBTYPE uint14 IS natural RANGE 0 TO 16383;
SUBTYPE uint15 IS natural RANGE 0 TO 32767;
SUBTYPE uint16 IS natural RANGE 0 TO 65535;
SUBTYPE uint24 IS natural RANGE 0 TO 16777215;
SUBTYPE int2 IS integer RANGE -2 TO 1;
SUBTYPE int3 IS integer RANGE -4 TO 3;
SUBTYPE int4 IS integer RANGE -8 TO 7;
SUBTYPE int5 IS integer RANGE -16 TO 15;
SUBTYPE int6 IS integer RANGE -32 TO 31;
SUBTYPE int7 IS integer RANGE -64 TO 63;
SUBTYPE int8 IS integer RANGE -128 TO 127;
SUBTYPE int9 IS integer RANGE -256 TO 255;
SUBTYPE int10 IS integer RANGE -512 TO 511;
SUBTYPE int11 IS integer RANGE -1024 TO 1023;
SUBTYPE int12 IS integer RANGE -2048 TO 2047;
SUBTYPE int13 IS integer RANGE -4096 TO 4095;
SUBTYPE int14 IS integer RANGE -8192 TO 8191;
SUBTYPE int15 IS integer RANGE -16384 TO 16383;
SUBTYPE int16 IS integer RANGE -32768 TO 32767;
SUBTYPE int17 IS integer RANGE -65536 TO 65535;
-------------------------------------------------------------
FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic;
FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic;
FUNCTION vv (CONSTANT s : std_logic;
CONSTANT N : natural) RETURN unsigned;
--------------------------------------
FUNCTION to_std_logic (a : boolean) RETURN std_logic;
--------------------------------------
FUNCTION mux (
s : std_logic;
a : unsigned;
b : unsigned) RETURN unsigned;
--------------------------------------
FUNCTION mux (
s : boolean;
a : unsigned;
b : unsigned) RETURN unsigned;
--------------------------------------
FUNCTION mux (
s : std_logic;
a : std_logic;
b : std_logic) RETURN std_logic;
--------------------------------------
FUNCTION mux (
s : boolean;
a : std_logic;
b : std_logic) RETURN std_logic;
--------------------------------------
FUNCTION mux (
s : boolean;
a : boolean;
b : boolean) RETURN boolean;
--------------------------------------
FUNCTION mux (
s : boolean;
a : integer;
b : integer) RETURN integer;
--------------------------------------
FUNCTION mux (
s : std_logic;
a : character;
b : character) RETURN character;
--------------------------------------
FUNCTION mux (
s : boolean;
a : character;
b : character) RETURN character;
--------------------------------------
FUNCTION sext (
e : unsigned;
l : natural) RETURN unsigned;
--------------------------------------
FUNCTION sext (
e : std_logic;
l : natural) RETURN unsigned;
--------------------------------------
FUNCTION uext (
e : unsigned;
l : natural) RETURN unsigned;
--------------------------------------
FUNCTION uext (
e : std_logic;
l : natural) RETURN unsigned;
--------------------------------------
PROCEDURE wure (
SIGNAL clk : IN std_logic;
CONSTANT n : IN natural:=1);
--------------------------------------
PROCEDURE wufe (
SIGNAL clk : IN std_logic;
CONSTANT n : IN natural:=1);
--------------------------------------
FUNCTION To_HString (v : unsigned) RETURN string;
FUNCTION To_String (v : unsigned) RETURN string;
--------------------------------------
FUNCTION To_Upper (c : character) RETURN character;
FUNCTION To_Upper (s : string) RETURN string;
FUNCTION To_String (i : natural; b : integer) RETURN string;
FUNCTION To_Natural (s : string; b : integer) RETURN natural;
FUNCTION ilog2 (CONSTANT v : natural) RETURN natural;
END PACKAGE base_pack;
--------------------------------------------------------------------------------
PACKAGE BODY base_pack IS
-------------------------------------------------------------
FUNCTION vv (CONSTANT s : std_logic;
CONSTANT N : natural) RETURN unsigned IS
VARIABLE v : unsigned(N-1 DOWNTO 0);
BEGIN
v:=(OTHERS => s);
RETURN v;
END FUNCTION vv;
-------------------------------------------------------------
-- Vector OR (reduce)
FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic IS
VARIABLE r : std_logic := '0';
VARIABLE Z : unsigned(v'range) := (OTHERS =>'0');
BEGIN
--pragma synthesis_off
IF 1=1 THEN
FOR I IN v'range LOOP
r:=r OR v(I);
END LOOP;
RETURN r;
ELSE
--pragma synthesis_on
IF v/=Z THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
--pragma synthesis_off
END IF;
--pragma synthesis_on
END FUNCTION v_or;
-------------------------------------------------------------
-- Vector AND (reduce)
FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic IS
VARIABLE r : std_logic := '1';
VARIABLE U : unsigned(v'range) := (OTHERS =>'1');
BEGIN
--pragma synthesis_off
IF 1=1 THEN
FOR I IN v'range LOOP
r:=r AND v(I);
END LOOP;
RETURN r;
ELSE
--pragma synthesis_on
IF v/=U THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
--pragma synthesis_off
END IF;
--pragma synthesis_on
END FUNCTION v_and;
--------------------------------------
FUNCTION to_std_logic (a : boolean) RETURN std_logic IS
BEGIN
IF a THEN RETURN '1';
ELSE RETURN '0';
END IF;
END FUNCTION to_std_logic;
--------------------------------------
-- Sélection/Multiplexage s=1:a, s=0:b
FUNCTION mux (
s : std_logic;
a : unsigned;
b : unsigned) RETURN unsigned IS
VARIABLE x : unsigned(a'range) :=(OTHERS => 'X');
BEGIN
ASSERT a'length=b'length
REPORT "mux(): Different lengths" SEVERITY failure;
IF s='1' THEN
RETURN a;
ELSIF s='0' THEN
RETURN b;
ELSE
RETURN x;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : boolean;
a : unsigned;
b : unsigned) RETURN unsigned IS
BEGIN
ASSERT a'length=b'length
REPORT "mux(): Different lengths" SEVERITY failure;
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=1:a, s=0:b
FUNCTION mux (
s : std_logic;
a : std_logic;
b : std_logic)
RETURN std_logic IS
BEGIN
RETURN (S AND A) OR (NOT S AND B);
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : boolean;
a : std_logic;
b : std_logic)
RETURN std_logic IS
BEGIN
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : boolean;
a : boolean;
b : boolean)
RETURN boolean IS
BEGIN
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=1:a, s=0:b
FUNCTION mux (
s : boolean;
a : integer;
b : integer)
RETURN integer IS
BEGIN
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : std_logic;
a : character;
b : character)
RETURN character IS
BEGIN
IF s='1' THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : boolean;
a : character;
b : character)
RETURN character IS
BEGIN
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Étend un vecteur avec extension de signe
FUNCTION sext (
e : unsigned;
l : natural) RETURN unsigned IS
VARIABLE t : unsigned(l-1 DOWNTO 0);
BEGIN
-- <AFAIRE> Vérifier numeric_std.resize ...
t:=(OTHERS => e(e'left));
t(e'length-1 DOWNTO 0):=e;
RETURN t;
END FUNCTION sext;
--------------------------------------
-- Étend un vecteur avec extension de signe
FUNCTION sext (
e : std_logic;
l : natural) RETURN unsigned IS
VARIABLE t : unsigned(l-1 DOWNTO 0);
BEGIN
-- <AFAIRE> Vérifier numeric_std.resize ...
t:=(OTHERS => e);
RETURN t;
END FUNCTION sext;
--------------------------------------
-- Étend un vecteur sans extension de signe
FUNCTION uext (
e : unsigned;
l : natural) RETURN unsigned IS
VARIABLE t : unsigned(l-1 DOWNTO 0);
BEGIN
-- <AFAIRE> Vérifier numeric_std.resize ...
t:=(OTHERS => '0');
t(e'length-1 DOWNTO 0):=e;
RETURN t;
END FUNCTION uext;
--------------------------------------
-- Étend un vecteur sans extension de signe
FUNCTION uext (
e : std_logic;
l : natural) RETURN unsigned IS
VARIABLE t : unsigned(l-1 DOWNTO 0);
BEGIN
-- <AFAIRE> Vérifier numeric_std.resize ...
t:=(OTHERS => '0');
t(0):=e;
RETURN t;
END FUNCTION uext;
--------------------------------------
-- Wait Until Rising Edge
PROCEDURE wure(
SIGNAL clk : IN std_logic;
CONSTANT n : IN natural:=1) IS
BEGIN
FOR i IN 1 TO n LOOP
WAIT UNTIL rising_edge(clk);
END LOOP;
END PROCEDURE wure;
--------------------------------------
-- Wait Until Rising Edge
PROCEDURE wufe(
SIGNAL clk : IN std_logic;
CONSTANT n : IN natural:=1) IS
BEGIN
FOR i IN 1 TO n LOOP
WAIT UNTIL falling_edge(clk);
END LOOP;
END PROCEDURE wufe;
--------------------------------------
CONSTANT HexString : string(1 TO 16):="0123456789ABCDEF";
-- Conversion unsigned -> Chaîne hexadécimale
FUNCTION To_HString(v : unsigned) RETURN string IS
VARIABLE r : string(1 TO ((v'length)+3)/4);
VARIABLE x : unsigned(1 TO v'length);
VARIABLE i,j : integer;
BEGIN
x:=v;
i:=1;
j:=1;
r:=(OTHERS =>' ');
WHILE i<v'length LOOP
IF x(i)='X' OR x(i+1)='X' OR x(i+2)='X' OR x(i+3)='X' THEN
r(j):='X';
ELSIF x(i)='U' OR x(i+1)='U' OR x(i+2)='U' OR x(i+3)='U' THEN
r(j):='U';
ELSIF x(i)='Z' OR x(i+1)='Z' OR x(i+2)='Z' OR x(i+3)='Z' THEN
r(j):='Z';
ELSIF x(i)='H' OR x(i+1)='H' OR x(i+2)='H' OR x(i+3)='H' THEN
r(j):='H';
ELSIF x(i)='L' OR x(i+1)='L' OR x(i+2)='L' OR x(i+3)='L' THEN
r(j):='L';
ELSIF x(i)='W' OR x(i+1)='W' OR x(i+2)='W' OR x(i+3)='W' THEN
r(j):='W';
ELSE
r(j):=HexString(to_integer(unsigned(x(i TO i+3)))+1);
END IF;
i:=i+4;
j:=j+1;
END LOOP;
RETURN r;
END FUNCTION To_HString;
-- Conversion unsigned -> Chaîne binaire
FUNCTION To_String(v : unsigned) RETURN string IS
VARIABLE r : string(1 TO v'length);
VARIABLE x : unsigned(1 TO v'length);
BEGIN
x:=v;
FOR i IN 1 TO v'length LOOP
CASE x(i) IS
WHEN '0' => r(i):='0';
WHEN '1' => r(i):='1';
WHEN 'X' => r(i):='X';
WHEN 'Z' => r(i):='Z';
WHEN 'U' => r(i):='U';
WHEN 'H' => r(i):='H';
WHEN 'L' => r(i):='L';
WHEN '-' => r(i):='-';
WHEN 'W' => r(i):='W';
END CASE;
-- r(i):=std_logic'image(x(i))(1);
END LOOP;
RETURN r;
END FUNCTION To_String;
--------------------------------------
-- Conversion majuscules caractère
FUNCTION To_Upper(c : character) RETURN character IS
VARIABLE r : character;
BEGIN
CASE c IS
WHEN 'a' => r := 'A';
WHEN 'b' => r := 'B';
WHEN 'c' => r := 'C';
WHEN 'd' => r := 'D';
WHEN 'e' => r := 'E';
WHEN 'f' => r := 'F';
WHEN 'g' => r := 'G';
WHEN 'h' => r := 'H';
WHEN 'i' => r := 'I';
WHEN 'j' => r := 'J';
WHEN 'k' => r := 'K';
WHEN 'l' => r := 'L';
WHEN 'm' => r := 'M';
WHEN 'n' => r := 'N';
WHEN 'o' => r := 'O';
WHEN 'p' => r := 'P';
WHEN 'q' => r := 'Q';
WHEN 'r' => r := 'R';
WHEN 's' => r := 'S';
WHEN 't' => r := 'T';
WHEN 'u' => r := 'U';
WHEN 'v' => r := 'V';
WHEN 'w' => r := 'W';
WHEN 'x' => r := 'X';
WHEN 'y' => r := 'Y';
WHEN 'z' => r := 'Z';
WHEN OTHERS => r := c;
END CASE;
RETURN r;
END To_Upper;
--------------------------------------
-- Conversion majuscules chaîne
FUNCTION To_Upper(s: string) RETURN string IS
VARIABLE r: string (s'range);
BEGIN
FOR i IN s'range LOOP
r(i):= to_upper(s(i));
END LOOP;
RETURN r;
END To_Upper;
--------------------------------------
-- Conversion entier -> chaîne
FUNCTION To_String(i: natural; b: integer) RETURN string IS
VARIABLE r : string(1 TO 10);
VARIABLE j,k : natural;
VARIABLE t : character;
BEGIN
j:=i;
k:=10;
WHILE j>=b LOOP
r(k):=HexString(j MOD b);
j:=j/b;
k:=k-1;
END LOOP;
RETURN r(k TO 10);
END FUNCTION To_String;
--------------------------------------
-- Conversion chaîne -> entier
FUNCTION To_Natural (s : string; b : integer) RETURN natural IS
VARIABLE v,r : natural;
BEGIN
r:=0;
FOR i IN s'range LOOP
CASE s(i) IS
WHEN '0' => v:=0;
WHEN '1' => v:=1;
WHEN '2' => v:=2;
WHEN '3' => v:=3;
WHEN '4' => v:=4;
WHEN '5' => v:=5;
WHEN '6' => v:=6;
WHEN '7' => v:=7;
WHEN '8' => v:=8;
WHEN '9' => v:=9;
WHEN 'a' | 'A' => v:=10;
WHEN 'b' | 'B' => v:=11;
WHEN 'c' | 'C' => v:=12;
WHEN 'd' | 'D' => v:=13;
WHEN 'e' | 'E' => v:=14;
WHEN 'f' | 'F' => v:=15;
WHEN OTHERS =>
v:=1000;
END CASE;
ASSERT v<b REPORT "To_Natural : Chaîne invalide :" & s SEVERITY error;
r:=r*b+v;
END LOOP;
RETURN r;
END FUNCTION To_Natural;
--------------------------------------
-- Renvoie le log entier en base 2, à peu près
FUNCTION ilog2 (CONSTANT v : natural) RETURN natural IS
VARIABLE r : natural := 1;
VARIABLE n : natural := 0;
BEGIN
WHILE v>r LOOP
n:=n+1;
r:=r*2;
END LOOP;
RETURN n;
END FUNCTION ilog2;
END PACKAGE BODY base_pack;

35
Console_MiST/Interton VC4000_MiST/rtl/build_id.tcl Normal file
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@@ -0,0 +1,35 @@
# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

4
Console_MiST/Interton VC4000_MiST/rtl/pll.qip Normal file
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@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

365
Console_MiST/Interton VC4000_MiST/rtl/pll.vhd Normal file
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@@ -0,0 +1,365 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 51,
clk0_duty_cycle => 50,
clk0_multiply_by => 67,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "51"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "35.470589"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "35.46895000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "51"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "67"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

1057
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--------------------------------------------------------------------------------
--
-- SGS2650 CPU
--------------------------------------------------------------------------------
-- Package :
-- - ALU operations
-- - Instruction decode
--------------------------------------------------------------------------------
-- DO 4/2018
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- This design can be used for any purpose.
-- Please send any bug report or remark to : dev@temlib.org
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.base_pack.ALL;
PACKAGE sgs2650_pack IS
TYPE enum_fmt IS (
Z, -- 1 Register Zero, register in [1:0]
I, -- 2 Immediate, register in [1:0]
R, -- 2 Relative, register in [1:0]
A, -- 3 Absolute, non branch, register in [1:0]
B, -- 3 Absolute, branch instruction
C, -- 3 (LDPL/STPL)
E, -- 1 Misc, implicit
EI, -- 2 Immediate, no register
ER, -- 2 Relative, no register
EB); -- 3 Absolute, branch, no register
TYPE enum_ins IS (
STR, -- STR_ : Z.RA : Store
LDP, -- LDPL : C : Load program status lower from memory (2650-B)
STP, -- STPL : C : Store program status lower to memory (2650-B)
SPS, -- SPSU : E : Store program status upper
-- SPSL : E : Store program status lower
LPS, -- LPSU : E : Load program status, upper
-- LPSL : E : Load program status, lower
CPPS, -- CPSU : EI : Clear program status Upper, Masked
-- CPSL : EI : Clear program status Lower, Masked
-- PPSU : EI : Preset program status Upper, Masked
-- PPSL : EI : Preset program status Lower, Masked
TPS, -- TPSU : EI : Test Program Status Upper, Masked
-- TPSL : EI : Test Program Status Lower, Masked
ALU, -- LOD_ : ZIRA : Load
-- EOR_ : ZIRA : Exclusive Or
-- IOR_ : ZIRA : Or
-- AND_ : ZIRA : And
-- ADD_ : ZIRA : Add
-- SUB_ : ZIRA : Sub
-- COM_ : ZIRA : Compare
ROT, -- RRR : Z : Rotate Register Right
-- RRL : Z : Rotate Register Left
TMI, -- TMI : I : Test Under Mask, Immediate
DAR, -- DAR : Z : Decimal Adjust Register
BSTF, -- BST_ : RB : Branch to Sub on Condition True
-- BSF_ : RB : Branch to Sub on Condition false
HALT, -- HALT : E : Halt, enter wait state
IO , -- REDE : I : Read Extended
-- REDD : Z : Read Data
-- REDC : Z : Read Control
-- WRTC : Z : Write Control
-- WRTE : I : Write Extended
-- WRTD : Z : Write Data
BCTF, -- BCT_ : RB : Branch on Condition True
-- BCF_ : RB : Branch on Condition False
BRN, -- BRN_ : RB : Branch on Register non-zero
BIDR, -- BIR_ : RB : Branch on Incrementing Register
-- BDR_ : RB : Branch on Decrementing Register
BXA, -- BXA : EB : Branch indexed absolute, unconditional
ZBRR, -- ZBRR : ER : Zero Branch, Relative, unconditional
BSN, -- BSN_ : RB : Branch to sub on non-zero reg
BSXA, -- BSXA : EB : Branch to Sub indexed absolute unconditional
ZBSR, -- ZBSR : ER : Zero branch to sub relative unconditional
RET -- RETC : Z : Return from Subroutine, Conditional
-- RETE : Z : Return from Sub and Enable Int, Conditional
);
TYPE type_deco IS RECORD
dis : string(1 TO 7); -- TRACE : Instruction
fmt : enum_fmt; -- Instruction format (addressing mode)
ins : enum_ins; -- Instruction type
len : natural RANGE 1 TO 3; -- Instruction lenght
cycles : natural RANGE 0 TO 4; -- Instruction time
END RECORD;
TYPE arr_deco IS ARRAY (natural RANGE <>) OF type_deco;
CONSTANT opcodes:arr_deco(0 TO 255):=(
("LODZ R0", Z,ALU ,1,2), -- 00 <Invalid>
("LODZ R1", Z,ALU ,1,2), -- 01 Load, Register Zero (1 cycle -B)
("LODZ R2", Z,ALU ,1,2), -- 02 Load, Register Zero (1 cycle -B)
("LODZ R3", Z,ALU ,1,2), -- 03 Load, Register Zero (1 cycle -B)
("LODI R0", I,ALU ,2,2), -- 04 Load, Immediate
("LODI R1", I,ALU ,2,2), -- 05 Load, Immediate
("LODI R2", I,ALU ,2,2), -- 06 Load, Immediate
("LODI R3", I,ALU ,2,2), -- 07 Load, Immediate
("LODR R0", R,ALU ,2,3), -- 08 Load, Relative
("LODR R1", R,ALU ,2,3), -- 09 Load, Relative
("LODR R2", R,ALU ,2,3), -- 0A Load, Relative
("LODR R3", R,ALU ,2,3), -- 0B Load, Relative
("LODA R0", A,ALU ,3,4), -- 0C Load, Absolute
("LODA R1", A,ALU ,3,4), -- 0D Load, Absolute
("LODA R2", A,ALU ,3,4), -- 0E Load, Absolute
("LODA R3", A,ALU ,3,4), -- 0F Load, Absolute
("LDPL ", C,LDP ,3,4), -- 10 Load program status lower from mem (-B)
("STPL ", C,STP ,3,4), -- 11 Store program status lower to mem (-B)
("SPSU ", E,SPS ,1,2), -- 12 Store program status upper
("SPSL ", E,SPS ,1,2), -- 13 Store program status lower
("RETC =", Z,RET ,1,3), -- 14 Return from Subroutine, Conditional
("RETC >", Z,RET ,1,3), -- 15 Return from Subroutine, Conditional
("RETC <", Z,RET ,1,3), -- 16 Return from Subroutine, Conditional
("RETC *", Z,RET ,1,3), -- 17 Return from Subroutine, Conditional
("BCTR =", R,BCTF,2,3), -- 18 Branch on Condition True, Relative
("BCTR >", R,BCTF,2,3), -- 19 Branch on Condition True, Relative
("BCTR <", R,BCTF,2,3), -- 1A Branch on Condition True, Relative
("BCTR *", R,BCTF,2,3), -- 1B Branch on Condition True, Relative
("BCTA =", B,BCTF,3,3), -- 1C Branch on Condition True, Absolute
("BCTA >", B,BCTF,3,3), -- 1D Branch on Condition True, Absolute
("BCTA <", B,BCTF,3,3), -- 1E Branch on Condition True, Absolute
("BCTA *", B,BCTF,3,3), -- 1F Branch on Condition True, Absolute
("EORZ R0", Z,ALU ,1,2), -- 20 Exclusive Or, Register Zero (1 cycle -B)
("EORZ R1", Z,ALU ,1,2), -- 21 Exclusive Or, Register Zero (1 cycle -B)
("EORZ R2", Z,ALU ,1,2), -- 22 Exclusive Or, Register Zero (1 cycle -B)
("EORZ R3", Z,ALU ,1,2), -- 23 Exclusive Or, Register Zero (1 cycle -B)
("EORI R0", I,ALU ,2,2), -- 24 Exclusive Or, Immediate
("EORI R1", I,ALU ,2,2), -- 25 Exclusive Or, Immediate
("EORI R2", I,ALU ,2,2), -- 26 Exclusive Or, Immediate
("EORI R3", I,ALU ,2,2), -- 27 Exclusive Or, Immediate
("EORR R0", R,ALU ,2,3), -- 28 Exclusive Or, Relative
("EORR R1", R,ALU ,2,3), -- 29 Exclusive Or, Relative
("EORR R2", R,ALU ,2,3), -- 2A Exclusive Or, Relative
("EORR R3", R,ALU ,2,3), -- 2B Exclusive Or, Relative
("EORA R0", A,ALU ,3,4), -- 2C Exclusive Or, Absolute
("EORA R1", A,ALU ,3,4), -- 2D Exclusive Or, Absolute
("EORA R2", A,ALU ,3,4), -- 2E Exclusive Or, Absolute
("EORA R3", A,ALU ,3,4), -- 2F Exclusive Or, Absolute
("REDC R0", Z,IO ,1,2), -- 30 Read Control
("REDC R1", Z,IO ,1,2), -- 31 Read Control
("REDC R2", Z,IO ,1,2), -- 32 Read Control
("REDC R3", Z,IO ,1,2), -- 33 Read Control
("RETE =", Z,RET ,1,3), -- 34 Return from Sub and Enable Int, Conditional
("RETE >", Z,RET ,1,3), -- 35 Return from Sub and Enable Int, Conditional
("RETE <", Z,RET ,1,3), -- 36 Return from Sub and Enable Int, Conditional
("RETE *", Z,RET ,1,3), -- 37 Return from Sub and Enable Int, Conditional
("BSTR =", R,BSTF,2,3), -- 38 Branch to Sub on Condition True, Relative
("BSTR >", R,BSTF,2,3), -- 39 Branch to Sub on Condition True, Relative
("BSTR <", R,BSTF,2,3), -- 3A Branch to Sub on Condition True, Relative
("BSTR *", R,BSTF,2,3), -- 3B Branch to Sub on Condition True, Relative
("BSTA =", B,BSTF,3,3), -- 3C Branch to Sub on Condition True, Absolute
("BSTA >", B,BSTF,3,3), -- 3D Branch to Sub on Condition True, Absolute
("BSTA <", B,BSTF,3,3), -- 3E Branch to Sub on Condition True, Absolute
("BSTA *", B,BSTF,3,3), -- 3F Branch to Sub on Condition True, Absolute
("HALT ", E,HALT,1,2), -- 40 Halt, enter wait state
("ANDZ R1", Z,ALU ,1,2), -- 41 And, Register Zero (1 cycle -B)
("ANDZ R2", Z,ALU ,1,2), -- 42 And, Register Zero (1 cycle -B)
("ANDZ R3", Z,ALU ,1,2), -- 43 And, Register Zero (1 cycle -B)
("ANDI R0", I,ALU ,2,2), -- 44 And, Immediate
("ANDI R1", I,ALU ,2,2), -- 45 And, Immediate
("ANDI R2", I,ALU ,2,2), -- 46 And, Immediate
("ANDI R3", I,ALU ,2,2), -- 47 And, Immediate
("ANDR R0", R,ALU ,2,3), -- 48 And, Relative
("ANDR R1", R,ALU ,2,3), -- 49 And, Relative
("ANDR R2", R,ALU ,2,3), -- 4A And, Relative
("ANDR R3", R,ALU ,2,3), -- 4B And, Relative
("ANDA R0", A,ALU ,3,4), -- 4C And, Absolute
("ANDA R1", A,ALU ,3,4), -- 4D And, Absolute
("ANDA R2", A,ALU ,3,4), -- 4E And, Absolute
("ANDA R3", A,ALU ,3,4), -- 4F And, Absolute
("RRR R0", Z,ROT ,1,2), -- 50 Rotate Register Right
("RRR R1", Z,ROT ,1,2), -- 51 Rotate Register Right
("RRR R2", Z,ROT ,1,2), -- 52 Rotate Register Right
("RRR R3", Z,ROT ,1,2), -- 53 Rotate Register Right
("REDE R0", I,IO ,2,3), -- 54 Read Extended
("REDE R1", I,IO ,2,3), -- 55 Read Extended
("REDE R2", I,IO ,2,3), -- 56 Read Extended
("REDE R3", I,IO ,2,3), -- 57 Read Extended
("BRNR R0", R,BRN ,2,3), -- 58 Branch on Register non-zero, Relative
("BRNR R1", R,BRN ,2,3), -- 59 Branch on Register non-zero, Relative
("BRNR R2", R,BRN ,2,3), -- 5A Branch on Register non-zero, Relative
("BRNR R3", R,BRN ,2,3), -- 5B Branch on Register non-zero, Relative
("BRNA R0", B,BRN ,3,3), -- 5C Branch on Register non-zero, Absolute
("BRNA R1", B,BRN ,3,3), -- 5D Branch on Register non-zero, Absolute
("BRNA R2", B,BRN ,3,3), -- 5E Branch on Register non-zero, Absolute
("BRNA R3", B,BRN ,3,3), -- 5F Branch on Register non-zero, Absolute
("IORZ R0", Z,ALU ,1,2), -- 60 Or, Register Zero (1 cycle -B)
("IORZ R1", Z,ALU ,1,2), -- 61 Or, Register Zero (1 cycle -B)
("IORZ R2", Z,ALU ,1,2), -- 62 Or, Register Zero (1 cycle -B)
("IORZ R3", Z,ALU ,1,2), -- 63 Or, Register Zero (1 cycle -B)
("IORI R0", I,ALU ,2,2), -- 64 Or, Immediate
("IORI R1", I,ALU ,2,2), -- 65 Or, Immediate
("IORI R2", I,ALU ,2,2), -- 66 Or, Immediate
("IORI R3", I,ALU ,2,2), -- 67 Or, Immediate
("IORR R0", R,ALU ,2,3), -- 68 Or, Relative
("IORR R1", R,ALU ,2,3), -- 69 Or, Relative
("IORR R2", R,ALU ,2,3), -- 6A Or, Relative
("IORR R3", R,ALU ,2,3), -- 6B Or, Relative
("IORA R0", A,ALU ,3,4), -- 6C Or, Absolute
("IORA R1", A,ALU ,3,4), -- 6D Or, Absolute
("IORA R2", A,ALU ,3,4), -- 6E Or, Absolute
("IORA R3", A,ALU ,3,4), -- 6F Or, Absolute
("REDD R0", Z,IO ,1,2), -- 70 Read Data
("REDD R1", Z,IO ,1,2), -- 71 Read Data
("REDD R2", Z,IO ,1,2), -- 72 Read Data
("REDD R3", Z,IO ,1,2), -- 73 Read Data
("CPSU ",EI,CPPS,2,3), -- 74 Clear program status Upper, Masked
("CPSL ",EI,CPPS,2,3), -- 75 Clear program status Lower, Masked
("PPSU ",EI,CPPS,2,3), -- 76 Preset program status Upper, Masked
("PPSL ",EI,CPPS,2,3), -- 77 Preset program status Lower, Masked
("BSNR R0", R,BSN ,2,3), -- 78 Branch to sub on non-zero reg, Relative
("BSNR R1", R,BSN ,2,3), -- 79 Branch to sub on non-zero reg, Relative
("BSNR R2", R,BSN ,2,3), -- 7A Branch to sub on non-zero reg, Relative
("BSNR R3", R,BSN ,2,3), -- 7B Branch to sub on non-zero reg, Relative
("BSNA R0", B,BSN ,3,3), -- 7C Branch to sub on non-zero reg, Absolute
("BSNA R1", B,BSN ,3,3), -- 7D Branch to sub on non-zero reg, Absolute
("BSNA R2", B,BSN ,3,3), -- 7E Branch to sub on non-zero reg, Absolute
("BSNA R3", B,BSN ,3,3), -- 7F Branch to sub on non-zero reg, Absolute
("ADDZ R0", Z,ALU ,1,2), -- 80 Add, Register Zero (1 cycle -B)
("ADDZ R1", Z,ALU ,1,2), -- 81 Add, Register Zero (1 cycle -B)
("ADDZ R2", Z,ALU ,1,2), -- 82 Add, Register Zero (1 cycle -B)
("ADDZ R3", Z,ALU ,1,2), -- 83 Add, Register Zero (1 cycle -B)
("ADDI R0", I,ALU ,2,2), -- 84 Add, Immediate
("ADDI R1", I,ALU ,2,2), -- 85 Add, Immediate
("ADDI R2", I,ALU ,2,2), -- 86 Add, Immediate
("ADDI R3", I,ALU ,2,2), -- 87 Add, Immediate
("ADDR R0", R,ALU ,2,3), -- 88 Add, Relative
("ADDR R1", R,ALU ,2,3), -- 89 Add, Relative
("ADDR R2", R,ALU ,2,3), -- 8A Add, Relative
("ADDR R3", R,ALU ,2,3), -- 8B Add, Relative
("ADDA R0", A,ALU ,3,4), -- 8C Add, Absolute
("ADDA R1", A,ALU ,3,4), -- 8D Add, Absolute
("ADDA R2", A,ALU ,3,4), -- 8E Add, Absolute
("ADDA R3", A,ALU ,3,4), -- 8F Add, Absolute
("INVALID", E,LPS ,1,2), -- 90 <Invalid>
("INVALID", E,LPS ,1,2), -- 91 <Invalid>
("LPSU ", E,LPS ,1,2), -- 92 Load program status, upper
("LPSL ", E,LPS ,1,2), -- 93 Load program status, lower
("DAR R0", Z,DAR ,1,3), -- 94 Decimal Adjust Register
("DAR R1", Z,DAR ,1,3), -- 95 Decimal Adjust Register
("DAR R2", Z,DAR ,1,3), -- 96 Decimal Adjust Register
("DAR R3", Z,DAR ,1,3), -- 97 Decimal Adjust Register
("BCFR =", R,BCTF,2,3), -- 98 Branch on Condition False, Relative
("BCFR >", R,BCTF,2,3), -- 99 Branch on Condition False, Relative
("BCFR <", R,BCTF,2,3), -- 9A Branch on Condition False, Relative
("ZBRR ",ER,ZBRR,2,3), -- 9B Zero Branch, Relative, unconditional
("BCFA =", B,BCTF,3,3), -- 9C Branch on Condition False, Absolute
("BCFA >", B,BCTF,3,3), -- 9D Branch on Condition False, Absolute
("BCFA <", B,BCTF,3,3), -- 9E Branch on Condition False, Absolute
("BXA R3",EB,BXA ,3,3), -- 9F Branch indexed absolute, unconditional
("SUBZ R0", Z,ALU ,1,2), -- A0 Subtract, Register Zero (1 cycle -B)
("SUBZ R1", Z,ALU ,1,2), -- A1 Subtract, Register Zero (1 cycle -B)
("SUBZ R2", Z,ALU ,1,2), -- A2 Subtract, Register Zero (1 cycle -B)
("SUBZ R3", Z,ALU ,1,2), -- A3 Subtract, Register Zero (1 cycle -B)
("SUBI R0", I,ALU ,2,2), -- A4 Subtract, Immediate
("SUBI R1", I,ALU ,2,2), -- A5 Subtract, Immediate
("SUBI R2", I,ALU ,2,2), -- A6 Subtract, Immediate
("SUBI R3", I,ALU ,2,2), -- A7 Subtract, Immediate
("SUBR R0", R,ALU ,2,3), -- A8 Subtract, Relative
("SUBR R1", R,ALU ,2,3), -- A9 Subtract, Relative
("SUBR R2", R,ALU ,2,3), -- AA Subtract, Relative
("SUBR R3", R,ALU ,2,3), -- AB Subtract, Relative
("SUBA R0", A,ALU ,3,4), -- AC Subtract, Absolute
("SUBA R1", A,ALU ,3,4), -- AD Subtract, Absolute
("SUBA R2", A,ALU ,3,4), -- AE Subtract, Absolute
("SUBA R3", A,ALU ,3,4), -- AF Subtract, Absolute
("WRTC R0", Z,IO ,1,2), -- B0 Write Control
("WRTC R1", Z,IO ,1,2), -- B1 Write Control
("WRTC R2", Z,IO ,1,2), -- B2 Write Control
("WRTC R3", Z,IO ,1,2), -- B3 Write Control
("TPSU ",EI,TPS ,2,3), -- B4 Test Program Status Upper, Masked
("TPSL ",EI,TPS ,2,3), -- B5 Test Program Status Lower, Masked
("INVALID",EI,TPS ,2,3), -- B6 <Invalid>
("INVALID",EI,TPS ,2,3), -- B7 <Invalid>
("BSFR 0", R,BSTF,2,3), -- B8 Branch to Sub on Condition false, Relative
("BSFR 1", R,BSTF,2,3), -- B9 Branch to Sub on Condition false, Relative
("BSFR 2", R,BSTF,2,3), -- BA Branch to Sub on Condition false, Relative
("ZBSR ",ER,ZBSR,2,3), -- BB Zero branch to sub relative unconditional
("BSFA 0", B,BSTF,3,3), -- BC Branch to Sub on Condition false, Absolute
("BSFA 1", B,BSTF,3,3), -- BD Branch to Sub on Condition false, Absolute
("BSFA 2", B,BSTF,3,3), -- BE Branch to Sub on Condition false, Absolute
("BSXA ",EB,BSXA,3,3), -- BF Branch to Sub indexed absolute unconditional
("NOP ", Z,STR ,1,2), -- C0 No Operation
("STRZ R1", Z,STR ,1,2), -- C1 Store, Register Zero (1 cycle -B)
("STRZ R2", Z,STR ,1,2), -- C2 Store, Register Zero (1 cycle -B)
("STRZ R3", Z,STR ,1,2), -- C3 Store, Register Zero (1 cycle -B)
("INVALID", I,STR ,2,2), -- C4 <Invalid>
("INVALID", I,STR ,2,2), -- C5 <Invalid>
("INVALID", I,STR ,2,2), -- C6 <Invalid>
("INVALID", I,STR ,2,2), -- C7 <Invalid>
("STRR R0", R,STR ,2,3), -- C8 Store, Relative
("STRR R1", R,STR ,2,3), -- C9 Store, Relative
("STRR R2", R,STR ,2,3), -- CA Store, Relative
("STRR R3", R,STR ,2,3), -- CB Store, Relative
("STRA R0", A,STR ,3,4), -- CC Store, Absolute
("STRA R1", A,STR ,3,4), -- CD Store, Absolute
("STRA R2", A,STR ,3,4), -- CE Store, Absolute
("STRA R3", A,STR ,3,4), -- CF Store, Absolute
("RRL R0", Z,ROT ,1,2), -- D0 Rotate Register Left
("RRL R1", Z,ROT ,1,2), -- D1 Rotate Register Left
("RRL R2", Z,ROT ,1,2), -- D2 Rotate Register Left
("RRL R3", Z,ROT ,1,2), -- D3 Rotate Register Left
("WRTE R0", I,IO ,2,3), -- D4 Write Extended
("WRTE R1", I,IO ,2,3), -- D5 Write Extended
("WRTE R2", I,IO ,2,3), -- D6 Write Extended
("WRTE R3", I,IO ,2,3), -- D7 Write Extended
("BIRR R0", R,BIDR,2,3), -- D8 Branch on Incrementing Register, Relative
("BIRR R1", R,BIDR,2,3), -- D9 Branch on Incrementing Register, Relative
("BIRR R2", R,BIDR,2,3), -- DA Branch on Incrementing Register, Relative
("BIRR R3", R,BIDR,2,3), -- DB Branch on Incrementing Register, Relative
("BIRA R0", B,BIDR,3,3), -- DC Branch on Incrementing Register, Absolute
("BIRA R1", B,BIDR,3,3), -- DD Branch on Incrementing Register, Absolute
("BIRA R2", B,BIDR,3,3), -- DE Branch on Incrementing Register, Absolute
("BIRA R3", B,BIDR,3,3), -- DF Branch on Incrementing Register, Absolute
("COMZ R0", Z,ALU ,1,2), -- E0 Compare, Register Zero (1 cycle -B)
("COMZ R1", Z,ALU ,1,2), -- E1 Compare, Register Zero (1 cycle -B)
("COMZ R2", Z,ALU ,1,2), -- E2 Compare, Register Zero (1 cycle -B)
("COMZ R3", Z,ALU ,1,2), -- E3 Compare, Register Zero (1 cycle -B)
("COMI R0", I,ALU ,2,2), -- E4 Compare, Immediate
("COMI R1", I,ALU ,2,2), -- E5 Compare, Immediate
("COMI R2", I,ALU ,2,2), -- E6 Compare, Immediate
("COMI R3", I,ALU ,2,2), -- E7 Compare, Immediate
("COMR R0", R,ALU ,2,3), -- E8 Compare, Relative
("COMR R1", R,ALU ,2,3), -- E9 Compare, Relative
("COMR R2", R,ALU ,2,3), -- EA Compare, Relative
("COMR R3", R,ALU ,2,3), -- EB Compare, Relative
("COMA R0", A,ALU ,3,4), -- EC Compare, Absolute
("COMA R1", A,ALU ,3,4), -- ED Compare, Absolute
("COMA R2", A,ALU ,3,4), -- EE Compare, Absolute
("COMA R3", A,ALU ,3,4), -- EF Compare, Absolute
("WRTD R0", Z,IO ,1,2), -- F0 Write Data
("WRTD R1", Z,IO ,1,2), -- F1 Write Data
("WRTD R2", Z,IO ,1,2), -- F2 Write Data
("WRTD R3", Z,IO ,1,2), -- F3 Write Data
("TMI R0", I,TMI ,2,3), -- F4 Test Under Mask, Immediate
("TMI R1", I,TMI ,2,3), -- F5 Test Under Mask, Immediate
("TMI R2", I,TMI ,2,3), -- F6 Test Under Mask, Immediate
("TMI R3", I,TMI ,2,3), -- F7 Test Under Mask, Immediate
("BDRR R0", R,BIDR,2,3), -- F8 Branch on Decrementing Register, Relative
("BDRR R1", R,BIDR,2,3), -- F9 Branch on Decrementing Register, Relative
("BDRR R2", R,BIDR,2,3), -- FA Branch on Decrementing Register, Relative
("BDRR R3", R,BIDR,2,3), -- FB Branch on Decrementing Register, Relative
("BDRA R0", B,BIDR,3,3), -- FC Branch on Decrementing Register, Absolute
("BDRA R1", B,BIDR,3,3), -- FD Branch on Decrementing Register, Absolute
("BDRA R2", B,BIDR,3,3), -- FE Branch on Decrementing Register, Absolute
("BDRA R3", B,BIDR,3,3) -- FF Branch on Decrementing Register, Absolute
);
------------------------------------------------
FUNCTION sign(v : uv8) RETURN unsigned;
-- LOAD : 00 EOR : 20 AND : 40 OR : 60
-- ADD : 80 SUB : A0 STORE: C0 CMP : EO
PROCEDURE op_alu(
op : IN uv8; -- opcode
vi1 : IN uv8; -- Register
vi2 : IN uv8; -- Parameter, reg. zero
psli : IN uv8; -- Program status In
vo : OUT uv8; -- Register out
pslo : OUT uv8); -- Program Status Out
------------------------------------------------
PROCEDURE op_dar(
vi : IN uv8;
vo : OUT uv8;
psli : IN uv8;
pslo : OUT uv8);
------------------------------------------------
-- RRR = 50 RRL=D0
PROCEDURE op_rotate(
op : IN uv8;
vi : IN uv8;
vo : OUT uv8;
psli : IN uv8;
pslo : OUT uv8);
------------------------------------------------
PROCEDURE op_tmi(
vi1 : IN uv8;
vi2 : IN uv8;
psli : IN uv8;
pslo : OUT uv8);
----------------------------
END PACKAGE;
--##############################################################################
PACKAGE BODY sgs2650_pack IS
FUNCTION sign(v : uv8) RETURN unsigned IS
BEGIN
IF v=x"00" THEN
RETURN "00";
ELSIF v(7)='0' THEN
RETURN "01";
ELSE
RETURN "10";
END IF;
END FUNCTION;
-- LOAD : 00 EOR : 20 AND : 40 OR : 60
-- ADD : 80 SUB : A0 STORE: C0 CMP : EO
PROCEDURE op_alu(
op : IN uv8; -- opcode
vi1 : IN uv8; -- Register
vi2 : IN uv8; -- Parameter, reg. zero
psli : IN uv8; -- Program status In
vo : OUT uv8; -- Register out
pslo : OUT uv8) IS -- Program Status Out
VARIABLE vt : uv8; -- Temporary result
ALIAS psli_c : std_logic IS psli(0); -- Carry
ALIAS psli_com : std_logic IS psli(1); -- Compare logical / arithmetic
ALIAS psli_ovf : std_logic IS psli(2); -- Overflow
ALIAS psli_wc : std_logic IS psli(3); -- With Carry
ALIAS psli_idc : std_logic IS psli(5); -- Inter-Digit Carry
ALIAS psli_cc : uv2 IS psli(7 DOWNTO 6); -- Condition Code
ALIAS pslo_c : std_logic IS pslo(0); -- Carry
ALIAS pslo_com : std_logic IS pslo(1); -- Compare logical=1 / arithmetic=0
ALIAS pslo_ovf : std_logic IS pslo(2); -- Overflow
ALIAS pslo_wc : std_logic IS pslo(3); -- With Carry
ALIAS pslo_idc : std_logic IS pslo(5); -- Inter-Digit Carry
ALIAS pslo_cc : uv2 IS pslo(7 DOWNTO 6); -- Condition Code
BEGIN
pslo:=psli;
vt:=vi1;
vo:=vt;
CASE op(7 DOWNTO 5) IS
WHEN "000" => -- LOAD
vt:=vi2;
vo:=vt;
WHEN "001" => -- EOR
vt:=vi1 XOR vi2;
vo:=vt;
WHEN "010" => -- AND
vt:=vi1 AND vi2;
vo:=vt;
WHEN "011" => -- OR
vt:=vi1 OR vi2;
vo:=vt;
WHEN "100" => -- ADD
vt:=vi1 + vi2 + ("0000000" & (psli_c AND psli_wc));
vo:=vt;
pslo_c :=(vi1(7) AND vi2(7)) OR (NOT vt(7) AND (vi1(7) OR vi2(7)));
pslo_ovf:=(vi1(7) AND vi2(7) AND NOT vt(7)) OR
(NOT vi1(7) AND NOT vi2(7) AND vt(7));
pslo_idc:=to_std_logic(vt(3 DOWNTO 0)<vi1(3 DOWNTO 0));
WHEN "101" => -- SUB
vt:=vi1 - vi2 - ("0000000" & (NOT psli_c AND psli_wc));
vo:=vt;
pslo_c :=NOT ((NOT vi1(7) AND vi2(7)) OR (vt(7) AND (NOT vi1(7) OR vi2(7))));
pslo_ovf:=(vi1(7) AND NOT vi2(7) AND NOT vt(7)) OR
(NOT vi1(7) AND vi2(7) AND vt(7));
pslo_idc:=to_std_logic(vt(3 DOWNTO 0)<=vi1(3 DOWNTO 0));
WHEN "110" => -- STORE
vt:=vi2;
vo:=vt;
WHEN OTHERS => -- COM
vt:=vi1 - vi2;
vo:=vi1;
IF vt=x"00" THEN -- =
pslo_cc:="00";
ELSIF psli_com='1' AND -- Unsigned <
((vi1(7)='0' AND vi2(7)='1') OR
(vt(7)='1' AND NOT (vi1(7)='1' AND vi2(7)='0'))) THEN
pslo_cc:="10";
ELSIF psli_com='0' AND -- Signed <
((vi1(7)='1' AND vi2(7)='0') OR
(vi1(7)='0' AND vi2(7)='0' AND vt(7)='1') OR
(vi1(7)='1' AND vi2(7)='1' AND vt(7)='0')) THEN -- Signed <
pslo_cc:="10";
ELSE -- >
pslo_cc:="01";
END IF;
END CASE;
IF op(7 DOWNTO 5)/="111" THEN
pslo_cc:=sign(vt);
END IF;
END PROCEDURE op_alu;
------------------------------------------------
PROCEDURE op_dar(
vi : IN uv8;
vo : OUT uv8;
psli : IN uv8;
pslo : OUT uv8) IS
VARIABLE vt : uv8;
ALIAS psli_c : std_logic IS psli(0); -- Carry
ALIAS psli_com : std_logic IS psli(1); -- Compare logical / arithmetic
ALIAS psli_ovf : std_logic IS psli(2); -- Overflow
ALIAS psli_wc : std_logic IS psli(3); -- With Carry
ALIAS psli_idc : std_logic IS psli(5); -- Inter-Digit Carry
ALIAS psli_cc : uv2 IS psli(7 DOWNTO 6); -- Condition Code
ALIAS pslo_c : std_logic IS pslo(0); -- Carry
ALIAS pslo_com : std_logic IS pslo(1); -- Compare logical=1 / arithmetic=0
ALIAS pslo_ovf : std_logic IS pslo(2); -- Overflow
ALIAS pslo_wc : std_logic IS pslo(3); -- With Carry
ALIAS pslo_idc : std_logic IS pslo(5); -- Inter-Digit Carry
ALIAS pslo_cc : uv2 IS pslo(7 DOWNTO 6); -- Condition Code
BEGIN
pslo:=psli;
vt:=vi;
IF psli_c='0' THEN
vt:=vt+x"A0";
END IF;
IF psli_idc='0' THEN
vt:=vt(7 DOWNTO 4) & (vt(3 DOWNTO 0)+x"A");
END IF;
pslo_cc:=sign(vt);
vo:=vt;
END PROCEDURE op_dar;
------------------------------------------------
-- RRR = 50 RRL=D0
PROCEDURE op_rotate(
op : IN uv8;
vi : IN uv8;
vo : OUT uv8;
psli : IN uv8;
pslo : OUT uv8) IS
VARIABLE vt : uv8;
ALIAS psli_c : std_logic IS psli(0); -- Carry
ALIAS psli_wc : std_logic IS psli(3); -- With Carry
ALIAS pslo_c : std_logic IS pslo(0); -- Carry
ALIAS pslo_idc : std_logic IS pslo(5); -- Inter-Digit Carry
ALIAS pslo_cc : uv2 IS pslo(7 DOWNTO 6); -- Condition Code
BEGIN
pslo:=psli;
IF op(7)='1' THEN
IF psli_wc='1' THEN
vt:=vi(6 DOWNTO 0) & psli_c;
pslo_c:=vi(7);
pslo_idc:=vi(4);
ELSE
vt:=vi(6 DOWNTO 0) & vi(7);
END IF;
ELSE
IF psli_wc='1' THEN
vt:=psli_c & vi(7 DOWNTO 1);
pslo_c:=vi(0);
pslo_idc:=vi(6);
ELSE
vt:=vi(0) & vi(7 DOWNTO 1);
END IF;
END IF;
pslo_cc:=sign(vt);
vo:=vt;
END PROCEDURE op_rotate;
------------------------------------------------
PROCEDURE op_tmi(
vi1 : IN uv8;
vi2 : IN uv8;
psli : IN uv8;
pslo : OUT uv8) IS
BEGIN
pslo:=psli;
IF (vi1 AND vi2)=vi2 THEN
pslo(7 DOWNTO 6):="00";
ELSE
pslo(7 DOWNTO 6):="10";
END IF;
END PROCEDURE op_tmi;
------------------------------------------------
END PACKAGE BODY sgs2650_pack;

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---------------------------------------------------------------------------------
-- Games consoles with Signetics 2650 CPU and 2636 VIDEO
-- Interton VC4000 & clones
---------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
USE std.textio.ALL;
LIBRARY work;
USE work.base_pack.ALL;
ENTITY vc4000_core IS
PORT (
-- Master input clock
clk : IN std_logic;
-- Async reset from top-level module. Can be used as initial reset.
reset : IN std_logic;
-- Must be passed to hps_io module
ntsc_pal : IN std_logic;
swap : IN std_logic;
swapxy : IN std_logic;
integ : IN std_logic;
bright : IN std_logic;
-- Base video clock. Usually equals to CLK_SYS.
clk_video : OUT std_logic;
-- Multiple resolutions are supported using different CE_PIXEL rates.
-- Must be based on CLK_VIDEO
ce_pixel : OUT std_logic;
-- VGA
vga_r : OUT std_logic_vector(7 DOWNTO 0);
vga_g : OUT std_logic_vector(7 DOWNTO 0);
vga_b : OUT std_logic_vector(7 DOWNTO 0);
vga_hs : OUT std_logic; -- positive pulse!
vga_vs : OUT std_logic; -- positive pulse!
vga_de : OUT std_logic; -- = not (VBlank or HBlank)
-- AUDIO
sound : OUT std_logic_vector(7 DOWNTO 0);
ps2_key : IN std_logic_vector(10 DOWNTO 0);
joystick_0 : IN std_logic_vector(31 DOWNTO 0);
joystick_1 : IN std_logic_vector(31 DOWNTO 0);
joystick_analog_0 : IN std_logic_vector(15 DOWNTO 0);
joystick_analog_1 : IN std_logic_vector(15 DOWNTO 0);
ioctl_download : IN std_logic;
ioctl_index : IN std_logic_vector(7 DOWNTO 0);
ioctl_wr : IN std_logic;
ioctl_addr : IN std_logic_vector(24 DOWNTO 0);
ioctl_dout : IN std_logic_vector(7 DOWNTO 0);
ioctl_wait : OUT std_logic
);
END vc4000_core;
ARCHITECTURE struct OF vc4000_core IS
CONSTANT CDIV : natural := 4 * 8;
--------------------------------------
SIGNAL keypad1_1, keypad1_2, keypad1_3 : unsigned(7 DOWNTO 0);
SIGNAL keypad2_1, keypad2_2, keypad2_3 : unsigned(7 DOWNTO 0);
SIGNAL keypanel, volnoise : unsigned(7 DOWNTO 0);
--------------------------------------
SIGNAL vol : unsigned(1 DOWNTO 0);
SIGNAL icol,explo,explo2,noise,snd : std_logic;
SIGNAL sound1,sound2 : unsigned(7 DOWNTO 0);
SIGNAL lfsr : uv15;
SIGNAL nexplo : natural RANGE 0 TO 1000000;
SIGNAL divlfsr : uint8;
SIGNAL pot1,pot2 : unsigned(7 DOWNTO 0);
SIGNAL potl_a,potl_b,potr_a,potr_b : unsigned(7 DOWNTO 0);
SIGNAL potl_v,potl_h,potr_v,potr_h : unsigned(7 DOWNTO 0);
SIGNAL pot0_a,pot0_b,pot1_a,pot1_b : unsigned(7 DOWNTO 0);
SIGNAL clkcpt : natural RANGE 0 TO 256*256*4-1;
SIGNAL dpad0,dpad1 : std_logic;
SIGNAL tick_cpu_cpt : natural RANGE 0 TO CDIV-1;
SIGNAL tick_cpu : std_logic;
SIGNAL ad,ad_delay,ad_rom : unsigned(14 DOWNTO 0);
SIGNAL dr,dw,dr_pvi,dr_rom,dr_key : unsigned(7 DOWNTO 0);
SIGNAL req,req_pvi,req_mem : std_logic;
SIGNAL ack,ackp,ack_pvi,ack_mem : std_logic;
SIGNAL sel_pvi,sel_mem : std_logic;
SIGNAL ack_mem_p,ack_mem_p2 : std_logic :='0';
SIGNAL int, int_pvi,intack,creset : std_logic;
SIGNAL sense,flag : std_logic;
SIGNAL mio,ene,dc,wr : std_logic;
SIGNAL ph : unsigned(1 DOWNTO 0);
SIGNAL ivec : unsigned(7 DOWNTO 0);
SIGNAL reset_na : std_logic;
SIGNAL w_d : unsigned(7 DOWNTO 0);
SIGNAL w_a : unsigned(12 DOWNTO 0);
SIGNAL w_wr : std_logic;
TYPE arr_cart IS ARRAY(natural RANGE <>) OF unsigned(7 DOWNTO 0);
--SIGNAL cart : arr_cart(0 TO 4095);
--ATTRIBUTE ramstyle : string;
--ATTRIBUTE ramstyle OF cart : SIGNAL IS "no_rw_check";
SHARED VARIABLE cart : arr_cart(0 TO 16383) :=(OTHERS =>x"00");
ATTRIBUTE ramstyle : string;
ATTRIBUTE ramstyle OF cart : VARIABLE IS "no_rw_check";
SIGNAL wcart : std_logic;
SIGNAL vga_argb : unsigned(3 DOWNTO 0);
SIGNAL vga_dei : std_logic;
SIGNAL vga_hsyn : std_logic;
SIGNAL vga_vsyn : std_logic;
SIGNAL vga_ce : std_logic;
SIGNAL vrst : std_logic;
SIGNAL vga_r_i,vga_g_i,vga_b_i : uv8;
FILE fil : text OPEN write_mode IS "trace_mem.log";
BEGIN
----------------------------------------------------------
-- Interton VC4000 & clones
-- xx0 0aaa aaaa aaaa : Cardtrige : 2ko
-- xx0 1aaa aaaa aaaa : RAM hobby computer / Cartdridge 4ko
-- xx1 00aa aaaa aaaa : RAM option 1ko
-- xx1 x110 1aaa aaaa : Key inputs
-- xx1 x111 aaaa aaaa : Video PVI
-- PVI : Programmable Video Interface
i_sgs2636: ENTITY work.sgs2636
PORT MAP (
ad => ad,
dw => dw,
dr => dr_pvi,
req => req_pvi,
ack => ack_pvi,
wr => wr,
tick => tick_cpu,
int => int_pvi,
intack => intack,
ivec => ivec,
vrst => vrst,
vid_argb => vga_argb,
vid_de => vga_de,
vid_hsyn => vga_hsyn,
vid_vsyn => vga_vsyn,
vid_ce => vga_ce,
sound => sound1,
icol => icol,
bright => bright,
pot1 => pot1,
pot2 => pot2,
np => ntsc_pal,
reset => reset,
clk => clk,
reset_na => reset_na);
dr_key<=volnoise WHEN ad_delay(3 DOWNTO 0)=x"0" ELSE -- 1E80
keypad1_1 WHEN ad_delay(3 DOWNTO 0)=x"8" ELSE -- 1E88
keypad1_2 WHEN ad_delay(3 DOWNTO 0)=x"9" ELSE -- 1E89
keypad1_3 WHEN ad_delay(3 DOWNTO 0)=x"A" ELSE -- 1E8A
keypanel WHEN ad_delay(3 DOWNTO 0)=x"B" ELSE -- 1E8B
keypad2_1 WHEN ad_delay(3 DOWNTO 0)=x"C" ELSE -- 1E8C
keypad2_2 WHEN ad_delay(3 DOWNTO 0)=x"D" ELSE -- 1E8D
keypad2_3 WHEN ad_delay(3 DOWNTO 0)=x"E" ELSE -- 1E8E
x"00";
keypad1_1<=(joystick_0( 6) & joystick_0( 9) & joystick_0(12) & joystick_0(15)) & "0000";
keypad1_2<=(joystick_0( 7) & joystick_0(10) & joystick_0(13) & joystick_0(16)) & "0000";
keypad1_3<=(joystick_0( 8) & joystick_0(11) & joystick_0(14) & joystick_0(17)) & "0000";
keypad2_1<=(joystick_1( 6) & joystick_1( 9) & joystick_1(12) & joystick_1(15)) & "0000";
keypad2_2<=(joystick_1( 7) & joystick_1(10) & joystick_1(13) & joystick_1(16)) & "0000";
keypad2_3<=(joystick_1( 8) & joystick_1(11) & joystick_1(14) & joystick_1(17)) & "0000";
keypanel <=((joystick_0(4) & joystick_0(5)) OR
(joystick_1(4) & joystick_1(5))) & "000000";
volnoise <=vol & icol & explo & noise & snd & "00";
PROCESS(clk,reset_na) IS
VARIABLE a_v,b_v : uv8;
BEGIN
IF reset_na='0' THEN
vol<="00";
icol<='0';
explo<='0';
noise<='0';
snd<='0';
lfsr<=to_unsigned(1,15);
ELSIF rising_edge(clk) THEN
IF ad_delay(3 DOWNTO 0)=x"0" AND ad_delay(12)='1' AND
ad_delay(11 DOWNTO 8)="1110" AND wr='1' AND tick_cpu='1' THEN
vol<=dw(7 DOWNTO 6);
icol<=dw(5);
explo<=dw(4);
noise<=dw(3);
snd<=dw(2);
END IF;
explo2<=explo;
--------------------------------
IF explo='1' AND explo2='0' THEN
nexplo<=100000;
END IF;
IF tick_cpu='1' AND nexplo/=0 THEN
nexplo<=nexplo-1;
END IF;
--------------------------------
IF tick_cpu='1' THEN
divlfsr<=(divlfsr+1) MOD 64;
IF divlfsr=0 THEN
lfsr<=('0' & lfsr(14 DOWNTO 1)) XOR
(lfsr(0) & "0000000000000" & lfsr(0));
END IF;
END IF;
CASE vol IS
WHEN "00" => a_v:=mux(sound1(7),x"C0",x"3F");
WHEN "01" => a_v:=mux(sound1(7),x"E0",x"1F");
WHEN "10" => a_v:=mux(sound1(7),x"F0",x"0F");
WHEN OTHERS => a_v:=mux(sound1(7),x"F8",x"07");
END CASE;
IF snd='0' THEN
a_v:=x"00";
END IF;
b_v:=x"00";
IF noise='1' THEN
b_v:=mux(lfsr(0),x"08",x"f8");
END IF;
IF nexplo/=0 THEN
b_v:=mux(lfsr(0),x"20",x"E0");
END IF;
sound2<=a_v + b_v;
--------------------------------
END IF;
END PROCESS;
-- Layout, most games :
-- Key Layout, hobby computer :
-- LEFT RIGHT
-- - + 0 1 2 3
-- PC Ad 4 5 6 7
-- BP Rx 8 9 A b
-- R W C d E F
-- Joystick mapping :
--15 16 17 select=4
--12 13 14 start =5
-- 9 10 11
-- 6 7 8
-- flag : Joystick : 0=Horizontal 1=Vertical
pot2<=potr_v WHEN flag='1' ELSE potr_h;
pot1<=potl_v WHEN flag='1' ELSE potl_h;
----------------------------------------------------------
sense <=vrst;
Joysticks:PROCESS (clk) IS
BEGIN
IF rising_edge(clk) THEN
-------------------------------------------------------------------------------
IF dpad0='0' THEN
pot0_a<=unsigned(joystick_analog_0(15 DOWNTO 8))+x"80";
pot0_b<=unsigned(joystick_analog_0( 7 DOWNTO 0))+x"80";
ELSE
IF integ='0' THEN
pot0_a<=x"80";
pot0_b<=x"80";
IF joystick_0(0)='1' THEN pot0_b<=x"FF"; END IF;
IF joystick_0(1)='1' THEN pot0_b<=x"00"; END IF;
IF joystick_0(2)='1' THEN pot0_a<=x"FF"; END IF;
IF joystick_0(3)='1' THEN pot0_a<=x"00"; END IF;
ELSE
IF clkcpt=0 THEN
IF joystick_0(0)='1' AND pot0_b<x"FF" THEN pot0_b<=pot0_b + 1; END IF;
IF joystick_0(1)='1' AND pot0_b>x"00" THEN pot0_b<=pot0_b - 1; END IF;
IF joystick_0(2)='1' AND pot0_a<x"FF" THEN pot0_a<=pot0_a + 1; END IF;
IF joystick_0(3)='1' AND pot0_a>x"00" THEN pot0_a<=pot0_a - 1; END IF;
END IF;
END IF;
END IF;
IF joystick_0(3 DOWNTO 0)/="0000" THEN
dpad0<='1';
END IF;
IF joystick_analog_0(7 DOWNTO 5)="100" OR joystick_analog_0(7 DOWNTO 5)="011" OR
joystick_analog_0(15 DOWNTO 13)="100" OR joystick_analog_0(15 DOWNTO 13)="011" THEN
dpad0<='0';
END IF;
-------------------------------------------------------------------------------
IF dpad1='0' THEN
pot1_a<=unsigned(joystick_analog_1(15 DOWNTO 8))+x"80";
pot1_b<=unsigned(joystick_analog_1( 7 DOWNTO 0))+x"80";
ELSE
IF integ='0' THEN
pot1_a<=x"80";
pot1_b<=x"80";
IF joystick_1(0)='1' THEN pot1_b<=x"FF"; END IF;
IF joystick_1(1)='1' THEN pot1_b<=x"00"; END IF;
IF joystick_1(2)='1' THEN pot1_a<=x"FF"; END IF;
IF joystick_1(3)='1' THEN pot1_a<=x"00"; END IF;
ELSE
IF clkcpt=0 THEN
IF joystick_1(0)='1' AND pot1_b<x"FF" THEN pot1_b<=pot1_b + 1; END IF;
IF joystick_1(1)='1' AND pot1_b>x"00" THEN pot1_b<=pot1_b - 1; END IF;
IF joystick_1(2)='1' AND pot1_a<x"FF" THEN pot1_a<=pot1_a + 1; END IF;
IF joystick_1(3)='1' AND pot1_a>x"00" THEN pot1_a<=pot1_a - 1; END IF;
END IF;
END IF;
END IF;
IF joystick_1(3 DOWNTO 0)/="0000" THEN
dpad1<='1';
END IF;
IF joystick_analog_1(7 DOWNTO 5)="100" OR joystick_analog_1(7 DOWNTO 5)="011" OR
joystick_analog_1(15 DOWNTO 13)="100" OR joystick_analog_1(15 DOWNTO 13)="011" THEN
dpad1<='0';
END IF;
-------------------------------------------------------------------------------
potl_a<=mux(swap,pot1_a,pot0_a);
potl_b<=mux(swap,pot1_b,pot0_b);
potr_a<=mux(swap,pot0_a,pot1_a);
potr_b<=mux(swap,pot0_b,pot1_b);
clkcpt<=(clkcpt+1) MOD (256*256*4);
-------------------------------------------------------------------------------
IF reset_na='0' THEN
dpad0<='0';
dpad1<='0';
END IF;
END IF;
END PROCESS Joysticks;
potl_h<=mux(swapxy,potl_a,potl_b);
potl_v<=mux(swapxy,potl_b,potl_a);
potr_h<=mux(swapxy,potr_a,potr_b);
potr_v<=mux(swapxy,potr_b,potr_a);
----------------------------------------------------------
dr<=dr_pvi WHEN
ad_delay(12)='1' AND ad_delay(10 DOWNTO 8)="111" ELSE -- PVI Interton
dr_key WHEN
ad_delay(12)='1' AND ad_delay(11 DOWNTO 8)="1110" ELSE
dr_rom -- Cardridge
;
sel_pvi<=to_std_logic(ad(12)='1' AND ad(10 DOWNTO 8)="111");
sel_mem<=NOT sel_pvi;
req_pvi<=sel_pvi AND req;
req_mem<=sel_mem AND req;
ackp<=tick_cpu AND ack_pvi WHEN sel_pvi='1' ELSE
tick_cpu AND ack_mem;
PROCESS (clk) IS
BEGIN
IF rising_edge(clk) THEN
IF tick_cpu='1' THEN
ack_mem_p<=req_mem AND NOT ack_mem;
ack_mem_p2<=ack_mem_p AND req_mem;
END IF;
END IF;
END PROCESS;
ack_mem<=ack_mem_p2 AND ack_mem_p;
--ack<='0';
ack<=ackp WHEN rising_edge(clk);
ad_rom <= ad;
-- CPU
i_sgs2650: ENTITY work.sgs2650
PORT MAP (
req => req,
ack => ack,
ad => ad,
wr => wr,
dw => dw,
dr => dr,
mio => mio,
ene => ene,
dc => dc,
ph => ph,
int => int,
intack => intack,
ivec => ivec,
sense => sense,
flag => flag,
reset => creset,
clk => clk,
reset_na => reset_na);
int<=int_pvi;
ad_delay<=ad WHEN rising_edge(clk);
----------------------------------------------------------
--pragma synthesis_off
Dump:PROCESS IS
VARIABLE lout : line;
VARIABLE doread : boolean := false;
VARIABLE adr : uv15;
BEGIN
wure(clk);
IF doread THEN
write(lout,"RD(" & to_hstring('0' & adr) & ")=" & to_hstring(dr));
writeline(fil,lout);
doread:=false;
END IF;
IF req='1' AND ack='1' AND reset='0' AND reset_na='1' THEN
IF wr='1' THEN
write(lout,"WR(" & to_hstring('0' & ad) & ")=" & to_hstring(dw));
writeline(fil,lout);
ELSE
doread:=true;
adr:=ad;
END IF;
END IF;
END PROCESS Dump;
--pragma synthesis_on
----------------------------------------------------------
sound <=std_logic_vector(sound2) WHEN rising_edge(clk);
----------------------------------------------------------
-- MUX VIDEO
clk_video<=clk;
ce_pixel<=vga_ce WHEN rising_edge(clk);
vga_de<=vga_dei WHEN rising_edge(clk);
vga_hs<=vga_hsyn WHEN rising_edge(clk);
vga_vs<=vga_vsyn WHEN rising_edge(clk);
vga_argb<=vga_argb WHEN rising_edge(clk);
vga_r_i<=(7=>vga_argb(2) AND vga_argb(3),OTHERS => vga_argb(2));
vga_g_i<=(7=>vga_argb(1) AND vga_argb(3),OTHERS => vga_argb(1));
vga_b_i<=(7=>vga_argb(0) AND vga_argb(3),OTHERS => vga_argb(0));
vga_r<=std_logic_vector(vga_r_i);
vga_g<=std_logic_vector(vga_g_i);
vga_b<=std_logic_vector(vga_b_i);
----------------------------------------------------------
-- ROM / RAM
wcart<=wr AND req AND ack; -- WHEN ad(12)='0' ELSE '0';
icart:PROCESS(clk) IS
BEGIN
IF rising_edge(clk) THEN
dr_rom<=cart(to_integer(ad_rom(13 DOWNTO 0))); -- 8kB
IF wcart='1' THEN
-- RAM
cart(to_integer(ad_rom(13 DOWNTO 0))):=dw;
END IF;
END IF;
END PROCESS icart;
icart2:PROCESS(clk) IS
BEGIN
IF rising_edge(clk) THEN
-- Download
IF w_wr='1' THEN
cart(to_integer(w_a)):=w_d;
END IF;
END IF;
END PROCESS icart2;
PROCESS(clk) IS
BEGIN
IF rising_edge(clk) THEN
w_wr<=ioctl_download AND ioctl_wr;
w_d <=unsigned(ioctl_dout);
w_a <=unsigned(ioctl_addr(12 DOWNTO 0));
END IF;
END PROCESS;
ioctl_wait<='0';
----------------------------------------------------------
-- CPU CLK
DivCLK:PROCESS (clk,reset_na) IS
BEGIN
IF reset_na='0' THEN
tick_cpu<='0';
ELSIF rising_edge(clk) THEN
IF tick_cpu_cpt=CDIV - 1 THEN
tick_cpu_cpt<=0;
tick_cpu<='1';
ELSE
tick_cpu_cpt<=tick_cpu_cpt+1;
tick_cpu<='0';
END IF;
END IF;
END PROCESS DivCLK;
reset_na<=NOT reset OR NOT ioctl_download;
creset<=ioctl_download;
END struct;

179
Console_MiST/Interton VC4000_MiST/rtl/vc4000_mist.sv Normal file
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module vc4000_mist (
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"VC4000;BIN;",
"O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
"O5,Swap Joystick,Off,On;",
"O6,Swap Joystick XY,Off,On;",
"O7,D-pad,Absolute,Integration;",
"O8,Bright,Off,On;" ,
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
assign LED = ~ioctl_downl;
assign AUDIO_R = AUDIO_L;
wire clksys, pll_locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clksys),//35.46895
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [31:0] joystick_0,joystick_1;
wire [31:0] joystick_analog_0,joystick_analog_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire [7:0] audio;
wire hs, vs;
wire blankn;
wire [7:0] r, g, b;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
wire [15:0] rom_addr;
wire [15:0] rom_do;
wire [12:0] bg_addr;
wire [31:0] bg_do;
//wire rom_rd;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clksys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
vc4000_core vc4000_core(
.clk(clksys),
.reset(status[0] | buttons[1] | ~ioctl_downl),
.ntsc_pal(1'b1),
.swap(status[5]),
.swapxy(status[6]),
.integ(status[7]),
.bright(status[8]),
.vga_r(r),
.vga_g(g),
.vga_b(b),
.vga_hs(hs),
.vga_vs(vs),
.vga_de(blankn),
.sound(audio),
// .joystick_0({joystick_0[31:6], m_fireB, m_fireA, m_left, m_right, m_up, m_down}),
// .joystick_1({joystick_1[31:6], m_fire2B, m_fire2A, m_left2, m_right2, m_up2, m_down2}),
.joystick_0(joystick_0),
.joystick_1(joystick_1),
.joystick_analog_0(joystick_analog_0),
.joystick_analog_1(joystick_analog_1),
.ioctl_download(ioctl_downl),
.ioctl_index(ioctl_index),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout)//,
// .ioctl_wait(ioctl_wait)
);
mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clksys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r[7:2] : 0 ),
.G ( blankn ? g[7:2] : 0 ),
.B ( blankn ? b[7:2] : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.scandoubler_disable( scandoublerD ),
.scanlines ( status[4:3] ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clksys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.joystick_analog_0(joystick_analog_0),
.joystick_analog_1(joystick_analog_1),
.status (status )
);
dac #(.C_bits(8))dac(
.clk_i(clksys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clksys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule