mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-05-21 13:09:25 +00:00
New Core
This commit is contained in:
Marcel
|
Before Width: | Height: | Size: 975 KiB After Width: | Height: | Size: 975 KiB |
BIN
Arcade_MiST/Crazy Climbe Hardware/River Patrol.jpg
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BIN
Arcade_MiST/Crazy Climbe Hardware/River Patrol.jpg
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Binary file not shown.
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After Width: | Height: | Size: 116 KiB |
159
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/README.txt
Normal file
159
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/README.txt
Normal file
@@ -0,0 +1,159 @@
|
||||
|
||||
River Patrol Port to Mist FPGA by Gehstock
|
||||
|
||||
|
||||
SPACE / FIRE = Accelerate
|
||||
ARROW KEYS / JOYSTICK = CONTROL
|
||||
|
||||
|
||||
-------------------------------------------------
|
||||
Crazy climber FPGA by Dar - (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-------------------------------------------------
|
||||
-- Crazy climber releases
|
||||
--
|
||||
-- Release 0.0 - 03/06/2018 - Dar
|
||||
-------------------------------------------------
|
||||
Educational use only
|
||||
Do not redistribute synthetized file with roms
|
||||
Do not redistribute roms whatever the form
|
||||
Use at your own risk
|
||||
|
||||
--------------------------------------------------------------------
|
||||
make sure to use cclimber.zip roms
|
||||
--------------------------------------------------------------------
|
||||
See my previous ckong release (2014) for som more explanation
|
||||
--------------------------------------------------------------------
|
||||
The original arcade hardware PCB contains 10 memory regions
|
||||
|
||||
cpu addressable space
|
||||
|
||||
- program rom 20Kx8, cpu only access
|
||||
- working ram ram 1Kx8, cpu only access
|
||||
- color/sprite-data ram 1Kx8, cpu + (2 access / 8 pixels)
|
||||
- background buffer ram 1Kx8, cpu + (1 access / 8 pixels)
|
||||
- big sprite buffer ram 256x8 cpu + (1 access / 8 pixels)
|
||||
|
||||
non cpu addressable region
|
||||
|
||||
- background/sprite graphics rom 4Kx16, (1 access / 8 pixels)
|
||||
- big sprite graphics rom 2Kx16, (1 access / 8 pixels)
|
||||
- background/sprite color palette rom 64x8 , (1 access / pixels)
|
||||
- big sprite color palette rom 32x8 , (1 access / pixels)
|
||||
- sound samples rom 8Kx8 , low rate
|
||||
|
||||
The pixel clock is 6MHz, the cpu clock is 3MHz.
|
||||
|
||||
Video display is 256 pixels x 240 lines.
|
||||
Each lines contains 8 sprites and 32 background tiles.
|
||||
Each frames contains 28 background tiles height.
|
||||
|
||||
Each tile is 8x8 pixels
|
||||
Each sprite is 16x16 pixels
|
||||
|
||||
Big sprite is a 8x8 tile graphic
|
||||
|
||||
Sound is composed of AY-3-8910 music and sound samples.
|
||||
--------------------------------------------------------------------
|
||||
|
||||
---------------
|
||||
VHDL File list
|
||||
---------------
|
||||
|
||||
crazy_climber_de10_lite.vhd Top level for de10-lite board
|
||||
|
||||
max10_pll_12M.vhd Pll 12MHz from 50MHz altera mf
|
||||
|
||||
crazy_climber.vhd Main logic
|
||||
|
||||
video_gen.vhd Video scheduler, syncs (h,v and composite)
|
||||
line_doubler.vhd Line doubler 15kHz -> 31kHz
|
||||
|
||||
crazy_climber_sound.vhd Music and samples logic
|
||||
|
||||
kbd_joystick.vhd Keyboard key to player/coin input
|
||||
|
||||
rtl_T80/T80s.vhd T80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
rtl_T80/T80_Reg.vhd
|
||||
rtl_T80/T80_Pack.vhd
|
||||
rtl_T80/T80_MCode.vhd
|
||||
rtl_T80/T80_ALU.vhd
|
||||
rtl_T80/T80.vhd
|
||||
|
||||
io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
|
||||
ym_2149_linmix.vhd Copyright (c) MikeJ - Jan 2005
|
||||
|
||||
----------------------
|
||||
Quartus project files
|
||||
----------------------
|
||||
de10_lite/crazy_climber_de10_lite.qsf de10_lite settings (files,pins,...)
|
||||
de10_lite/crazy_climber_de10_lite.qpf de10_lite project
|
||||
|
||||
-----------------------------
|
||||
Required ROMs (Not included)
|
||||
-----------------------------
|
||||
You need the following 16 ROMs from cclimber.zip
|
||||
|
||||
cc11 CRC(217ec4ff) SHA1(334604c3a051d57440a9d0bfc34b809418ef1d2d)
|
||||
cc10 CRC(b3c26cef) SHA1(f52cb5482c12a9c5fb56e2e2aec7cab0ed23e5a5)
|
||||
cc09 CRC(6db0879c) SHA1(c0ba1976c1dcd6edadd78073173a26851ae8dd4f)
|
||||
cc08 CRC(f48c5fe3) SHA1(79072bbbf37387998ffd031afe8eb569a16fa9bd)
|
||||
cc07 CRC(3e873baf) SHA1(8870dc5948cdd3c8d2fe9e54a20cf6c311c94e53)
|
||||
|
||||
cc06 CRC(481b64cc) SHA1(3f35c545fc784ed4f969aba2d7be6e13a5ae32b7)
|
||||
cc05 CRC(2c33b760) SHA1(2edea8fe13376fbd51a5586d97aba3b30d78e94b)
|
||||
cc04 CRC(332347cb) SHA1(4115ca32af73f1791635b7d9e093bf77088a8222)
|
||||
cc03 CRC(4e4b3658) SHA1(0d39a8cb5cd6cf06008be60707f9b277a8a32a2d)
|
||||
|
||||
cc02 CRC(14f3ecc9) SHA1(a1b5121abfbe8f07580eb3fa6384352d239a3d75)
|
||||
cc01 CRC(21c0f9fb) SHA1(44fad56d302a439257216ddac9fd62b3666589f1)
|
||||
|
||||
cclimber.pr1 CRC(751c3325) SHA1(edce2bc883996c1d72dc6c1c9f62799b162d415a)
|
||||
cclimber.pr2 CRC(ab1940fa) SHA1(8d98e05cbaa6f55770c12e0a9a8ed9c73cc54423)
|
||||
cclimber.pr3 CRC(71317756) SHA1(1195f0a037e379cc1a3c0314cb746f5cd2bffe50)
|
||||
|
||||
cc13 CRC(e0042f75) SHA1(86cb31b110742a0f7ae33052c88f42d00deb5468)
|
||||
cc12 CRC(5da13aaa) SHA1(b2d41e69435d09c456648a10e33f5e1fbb0bc64c)
|
||||
|
||||
------
|
||||
Tools
|
||||
------
|
||||
You need to build vhdl ROM image files from the binary file :
|
||||
- Unzip the roms file in the tools/cclimber_unzip directory
|
||||
- Double click (execute) the script tools/cclimber_unzip/make_crazy_climber_proms.bat to get the following files
|
||||
|
||||
cclimber_program.vhd
|
||||
cclimber_tile_bit0.vhd
|
||||
cclimber_tile_bit1.vhd
|
||||
cclimber_big_sprite_tile_bit0.vhd
|
||||
cclimber_big_sprite_tile_bit1.vhd
|
||||
cclimber_palette.vhd
|
||||
cclimber_big_sprite_palette.vhd
|
||||
cclimber_samples.vhd
|
||||
|
||||
*DO NOT REDISTRIBUTE THESE FILES*
|
||||
|
||||
The script make_crazy_climber_proms uses make_vhdl_prom and and duplicate_byte executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux.
|
||||
|
||||
Source code of make_vhdl_prom.c and and duplicate_byte.c is also delivered.
|
||||
|
||||
---------------------------------
|
||||
Compiling for de10_lite
|
||||
---------------------------------
|
||||
You can rebuild the project with ROM image embeded in the sof file. DO NOT REDISTRIBUTE THESE FILES.
|
||||
4 steps
|
||||
|
||||
- put the VHDL rom files into the project directory
|
||||
- rebuild crazy_climber_de10_lite
|
||||
- program crazy_climber_de10_lite.sof into the fpga
|
||||
|
||||
--------------------
|
||||
Keyboard and swicth
|
||||
--------------------
|
||||
Use directional key to move, space to change movement, F1/F2 to start 1/2 players and F3 for coins.
|
||||
de10_lie sw0 allow to switch 15kHz/31kHz
|
||||
|
||||
------------------------
|
||||
End of file
|
||||
------------------------
|
||||
Binary file not shown.
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 12:37:03 March 21, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
|
||||
DATE = "12:37:03 March 21, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "RiverPatrol"
|
||||
@@ -0,0 +1,174 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 12:30:41 March 21, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# RiverPatrol_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/RiverPatrol_mist.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/crazy_climber.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cclimber_palette.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cclimber_big_sprite_palette.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cclimber_big_sprite_tile_bit0.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cclimber_big_sprite_tile_bit1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cclimber_program.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cclimber_tile_bit0.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cclimber_tile_bit1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/crazy_climber_sound.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_90 -to SPI_SS4
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY RiverPatrol_mist
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
# SignalTap II Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# ---------------------------
|
||||
# start ENTITY(RiverPatrol_mist)
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(RiverPatrol_mist)
|
||||
# -------------------------
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,38 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
cd sys
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
cd ..
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
del /s PLLJ_PLLSPE_INFO.txt
|
||||
|
||||
pause
|
||||
@@ -0,0 +1,172 @@
|
||||
module RiverPatrol_mist (
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27
|
||||
);
|
||||
|
||||
`include "rtl\build_id.sv"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"RiverPat.;;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"T6,Reset;",
|
||||
"V,v1.20.",`BUILD_DATE
|
||||
};
|
||||
|
||||
|
||||
assign LED = 1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clock_24, clock_12, clock_6;
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clock_24),//48.784
|
||||
.c1(clock_12),//12.196
|
||||
.c2(clock_6)
|
||||
);
|
||||
|
||||
wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [7:0] joystick_0;
|
||||
wire [7:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire [10:0] ps2_key;
|
||||
wire [15:0] audio;
|
||||
wire hs, vs;
|
||||
wire hb, vb;
|
||||
wire blankn = ~(hb | vb);
|
||||
wire [2:0] r, g;
|
||||
wire [1:0] b;
|
||||
|
||||
crazy_climber crazy_climber (
|
||||
.clock_12(clock_12),
|
||||
.reset(status[0] | status[6] | buttons[1]),
|
||||
.video_r(r),
|
||||
.video_g(g),
|
||||
.video_b(b),
|
||||
.video_hb(hb),
|
||||
.video_vb(vb),
|
||||
.video_hs(hs),
|
||||
.video_vs(vs),
|
||||
.audio_out(audio),
|
||||
.start2(btn_two_players),
|
||||
.start1(btn_one_player),
|
||||
.coin1(btn_coin),
|
||||
.right1(m_right),
|
||||
.left1(m_left),
|
||||
.fire1(m_fire),
|
||||
.right2(m_right),
|
||||
.left2(m_left),
|
||||
.fire2(m_fire)
|
||||
);
|
||||
|
||||
video_mixer video_mixer(
|
||||
.clk_sys(clock_24),
|
||||
.ce_pix(clock_6),
|
||||
.ce_pix_actual(clock_6),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(blankn ? {r} : "000"),
|
||||
.G(blankn ? {g} : "000"),
|
||||
.B(blankn ? {b,1'b0} : "000"),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.scandoublerD(scandoublerD),
|
||||
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
|
||||
.ypbpr(ypbpr),
|
||||
.ypbpr_full(1),
|
||||
.line_start(0),
|
||||
.mono(0)
|
||||
);
|
||||
|
||||
|
||||
mist_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
mist_io(
|
||||
.clk_sys (clock_24 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_SCK (SPI_SCK ),
|
||||
.CONF_DATA0 (CONF_DATA0 ),
|
||||
.SPI_SS2 (SPI_SS2 ),
|
||||
.SPI_DO (SPI_DO ),
|
||||
.SPI_DI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoublerD (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.ps2_key (ps2_key ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(
|
||||
.MSBI(15),
|
||||
.INV(1'b1))
|
||||
dac(
|
||||
.CLK(clock_24),
|
||||
.RESET(0),
|
||||
.DACin(audio),
|
||||
.DACout(AUDIO_L)
|
||||
);
|
||||
|
||||
//wire m_up = btn_up | joystick_0[3] | joystick_1[3];
|
||||
//wire m_down = btn_down | joystick_0[2] | joystick_1[2];
|
||||
wire m_left = btn_left | joystick_0[1] | joystick_1[1];
|
||||
wire m_right = btn_right | joystick_0[0] | joystick_1[0];
|
||||
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
|
||||
//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
|
||||
|
||||
reg btn_one_player = 0;
|
||||
reg btn_two_players = 0;
|
||||
reg btn_left = 0;
|
||||
reg btn_right = 0;
|
||||
reg btn_down = 0;
|
||||
reg btn_up = 0;
|
||||
reg btn_fire1 = 0;
|
||||
reg btn_fire2 = 0;
|
||||
reg btn_fire3 = 0;
|
||||
reg btn_coin = 0;
|
||||
wire pressed = ps2_key[9];
|
||||
wire [7:0] code = ps2_key[7:0];
|
||||
|
||||
always @(posedge clock_24) begin
|
||||
reg old_state;
|
||||
old_state <= ps2_key[10];
|
||||
if(old_state != ps2_key[10]) begin
|
||||
case(code)
|
||||
'h75: btn_up <= pressed; // up
|
||||
'h72: btn_down <= pressed; // down
|
||||
'h6B: btn_left <= pressed; // left
|
||||
'h74: btn_right <= pressed; // right
|
||||
'h76: btn_coin <= pressed; // ESC
|
||||
'h05: btn_one_player <= pressed; // F1
|
||||
'h06: btn_two_players <= pressed; // F2
|
||||
'h14: btn_fire3 <= pressed; // ctrl
|
||||
'h11: btn_fire2 <= pressed; // alt
|
||||
'h29: btn_fire1 <= pressed; // Space
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1073
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80.vhd
Normal file
1073
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80.vhd
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,351 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_ALU;
|
||||
|
||||
architecture rtl of T80_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,208 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T80_Pack is
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
@@ -0,0 +1,105 @@
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
|
||||
end;
|
||||
@@ -0,0 +1,190 @@
|
||||
--
|
||||
-- Z80 compatible microprocessor core, synchronous top level
|
||||
-- Different timing than the original z80
|
||||
-- Inputs needs to be synchronous and outputs may glitch
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0208 : First complete release
|
||||
--
|
||||
-- 0210 : Fixed read with wait
|
||||
--
|
||||
-- 0211 : Fixed interrupt cycle
|
||||
--
|
||||
-- 0235 : Updated for T80 interface change
|
||||
--
|
||||
-- 0236 : Added T2Write generic
|
||||
--
|
||||
-- 0237 : Fixed T2Write with wait state
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0240 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80s is
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
||||
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80s;
|
||||
|
||||
architecture rtl of T80s is
|
||||
|
||||
signal CEN : std_logic;
|
||||
signal IntCycle_n : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
CEN <= '1';
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => Mode,
|
||||
IOWait => IOWait)
|
||||
port map(
|
||||
CEN => CEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => RESET_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
CLK_n => CLK_n,
|
||||
A => A,
|
||||
DInst => DI,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
DI_Reg <= "00000000";
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
if MCycle = "001" then
|
||||
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||
RD_n <= not IntCycle_n;
|
||||
MREQ_n <= not IntCycle_n;
|
||||
IORQ_n <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
MREQ_n <= '0';
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
|
||||
RD_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
if T2Write = 0 then
|
||||
if TState = "010" and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "010" and Wait_n = '1' then
|
||||
DI_Reg <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
@@ -0,0 +1,2 @@
|
||||
`define BUILD_DATE "190321"
|
||||
`define BUILD_TIME "131156"
|
||||
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.sv"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
@@ -0,0 +1,24 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity cclimber_big_sprite_palette is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(4 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of cclimber_big_sprite_palette is
|
||||
type rom is array(0 to 31) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"38",X"07",X"F6",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,150 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity cclimber_big_sprite_tile_bit0 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(10 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of cclimber_big_sprite_tile_bit0 is
|
||||
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"00",X"00",X"00",X"1F",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"60",X"FE",X"FE",X"FE",X"FE",X"FE",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"FF",X"FF",
|
||||
X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"1F",X"00",X"00",X"00",
|
||||
X"FE",X"FE",X"FE",X"FE",X"FE",X"60",X"00",X"00",X"FF",X"FF",X"F0",X"F0",X"F0",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"01",X"03",X"03",X"01",X"01",X"01",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"F8",X"FC",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"30",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"7F",X"3F",X"3F",X"07",X"03",X"01",X"00",
|
||||
X"FF",X"FE",X"FE",X"FE",X"FC",X"F9",X"F9",X"1B",X"7C",X"7C",X"7C",X"FE",X"FF",X"FF",X"FF",X"FE",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C2",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FC",X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"7F",
|
||||
X"00",X"80",X"C0",X"E0",X"F0",X"FC",X"FC",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7F",X"3F",X"1F",X"0F",X"07",X"07",X"01",X"00",
|
||||
X"FF",X"FF",X"FE",X"FC",X"F9",X"F3",X"E7",X"CF",X"00",X"00",X"40",X"E0",X"F0",X"E0",X"C0",X"E0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"1F",X"3F",X"1D",X"08",X"00",X"00",X"00",X"00",X"F0",X"F8",X"F0",X"E0",X"40",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"3F",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",
|
||||
X"80",X"C0",X"F0",X"F0",X"F0",X"F8",X"FC",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"1F",X"1F",X"1F",X"1F",X"0F",X"07",X"07",
|
||||
X"FE",X"FE",X"FE",X"FF",X"FF",X"F8",X"F1",X"87",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"01",X"01",X"00",X"00",X"00",X"00",
|
||||
X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"1F",X"0E",X"C0",X"C0",X"00",X"00",X"00",X"00",X"80",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",
|
||||
X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"1F",X"1F",X"1F",X"1F",X"1F",
|
||||
X"F0",X"F0",X"F0",X"F8",X"F8",X"F8",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"3F",X"3F",X"1F",X"1F",X"1F",X"1F",X"00",
|
||||
X"F8",X"FC",X"FC",X"F8",X"F8",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"1F",X"1F",X"1F",X"03",X"03",X"03",X"03",
|
||||
X"F8",X"F8",X"F8",X"F8",X"C0",X"C0",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",
|
||||
X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",
|
||||
X"00",X"02",X"0C",X"08",X"08",X"10",X"20",X"20",X"0F",X"0F",X"0F",X"1F",X"1F",X"1F",X"9F",X"1F",
|
||||
X"F0",X"F0",X"F1",X"F8",X"F8",X"F8",X"F8",X"F8",X"60",X"10",X"08",X"C8",X"44",X"42",X"42",X"30",
|
||||
X"04",X"08",X"10",X"10",X"10",X"20",X"18",X"07",X"1F",X"3F",X"3F",X"1F",X"1D",X"18",X"00",X"00",
|
||||
X"F8",X"FC",X"FC",X"F8",X"F8",X"78",X"00",X"00",X"08",X"0C",X"04",X"04",X"04",X"08",X"10",X"70",
|
||||
X"10",X"10",X"0C",X"03",X"00",X"00",X"00",X"00",X"C3",X"3C",X"00",X"0A",X"F5",X"00",X"00",X"00",
|
||||
X"E3",X"1C",X"00",X"00",X"01",X"E2",X"00",X"00",X"80",X"00",X"10",X"20",X"C0",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"01",X"02",X"1E",X"20",X"00",X"00",X"01",X"00",X"E0",X"00",X"00",X"18",
|
||||
X"00",X"00",X"C1",X"20",X"00",X"78",X"04",X"02",X"00",X"00",X"C0",X"20",X"20",X"40",X"30",X"0C",
|
||||
X"20",X"00",X"05",X"04",X"08",X"08",X"08",X"10",X"20",X"C0",X"00",X"00",X"00",X"01",X"03",X"07",
|
||||
X"01",X"01",X"00",X"02",X"01",X"80",X"C0",X"E0",X"04",X"E0",X"10",X"10",X"08",X"88",X"88",X"80",
|
||||
X"08",X"10",X"10",X"20",X"10",X"00",X"00",X"20",X"0F",X"0F",X"0F",X"1F",X"1F",X"1F",X"0C",X"00",
|
||||
X"F0",X"F0",X"F0",X"F8",X"F8",X"08",X"00",X"00",X"40",X"20",X"40",X"00",X"0C",X"04",X"04",X"3C",
|
||||
X"12",X"11",X"10",X"18",X"04",X"02",X"01",X"00",X"00",X"00",X"C0",X"38",X"07",X"00",X"00",X"00",
|
||||
X"0E",X"30",X"00",X"23",X"C0",X"00",X"00",X"00",X"20",X"20",X"C0",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"04",X"0C",X"1E",X"00",X"00",X"2E",X"FF",X"3E",X"F8",X"99",X"A7",
|
||||
X"00",X"00",X"30",X"AE",X"31",X"08",X"88",X"F8",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"20",
|
||||
X"1E",X"1C",X"28",X"20",X"33",X"24",X"07",X"0F",X"43",X"07",X"7F",X"85",X"0E",X"0E",X"A1",X"BE",
|
||||
X"FC",X"FC",X"F0",X"F1",X"59",X"47",X"C1",X"30",X"30",X"70",X"F8",X"F8",X"E0",X"E0",X"E0",X"B0",
|
||||
X"0F",X"0F",X"25",X"25",X"12",X"10",X"10",X"13",X"21",X"D9",X"23",X"3E",X"E1",X"C1",X"43",X"2F",
|
||||
X"08",X"08",X"3F",X"DE",X"5F",X"1F",X"9F",X"F7",X"A8",X"98",X"10",X"10",X"20",X"88",X"8C",X"8C",
|
||||
X"0B",X"0B",X"09",X"04",X"02",X"00",X"00",X"00",X"13",X"C9",X"E1",X"F9",X"47",X"20",X"3E",X"00",
|
||||
X"F0",X"F8",X"F9",X"3B",X"03",X"FE",X"00",X"00",X"14",X"3C",X"F0",X"E0",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"40",X"81",X"41",X"21",X"40",X"40",X"80",X"80",X"98",X"04",X"02",X"02",X"81",X"41",X"21",X"10",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"08",X"04",X"08",X"08",
|
||||
X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"04",X"08",X"10",X"10",X"20",X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"42",X"42",X"84",X"84",X"82",X"00",X"00",X"00",X"42",X"42",X"21",X"21",X"41",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"08",X"04",X"08",X"08",
|
||||
X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"00",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"40",X"81",X"41",X"21",X"40",X"40",X"80",X"40",X"98",X"04",X"02",X"02",X"81",X"41",X"21",X"10",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"08",X"08",X"10",X"08",X"04",X"04",X"04",X"02",X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"84",X"82",X"81",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"41",X"21",X"11",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"08",X"08",X"10",X"20",X"20",X"00",X"00",X"00",X"10",X"10",X"08",X"04",X"04",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"84",X"82",X"81",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"41",X"21",X"11",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"08",X"08",X"10",X"08",X"04",X"04",X"04",X"02",X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,150 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity cclimber_big_sprite_tile_bit1 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(10 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of cclimber_big_sprite_tile_bit1 is
|
||||
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"03",X"0F",X"3F",X"7F",X"FF",X"00",X"3F",X"FF",X"FF",X"FE",X"FC",X"F8",X"F8",
|
||||
X"00",X"FF",X"9F",X"9F",X"3F",X"7F",X"7F",X"7F",X"00",X"FC",X"FC",X"FC",X"FC",X"FC",X"C0",X"C0",
|
||||
X"FF",X"7F",X"3F",X"0F",X"03",X"00",X"00",X"00",X"F8",X"F8",X"FC",X"FE",X"FF",X"FF",X"3F",X"00",
|
||||
X"7F",X"7F",X"7F",X"3F",X"9F",X"9F",X"FF",X"00",X"C0",X"C0",X"FC",X"FC",X"FC",X"FC",X"FC",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"1F",X"3F",X"3F",X"3F",X"3F",X"1F",X"0F",X"0F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FC",X"F8",X"F8",
|
||||
X"00",X"E0",X"FC",X"FF",X"07",X"1F",X"3F",X"3F",X"00",X"00",X"00",X"00",X"C0",X"F8",X"FE",X"FF",
|
||||
X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"FC",X"FC",X"7E",X"1F",X"03",X"00",
|
||||
X"7F",X"7F",X"FF",X"7F",X"7F",X"7F",X"FF",X"FF",X"FE",X"FE",X"CC",X"80",X"80",X"80",X"C0",X"F0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"7F",X"1F",X"03",X"00",X"00",X"00",X"00",X"00",X"F0",X"E0",X"E0",X"60",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"07",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"80",X"F0",X"FE",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"0F",X"07",X"07",X"07",X"03",X"03",X"03",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FC",X"F8",X"F8",
|
||||
X"E0",X"F0",X"F8",X"FC",X"FE",X"03",X"07",X"3F",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",
|
||||
X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"F9",X"79",X"39",X"1B",X"0F",X"07",
|
||||
X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"FC",X"E0",X"F0",X"F8",X"FC",X"FE",X"FC",X"38",X"10",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FC",X"FC",X"FE",X"7F",X"3E",X"1C",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"FC",X"FF",X"FF",X"FF",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FC",X"F8",X"F8",
|
||||
X"F0",X"F8",X"F8",X"FC",X"FC",X"3E",X"0E",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"70",X"73",X"37",X"37",X"1F",X"1F",X"1F",
|
||||
X"23",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"80",X"80",X"C0",X"C0",X"C0",X"E0",X"E0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"07",X"07",X"07",X"03",X"03",X"01",
|
||||
X"FF",X"E3",X"C1",X"C1",X"E0",X"E0",X"C0",X"00",X"E0",X"F0",X"F0",X"80",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"07",X"0F",X"0F",X"1F",X"1F",
|
||||
X"80",X"C0",X"E0",X"E0",X"F0",X"F0",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3F",X"3F",X"7F",X"7F",X"7F",X"7C",X"78",X"70",
|
||||
X"FC",X"FC",X"FE",X"FE",X"FE",X"3E",X"1E",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"47",X"4F",X"7F",X"7F",X"7F",X"7F",X"7F",
|
||||
X"0E",X"E2",X"F2",X"FE",X"FE",X"FE",X"FE",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7F",X"7F",X"7C",X"7C",X"7C",X"7C",X"00",X"00",
|
||||
X"FE",X"FE",X"3E",X"3E",X"3E",X"3E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"07",X"0F",X"0F",X"1F",X"1F",
|
||||
X"80",X"C0",X"E0",X"E0",X"F0",X"F0",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",
|
||||
X"00",X"02",X"0C",X"08",X"08",X"10",X"20",X"23",X"3F",X"3F",X"7F",X"7F",X"7F",X"7C",X"F8",X"70",
|
||||
X"FC",X"FC",X"FF",X"FE",X"FE",X"3E",X"1E",X"0E",X"60",X"10",X"08",X"C8",X"44",X"42",X"42",X"30",
|
||||
X"04",X"08",X"10",X"10",X"10",X"20",X"18",X"07",X"70",X"47",X"4F",X"7F",X"7D",X"78",X"00",X"00",
|
||||
X"0E",X"E2",X"F2",X"FE",X"FE",X"7E",X"00",X"00",X"08",X"0C",X"04",X"04",X"04",X"08",X"10",X"70",
|
||||
X"10",X"10",X"0C",X"03",X"00",X"00",X"00",X"00",X"C3",X"3C",X"00",X"0A",X"F5",X"00",X"00",X"00",
|
||||
X"E3",X"1C",X"00",X"00",X"01",X"E2",X"00",X"00",X"80",X"00",X"10",X"20",X"C0",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"01",X"02",X"1E",X"20",X"00",X"00",X"01",X"00",X"E0",X"00",X"00",X"18",
|
||||
X"00",X"00",X"C1",X"20",X"00",X"78",X"04",X"02",X"00",X"00",X"C0",X"20",X"20",X"40",X"30",X"0C",
|
||||
X"20",X"00",X"05",X"04",X"08",X"08",X"08",X"10",X"20",X"C1",X"03",X"07",X"07",X"0F",X"0F",X"1F",
|
||||
X"01",X"81",X"C0",X"E2",X"E1",X"F0",X"F0",X"F8",X"04",X"E0",X"10",X"10",X"08",X"88",X"88",X"80",
|
||||
X"08",X"10",X"10",X"20",X"10",X"00",X"00",X"20",X"1F",X"3F",X"3F",X"7F",X"7F",X"3F",X"0C",X"00",
|
||||
X"F8",X"FC",X"FC",X"FE",X"FE",X"0E",X"00",X"00",X"40",X"20",X"40",X"00",X"0C",X"04",X"04",X"3C",
|
||||
X"12",X"11",X"10",X"18",X"04",X"02",X"01",X"00",X"00",X"00",X"C0",X"38",X"07",X"00",X"80",X"00",
|
||||
X"FE",X"30",X"00",X"23",X"C0",X"00",X"00",X"00",X"20",X"20",X"C0",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"03",X"07",X"0F",X"1E",X"00",X"00",X"3E",X"FF",X"FF",X"FF",X"9E",X"A6",
|
||||
X"00",X"00",X"30",X"CE",X"C1",X"F1",X"30",X"3E",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"20",
|
||||
X"1E",X"1C",X"38",X"30",X"33",X"27",X"07",X"0F",X"62",X"07",X"78",X"FD",X"FF",X"FF",X"FF",X"FE",
|
||||
X"C2",X"05",X"00",X"F0",X"D8",X"C6",X"C1",X"30",X"D0",X"D0",X"C8",X"08",X"00",X"E0",X"E0",X"D0",
|
||||
X"0F",X"0F",X"3C",X"3D",X"1F",X"1F",X"1F",X"1C",X"E1",X"D9",X"23",X"9E",X"11",X"8D",X"41",X"3F",
|
||||
X"08",X"48",X"2F",X"9B",X"51",X"10",X"98",X"7F",X"C8",X"E8",X"90",X"90",X"F0",X"F8",X"F4",X"F4",
|
||||
X"0C",X"0E",X"0D",X"04",X"02",X"00",X"00",X"00",X"12",X"49",X"21",X"99",X"47",X"20",X"3E",X"00",
|
||||
X"1F",X"0F",X"CE",X"FC",X"FD",X"FE",X"00",X"00",X"E4",X"CC",X"10",X"60",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"40",X"81",X"41",X"21",X"40",X"40",X"80",X"40",X"98",X"04",X"02",X"02",X"81",X"41",X"21",X"10",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"08",X"04",X"08",X"08",
|
||||
X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"00",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"04",X"08",X"10",X"10",X"20",X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"42",X"42",X"84",X"84",X"82",X"00",X"00",X"00",X"42",X"42",X"21",X"21",X"41",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"08",X"04",X"08",X"08",
|
||||
X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"00",X"01",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"40",X"81",X"41",X"21",X"40",X"40",X"80",X"40",X"98",X"04",X"02",X"02",X"81",X"41",X"21",X"10",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"08",X"08",X"10",X"08",X"04",X"04",X"04",X"02",X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"84",X"82",X"81",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"41",X"21",X"11",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"08",X"08",X"10",X"20",X"20",X"00",X"00",X"00",X"10",X"10",X"08",X"04",X"04",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"84",X"82",X"81",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"41",X"21",X"11",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"08",X"08",X"10",X"08",X"04",X"04",X"04",X"02",X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,26 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity cclimber_palette is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(5 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of cclimber_palette is
|
||||
type rom is array(0 to 63) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"80",X"F7",X"F7",X"F6",X"00",X"F4",X"01",X"01",X"00",X"31",X"07",X"00",X"00",X"7F",X"66",X"00",
|
||||
X"00",X"FA",X"F6",X"00",X"00",X"B8",X"00",X"3F",X"00",X"FC",X"B7",X"FA",X"00",X"4E",X"AF",X"00",
|
||||
X"00",X"00",X"9C",X"7E",X"00",X"00",X"9C",X"07",X"00",X"00",X"00",X"00",X"00",X"FF",X"BE",X"00",
|
||||
X"00",X"FA",X"76",X"00",X"00",X"87",X"87",X"00",X"00",X"B7",X"6F",X"00",X"00",X"FA",X"FA",X"07");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,278 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity cclimber_tile_bit0 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(11 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of cclimber_tile_bit0 is
|
||||
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"1C",X"26",X"63",X"63",X"63",X"32",X"1C",X"00",X"0C",X"1C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",
|
||||
X"3E",X"63",X"07",X"1E",X"3C",X"70",X"7F",X"00",X"3F",X"06",X"0C",X"1E",X"03",X"63",X"3E",X"00",
|
||||
X"0E",X"1E",X"36",X"66",X"7F",X"06",X"06",X"00",X"3E",X"30",X"3E",X"03",X"03",X"33",X"1E",X"00",
|
||||
X"1E",X"30",X"60",X"7E",X"63",X"63",X"3E",X"00",X"3F",X"23",X"06",X"0C",X"18",X"18",X"18",X"00",
|
||||
X"3C",X"62",X"72",X"3C",X"4F",X"43",X"3E",X"00",X"3E",X"63",X"63",X"3F",X"03",X"06",X"3C",X"00",
|
||||
X"1C",X"36",X"63",X"63",X"7F",X"63",X"63",X"00",X"7E",X"63",X"63",X"7E",X"63",X"63",X"7E",X"00",
|
||||
X"1E",X"33",X"60",X"60",X"60",X"33",X"1E",X"00",X"7C",X"66",X"63",X"63",X"63",X"66",X"7C",X"00",
|
||||
X"3F",X"30",X"30",X"3E",X"30",X"30",X"3F",X"00",X"7F",X"60",X"60",X"7E",X"60",X"60",X"60",X"00",
|
||||
X"1F",X"30",X"60",X"67",X"63",X"33",X"1F",X"00",X"63",X"63",X"63",X"7F",X"63",X"63",X"63",X"00",
|
||||
X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",X"03",X"03",X"03",X"03",X"03",X"63",X"3E",X"00",
|
||||
X"63",X"66",X"6C",X"78",X"7C",X"6E",X"67",X"00",X"30",X"30",X"30",X"30",X"30",X"30",X"3F",X"00",
|
||||
X"63",X"77",X"7F",X"7F",X"6B",X"63",X"63",X"00",X"63",X"73",X"7B",X"7F",X"6F",X"67",X"63",X"00",
|
||||
X"3E",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"7E",X"63",X"63",X"63",X"7E",X"60",X"60",X"00",
|
||||
X"3E",X"63",X"63",X"63",X"6F",X"66",X"3D",X"00",X"7E",X"63",X"63",X"67",X"7C",X"6E",X"67",X"00",
|
||||
X"3C",X"66",X"60",X"3E",X"03",X"63",X"3E",X"00",X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"00",
|
||||
X"63",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"63",X"63",X"63",X"77",X"3E",X"1C",X"08",X"00",
|
||||
X"63",X"63",X"6B",X"7F",X"7F",X"36",X"22",X"00",X"63",X"77",X"3E",X"1C",X"3E",X"77",X"63",X"00",
|
||||
X"33",X"33",X"12",X"1E",X"0C",X"0C",X"0C",X"00",X"7F",X"07",X"0E",X"1C",X"38",X"70",X"7F",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"18",X"30",X"30",X"30",X"30",X"30",X"18",X"00",
|
||||
X"18",X"0C",X"0C",X"0C",X"0C",X"0C",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",
|
||||
X"00",X"00",X"00",X"18",X"1C",X"04",X"08",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"02",X"02",X"02",X"02",X"02",X"02",X"04",X"04",X"20",X"00",X"20",X"20",X"20",X"20",X"20",X"20",
|
||||
X"04",X"00",X"01",X"06",X"0C",X"09",X"09",X"00",X"10",X"10",X"80",X"60",X"30",X"90",X"90",X"00",
|
||||
X"00",X"00",X"00",X"00",X"08",X"02",X"02",X"02",X"00",X"00",X"00",X"00",X"20",X"20",X"00",X"00",
|
||||
X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"40",X"40",X"40",X"40",X"00",X"00",X"20",
|
||||
X"02",X"02",X"02",X"02",X"04",X"04",X"00",X"00",X"80",X"00",X"20",X"20",X"20",X"40",X"40",X"40",
|
||||
X"00",X"03",X"0F",X"18",X"16",X"06",X"00",X"00",X"00",X"00",X"80",X"C0",X"40",X"40",X"40",X"00",
|
||||
X"00",X"00",X"00",X"04",X"00",X"00",X"04",X"04",X"00",X"00",X"00",X"00",X"20",X"20",X"00",X"00",
|
||||
X"04",X"04",X"04",X"00",X"01",X"01",X"21",X"24",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00",
|
||||
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"03",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"E0",X"C0",
|
||||
X"00",X"00",X"00",X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"80",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"04",X"04",X"04",X"04",X"00",X"00",X"00",X"00",X"20",X"20",X"20",X"20",
|
||||
X"05",X"05",X"00",X"00",X"07",X"0F",X"0F",X"0F",X"A0",X"A0",X"00",X"00",X"E0",X"F0",X"F0",X"F0",
|
||||
X"03",X"03",X"07",X"07",X"03",X"03",X"00",X"00",X"FC",X"F8",X"F8",X"F8",X"F8",X"F0",X"60",X"00",
|
||||
X"00",X"04",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"01",X"02",X"02",X"02",X"04",X"04",X"00",X"00",X"00",X"08",X"10",X"10",X"D0",X"D0",
|
||||
X"00",X"00",X"08",X"1F",X"1F",X"1F",X"1F",X"3F",X"20",X"00",X"00",X"00",X"C0",X"E0",X"C0",X"C0",
|
||||
X"01",X"06",X"08",X"00",X"00",X"00",X"01",X"07",X"C0",X"30",X"08",X"00",X"00",X"00",X"C0",X"F0",
|
||||
X"0F",X"0F",X"0F",X"07",X"03",X"00",X"00",X"00",X"F8",X"F8",X"F8",X"F0",X"E0",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"01",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"C0",X"30",X"08",X"00",
|
||||
X"00",X"00",X"01",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"C0",X"30",X"08",X"00",X"00",X"00",
|
||||
X"07",X"00",X"00",X"00",X"00",X"1F",X"3F",X"3F",X"C0",X"20",X"10",X"08",X"00",X"00",X"80",X"C0",
|
||||
X"7F",X"3F",X"3F",X"1F",X"07",X"00",X"00",X"00",X"E0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"08",X"08",
|
||||
X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"04",X"02",X"02",X"80",X"40",X"20",X"10",X"00",
|
||||
X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"80",X"BC",X"00",X"00",X"00",
|
||||
X"08",X"00",X"00",X"01",X"3D",X"00",X"00",X"00",X"40",X"80",X"80",X"00",X"00",X"00",X"00",X"00",
|
||||
X"11",X"11",X"01",X"00",X"00",X"04",X"04",X"04",X"00",X"10",X"10",X"88",X"84",X"80",X"30",X"20",
|
||||
X"00",X"08",X"08",X"11",X"21",X"01",X"06",X"04",X"88",X"88",X"80",X"00",X"00",X"20",X"20",X"20",
|
||||
X"04",X"04",X"04",X"00",X"00",X"01",X"11",X"11",X"20",X"60",X"80",X"84",X"88",X"10",X"10",X"00",
|
||||
X"04",X"06",X"01",X"21",X"11",X"08",X"08",X"00",X"20",X"20",X"20",X"00",X"00",X"80",X"88",X"88",
|
||||
X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"00",X"00",X"00",X"BC",X"80",X"00",X"00",X"10",
|
||||
X"00",X"00",X"00",X"3D",X"01",X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"00",X"C0",X"18",X"01",X"00",X"00",
|
||||
X"E0",X"00",X"00",X"03",X"18",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"08",X"08",X"10",X"00",X"00",X"80",X"88",X"02",X"00",X"00",X"C0",X"00",X"30",
|
||||
X"01",X"11",X"40",X"00",X"00",X"03",X"00",X"0C",X"00",X"00",X"00",X"10",X"10",X"08",X"00",X"00",
|
||||
X"00",X"00",X"10",X"08",X"08",X"00",X"00",X"00",X"30",X"00",X"C0",X"00",X"00",X"02",X"88",X"80",
|
||||
X"0C",X"00",X"03",X"00",X"00",X"40",X"11",X"01",X"00",X"00",X"08",X"01",X"01",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"18",X"C0",X"00",X"00",X"07",
|
||||
X"00",X"00",X"80",X"18",X"03",X"00",X"00",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"80",X"90",X"10",X"06",X"00",X"00",
|
||||
X"40",X"00",X"01",X"09",X"00",X"60",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"01",X"01",X"10",X"18",X"08",X"00",X"00",X"0C",X"00",X"00",X"84",X"80",X"00",X"00",X"20",X"40",
|
||||
X"00",X"00",X"21",X"01",X"00",X"00",X"04",X"20",X"80",X"80",X"08",X"18",X"10",X"00",X"00",X"30",
|
||||
X"0C",X"00",X"00",X"08",X"18",X"10",X"01",X"01",X"04",X"20",X"00",X"00",X"80",X"84",X"00",X"00",
|
||||
X"20",X"04",X"00",X"00",X"01",X"21",X"00",X"00",X"30",X"00",X"00",X"10",X"18",X"08",X"80",X"80",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"06",X"10",X"90",X"80",X"00",X"02",
|
||||
X"00",X"00",X"60",X"08",X"09",X"01",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",
|
||||
X"12",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"04",X"12",X"00",X"20",X"10",X"01",X"00",X"00",
|
||||
X"20",X"48",X"00",X"04",X"08",X"80",X"00",X"00",X"48",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"01",X"00",X"10",X"10",X"00",X"08",X"08",X"00",X"08",X"04",X"00",X"81",X"40",X"00",X"00",
|
||||
X"00",X"10",X"20",X"00",X"81",X"02",X"00",X"00",X"00",X"80",X"00",X"08",X"08",X"00",X"10",X"10",
|
||||
X"08",X"08",X"00",X"10",X"10",X"00",X"01",X"00",X"00",X"00",X"40",X"81",X"00",X"04",X"08",X"00",
|
||||
X"00",X"00",X"02",X"81",X"00",X"20",X"10",X"00",X"10",X"10",X"00",X"08",X"08",X"00",X"80",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"12",X"00",X"00",X"01",X"10",X"20",X"00",X"12",X"04",
|
||||
X"00",X"00",X"80",X"08",X"04",X"00",X"48",X"20",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"48",
|
||||
X"01",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",
|
||||
X"06",X"06",X"00",X"00",X"00",X"00",X"02",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"40",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"01",X"00",X"01",X"00",X"01",X"00",X"01",X"00",X"80",X"00",X"80",X"00",X"80",X"00",X"80",X"00",
|
||||
X"06",X"00",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",
|
||||
X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"00",X"00",X"00",X"08",X"00",X"20",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"06",X"00",X"06",X"00",X"06",X"00",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"01",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",
|
||||
X"06",X"06",X"00",X"00",X"00",X"00",X"02",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"40",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"01",X"00",X"01",X"00",X"01",X"00",X"01",X"00",X"80",X"00",X"80",X"00",X"80",X"00",X"80",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"60",X"00",X"60",X"00",X"00",X"00",X"00",X"00",
|
||||
X"06",X"00",X"00",X"00",X"00",X"10",X"00",X"04",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"60",X"00",X"60",X"00",X"60",X"00",
|
||||
X"47",X"E6",X"E0",X"4F",X"2A",X"57",X"39",X"3E",X"60",X"08",X"DD",X"7E",X"01",X"BC",X"20",X"06",
|
||||
X"DD",X"7E",X"00",X"BD",X"28",X"0C",X"5E",X"23",X"7E",X"57",X"E6",X"E0",X"23",X"B9",X"30",X"19",
|
||||
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X"1D",X"21",X"A8",X"17",X"CD",X"30",X"00",X"D8",X"08",X"47",X"08",X"78",X"E6",X"20",X"B1",X"DD",
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X"77",X"06",X"0E",X"01",X"FE",X"06",X"30",X"06",X"DD",X"CB",X"54",X"76",X"20",X"0F",X"2A",X"77",
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X"13",X"0E",X"C0",X"21",X"FC",X"0F",X"18",X"E2",X"CB",X"71",X"C2",X"1D",X"16",X"DD",X"7E",X"51",
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X"49",X"52",X"53",X"CB",X"CE",X"01",X"D0",X"03",X"D2",X"05",X"06",X"D3",X"09",X"D7",X"81",X"46",
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X"1D",X"07",X"81",X"43",X"10",X"00",X"81",X"45",X"14",X"02",X"81",X"4C",X"18",X"04",X"82",X"58",
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X"59",X"19",X"1A",X"08",X"A1",X"50",X"1C",X"DD",X"CB",X"08",X"86",X"DD",X"CB",X"09",X"AE",X"21",
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X"11",X"7F",X"3A",X"A7",X"ED",X"52",X"ED",X"5B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"38",X"7C",X"7C",X"44",X"44",X"7C",X"7C",
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X"02",X"06",X"0A",X"12",X"12",X"1F",X"02",X"00",X"0F",X"08",X"08",X"07",X"01",X"09",X"0F",X"00",
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|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"1E",X"72",X"00",X"00",X"00",X"00",X"3F",X"61",X"40",X"40",
|
||||
X"00",X"00",X"00",X"00",X"00",X"C0",X"60",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"03",X"0E",X"18",X"30",X"63",X"47",X"4D",X"00",X"FE",X"03",X"01",X"00",X"8E",X"9A",X"13",
|
||||
X"00",X"00",X"00",X"81",X"C3",X"66",X"24",X"2C",X"00",X"00",X"00",X"F0",X"18",X"0D",X"07",X"C6",
|
||||
X"00",X"00",X"00",X"00",X"00",X"F8",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"9E",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",
|
||||
X"00",X"00",X"00",X"00",X"00",X"07",X"04",X"C6",X"00",X"00",X"1C",X"74",X"46",X"C2",X"63",X"31",
|
||||
X"3F",X"23",X"67",X"45",X"45",X"47",X"46",X"C7",X"C2",X"02",X"1E",X"1E",X"1A",X"02",X"06",X"1C",
|
||||
X"4E",X"4B",X"49",X"49",X"49",X"4B",X"4E",X"4C",X"10",X"10",X"10",X"10",X"10",X"10",X"30",X"60",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C9",X"89",X"89",X"89",X"CF",X"46",X"64",X"34",
|
||||
X"13",X"12",X"16",X"3C",X"01",X"03",X"0E",X"38",X"38",X"61",X"70",X"D0",X"B3",X"22",X"26",X"64",
|
||||
X"E7",X"E4",X"04",X"0C",X"89",X"C9",X"CB",X"9A",X"C0",X"4F",X"C8",X"98",X"90",X"10",X"31",X"41",
|
||||
X"B3",X"A0",X"60",X"44",X"CF",X"89",X"89",X"1B",X"80",X"C0",X"60",X"40",X"30",X"10",X"11",X"17",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"E0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"02",X"06",X"04",X"04",
|
||||
X"18",X"E0",X"80",X"07",X"26",X"62",X"63",X"F1",X"72",X"1A",X"0F",X"85",X"C5",X"45",X"45",X"44",
|
||||
X"30",X"38",X"38",X"1C",X"16",X"16",X"9B",X"89",X"C5",X"C4",X"44",X"0C",X"08",X"08",X"08",X"08",
|
||||
X"90",X"90",X"90",X"90",X"98",X"98",X"8F",X"89",X"40",X"41",X"41",X"48",X"4C",X"4E",X"4B",X"49",
|
||||
X"C0",X"80",X"80",X"C0",X"60",X"30",X"10",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"0E",X"04",X"04",X"04",X"0C",X"09",X"0B",X"0E",X"60",X"40",X"40",X"40",X"40",X"C0",X"00",X"00",
|
||||
X"45",X"4D",X"C9",X"89",X"8B",X"8A",X"FA",X"03",X"92",X"16",X"34",X"24",X"2C",X"68",X"48",X"CD",
|
||||
X"23",X"62",X"46",X"C4",X"8C",X"98",X"91",X"11",X"12",X"3E",X"38",X"00",X"07",X"1C",X"88",X"88",
|
||||
X"3C",X"38",X"73",X"E2",X"C6",X"CC",X"8C",X"88",X"00",X"FE",X"83",X"00",X"00",X"00",X"00",X"00",
|
||||
X"30",X"18",X"8C",X"C4",X"46",X"42",X"42",X"42",X"00",X"00",X"00",X"00",X"38",X"6C",X"C4",X"8C",
|
||||
X"04",X"04",X"04",X"04",X"04",X"06",X"03",X"01",X"91",X"91",X"D1",X"58",X"78",X"18",X"0C",X"84",
|
||||
X"C4",X"8C",X"18",X"10",X"1C",X"06",X"C3",X"70",X"89",X"88",X"CC",X"44",X"44",X"44",X"C4",X"DC",
|
||||
X"88",X"88",X"C8",X"58",X"70",X"00",X"00",X"00",X"C1",X"41",X"5F",X"70",X"00",X"00",X"00",X"00",
|
||||
X"78",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"88",X"CC",X"44",X"74",X"1C",X"00",X"00",X"00",X"88",X"8C",X"C4",X"46",X"63",X"30",X"18",X"0E",
|
||||
X"00",X"00",X"01",X"03",X"DE",X"70",X"01",X"07",X"47",X"C7",X"8E",X"1C",X"38",X"F1",X"B3",X"62",
|
||||
X"98",X"30",X"20",X"60",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"FC",X"02",X"02",X"02",X"02",X"03",X"00",X"00",X"78",X"2F",X"20",X"60",X"C0",X"80",X"00",X"00",
|
||||
X"70",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FC",X"01",X"01",X"01",X"00",X"00",X"00",X"00",
|
||||
X"C6",X"8C",X"06",X"82",X"E2",X"3E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"18",X"01",X"B6",X"77",X"3C",X"C9",X"1E",X"08",X"DD",X"36",X"0C",X"06",X"DD",X"CB",X"50",X"DE",
|
||||
X"53",X"CD",X"83",X"1C",X"21",X"12",X"10",X"ED",X"7B",X"4B",X"39",X"DD",X"21",X"FF",X"38",X"E9",
|
||||
X"21",X"6E",X"10",X"30",X"F2",X"C2",X"69",X"1B",X"EB",X"E5",X"2B",X"36",X"0D",X"22",X"0F",X"39",
|
||||
X"16",X"10",X"CD",X"83",X"1C",X"D1",X"C3",X"8E",X"2B",X"21",X"FA",X"10",X"18",X"E5",X"21",X"52",
|
||||
X"45",X"3E",X"4C",X"DD",X"CB",X"0F",X"76",X"28",X"05",X"21",X"41",X"42",X"3E",X"53",X"22",X"E3",
|
||||
X"38",X"32",X"E5",X"38",X"3E",X"32",X"32",X"CC",X"38",X"AF",X"32",X"09",X"39",X"21",X"00",X"00",
|
||||
X"22",X"65",X"39",X"22",X"75",X"39",X"22",X"5F",X"39",X"22",X"67",X"39",X"22",X"1D",X"39",X"22",
|
||||
X"3B",X"39",X"22",X"3D",X"39",X"22",X"1F",X"39",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,278 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity cclimber_tile_bit1 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(11 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of cclimber_tile_bit1 is
|
||||
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"1C",X"26",X"63",X"63",X"63",X"32",X"1C",X"00",X"0C",X"1C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",
|
||||
X"3E",X"63",X"07",X"1E",X"3C",X"70",X"7F",X"00",X"3F",X"06",X"0C",X"1E",X"03",X"63",X"3E",X"00",
|
||||
X"0E",X"1E",X"36",X"66",X"7F",X"06",X"06",X"00",X"3E",X"30",X"3E",X"03",X"03",X"33",X"1E",X"00",
|
||||
X"1E",X"30",X"60",X"7E",X"63",X"63",X"3E",X"00",X"3F",X"23",X"06",X"0C",X"18",X"18",X"18",X"00",
|
||||
X"3C",X"62",X"72",X"3C",X"4F",X"43",X"3E",X"00",X"3E",X"63",X"63",X"3F",X"03",X"06",X"3C",X"00",
|
||||
X"1C",X"36",X"63",X"63",X"7F",X"63",X"63",X"00",X"7E",X"63",X"63",X"7E",X"63",X"63",X"7E",X"00",
|
||||
X"1E",X"33",X"60",X"60",X"60",X"33",X"1E",X"00",X"7C",X"66",X"63",X"63",X"63",X"66",X"7C",X"00",
|
||||
X"3F",X"30",X"30",X"3E",X"30",X"30",X"3F",X"00",X"7F",X"60",X"60",X"7E",X"60",X"60",X"60",X"00",
|
||||
X"1F",X"30",X"60",X"67",X"63",X"33",X"1F",X"00",X"63",X"63",X"63",X"7F",X"63",X"63",X"63",X"00",
|
||||
X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",X"03",X"03",X"03",X"03",X"03",X"63",X"3E",X"00",
|
||||
X"63",X"66",X"6C",X"78",X"7C",X"6E",X"67",X"00",X"30",X"30",X"30",X"30",X"30",X"30",X"3F",X"00",
|
||||
X"63",X"77",X"7F",X"7F",X"6B",X"63",X"63",X"00",X"63",X"73",X"7B",X"7F",X"6F",X"67",X"63",X"00",
|
||||
X"3E",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"7E",X"63",X"63",X"63",X"7E",X"60",X"60",X"00",
|
||||
X"3E",X"63",X"63",X"63",X"6F",X"66",X"3D",X"00",X"7E",X"63",X"63",X"67",X"7C",X"6E",X"67",X"00",
|
||||
X"3C",X"66",X"60",X"3E",X"03",X"63",X"3E",X"00",X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"00",
|
||||
X"63",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"63",X"63",X"63",X"77",X"3E",X"1C",X"08",X"00",
|
||||
X"63",X"63",X"6B",X"7F",X"7F",X"36",X"22",X"00",X"63",X"77",X"3E",X"1C",X"3E",X"77",X"63",X"00",
|
||||
X"33",X"33",X"12",X"1E",X"0C",X"0C",X"0C",X"00",X"7F",X"07",X"0E",X"1C",X"38",X"70",X"7F",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"18",X"30",X"30",X"30",X"30",X"30",X"18",X"00",
|
||||
X"18",X"0C",X"0C",X"0C",X"0C",X"0C",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",
|
||||
X"00",X"00",X"00",X"18",X"1C",X"04",X"08",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
|
||||
X"0F",X"0F",X"0E",X"09",X"03",X"06",X"02",X"00",X"F0",X"F0",X"70",X"90",X"C0",X"60",X"20",X"00",
|
||||
X"00",X"01",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"00",X"80",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0",
|
||||
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
|
||||
X"07",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"1F",X"F8",X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"E0",
|
||||
X"1F",X"1C",X"10",X"27",X"29",X"01",X"00",X"00",X"E0",X"E0",X"60",X"20",X"A0",X"A0",X"A0",X"00",
|
||||
X"00",X"01",X"0F",X"0F",X"1F",X"1F",X"1F",X"1F",X"00",X"80",X"E0",X"E0",X"F0",X"F0",X"E0",X"E0",
|
||||
X"3F",X"3F",X"3F",X"3F",X"7F",X"7F",X"7F",X"7F",X"E0",X"E0",X"C0",X"C0",X"C0",X"C0",X"00",X"C0",
|
||||
X"10",X"10",X"10",X"10",X"10",X"18",X"1F",X"1F",X"08",X"08",X"08",X"08",X"08",X"18",X"F8",X"F8",
|
||||
X"0F",X"0F",X"07",X"07",X"03",X"03",X"01",X"00",X"F0",X"F0",X"E0",X"E0",X"C0",X"C0",X"80",X"00",
|
||||
X"00",X"00",X"0F",X"1F",X"1F",X"1F",X"1F",X"1F",X"00",X"00",X"F0",X"F8",X"F8",X"F8",X"F8",X"F8",
|
||||
X"1F",X"1F",X"1F",X"1F",X"18",X"10",X"10",X"10",X"F8",X"F8",X"F8",X"F8",X"18",X"08",X"08",X"08",
|
||||
X"04",X"0C",X"0C",X"1E",X"1F",X"0F",X"0F",X"0F",X"02",X"06",X"04",X"04",X"84",X"FC",X"F8",X"F8",
|
||||
X"0F",X"0F",X"0F",X"0F",X"07",X"02",X"00",X"00",X"F0",X"E0",X"C0",X"80",X"80",X"00",X"00",X"00",
|
||||
X"00",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"1F",X"00",X"C0",X"F8",X"FC",X"FC",X"FC",X"FC",X"FC",
|
||||
X"1F",X"1F",X"37",X"20",X"20",X"20",X"60",X"40",X"F8",X"F8",X"F8",X"F0",X"30",X"10",X"20",X"20",
|
||||
X"0E",X"09",X"07",X"0F",X"0F",X"0F",X"0E",X"09",X"38",X"C8",X"F0",X"F8",X"F8",X"F8",X"38",X"C8",
|
||||
X"07",X"07",X"07",X"03",X"01",X"00",X"00",X"00",X"70",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"01",X"07",X"0F",X"00",X"00",X"00",X"00",X"00",X"C0",X"F0",X"F8",
|
||||
X"0F",X"0F",X"0E",X"09",X"07",X"0F",X"0F",X"0F",X"F8",X"F8",X"38",X"C8",X"F0",X"F8",X"F8",X"F8",
|
||||
X"00",X"07",X"0F",X"0F",X"1F",X"00",X"1F",X"1D",X"3E",X"DE",X"EC",X"F4",X"F8",X"F8",X"70",X"B0",
|
||||
X"3F",X"1F",X"1F",X"1F",X"07",X"00",X"00",X"00",X"C0",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"F0",
|
||||
X"07",X"07",X"0F",X"00",X"1F",X"1F",X"3F",X"3F",X"F8",X"FC",X"FC",X"7C",X"B8",X"D8",X"E0",X"F0",
|
||||
X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"08",X"06",X"03",X"00",X"00",X"00",
|
||||
X"00",X"00",X"01",X"0E",X"F0",X"00",X"00",X"00",X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"10",X"10",X"10",X"10",X"08",X"08",X"08",X"04",X"08",X"08",X"84",X"82",X"40",X"40",X"30",X"0C",
|
||||
X"00",X"10",X"21",X"C1",X"02",X"02",X"0C",X"30",X"88",X"88",X"00",X"00",X"00",X"10",X"10",X"20",
|
||||
X"04",X"01",X"01",X"00",X"00",X"00",X"11",X"11",X"0C",X"30",X"40",X"40",X"83",X"84",X"08",X"00",
|
||||
X"30",X"0C",X"02",X"02",X"41",X"21",X"10",X"10",X"20",X"10",X"10",X"10",X"08",X"08",X"08",X"08",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"02",X"00",X"00",X"00",X"0F",X"70",X"80",X"00",X"00",
|
||||
X"00",X"00",X"00",X"C0",X"06",X"01",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"80",X"F0",X"1E",X"01",X"00",X"00",
|
||||
X"E0",X"00",X"01",X"0F",X"78",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"10",X"08",X"10",X"08",X"08",X"04",X"04",X"00",X"88",X"88",X"00",X"07",X"80",X"40",X"30",X"08",
|
||||
X"11",X"11",X"00",X"E0",X"01",X"02",X"0C",X"10",X"08",X"10",X"08",X"10",X"10",X"20",X"20",X"00",
|
||||
X"00",X"04",X"04",X"08",X"08",X"10",X"08",X"10",X"08",X"30",X"40",X"80",X"07",X"00",X"88",X"88",
|
||||
X"10",X"0C",X"02",X"01",X"E0",X"00",X"11",X"11",X"00",X"20",X"20",X"10",X"10",X"08",X"10",X"08",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"1E",X"F0",X"80",X"00",X"07",
|
||||
X"00",X"00",X"80",X"71",X"0F",X"01",X"00",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"80",X"00",X"18",X"07",X"00",X"00",
|
||||
X"C0",X"00",X"01",X"00",X"18",X"E0",X"00",X"00",X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"11",X"10",X"10",X"10",X"00",X"00",X"00",X"04",X"08",X"88",X"84",X"C3",X"00",X"00",X"20",X"1C",
|
||||
X"10",X"11",X"21",X"C3",X"00",X"00",X"04",X"31",X"88",X"08",X"08",X"08",X"10",X"10",X"10",X"20",
|
||||
X"04",X"08",X"08",X"08",X"10",X"10",X"10",X"11",X"1C",X"20",X"00",X"00",X"C3",X"84",X"88",X"08",
|
||||
X"38",X"04",X"00",X"00",X"C3",X"21",X"11",X"10",X"20",X"10",X"10",X"10",X"08",X"08",X"08",X"88",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"00",X"00",X"07",X"18",X"00",X"80",X"00",X"03",
|
||||
X"00",X"00",X"E0",X"18",X"00",X"01",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",
|
||||
X"06",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"80",X"70",X"00",X"01",X"00",X"00",
|
||||
X"F0",X"00",X"01",X"0E",X"00",X"80",X"00",X"00",X"60",X"00",X"80",X"00",X"00",X"00",X"00",X"00",
|
||||
X"11",X"11",X"11",X"10",X"10",X"08",X"08",X"08",X"08",X"08",X"04",X"84",X"81",X"60",X"00",X"00",
|
||||
X"10",X"10",X"20",X"21",X"81",X"06",X"00",X"00",X"88",X"88",X"88",X"08",X"08",X"10",X"10",X"10",
|
||||
X"08",X"08",X"08",X"10",X"10",X"11",X"11",X"11",X"00",X"00",X"60",X"81",X"84",X"04",X"08",X"08",
|
||||
X"00",X"00",X"06",X"81",X"21",X"20",X"10",X"10",X"10",X"10",X"10",X"08",X"08",X"88",X"88",X"88",
|
||||
X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"06",X"00",X"00",X"01",X"00",X"70",X"80",X"00",X"0F",
|
||||
X"00",X"00",X"80",X"00",X"0E",X"01",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"60",
|
||||
X"07",X"07",X"07",X"3F",X"23",X"77",X"2F",X"0F",X"E8",X"FC",X"E8",X"F8",X"C0",X"E0",X"F0",X"F0",
|
||||
X"09",X"01",X"07",X"03",X"03",X"03",X"03",X"01",X"90",X"80",X"E0",X"C0",X"C0",X"C0",X"C0",X"80",
|
||||
X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"30",X"60",X"60",X"C0",X"C0",X"80",X"C0",X"C0",
|
||||
X"13",X"3B",X"13",X"1F",X"07",X"07",X"07",X"07",X"C0",X"C0",X"C4",X"FE",X"E4",X"E0",X"E0",X"E0",
|
||||
X"1F",X"1F",X"1F",X"3F",X"2F",X"77",X"2F",X"0F",X"A0",X"F0",X"A0",X"E0",X"80",X"E0",X"F0",X"90",
|
||||
X"1F",X"09",X"09",X"03",X"01",X"00",X"00",X"00",X"80",X"E0",X"E0",X"F0",X"F0",X"F8",X"70",X"20",
|
||||
X"30",X"18",X"18",X"0C",X"0C",X"06",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"4F",X"EF",X"4F",X"7F",X"1F",X"1F",X"1F",X"1F",X"00",X"00",X"20",X"F0",X"A0",X"80",X"80",X"80",
|
||||
X"17",X"3F",X"17",X"1F",X"03",X"07",X"0F",X"0F",X"E0",X"E0",X"E0",X"FC",X"C4",X"EE",X"F4",X"F0",
|
||||
X"09",X"01",X"07",X"03",X"03",X"03",X"03",X"01",X"90",X"80",X"E0",X"C0",X"C0",X"C0",X"C0",X"80",
|
||||
X"0C",X"06",X"06",X"03",X"03",X"01",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"C0",
|
||||
X"03",X"03",X"43",X"7F",X"47",X"07",X"07",X"07",X"C8",X"DC",X"C8",X"F8",X"E0",X"E0",X"E0",X"E0",
|
||||
X"01",X"01",X"09",X"1F",X"09",X"07",X"0F",X"09",X"FA",X"FF",X"FA",X"FE",X"F0",X"E0",X"E0",X"F0",
|
||||
X"01",X"07",X"07",X"0F",X"0F",X"1F",X"0E",X"04",X"F8",X"90",X"90",X"C0",X"80",X"00",X"00",X"00",
|
||||
X"03",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"C0",X"C0",X"60",X"F0",X"F0",
|
||||
X"04",X"0E",X"04",X"07",X"01",X"01",X"01",X"01",X"F0",X"F0",X"F2",X"FF",X"FA",X"F8",X"F8",X"F8",
|
||||
X"8C",X"08",X"DD",X"CB",X"0A",X"76",X"28",X"05",X"CD",X"E7",X"31",X"28",X"0F",X"01",X"04",X"00",
|
||||
X"21",X"11",X"39",X"11",X"15",X"39",X"ED",X"B0",X"DD",X"CB",X"09",X"C6",X"DD",X"CB",X"0E",X"5E",
|
||||
X"20",X"C7",X"CD",X"F9",X"18",X"28",X"C5",X"18",X"62",X"DD",X"CB",X"0E",X"E6",X"CD",X"49",X"1F",
|
||||
X"DA",X"F6",X"11",X"EF",X"3A",X"CA",X"DD",X"11",X"CD",X"0D",X"19",X"0E",X"01",X"CD",X"C0",X"2D",
|
||||
X"0E",X"13",X"DD",X"CB",X"0F",X"56",X"20",X"1E",X"21",X"FB",X"0C",X"CD",X"30",X"00",X"38",X"14",
|
||||
X"DD",X"CB",X"09",X"D6",X"CD",X"0D",X"19",X"0E",X"00",X"CD",X"D8",X"18",X"0E",X"82",X"CD",X"C0",
|
||||
X"2D",X"C3",X"8C",X"08",X"0E",X"07",X"CD",X"73",X"24",X"2E",X"2D",X"41",X"2B",X"DD",X"CB",X"0F",
|
||||
X"56",X"28",X"08",X"21",X"FB",X"0C",X"CD",X"30",X"00",X"28",X"D5",X"0E",X"11",X"CD",X"73",X"19",
|
||||
X"18",X"15",X"DD",X"CB",X"0E",X"66",X"20",X"0F",X"CD",X"F9",X"18",X"16",X"E1",X"CD",X"83",X"1C",
|
||||
X"DD",X"CB",X"09",X"D6",X"C3",X"1D",X"12",X"0E",X"01",X"CD",X"C0",X"2D",X"16",X"E2",X"CD",X"83",
|
||||
X"1C",X"DD",X"CB",X"09",X"F6",X"DD",X"CB",X"09",X"D6",X"C3",X"1C",X"10",X"2A",X"37",X"39",X"DD",
|
||||
X"CB",X"76",X"66",X"C2",X"2C",X"12",X"E5",X"CD",X"E5",X"04",X"E1",X"22",X"37",X"39",X"DD",X"CB",
|
||||
X"0A",X"6E",X"20",X"E1",X"DD",X"36",X"0C",X"07",X"DD",X"CB",X"0A",X"76",X"28",X"05",X"0E",X"6B",
|
||||
X"CD",X"56",X"2B",X"0E",X"6D",X"CD",X"56",X"2B",X"0E",X"02",X"CD",X"59",X"1A",X"CD",X"B8",X"34",
|
||||
X"CD",X"E3",X"18",X"28",X"C0",X"EF",X"2C",X"28",X"14",X"CD",X"F1",X"34",X"CD",X"9E",X"33",X"CD",
|
||||
X"E3",X"18",X"28",X"B1",X"EF",X"2C",X"38",X"F1",X"CD",X"E3",X"18",X"38",X"E8",X"CD",X"8F",X"31",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"7C",X"7C",X"00",X"00",X"00",X"00",X"00",X"00",X"7C",X"7C",X"7C",X"00",X"00",X"00",X"00",X"00",
|
||||
X"7C",X"7C",X"7C",X"7C",X"00",X"00",X"00",X"00",X"7C",X"7C",X"7C",X"7C",X"7C",X"00",X"00",X"00",
|
||||
X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"00",X"00",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"00",
|
||||
X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"CB",X"0A",X"5E",X"20",X"05",X"16",X"49",X"CD",
|
||||
X"83",X"1C",X"DD",X"7E",X"07",X"CD",X"21",X"00",X"18",X"1F",X"26",X"48",X"4B",X"B3",X"9D",X"CB",
|
||||
X"77",X"28",X"3C",X"DD",X"CB",X"08",X"F6",X"DD",X"CB",X"09",X"EE",X"CD",X"49",X"1F",X"28",X"48",
|
||||
X"21",X"8F",X"14",X"CD",X"61",X"14",X"28",X"C2",X"21",X"9A",X"14",X"CD",X"61",X"14",X"28",X"BA",
|
||||
X"CD",X"49",X"1F",X"28",X"33",X"EF",X"24",X"28",X"25",X"CD",X"22",X"1E",X"28",X"25",X"EF",X"28",
|
||||
X"28",X"02",X"37",X"DF",X"CD",X"46",X"13",X"EF",X"29",X"DF",X"CD",X"5E",X"14",X"28",X"9B",X"AF",
|
||||
X"C3",X"31",X"22",X"1E",X"08",X"18",X"02",X"1E",X"FF",X"CD",X"15",X"20",X"18",X"EC",X"CD",X"BA",
|
||||
X"1F",X"18",X"E7",X"CD",X"0D",X"20",X"18",X"E2",X"DD",X"CB",X"08",X"FE",X"0E",X"02",X"CD",X"73",
|
||||
X"24",X"30",X"2F",X"33",X"0B",X"0E",X"11",X"CD",X"73",X"19",X"CD",X"04",X"20",X"18",X"CB",X"DD",
|
||||
X"CB",X"08",X"56",X"20",X"1C",X"DD",X"CB",X"08",X"C6",X"DD",X"CB",X"0A",X"5E",X"20",X"12",X"DD",
|
||||
X"7E",X"03",X"E6",X"0F",X"20",X"06",X"DD",X"CB",X"09",X"6E",X"28",X"05",X"16",X"29",X"CD",X"83",
|
||||
X"1C",X"CD",X"F3",X"1F",X"18",X"A4",X"CD",X"15",X"25",X"18",X"CF",X"CD",X"46",X"13",X"CD",X"3F",
|
||||
X"20",X"EF",X"2C",X"38",X"06",X"CD",X"46",X"13",X"CD",X"5C",X"20",X"EF",X"5D",X"DF",X"18",X"8A",
|
||||
X"CD",X"49",X"1F",X"DF",X"DD",X"CB",X"08",X"FE",X"0E",X"0A",X"CD",X"73",X"24",X"0A",X"09",X"08",
|
||||
X"01",X"0E",X"08",X"11",X"68",X"84",X"92",X"A1",X"E0",X"20",X"10",X"2C",X"43",X"91",X"0A",X"21",
|
||||
X"92",X"85",X"48",X"21",X"12",X"0C",X"02",X"01",X"11",X"0A",X"92",X"04",X"22",X"5E",X"40",X"80",
|
||||
X"19",X"26",X"40",X"92",X"A5",X"88",X"80",X"94",X"00",X"E8",X"34",X"02",X"09",X"91",X"22",X"42",
|
||||
X"AA",X"41",X"50",X"2D",X"02",X"04",X"04",X"03",X"24",X"54",X"8A",X"04",X"18",X"60",X"80",X"80",
|
||||
X"0C",X"13",X"20",X"45",X"4A",X"91",X"80",X"89",X"C0",X"30",X"8C",X"04",X"22",X"12",X"49",X"11",
|
||||
X"92",X"44",X"2A",X"11",X"20",X"16",X"09",X"00",X"29",X"02",X"22",X"44",X"88",X"10",X"90",X"60",
|
||||
X"00",X"00",X"00",X"01",X"03",X"04",X"02",X"00",X"00",X"00",X"00",X"80",X"C0",X"20",X"40",X"04",
|
||||
X"01",X"00",X"04",X"40",X"80",X"1B",X"24",X"00",X"80",X"00",X"20",X"42",X"00",X"A2",X"5C",X"00",
|
||||
X"00",X"00",X"00",X"01",X"03",X"04",X"02",X"00",X"00",X"00",X"00",X"80",X"C0",X"20",X"40",X"00",
|
||||
X"01",X"00",X"00",X"04",X"01",X"4B",X"10",X"00",X"80",X"00",X"00",X"40",X"00",X"66",X"92",X"00",
|
||||
X"00",X"07",X"08",X"11",X"0F",X"04",X"22",X"70",X"00",X"E0",X"10",X"88",X"F0",X"20",X"44",X"0E",
|
||||
X"F9",X"FC",X"F0",X"E0",X"F1",X"F1",X"DF",X"80",X"9F",X"3F",X"0F",X"07",X"8F",X"8F",X"FB",X"01",
|
||||
X"03",X"04",X"09",X"14",X"63",X"A4",X"9C",X"42",X"B0",X"50",X"0C",X"B2",X"45",X"3A",X"C5",X"11",
|
||||
X"4A",X"24",X"43",X"2D",X"42",X"28",X"15",X"02",X"8A",X"66",X"19",X"85",X"EA",X"14",X"60",X"80",
|
||||
X"0C",X"13",X"2A",X"15",X"24",X"A2",X"A2",X"99",X"D0",X"28",X"54",X"24",X"AB",X"29",X"52",X"49",
|
||||
X"4C",X"95",X"4A",X"29",X"40",X"2A",X"15",X"00",X"15",X"91",X"6A",X"44",X"48",X"30",X"90",X"60",
|
||||
X"01",X"06",X"28",X"57",X"A1",X"98",X"66",X"51",X"40",X"A8",X"14",X"42",X"B4",X"C2",X"24",X"52",
|
||||
X"88",X"A3",X"5C",X"A2",X"4D",X"30",X"0A",X"0D",X"42",X"39",X"25",X"C6",X"28",X"90",X"20",X"C0",
|
||||
X"06",X"09",X"0C",X"12",X"22",X"56",X"89",X"A8",X"00",X"A8",X"54",X"02",X"94",X"52",X"A9",X"32",
|
||||
X"92",X"4A",X"94",X"D5",X"24",X"2A",X"14",X"0B",X"99",X"4A",X"4A",X"24",X"A8",X"54",X"C8",X"30",
|
||||
X"00",X"00",X"60",X"F0",X"70",X"38",X"18",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"00",
|
||||
X"79",X"70",X"20",X"02",X"00",X"01",X"03",X"00",X"72",X"3E",X"1C",X"8C",X"C4",X"90",X"88",X"84",
|
||||
X"84",X"14",X"48",X"08",X"28",X"88",X"10",X"50",X"8C",X"24",X"08",X"50",X"90",X"08",X"58",X"04",
|
||||
X"89",X"22",X"04",X"54",X"4A",X"82",X"26",X"04",X"15",X"22",X"82",X"0A",X"05",X"A1",X"45",X"01",
|
||||
X"2C",X"84",X"08",X"28",X"88",X"06",X"2A",X"01",X"90",X"50",X"28",X"08",X"28",X"C8",X"14",X"84",
|
||||
X"50",X"10",X"B0",X"10",X"20",X"60",X"A0",X"10",X"4A",X"06",X"94",X"04",X"58",X"28",X"10",X"90",
|
||||
X"84",X"20",X"02",X"90",X"4A",X"04",X"91",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"DD",X"CB",X"09",X"46",X"CD",X"BF",X"26",X"CD",X"09",X"27",X"DD",X"CB",X"09",X"66",X"CD",X"BF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"40",X"40",X"40",X"40",X"80",X"80",X"80",X"FF",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"10",X"20",X"20",X"20",X"20",
|
||||
X"04",X"04",X"04",X"04",X"08",X"08",X"08",X"08",X"20",X"20",X"40",X"40",X"40",X"80",X"80",X"80",
|
||||
X"04",X"08",X"08",X"08",X"10",X"10",X"10",X"20",X"00",X"00",X"00",X"00",X"00",X"C0",X"38",X"07",
|
||||
X"00",X"00",X"80",X"70",X"0E",X"01",X"00",X"00",X"E0",X"1C",X"03",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"C0",X"38",X"07",X"00",X"00",X"80",X"70",X"0E",X"01",X"00",X"00",
|
||||
X"E0",X"1C",X"03",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
|
||||
X"80",X"40",X"20",X"10",X"08",X"04",X"02",X"01",X"80",X"40",X"20",X"10",X"08",X"04",X"02",X"01",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"C0",X"30",X"0C",X"03",
|
||||
X"C0",X"30",X"0C",X"03",X"00",X"00",X"00",X"00",X"FF",X"FE",X"FC",X"F8",X"F0",X"F8",X"FC",X"FF",
|
||||
X"80",X"C0",X"E0",X"F0",X"F8",X"FC",X"FE",X"FF",X"01",X"01",X"01",X"02",X"02",X"02",X"04",X"04",
|
||||
X"E0",X"1C",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"70",X"0E",X"01",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"C0",X"38",X"07",X"4F",X"41",X"79",X"A7",X"28",X"EF",X"3E",X"20",
|
||||
X"77",X"23",X"10",X"FC",X"C9",X"3A",X"06",X"00",X"5F",X"C6",X"10",X"CD",X"D0",X"26",X"3A",X"07",
|
||||
X"00",X"93",X"4F",X"11",X"18",X"39",X"E5",X"21",X"13",X"39",X"CD",X"EA",X"27",X"E1",X"A7",X"C8",
|
||||
X"4F",X"06",X"00",X"EB",X"ED",X"B0",X"EB",X"C9",X"11",X"17",X"39",X"E5",X"0E",X"04",X"21",X"15",
|
||||
X"39",X"CD",X"EA",X"27",X"E1",X"18",X"02",X"3E",X"22",X"4F",X"E6",X"1F",X"C3",X"07",X"01",X"2A",
|
||||
X"47",X"39",X"3E",X"84",X"5E",X"BB",X"C8",X"23",X"56",X"ED",X"53",X"11",X"39",X"23",X"22",X"47",
|
||||
X"39",X"21",X"7F",X"39",X"3E",X"09",X"11",X"01",X"28",X"CD",X"FF",X"26",X"3A",X"11",X"39",X"57",
|
||||
X"3E",X"E1",X"CD",X"1A",X"27",X"36",X"20",X"23",X"E5",X"11",X"0E",X"00",X"21",X"0A",X"28",X"3A",
|
||||
X"11",X"39",X"D6",X"3F",X"28",X"15",X"47",X"19",X"7E",X"FE",X"04",X"28",X"07",X"A7",X"20",X"09",
|
||||
X"05",X"23",X"18",X"F4",X"21",X"43",X"29",X"18",X"02",X"10",X"EC",X"7B",X"EB",X"E1",X"CD",X"FF",
|
||||
X"26",X"E5",X"21",X"07",X"00",X"7E",X"2B",X"96",X"4F",X"2B",X"2B",X"11",X"40",X"39",X"3A",X"12",
|
||||
X"39",X"A7",X"ED",X"52",X"EB",X"06",X"04",X"BE",X"28",X"14",X"38",X"11",X"23",X"10",X"F8",X"2B",
|
||||
X"96",X"19",X"2B",X"91",X"28",X"03",X"30",X"FB",X"81",X"1E",X"23",X"18",X"05",X"2B",X"96",X"19",
|
||||
X"1E",X"2A",X"86",X"E1",X"CD",X"D7",X"26",X"01",X"0A",X"00",X"B7",X"ED",X"42",X"73",X"23",X"C3",
|
||||
X"AE",X"26",X"3A",X"07",X"39",X"A1",X"28",X"0C",X"79",X"FE",X"08",X"0E",X"72",X"28",X"02",X"0E",
|
||||
X"44",X"CD",X"56",X"2B",X"3C",X"C9",X"2A",X"17",X"39",X"BF",X"DD",X"CB",X"08",X"56",X"C8",X"AF",
|
||||
X"BD",X"20",X"05",X"BC",X"C8",X"3C",X"BC",X"C8",X"21",X"7F",X"39",X"0E",X"05",X"CD",X"DA",X"26",
|
||||
X"CD",X"09",X"27",X"CD",X"E6",X"26",X"C3",X"AE",X"26",X"1A",X"B9",X"30",X"01",X"4F",X"91",X"12",
|
||||
X"5E",X"23",X"56",X"79",X"E5",X"69",X"26",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"38",X"38",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"1E",X"3F",X"3F",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"01",X"07",X"0F",X"1C",X"38",X"30",X"00",X"00",X"FC",X"FE",X"FF",X"71",X"61",X"E0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"81",X"C3",X"C3",X"00",X"00",X"00",X"00",X"E0",X"F0",X"F8",X"39",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"08",X"38",X"3C",X"DC",X"CE",
|
||||
X"00",X"1C",X"18",X"38",X"38",X"38",X"39",X"38",X"3C",X"FC",X"E0",X"E0",X"E4",X"FC",X"F8",X"E0",
|
||||
X"31",X"30",X"30",X"30",X"30",X"30",X"31",X"33",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"C0",X"80",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"70",X"70",X"70",X"30",X"39",X"1D",X"0D",
|
||||
X"E0",X"E1",X"E1",X"C3",X"FE",X"FC",X"F0",X"C0",X"C7",X"9E",X"8F",X"0F",X"0C",X"1C",X"18",X"18",
|
||||
X"18",X"18",X"F8",X"F0",X"70",X"30",X"30",X"61",X"3F",X"30",X"30",X"60",X"60",X"E0",X"C0",X"C0",
|
||||
X"0C",X"1F",X"1F",X"3B",X"30",X"70",X"70",X"E0",X"00",X"00",X"80",X"C0",X"C0",X"E0",X"E0",X"E0",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"03",X"03",
|
||||
X"07",X"1F",X"7F",X"F8",X"D8",X"9C",X"9C",X"0E",X"81",X"E1",X"F0",X"78",X"38",X"38",X"38",X"38",
|
||||
X"CF",X"C7",X"C7",X"E3",X"E1",X"E1",X"60",X"70",X"38",X"38",X"A8",X"F0",X"F0",X"F0",X"F0",X"F0",
|
||||
X"60",X"60",X"60",X"60",X"60",X"70",X"70",X"76",X"3F",X"3E",X"3E",X"37",X"33",X"31",X"30",X"30",
|
||||
X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"01",X"03",X"03",X"03",X"03",X"06",X"04",X"00",X"80",X"80",X"80",X"80",X"80",X"00",X"00",X"00",
|
||||
X"38",X"30",X"30",X"70",X"70",X"71",X"01",X"00",X"61",X"E1",X"C3",X"C3",X"C3",X"87",X"86",X"01",
|
||||
X"C0",X"81",X"81",X"03",X"03",X"07",X"0E",X"0E",X"E1",X"C1",X"C7",X"FF",X"F8",X"60",X"70",X"70",
|
||||
X"C3",X"C7",X"8C",X"1C",X"38",X"30",X"70",X"70",X"FF",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"C0",X"E0",X"70",X"38",X"38",X"3C",X"3C",X"3C",X"00",X"00",X"00",X"00",X"00",X"10",X"38",X"70",
|
||||
X"03",X"03",X"03",X"03",X"03",X"01",X"00",X"00",X"0E",X"0E",X"0E",X"87",X"87",X"E7",X"F3",X"7B",
|
||||
X"38",X"70",X"E0",X"E0",X"E0",X"F8",X"3C",X"8F",X"70",X"70",X"30",X"38",X"38",X"38",X"38",X"20",
|
||||
X"70",X"70",X"30",X"20",X"00",X"00",X"00",X"00",X"3E",X"3E",X"20",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"70",X"30",X"38",X"08",X"00",X"00",X"00",X"00",X"70",X"70",X"38",X"38",X"1C",X"0F",X"07",X"01",
|
||||
X"00",X"00",X"00",X"00",X"01",X"8F",X"FE",X"F8",X"38",X"38",X"71",X"E3",X"C7",X"0E",X"0C",X"1C",
|
||||
X"60",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"03",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"87",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",
|
||||
X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"38",X"70",X"F8",X"7C",X"1C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
|
||||
X"2C",X"7E",X"4F",X"3C",X"C8",X"E5",X"CD",X"56",X"2B",X"E1",X"23",X"18",X"F4",X"CD",X"4E",X"1A",
|
||||
X"2A",X"6F",X"39",X"EB",X"CD",X"AE",X"2D",X"C4",X"60",X"2D",X"3E",X"C0",X"CD",X"E5",X"33",X"11",
|
||||
X"AF",X"3B",X"18",X"63",X"CD",X"7C",X"2D",X"2A",X"73",X"39",X"73",X"23",X"72",X"C9",X"2A",X"9C",
|
||||
X"37",X"3E",X"67",X"CD",X"E0",X"33",X"2A",X"C0",X"37",X"3E",X"69",X"CD",X"E0",X"33",X"2A",X"61",
|
||||
X"39",X"3E",X"6D",X"CD",X"E0",X"33",X"CD",X"7C",X"2D",X"ED",X"53",X"61",X"39",X"C9",X"ED",X"5B",
|
||||
X"6F",X"39",X"2A",X"61",X"39",X"CD",X"60",X"2D",X"3E",X"CD",X"CD",X"E5",X"33",X"22",X"61",X"39",
|
||||
X"3E",X"C7",X"CD",X"E5",X"33",X"EB",X"3E",X"C9",X"CD",X"E5",X"33",X"18",X"1A",X"18",X"48",X"FD",
|
||||
X"6E",X"02",X"FD",X"66",X"03",X"2B",X"22",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
@@ -0,0 +1,816 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Crazy climber - Dar - June 2018
|
||||
----------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity crazy_climber is
|
||||
port(
|
||||
clock_12 : in std_logic;
|
||||
reset : in std_logic;
|
||||
video_r : out std_logic_vector(2 downto 0);
|
||||
video_g : out std_logic_vector(2 downto 0);
|
||||
video_b : out std_logic_vector(1 downto 0);
|
||||
video_hb : out std_logic;
|
||||
video_vb : out std_logic;
|
||||
video_hs : out std_logic;
|
||||
video_vs : out std_logic;
|
||||
audio_out : out std_logic_vector(15 downto 0);
|
||||
start2 : in std_logic;
|
||||
start1 : in std_logic;
|
||||
coin1 : in std_logic;
|
||||
right1 : in std_logic;
|
||||
left1 : in std_logic;
|
||||
fire1 : in std_logic;
|
||||
right2 : in std_logic;
|
||||
left2 : in std_logic;
|
||||
fire2 : in std_logic
|
||||
);
|
||||
end crazy_climber;
|
||||
|
||||
architecture struct of crazy_climber is
|
||||
|
||||
-- clocks
|
||||
signal clock_12n : std_logic;
|
||||
signal reset_n : std_logic;
|
||||
|
||||
-- video syncs
|
||||
signal hsync : std_logic;
|
||||
signal vsync : std_logic;
|
||||
signal hblank : std_logic;
|
||||
signal vblank : std_logic;
|
||||
|
||||
-- global synchronisation
|
||||
signal ena_pixel : std_logic := '0';
|
||||
signal is_sprite : std_logic;
|
||||
signal sprite : std_logic_vector(2 downto 0);
|
||||
signal x_tile : std_logic_vector(4 downto 0);
|
||||
signal y_tile : std_logic_vector(4 downto 0);
|
||||
signal x_pixel : std_logic_vector(2 downto 0);
|
||||
signal y_pixel : std_logic_vector(2 downto 0);
|
||||
signal y_line : std_logic_vector(7 downto 0);
|
||||
|
||||
signal y_sp_bg : std_logic_vector(7 downto 0);
|
||||
signal y_line_shift : std_logic_vector(7 downto 0);
|
||||
signal attr_sp : std_logic_vector(7 downto 0);
|
||||
signal attr_sp_bg : std_logic_vector(7 downto 0);
|
||||
signal bg_tile_code : std_logic_vector(7 downto 0);
|
||||
|
||||
signal tile_graph_rom_addr : std_logic_vector(12 downto 0);
|
||||
signal tile_graph_rom_addr_mod: std_logic_vector(11 downto 0);
|
||||
signal tile_graph_rom_bit0_do : std_logic_vector(7 downto 0);
|
||||
signal tile_graph_rom_bit1_do : std_logic_vector(7 downto 0);
|
||||
|
||||
signal big_sprite_tile_rom_addr : std_logic_vector(10 downto 0);
|
||||
signal big_sprite_tile_rom_bit0_do : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_tile_rom_bit1_do : std_logic_vector(7 downto 0);
|
||||
|
||||
-- background and sprite tiles and graphics
|
||||
signal tile_code : std_logic_vector(12 downto 0);
|
||||
signal tile_color : std_logic_vector(3 downto 0);
|
||||
signal tile_graph1 : std_logic_vector(7 downto 0);
|
||||
signal tile_graph2 : std_logic_vector(7 downto 0);
|
||||
signal x_sprite : std_logic_vector(7 downto 0);
|
||||
signal y_sprite : std_logic_vector(7 downto 0);
|
||||
signal keep_sprite : std_logic;
|
||||
|
||||
signal tile_color_r : std_logic_vector(3 downto 0);
|
||||
signal tile_graph1_r : std_logic_vector(7 downto 0);
|
||||
signal tile_graph2_r : std_logic_vector(7 downto 0);
|
||||
|
||||
signal pixel_color : std_logic_vector(5 downto 0);
|
||||
signal pixel_color_r : std_logic_vector(5 downto 0);
|
||||
|
||||
signal sprite_pixel_color : std_logic_vector(5 downto 0);
|
||||
signal do_palette : std_logic_vector(7 downto 0);
|
||||
|
||||
signal addr_ram_sprite : std_logic_vector(8 downto 0);
|
||||
signal is_sprite_r : std_logic;
|
||||
|
||||
type ram_256x6 is array(0 to 255) of std_logic_vector(5 downto 0);
|
||||
signal ram_sprite : ram_256x6;
|
||||
|
||||
-- big sprite tiles and graphics
|
||||
signal x_big_sprite : std_logic_vector(7 downto 0);
|
||||
signal y_big_sprite : std_logic_vector(7 downto 0);
|
||||
signal y_line_big_sprite_shift: std_logic_vector(7 downto 0);
|
||||
signal attr_big_sprite : std_logic_vector(5 downto 0);
|
||||
|
||||
signal big_sprite_graph1 : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_graph2 : std_logic_vector(7 downto 0);
|
||||
signal xy_big_sprite : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_tile_code : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_tile_code_r : std_logic_vector(7 downto 0);
|
||||
signal is_big_sprite_on : std_logic;
|
||||
signal x_big_sprite_counter : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_graph1_delay : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_graph2_delay : std_logic_vector(7 downto 0);
|
||||
|
||||
signal do_big_sprite_palette : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_pixel_color : std_logic_vector(4 downto 0);
|
||||
signal big_sprite_pixel_color_r: std_logic_vector(4 downto 0);
|
||||
|
||||
signal video_mux : std_logic_vector(7 downto 0);
|
||||
|
||||
-- Z80 interface
|
||||
signal cpu_clock : std_logic;
|
||||
signal cpu_wr_n : std_logic;
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_do : std_logic_vector(7 downto 0);
|
||||
signal cpu_di : std_logic_vector(7 downto 0);
|
||||
signal cpu_mreq_n : std_logic;
|
||||
signal cpu_m1_n : std_logic;
|
||||
signal cpu_int_n : std_logic;
|
||||
signal cpu_iorq_n : std_logic;
|
||||
signal cpu_di_mem : std_logic_vector(7 downto 0);
|
||||
signal cpu_addr_mod : std_logic_vector(9 downto 0);
|
||||
|
||||
-- misc
|
||||
signal reg4_we_n : std_logic;
|
||||
signal reg5_we_n : std_logic;
|
||||
signal reg6_we_n : std_logic;
|
||||
signal raz_int_n : std_logic;
|
||||
|
||||
signal prog_do : std_logic_vector(7 downto 0);
|
||||
signal wram1_do : std_logic_vector(7 downto 0);
|
||||
signal wram1_we : std_logic;
|
||||
signal wram2_do : std_logic_vector(7 downto 0);
|
||||
signal wram2_we : std_logic;
|
||||
|
||||
signal tile_ram_addr : std_logic_vector(9 downto 0);
|
||||
signal tile_ram_do : std_logic_vector(7 downto 0);
|
||||
signal tile_ram_we : std_logic;
|
||||
signal tile_ram_cs : std_logic;
|
||||
|
||||
signal color_ram_addr: std_logic_vector(9 downto 0);
|
||||
signal color_ram_do : std_logic_vector(7 downto 0);
|
||||
signal color_ram_we : std_logic;
|
||||
signal color_ram_cs : std_logic;
|
||||
|
||||
signal big_sprite_ram_addr : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_ram_do : std_logic_vector(7 downto 0);
|
||||
signal big_sprite_ram_we : std_logic;
|
||||
signal big_sprite_ram_cs : std_logic;
|
||||
|
||||
-- data bus from AY-3-8910
|
||||
signal ym_8910_data : std_logic_vector(7 downto 0);
|
||||
|
||||
-- player I/O
|
||||
signal player1 : std_logic_vector(7 downto 0);
|
||||
signal player2 : std_logic_vector(7 downto 0);
|
||||
signal coins : std_logic_vector(7 downto 0);
|
||||
|
||||
signal video_i : std_logic_vector (7 downto 0);
|
||||
|
||||
-- decryption tool
|
||||
signal prog_do_decrypted : std_logic_vector(7 downto 0);
|
||||
signal index : integer range 0 to 127;
|
||||
signal index_vector : std_logic_vector(6 downto 0);
|
||||
type convtable_t is array(0 to 127) of std_logic_vector(7 downto 0);
|
||||
signal convtable: convtable_t:= (
|
||||
X"44",X"14",X"54",X"10",X"11",X"41",X"05",X"50",X"51",X"00",X"40",X"55",X"45",X"04",X"01",X"15",
|
||||
X"44",X"10",X"15",X"55",X"00",X"41",X"40",X"51",X"14",X"45",X"11",X"50",X"01",X"54",X"04",X"05",
|
||||
X"45",X"10",X"11",X"44",X"05",X"50",X"51",X"04",X"41",X"14",X"15",X"40",X"01",X"54",X"55",X"00",
|
||||
X"04",X"51",X"45",X"00",X"44",X"10",X"ff",X"55",X"11",X"54",X"50",X"40",X"05",X"ff",X"14",X"01",
|
||||
X"54",X"51",X"15",X"45",X"44",X"01",X"11",X"41",X"04",X"55",X"50",X"ff",X"00",X"10",X"40",X"ff",
|
||||
X"ff",X"54",X"14",X"50",X"51",X"01",X"ff",X"40",X"41",X"10",X"00",X"55",X"05",X"44",X"11",X"45",
|
||||
X"51",X"04",X"10",X"ff",X"50",X"40",X"00",X"ff",X"41",X"01",X"05",X"15",X"11",X"14",X"44",X"54",
|
||||
X"ff",X"ff",X"54",X"01",X"15",X"40",X"45",X"41",X"51",X"04",X"50",X"05",X"11",X"44",X"10",X"14");
|
||||
|
||||
begin
|
||||
|
||||
clock_12n <= not clock_12;
|
||||
reset_n <= not reset;
|
||||
|
||||
|
||||
-----------------------
|
||||
-- Enable pixel counter
|
||||
-----------------------
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
ena_pixel <= not ena_pixel;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------
|
||||
-- video output
|
||||
------------------
|
||||
video_mux <= do_palette when is_big_sprite_on = '0' else do_big_sprite_palette;
|
||||
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
if ena_pixel = '1' then
|
||||
if hblank = '0' then
|
||||
video_i <= video_mux;
|
||||
else
|
||||
video_i <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
video_r <= video_i(2 downto 0);
|
||||
video_g <= video_i(5 downto 3);
|
||||
video_b <= video_i(7 downto 6);
|
||||
video_hb <= hblank;
|
||||
video_vb <= vblank;
|
||||
video_hs <= hsync;
|
||||
video_vs <= vsync;
|
||||
|
||||
------------------
|
||||
-- player controls
|
||||
------------------
|
||||
player1 <= right1 & left1 & "00000" & fire1;
|
||||
player2 <= right2 & left2 & "00000" & fire2;
|
||||
coins <= ("0001" & start2 & start1 & '0' & coin1); -- upright cabinet
|
||||
|
||||
-----------------------
|
||||
-- cpu write addressing
|
||||
-----------------------
|
||||
wram2_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "01100" else '0'; -- 6000-67ff (ckong)
|
||||
--wram1_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "01101" else '0'; -- 6800-6bff (ckong)
|
||||
wram1_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10000" else '0'; -- 8000-87ff (cclimber)
|
||||
|
||||
tile_ram_cs <= '1' when cpu_addr(15 downto 11) = "10010" else '0'; -- 9000-93ff mirror 9400-97ff
|
||||
color_ram_cs <= '1' when cpu_addr(15 downto 11) = "10011" else '0'; -- 9800-9bff
|
||||
big_sprite_ram_cs <= '1' when cpu_addr(15 downto 8) = "10001000" else '0'; -- 8800-88ff
|
||||
|
||||
reg4_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10100" else '1';
|
||||
reg5_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10101" else '1';
|
||||
reg6_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10110" else '1';
|
||||
|
||||
---------------------------
|
||||
-- enable/disable interrupt
|
||||
---------------------------
|
||||
process (cpu_clock)
|
||||
begin
|
||||
if falling_edge(cpu_clock) then
|
||||
if cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
|
||||
raz_int_n <= cpu_do(0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------
|
||||
-- latch interrupt at last line
|
||||
-------------------------------
|
||||
process(clock_12, raz_int_n)
|
||||
begin
|
||||
if raz_int_n = '0' then
|
||||
cpu_int_n <= '1';
|
||||
else
|
||||
if rising_edge(clock_12) then
|
||||
if y_tile = "11100" and y_pixel = "000" then
|
||||
cpu_int_n <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------
|
||||
-- mux cpu data mem read and io read
|
||||
------------------------------------
|
||||
index_vector <= prog_do(7) & prog_do(1) & cpu_addr(0) & prog_do(6) & prog_do(4) & prog_do(2) & prog_do(0);
|
||||
index <= to_integer(unsigned(index_vector));
|
||||
|
||||
with cpu_m1_n select
|
||||
prog_do_decrypted <=
|
||||
prog_do when '1',
|
||||
(prog_do and X"AA") or convtable(index) when others;
|
||||
|
||||
with cpu_addr(15 downto 11) select
|
||||
cpu_di_mem <=
|
||||
prog_do when "00000", -- 0000-07ff
|
||||
prog_do when "00001", -- 0800-0fff
|
||||
prog_do when "00010", -- 1000-17ff
|
||||
prog_do when "00011", -- 1800-1fff
|
||||
prog_do when "00100", -- 2000-27ff
|
||||
prog_do when "00101", -- 2800-2fff
|
||||
prog_do when "00110", -- 3000-37ff
|
||||
prog_do when "00111", -- 3800-3fff
|
||||
prog_do when "01000", -- 4000-47ff
|
||||
prog_do when "01001", -- 4800-4fff
|
||||
prog_do when "01010", -- 5000-57ff
|
||||
prog_do when "01011", -- 5800-5fff
|
||||
|
||||
-- prog_do_decrypted when "00000", -- 0000-07ff
|
||||
-- prog_do_decrypted when "00001", -- 0800-0fff
|
||||
-- prog_do_decrypted when "00010", -- 1000-17ff
|
||||
-- prog_do_decrypted when "00011", -- 1800-1fff
|
||||
-- prog_do_decrypted when "00100", -- 2000-27ff
|
||||
-- prog_do_decrypted when "00101", -- 2800-2fff
|
||||
-- prog_do_decrypted when "00110", -- 3000-37ff
|
||||
-- prog_do_decrypted when "00111", -- 3800-3fff
|
||||
-- prog_do_decrypted when "01000", -- 4000-47ff
|
||||
-- prog_do_decrypted when "01001", -- 4800-4fff
|
||||
-- prog_do_decrypted when "01010", -- 5000-57ff
|
||||
-- prog_do_decrypted when "01011", -- 5800-5fff
|
||||
-- wram2_do when "01100", -- 6000-67ff ckong only
|
||||
-- wram1_do when "01101", -- 6800-6fff (ram only at 6800-6bff) ckong only
|
||||
wram1_do when "10000", -- 8000-87ff (ram only at 8000-83ff) cclimber only
|
||||
big_sprite_ram_do when "10001", -- 8800-8fff (ram only at 8800-88ff)
|
||||
tile_ram_do when "10010", -- 9000-97ff (ram only at 9000-93ff)
|
||||
color_ram_do when "10011", -- 9800-9fff (ram only at 9800-9bff)
|
||||
player1 when "10100", -- a000
|
||||
player2 when "10101", -- a800
|
||||
"00000000" when "10110", -- b000 - dip switch (upright cabinet)
|
||||
coins when "10111", -- b800
|
||||
"00000000" when others;
|
||||
|
||||
cpu_di <= ym_8910_data when cpu_iorq_n = '0' else cpu_di_mem;
|
||||
|
||||
------------------------------------------------------
|
||||
-- big_sprite_registers (ckong)
|
||||
------------------------------------------------------
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
if cpu_wr_n = '0' and cpu_mreq_n ='0' then
|
||||
if cpu_addr = X"98DD" then attr_big_sprite <= cpu_do(5 downto 0); end if;
|
||||
if cpu_addr = X"98DE" then y_big_sprite <= cpu_do; end if;
|
||||
if cpu_addr = X"98DF" then x_big_sprite <= cpu_do; end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------
|
||||
-- cpu addressing mode for color ram 98XX (ckong)
|
||||
------------------------------------------------------
|
||||
cpu_addr_mod <= cpu_addr(10 downto 6) & cpu_addr(4 downto 0);
|
||||
|
||||
-------------------------------------
|
||||
-- color ram addressing scheme
|
||||
-------------------------------------
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
color_ram_we <= '0';
|
||||
case x_pixel is
|
||||
|
||||
when "000" =>
|
||||
if is_sprite = '1' then
|
||||
color_ram_addr <= "00010" & sprite & "10"; -- y sprite -- ckong (color ram 040-05f)
|
||||
else
|
||||
color_ram_addr <= "00000" & x_tile;-- bg scroll column -- ckong (color ram 000-01f)
|
||||
end if;
|
||||
if ena_pixel = '1' then y_sp_bg <= color_ram_do; end if;
|
||||
|
||||
when "010" =>
|
||||
if is_sprite = '1' then
|
||||
color_ram_addr <= "00010" & sprite & "01"; -- color sprite -- ckong (color ram 040-05f)
|
||||
else
|
||||
color_ram_addr <= '1' & y_line_shift(7 downto 4) & x_tile; -- color background -- ckong (color ram 040-05f)
|
||||
end if;
|
||||
if ena_pixel = '1' then attr_sp_bg <= color_ram_do; end if;
|
||||
|
||||
when "100" =>
|
||||
if is_sprite = '1' then
|
||||
color_ram_addr <= "00010" & sprite & "00"; -- tile sprite -- ckong (color ram 040-05f)
|
||||
else
|
||||
color_ram_addr <= (others => '0');
|
||||
end if;
|
||||
if ena_pixel = '1' then attr_sp <= color_ram_do; end if;
|
||||
|
||||
when "110" =>
|
||||
if is_sprite = '1' then
|
||||
color_ram_addr <= "00010" & sprite & "11"; -- x sprite -- ckong (color ram 040-05f)
|
||||
else
|
||||
color_ram_addr <= (others => '0');
|
||||
end if;
|
||||
if ena_pixel = '1' then x_sprite <= color_ram_do; end if;
|
||||
|
||||
when others =>
|
||||
color_ram_addr <= cpu_addr_mod;
|
||||
color_ram_we <= not(cpu_wr_n) and not(cpu_mreq_n) and color_ram_cs;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------
|
||||
-- tile ram addressing scheme
|
||||
-------------------------------------
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
tile_ram_we <= '0';
|
||||
case x_pixel is
|
||||
|
||||
when "100" =>
|
||||
tile_ram_addr <= y_line_shift(7 downto 3) & x_tile;-- bg tile code
|
||||
|
||||
when others =>
|
||||
tile_ram_addr <= cpu_addr(9 downto 0);
|
||||
tile_ram_we <= not(cpu_wr_n) and not(cpu_mreq_n) and tile_ram_cs;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------
|
||||
-- tile graph rom addressing scheme
|
||||
-------------------------------------
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
case x_pixel is
|
||||
|
||||
when "100" =>
|
||||
if ena_pixel = '1' then
|
||||
bg_tile_code <= tile_ram_do;
|
||||
end if;
|
||||
|
||||
when "110" =>
|
||||
if is_sprite = '1' then
|
||||
case attr_sp(7 downto 6) is
|
||||
when "00" => tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & attr_sp(5 downto 0) & ((y_line_shift(3) & x_tile(0) & y_line_shift(2 downto 0)) xor "00000");
|
||||
when "01" => tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & attr_sp(5 downto 0) & ((y_line_shift(3) & x_tile(0) & y_line_shift(2 downto 0)) xor "01000");
|
||||
when "10" => tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & attr_sp(5 downto 0) & ((y_line_shift(3) & x_tile(0) & y_line_shift(2 downto 0)) xor "10111");
|
||||
when others => tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & attr_sp(5 downto 0) & ((y_line_shift(3) & x_tile(0) & y_line_shift(2 downto 0)) xor "11111");
|
||||
end case;
|
||||
else
|
||||
if attr_sp_bg(7) = '0' then
|
||||
tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & bg_tile_code & y_line_shift(2 downto 0);
|
||||
else
|
||||
tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & bg_tile_code & not(y_line_shift(2 downto 0));
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when "111" =>
|
||||
if ena_pixel = '1' then
|
||||
tile_graph1_r <= tile_graph_rom_bit0_do;
|
||||
tile_graph2_r <= tile_graph_rom_bit1_do;
|
||||
tile_color_r <= attr_sp_bg(3 downto 0);
|
||||
|
||||
if (is_sprite = '1' and attr_sp(6) = '1') or (is_sprite = '0' and attr_sp_bg(6) = '1' ) then
|
||||
for i in 0 to 7 loop
|
||||
tile_graph1_r(i) <= tile_graph_rom_bit0_do(7-i);
|
||||
tile_graph2_r(i) <= tile_graph_rom_bit1_do(7-i);
|
||||
end loop;
|
||||
end if;
|
||||
|
||||
is_sprite_r <= is_sprite;
|
||||
|
||||
keep_sprite <= '0';
|
||||
if (y_line_shift(7 downto 4) = "1111") and (x_sprite /= X"00") and (y_sp_bg /= X"00") then
|
||||
keep_sprite <= '1';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------
|
||||
-- sprite/ big sprite y position
|
||||
--------------------------------
|
||||
y_line <= y_tile & y_pixel;
|
||||
y_line_shift <= std_logic_vector(unsigned(y_line) + unsigned(y_sp_bg) + 1);
|
||||
y_line_big_sprite_shift <= std_logic_vector(unsigned(y_line) + unsigned(y_big_sprite) + 1);
|
||||
|
||||
------------------------------------------
|
||||
-- read/write sprite line-memory addresing
|
||||
------------------------------------------
|
||||
process (clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
|
||||
if ena_pixel = '1' then
|
||||
addr_ram_sprite <= addr_ram_sprite + '1';
|
||||
end if;
|
||||
|
||||
if is_sprite = '1' and x_pixel = "111" and ena_pixel = '1' and x_tile(0) = '0' then
|
||||
addr_ram_sprite <= '0' & x_sprite;
|
||||
end if;
|
||||
|
||||
if is_sprite = '0' and x_pixel = "111" and ena_pixel = '1' and x_tile = "00000" then
|
||||
addr_ram_sprite <= "000000001";
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-------------------------------------
|
||||
-- read/write sprite line-memory data
|
||||
-------------------------------------
|
||||
process (clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
if ena_pixel = '0' then
|
||||
sprite_pixel_color <= ram_sprite(to_integer(unsigned(addr_ram_sprite)));
|
||||
else
|
||||
if sprite_pixel_color(1 downto 0) = "00" then
|
||||
pixel_color_r <= pixel_color;
|
||||
else
|
||||
pixel_color_r <= sprite_pixel_color;
|
||||
end if;
|
||||
|
||||
if is_sprite_r = '1' then
|
||||
if (keep_sprite = '1') and (addr_ram_sprite(8) = '0') then
|
||||
if sprite_pixel_color(1 downto 0) = "00" then
|
||||
ram_sprite(to_integer(unsigned(addr_ram_sprite))) <= pixel_color;
|
||||
else
|
||||
ram_sprite(to_integer(unsigned(addr_ram_sprite))) <= sprite_pixel_color;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
else
|
||||
ram_sprite(to_integer(unsigned(addr_ram_sprite))) <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- serialize background/sprite graph to pixel + concatenate color
|
||||
-----------------------------------------------------------------
|
||||
pixel_color <= tile_color_r &
|
||||
tile_graph1_r(to_integer(unsigned(not x_pixel))) &
|
||||
tile_graph2_r(to_integer(unsigned(not x_pixel)));
|
||||
|
||||
-------------------------------------
|
||||
-- select big sprite ram tile address
|
||||
-------------------------------------
|
||||
with attr_big_sprite(5 downto 4) select
|
||||
xy_big_sprite <= y_line_big_sprite_shift(6 downto 3) & not(x_big_sprite_counter(6 downto 3)) when "01",
|
||||
not (y_line_big_sprite_shift(6 downto 3)) & not(x_big_sprite_counter(6 downto 3)) when "11",
|
||||
y_line_big_sprite_shift(6 downto 3) & (x_big_sprite_counter(6 downto 3)) when "00",
|
||||
not (y_line_big_sprite_shift(6 downto 3)) & (x_big_sprite_counter(6 downto 3)) when others;
|
||||
|
||||
----------------------------------------
|
||||
-- select big sprite graphic rom address
|
||||
----------------------------------------
|
||||
with attr_big_sprite(5) select
|
||||
big_sprite_tile_rom_addr <= big_sprite_tile_code_r & y_line_big_sprite_shift(2 downto 0) when '0',
|
||||
big_sprite_tile_code_r & not (y_line_big_sprite_shift(2 downto 0)) when others;
|
||||
|
||||
-------------------------------------
|
||||
-- big sprite ram addressing scheme
|
||||
-------------------------------------
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
big_sprite_ram_we <= '0';
|
||||
case x_pixel is
|
||||
|
||||
when "000" =>
|
||||
big_sprite_ram_addr <= xy_big_sprite;
|
||||
if ena_pixel = '1' then
|
||||
big_sprite_tile_code <= big_sprite_ram_do;
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
big_sprite_ram_addr <= cpu_addr(7 downto 0);
|
||||
big_sprite_ram_we <= not(cpu_wr_n) and not(cpu_mreq_n) and big_sprite_ram_cs;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------
|
||||
-- big sprite tile graph rom reading
|
||||
-------------------------------------
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
|
||||
if ena_pixel = '1' then
|
||||
x_big_sprite_counter <= x_big_sprite_counter + '1';
|
||||
end if;
|
||||
|
||||
if is_sprite = '1' and sprite = "110" and ena_pixel = '1' then
|
||||
x_big_sprite_counter <= std_logic_vector(to_unsigned(120,8) + unsigned(x_big_sprite and X"F8"));
|
||||
end if;
|
||||
|
||||
|
||||
if x_big_sprite_counter(2 downto 0) = "111" and ena_pixel = '1' then
|
||||
big_sprite_tile_code_r <= big_sprite_tile_code;
|
||||
|
||||
big_sprite_graph1 <= big_sprite_tile_rom_bit0_do;
|
||||
big_sprite_graph2 <= big_sprite_tile_rom_bit1_do;
|
||||
if attr_big_sprite(4) = '0' then
|
||||
for i in 0 to 7 loop
|
||||
big_sprite_graph1(i) <= big_sprite_tile_rom_bit0_do(7-i);
|
||||
big_sprite_graph2(i) <= big_sprite_tile_rom_bit1_do(7-i);
|
||||
end loop;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------
|
||||
-- serialize big sprite graph to pixel + concatenate color
|
||||
-- clip big sprite display
|
||||
-----------------------------------------------------------------
|
||||
process(clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
if ena_pixel = '1' then
|
||||
big_sprite_graph1_delay <= big_sprite_graph1_delay(6 downto 0) & big_sprite_graph1(to_integer(unsigned(x_big_sprite_counter(2 downto 0))));
|
||||
big_sprite_graph2_delay <= big_sprite_graph2_delay(6 downto 0) & big_sprite_graph2(to_integer(unsigned(x_big_sprite_counter(2 downto 0))));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
big_sprite_pixel_color <= attr_big_sprite(2 downto 0) &
|
||||
big_sprite_graph1_delay(to_integer(unsigned(not x_big_sprite(2 downto 0)))) &
|
||||
big_sprite_graph2_delay(to_integer(unsigned(not x_big_sprite(2 downto 0)))) ;
|
||||
|
||||
process (clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
big_sprite_pixel_color_r <= big_sprite_pixel_color;
|
||||
|
||||
if big_sprite_pixel_color_r(1 downto 0) /= "00" and y_line_big_sprite_shift(7) = '1' and
|
||||
x_big_sprite_counter >= (X"1F") and
|
||||
x_big_sprite_counter < (X"9F") then
|
||||
is_big_sprite_on <= '1';
|
||||
else
|
||||
is_big_sprite_on <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Sync and video counters
|
||||
video : entity work.video_gen
|
||||
port map (
|
||||
clock_12 => clock_12,
|
||||
ena_pixel => ena_pixel,
|
||||
hsync => hsync,
|
||||
vsync => vsync,
|
||||
csync => open,
|
||||
hblank => hblank,
|
||||
vblank => vblank,
|
||||
|
||||
is_sprite => is_sprite,
|
||||
sprite => sprite,
|
||||
x_tile => x_tile,
|
||||
y_tile => y_tile,
|
||||
x_pixel => x_pixel,
|
||||
y_pixel => y_pixel,
|
||||
|
||||
cpu_clock => cpu_clock
|
||||
);
|
||||
|
||||
-- sprite palette rom
|
||||
palette : entity work.cclimber_palette
|
||||
port map (
|
||||
addr => pixel_color_r,
|
||||
clk => clock_12,
|
||||
data => do_palette
|
||||
);
|
||||
|
||||
-- big sprite palette rom
|
||||
big_sprite_palette : entity work.cclimber_big_sprite_palette
|
||||
port map (
|
||||
addr => big_sprite_pixel_color_r,
|
||||
clk => clock_12,
|
||||
data => do_big_sprite_palette
|
||||
);
|
||||
|
||||
-- Z80
|
||||
Z80 : entity work.T80s
|
||||
generic map(Mode => 0, T2Write => 1, IOWait => 1)
|
||||
port map(
|
||||
RESET_n => reset_n,
|
||||
CLK_n => cpu_clock,
|
||||
WAIT_n => '1',
|
||||
INT_n => '1',
|
||||
NMI_n => cpu_int_n,
|
||||
BUSRQ_n => '1',
|
||||
M1_n => cpu_m1_n,
|
||||
MREQ_n => cpu_mreq_n,
|
||||
IORQ_n => cpu_iorq_n,
|
||||
RD_n => open,
|
||||
WR_n => cpu_wr_n,
|
||||
RFSH_n => open,
|
||||
HALT_n => open,
|
||||
BUSAK_n => open,
|
||||
A => cpu_addr,
|
||||
DI => cpu_di,
|
||||
DO => cpu_do
|
||||
);
|
||||
|
||||
|
||||
-- program rom
|
||||
program : entity work.cclimber_program
|
||||
port map (
|
||||
addr => cpu_addr(14 downto 0),
|
||||
clk => clock_12n,
|
||||
data => prog_do
|
||||
);
|
||||
|
||||
-- working ram1 - 6800-6bff (ckong)
|
||||
-- working ram1 - 8000-83ff (cclimber)
|
||||
wram1 : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clock_12n,
|
||||
we => wram1_we,
|
||||
addr => cpu_addr( 10 downto 0),
|
||||
d => cpu_do,
|
||||
q => wram1_do
|
||||
);
|
||||
|
||||
---- working ram2 - 6000-67ff (ckong only)
|
||||
--wram2 : entity work.gen_ram
|
||||
--generic map( dWidth => 8, aWidth => 11)
|
||||
--port map(
|
||||
-- clk => clock_12n,
|
||||
-- we => wram2_we,
|
||||
-- addr => cpu_addr( 10 downto 0),
|
||||
-- d => cpu_do,
|
||||
-- q => wram2_do
|
||||
--);
|
||||
|
||||
-- tile_ram - 9000-93ff
|
||||
tile_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 10)
|
||||
port map(
|
||||
clk => clock_12n,
|
||||
we => tile_ram_we,
|
||||
addr => tile_ram_addr,
|
||||
d => cpu_do,
|
||||
q => tile_ram_do
|
||||
);
|
||||
|
||||
-- color_ram - 9800-9bff (9800-981F = 9820-983f ...)
|
||||
color_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 10)
|
||||
port map(
|
||||
clk => clock_12n,
|
||||
we => color_ram_we,
|
||||
addr => color_ram_addr,
|
||||
d => cpu_do,
|
||||
q => color_ram_do
|
||||
);
|
||||
|
||||
-- big_sprite_tile_ram - 8800-88ff
|
||||
big_sprite_tile_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 8)
|
||||
port map(
|
||||
clk => clock_12n,
|
||||
we => big_sprite_ram_we,
|
||||
addr => big_sprite_ram_addr,
|
||||
d => cpu_do,
|
||||
q => big_sprite_ram_do
|
||||
);
|
||||
|
||||
-- sprite and background graphics rom
|
||||
tile_graph_rom_addr_mod <= tile_graph_rom_addr(12) & tile_graph_rom_addr(10 downto 0);
|
||||
|
||||
tile_bit0 : entity work.cclimber_tile_bit0
|
||||
port map (
|
||||
addr => tile_graph_rom_addr_mod,
|
||||
clk => clock_12n,
|
||||
data => tile_graph_rom_bit0_do
|
||||
);
|
||||
|
||||
-- sprite and background graphics rom
|
||||
tile_bit1 : entity work.cclimber_tile_bit1
|
||||
port map (
|
||||
addr => tile_graph_rom_addr_mod,
|
||||
clk => clock_12n,
|
||||
data => tile_graph_rom_bit1_do
|
||||
);
|
||||
|
||||
-- big sprite graphics rom
|
||||
big_sprite_tile_bit0 : entity work.cclimber_big_sprite_tile_bit0
|
||||
port map (
|
||||
addr => big_sprite_tile_rom_addr,
|
||||
clk => clock_12n,
|
||||
data => big_sprite_tile_rom_bit0_do
|
||||
);
|
||||
|
||||
-- big sprite graphics rom
|
||||
big_sprite_tile_bit1 : entity work.cclimber_big_sprite_tile_bit1
|
||||
port map (
|
||||
addr => big_sprite_tile_rom_addr,
|
||||
clk => clock_12n,
|
||||
data => big_sprite_tile_rom_bit1_do
|
||||
);
|
||||
|
||||
-- sound
|
||||
cclimber_sound : entity work.crazy_climber_sound
|
||||
port map(
|
||||
cpu_clock => cpu_clock,
|
||||
cpu_addr => cpu_addr,
|
||||
cpu_data => cpu_do,
|
||||
cpu_iorq_n => cpu_iorq_n,
|
||||
reg4_we_n => reg4_we_n,
|
||||
reg5_we_n => reg5_we_n,
|
||||
reg6_we_n => reg6_we_n,
|
||||
ym_2149_data => ym_8910_data,
|
||||
sound_sample => audio_out
|
||||
);
|
||||
------------------------------------------
|
||||
end architecture;
|
||||
@@ -0,0 +1,140 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Crazy climber sound AY-3-8910 and samples - Dar - June 2018
|
||||
---------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity crazy_climber_sound is
|
||||
port (
|
||||
cpu_clock : in std_logic;
|
||||
cpu_addr : in std_logic_vector(15 downto 0);
|
||||
cpu_data : in std_logic_vector( 7 downto 0);
|
||||
cpu_iorq_n : in std_logic;
|
||||
reg4_we_n : in std_logic;
|
||||
reg5_we_n : in std_logic;
|
||||
reg6_we_n : in std_logic;
|
||||
ym_2149_data : out std_logic_vector(7 downto 0);
|
||||
sound_sample : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end crazy_climber_sound;
|
||||
|
||||
architecture struct of crazy_climber_sound is
|
||||
|
||||
signal hdiv : std_logic_vector(1 downto 0);
|
||||
signal clock_1_5mhz : std_logic; -- 1.50Mhz
|
||||
signal clock_750khz : std_logic; -- 0.75MHz
|
||||
|
||||
signal ym_2149_audio : std_logic_vector(7 downto 0);
|
||||
|
||||
signal vctr_n : std_logic;
|
||||
signal scs_n : std_logic;
|
||||
signal frequency_div : std_logic_vector( 7 downto 0);
|
||||
|
||||
signal frequency_cnt : std_logic_vector( 7 downto 0);
|
||||
signal frequency_tick : std_logic;
|
||||
signal sample_volume : std_logic_vector( 7 downto 0);
|
||||
signal sample_start1 : std_logic_vector( 7 downto 0);
|
||||
signal sample_start2 : std_logic_vector( 7 downto 0);
|
||||
signal sample_cnt : std_logic_vector(11 downto 0);
|
||||
signal sample_rom_addr : std_logic_vector(12 downto 0);
|
||||
signal sound_data : std_logic_vector( 7 downto 0);
|
||||
signal sample_data : std_logic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
clock_1_5mhz <= hdiv(0);
|
||||
clock_750khz <= hdiv(1);
|
||||
|
||||
process(cpu_clock)
|
||||
begin
|
||||
if falling_edge(cpu_clock) then
|
||||
|
||||
if hdiv = "11" then
|
||||
hdiv <= "00";
|
||||
else
|
||||
hdiv <= std_logic_vector(unsigned(hdiv) + 1);
|
||||
end if;
|
||||
|
||||
if cpu_addr(2 downto 0) = "100" and reg4_we_n = '0' then
|
||||
vctr_n <= cpu_data(0);
|
||||
end if;
|
||||
|
||||
if cpu_addr(2 downto 0) = "111" and reg4_we_n = '0' then
|
||||
scs_n <= cpu_data(0);
|
||||
end if;
|
||||
|
||||
if reg5_we_n = '0' then
|
||||
frequency_div<= cpu_data(7 downto 0);
|
||||
end if;
|
||||
|
||||
if reg6_we_n = '0' then
|
||||
sample_volume<= cpu_data(7 downto 0);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Sample machine
|
||||
|
||||
process(clock_750khz)
|
||||
begin
|
||||
if rising_edge(clock_750khz) then
|
||||
if frequency_cnt = "11111111" then
|
||||
frequency_cnt <= frequency_div;
|
||||
frequency_tick <= '1';
|
||||
else
|
||||
frequency_cnt <= std_logic_vector(unsigned(frequency_cnt) + 1);
|
||||
frequency_tick <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(frequency_tick)
|
||||
begin
|
||||
if rising_edge(frequency_tick) then
|
||||
if vctr_n = '0' then
|
||||
sample_cnt <= sample_start1(5 downto 0) & "000000";
|
||||
else
|
||||
if sound_data = "01110000" then
|
||||
sample_cnt <= sample_cnt;
|
||||
else
|
||||
sample_cnt <= std_logic_vector(unsigned(sample_cnt) + 1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
sound_sample <= std_logic_vector( unsigned(ym_2149_audio) & unsigned(ym_2149_audio));
|
||||
|
||||
|
||||
ym2149 : entity work.ym2149
|
||||
port map (
|
||||
-- data bus
|
||||
I_DA => cpu_data, --: in std_logic_vector(7 downto 0);
|
||||
O_DA => ym_2149_data, --: out std_logic_vector(7 downto 0);
|
||||
O_DA_OE_L => open, --: out std_logic;
|
||||
-- control
|
||||
I_A9_L => '0', --scs_n, --: in std_logic;
|
||||
I_A8 => cpu_iorq_n or cpu_addr(3), --: in std_logic;
|
||||
I_BDIR => not(cpu_iorq_n or cpu_addr(2)), --: in std_logic;
|
||||
I_BC2 => not(cpu_iorq_n or cpu_addr(1)), --: in std_logic;
|
||||
I_BC1 => not(cpu_iorq_n or cpu_addr(0)), --: in std_logic;
|
||||
I_SEL_L => '1', --: in std_logic;
|
||||
-- audio
|
||||
O_AUDIO => ym_2149_audio, --: out std_logic_vector(7 downto 0);
|
||||
-- port a
|
||||
I_IOA => "11111111", --: in std_logic_vector(7 downto 0);
|
||||
O_IOA => sample_start1, --: out std_logic_vector(7 downto 0);
|
||||
O_IOA_OE_L => open, --: out std_logic;
|
||||
-- port b
|
||||
I_IOB => "11111111", --: in std_logic_vector(7 downto 0);
|
||||
O_IOB => sample_start2, --: out std_logic_vector(7 downto 0);
|
||||
O_IOB_OE_L => open, --: out std_logic;
|
||||
|
||||
ENA => '1', --: in std_logic; -- clock enable for higher speed operation
|
||||
RESET_L => '1', --: in std_logic;
|
||||
CLK => clock_1_5mhz --: in std_logic -- note 6 Mhz!
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@@ -0,0 +1,33 @@
|
||||
//
|
||||
// PWM DAC
|
||||
//
|
||||
// MSBI is the highest bit number. NOT amount of bits!
|
||||
//
|
||||
module dac #(parameter MSBI=15, parameter INV=1'b1)
|
||||
(
|
||||
output reg DACout, //Average Output feeding analog lowpass
|
||||
input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
|
||||
input CLK,
|
||||
input RESET
|
||||
);
|
||||
|
||||
reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
|
||||
reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
|
||||
reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
|
||||
reg [MSBI+2:0] DeltaB; //B input of Delta Adder
|
||||
|
||||
always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
|
||||
always @(*) DeltaAdder = DACin + DeltaB;
|
||||
always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
|
||||
|
||||
always @(posedge CLK or posedge RESET) begin
|
||||
if(RESET) begin
|
||||
SigmaLatch <= 1'b1 << (MSBI+1);
|
||||
DACout <= INV;
|
||||
end else begin
|
||||
SigmaLatch <= SigmaAdder;
|
||||
DACout <= SigmaLatch[MSBI+2] ^ INV;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,84 @@
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- Syntiac's generic VHDL support files.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
--
|
||||
-- Modified April 2016 by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- Remove address register when writing
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- gen_rwram.vhd
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- generic ram.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
entity gen_ram is
|
||||
generic (
|
||||
dWidth : integer := 8;
|
||||
aWidth : integer := 10
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
addr : in std_logic_vector((aWidth-1) downto 0);
|
||||
d : in std_logic_vector((dWidth-1) downto 0);
|
||||
q : out std_logic_vector((dWidth-1) downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
architecture rtl of gen_ram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
signal ram: ramDef;
|
||||
|
||||
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
|
||||
signal qReg : std_logic_vector((dWidth-1) downto 0);
|
||||
begin
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Signals to entity interface
|
||||
-- -----------------------------------------------------------------------
|
||||
-- q <= qReg;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory write
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if we = '1' then
|
||||
ram(to_integer(unsigned(addr))) <= d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory read
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
|
||||
-- rAddrReg <= addr;
|
||||
---- qReg <= ram(to_integer(unsigned(addr)));
|
||||
q <= ram(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
--q <= ram(to_integer(unsigned(addr)));
|
||||
end architecture;
|
||||
|
||||
454
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/hq2x.sv
Normal file
454
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/hq2x.sv
Normal file
@@ -0,0 +1,454 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2012-2013 Ludvig Strigeus
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
|
||||
`define BITS_TO_FIT(N) ( \
|
||||
N <= 2 ? 0 : \
|
||||
N <= 4 ? 1 : \
|
||||
N <= 8 ? 2 : \
|
||||
N <= 16 ? 3 : \
|
||||
N <= 32 ? 4 : \
|
||||
N <= 64 ? 5 : \
|
||||
N <= 128 ? 6 : \
|
||||
N <= 256 ? 7 : \
|
||||
N <= 512 ? 8 : \
|
||||
N <=1024 ? 9 : 10 )
|
||||
|
||||
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
wire [DWIDTH:0] out[2];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input [1:0] rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input [1:0] wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
|
||||
wire [DWIDTH:0] out[4];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
|
||||
(
|
||||
input clock,
|
||||
input [DWIDTH:0] data,
|
||||
input [AWIDTH:0] rdaddress,
|
||||
input [AWIDTH:0] wraddress,
|
||||
input wren,
|
||||
output [DWIDTH:0] q
|
||||
);
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (wraddress),
|
||||
.clock0 (clock),
|
||||
.data_a (data),
|
||||
.wren_a (wren),
|
||||
.address_b (rdaddress),
|
||||
.q_b(q),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_b ({(DWIDTH+1){1'b1}}),
|
||||
.eccstatus (),
|
||||
.q_a (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_b = "NONE",
|
||||
altsyncram_component.address_reg_b = "CLOCK0",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = NUMWORDS,
|
||||
altsyncram_component.numwords_b = NUMWORDS,
|
||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
||||
altsyncram_component.widthad_a = AWIDTH+1,
|
||||
altsyncram_component.widthad_b = AWIDTH+1,
|
||||
altsyncram_component.width_a = DWIDTH+1,
|
||||
altsyncram_component.width_b = DWIDTH+1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
endmodule
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module DiffCheck
|
||||
(
|
||||
input [17:0] rgb1,
|
||||
input [17:0] rgb2,
|
||||
output result
|
||||
);
|
||||
|
||||
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
|
||||
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
|
||||
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
|
||||
wire [6:0] t = $signed(r) + $signed(b);
|
||||
wire [6:0] gx = {g[5], g};
|
||||
wire [7:0] y = $signed(t) + $signed(gx);
|
||||
wire [6:0] u = $signed(r) - $signed(b);
|
||||
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
|
||||
|
||||
// if y is inside (-24..24)
|
||||
wire y_inside = (y < 8'h18 || y >= 8'he8);
|
||||
|
||||
// if u is inside (-4, 4)
|
||||
wire u_inside = (u < 7'h4 || u >= 7'h7c);
|
||||
|
||||
// if v is inside (-6, 6)
|
||||
wire v_inside = (v < 8'h6 || v >= 8'hfA);
|
||||
assign result = !(y_inside && u_inside && v_inside);
|
||||
endmodule
|
||||
|
||||
module InnerBlend
|
||||
(
|
||||
input [8:0] Op,
|
||||
input [5:0] A,
|
||||
input [5:0] B,
|
||||
input [5:0] C,
|
||||
output [5:0] O
|
||||
);
|
||||
|
||||
function [8:0] mul6x3;
|
||||
input [5:0] op1;
|
||||
input [2:0] op2;
|
||||
begin
|
||||
mul6x3 = 9'd0;
|
||||
if(op2[0]) mul6x3 = mul6x3 + op1;
|
||||
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
|
||||
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire OpOnes = Op[4];
|
||||
wire [8:0] Amul = mul6x3(A, Op[7:5]);
|
||||
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
|
||||
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
|
||||
wire [8:0] At = Amul;
|
||||
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
|
||||
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
|
||||
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
|
||||
assign O = Op[8] ? A : Res[9:4];
|
||||
endmodule
|
||||
|
||||
module Blend
|
||||
(
|
||||
input [5:0] rule,
|
||||
input disable_hq2x,
|
||||
input [17:0] E,
|
||||
input [17:0] A,
|
||||
input [17:0] B,
|
||||
input [17:0] D,
|
||||
input [17:0] F,
|
||||
input [17:0] H,
|
||||
output [17:0] Result
|
||||
);
|
||||
|
||||
reg [1:0] input_ctrl;
|
||||
reg [8:0] op;
|
||||
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
|
||||
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
|
||||
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
|
||||
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
|
||||
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
|
||||
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
|
||||
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
|
||||
localparam AB = 2'b00;
|
||||
localparam AD = 2'b01;
|
||||
localparam DB = 2'b10;
|
||||
localparam BD = 2'b11;
|
||||
wire is_diff;
|
||||
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
|
||||
|
||||
always @* begin
|
||||
case({!is_diff, rule[5:2]})
|
||||
1,17: {op, input_ctrl} = {BLEND1, AB};
|
||||
2,18: {op, input_ctrl} = {BLEND1, DB};
|
||||
3,19: {op, input_ctrl} = {BLEND1, BD};
|
||||
4,20: {op, input_ctrl} = {BLEND2, DB};
|
||||
5,21: {op, input_ctrl} = {BLEND2, AB};
|
||||
6,22: {op, input_ctrl} = {BLEND2, AD};
|
||||
|
||||
8: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
9: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
10: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
11: {op, input_ctrl} = {BLEND1, AB};
|
||||
12: {op, input_ctrl} = {BLEND1, AB};
|
||||
13: {op, input_ctrl} = {BLEND1, AB};
|
||||
14: {op, input_ctrl} = {BLEND1, DB};
|
||||
15: {op, input_ctrl} = {BLEND1, BD};
|
||||
|
||||
24: {op, input_ctrl} = {BLEND2, DB};
|
||||
25: {op, input_ctrl} = {BLEND5, DB};
|
||||
26: {op, input_ctrl} = {BLEND6, DB};
|
||||
27: {op, input_ctrl} = {BLEND2, DB};
|
||||
28: {op, input_ctrl} = {BLEND4, DB};
|
||||
29: {op, input_ctrl} = {BLEND5, DB};
|
||||
30: {op, input_ctrl} = {BLEND3, BD};
|
||||
31: {op, input_ctrl} = {BLEND3, DB};
|
||||
default: {op, input_ctrl} = 11'bx;
|
||||
endcase
|
||||
|
||||
// Setting op[8] effectively disables HQ2X because blend will always return E.
|
||||
if (disable_hq2x) op[8] = 1;
|
||||
end
|
||||
|
||||
// Generate inputs to the inner blender. Valid combinations.
|
||||
// 00: E A B
|
||||
// 01: E A D
|
||||
// 10: E D B
|
||||
// 11: E B D
|
||||
wire [17:0] Input1 = E;
|
||||
wire [17:0] Input2 = !input_ctrl[1] ? A :
|
||||
!input_ctrl[0] ? D : B;
|
||||
|
||||
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
|
||||
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
|
||||
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
|
||||
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
|
||||
endmodule
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
input clk,
|
||||
input ce_x4,
|
||||
input [DWIDTH:0] inputpixel,
|
||||
input mono,
|
||||
input disable_hq2x,
|
||||
input reset_frame,
|
||||
input reset_line,
|
||||
input [1:0] read_y,
|
||||
input [AWIDTH+1:0] read_x,
|
||||
output [DWIDTH:0] outpixel
|
||||
);
|
||||
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
|
||||
|
||||
wire [5:0] hqTable[256] = '{
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
|
||||
};
|
||||
|
||||
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
|
||||
reg [17:0] A, B, D, F, G, H;
|
||||
reg [7:0] pattern, nextpatt;
|
||||
reg [1:0] i;
|
||||
reg [7:0] y;
|
||||
|
||||
wire curbuf = y[0];
|
||||
reg prevbuf = 0;
|
||||
wire iobuf = !curbuf;
|
||||
|
||||
wire diff0, diff1;
|
||||
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
|
||||
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
|
||||
|
||||
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
|
||||
|
||||
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
|
||||
wire [17:0] blend_result;
|
||||
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
|
||||
|
||||
reg Curr2_addr1;
|
||||
reg [AWIDTH:0] Curr2_addr2;
|
||||
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
|
||||
wire [DWIDTH:0] Curr2tmp;
|
||||
|
||||
reg [AWIDTH:0] wrin_addr2;
|
||||
reg [DWIDTH:0] wrpix;
|
||||
reg wrin_en;
|
||||
|
||||
function [17:0] h2rgb;
|
||||
input [8:0] v;
|
||||
begin
|
||||
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [8:0] rgb2h;
|
||||
input [17:0] v;
|
||||
begin
|
||||
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(Curr2_addr2),
|
||||
.rdbuf(Curr2_addr1),
|
||||
.q(Curr2tmp),
|
||||
|
||||
.wraddr(wrin_addr2),
|
||||
.wrbuf(iobuf),
|
||||
.data(wrpix),
|
||||
.wren(wrin_en)
|
||||
);
|
||||
|
||||
reg [1:0] wrout_addr1;
|
||||
reg [AWIDTH+1:0] wrout_addr2;
|
||||
reg wrout_en;
|
||||
reg [DWIDTH:0] wrdata;
|
||||
|
||||
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(read_x),
|
||||
.rdbuf(read_y),
|
||||
.q(outpixel),
|
||||
|
||||
.wraddr(wrout_addr2),
|
||||
.wrbuf(wrout_addr1),
|
||||
.data(wrdata),
|
||||
.wren(wrout_en)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [AWIDTH:0] offs;
|
||||
reg old_reset_line;
|
||||
reg old_reset_frame;
|
||||
|
||||
wrout_en <= 0;
|
||||
wrin_en <= 0;
|
||||
|
||||
if(ce_x4) begin
|
||||
|
||||
pattern <= new_pattern;
|
||||
|
||||
if(~&offs) begin
|
||||
if (i == 0) begin
|
||||
Curr2_addr1 <= prevbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 1) begin
|
||||
Prev2 <= Curr2;
|
||||
Curr2_addr1 <= curbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 2) begin
|
||||
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
|
||||
wrpix <= inputpixel;
|
||||
wrin_addr2 <= offs;
|
||||
wrin_en <= 1;
|
||||
end
|
||||
if (i == 3) begin
|
||||
offs <= offs + 1'd1;
|
||||
end
|
||||
|
||||
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
|
||||
else wrdata <= blend_result;
|
||||
|
||||
wrout_addr1 <= {curbuf, i[1]};
|
||||
wrout_addr2 <= {offs, i[1]^i[0]};
|
||||
wrout_en <= 1;
|
||||
end
|
||||
|
||||
if(i==3) begin
|
||||
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
|
||||
{A, G} <= {Prev0, Next0};
|
||||
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
|
||||
{Prev0, Prev1} <= {Prev1, Prev2};
|
||||
{Curr0, Curr1} <= {Curr1, Curr2};
|
||||
{Next0, Next1} <= {Next1, Next2};
|
||||
end else begin
|
||||
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
|
||||
{B, F, H, D} <= {F, H, D, B};
|
||||
end
|
||||
|
||||
i <= i + 1'b1;
|
||||
if(old_reset_line && ~reset_line) begin
|
||||
old_reset_frame <= reset_frame;
|
||||
offs <= 0;
|
||||
i <= 0;
|
||||
y <= y + 1'd1;
|
||||
prevbuf <= curbuf;
|
||||
if(old_reset_frame & ~reset_frame) begin
|
||||
y <= 0;
|
||||
prevbuf <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
old_reset_line <= reset_line;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // Hq2x
|
||||
@@ -0,0 +1,530 @@
|
||||
//
|
||||
// mist_io.v
|
||||
//
|
||||
// mist_io for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2015-2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
|
||||
// (Sorgelig)
|
||||
//
|
||||
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
|
||||
// clk_ps2 = clk_sys/(PS2DIV*2)
|
||||
//
|
||||
|
||||
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
(
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
|
||||
// Global clock. It should be around 100MHz (higher is better).
|
||||
input clk_sys,
|
||||
|
||||
// Global SPI clock from ARM. 24MHz
|
||||
input SPI_SCK,
|
||||
|
||||
input CONF_DATA0,
|
||||
input SPI_SS2,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
// output reg [31:0] joystick_2,
|
||||
// output reg [31:0] joystick_3,
|
||||
// output reg [31:0] joystick_4,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
output scandoublerD,
|
||||
output ypbpr,
|
||||
|
||||
output reg [31:0] status,
|
||||
|
||||
// SD config
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output [1:0] img_mounted, // signaling that new image has been mounted
|
||||
output reg [31:0] img_size, // size of image in bytes
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba,
|
||||
input [1:0] sd_rd,
|
||||
input [1:0] sd_wr,
|
||||
output reg sd_ack,
|
||||
output reg sd_ack_conf,
|
||||
|
||||
// SD byte level access. Signals for 2-PORT altsyncram.
|
||||
output reg [8:0] sd_buff_addr,
|
||||
output reg [7:0] sd_buff_dout,
|
||||
input [7:0] sd_buff_din,
|
||||
output reg sd_buff_wr,
|
||||
|
||||
// ps2 keyboard emulation
|
||||
output ps2_kbd_clk,
|
||||
output reg ps2_kbd_data,
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
|
||||
// ps2 alternative interface.
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0,
|
||||
|
||||
// ARM -> FPGA download
|
||||
input ioctl_ce,
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg [7:0] ioctl_index, // menu index used to upload the file
|
||||
output reg ioctl_wr = 0,
|
||||
output reg [24:0] ioctl_addr,
|
||||
output reg [7:0] ioctl_dout
|
||||
);
|
||||
|
||||
reg [7:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
reg [1:0] mount_strobe = 0;
|
||||
assign img_mounted = mount_strobe;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign scandoublerD = but_sw[4];
|
||||
assign ypbpr = but_sw[5];
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire drive_sel = sd_rd[1] | sd_wr[1];
|
||||
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
|
||||
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
|
||||
reg spi_do;
|
||||
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
|
||||
|
||||
reg [7:0] spi_data_out;
|
||||
|
||||
// SPI transmitter
|
||||
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
|
||||
|
||||
reg [7:0] spi_data_in;
|
||||
reg spi_data_ready = 0;
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [31:0] sd_lba_r;
|
||||
reg drive_sel_r;
|
||||
|
||||
if(CONF_DATA0) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= 0;
|
||||
spi_data_out <= core_type;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt <= bit_cnt + 1'd1;
|
||||
sbuf <= {sbuf[5:0], SPI_DI};
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
spi_data_in <= {sbuf, SPI_DI};
|
||||
spi_data_ready <= ~spi_data_ready;
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
|
||||
|
||||
spi_data_out <= 0;
|
||||
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
|
||||
// reading config string
|
||||
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
|
||||
|
||||
// reading sd card status
|
||||
8'h16: if(byte_cnt == 0) begin
|
||||
spi_data_out <= sd_cmd;
|
||||
sd_lba_r <= sd_lba;
|
||||
drive_sel_r <= drive_sel;
|
||||
end else if (byte_cnt == 1) begin
|
||||
spi_data_out <= drive_sel_r;
|
||||
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
|
||||
|
||||
// reading sd card write data
|
||||
8'h18: spi_data_out <= sd_buff_din;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
// transfer to clk_sys domain
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_ss1, old_ss2;
|
||||
reg old_ready1, old_ready2;
|
||||
reg [2:0] b_wr;
|
||||
reg got_ps2 = 0;
|
||||
|
||||
old_ss1 <= CONF_DATA0;
|
||||
old_ss2 <= old_ss1;
|
||||
old_ready1 <= spi_data_ready;
|
||||
old_ready2 <= old_ready1;
|
||||
|
||||
sd_buff_wr <= b_wr[0];
|
||||
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
if(old_ss2) begin
|
||||
got_ps2 <= 0;
|
||||
sd_ack <= 0;
|
||||
sd_ack_conf <= 0;
|
||||
sd_buff_addr <= 0;
|
||||
if(got_ps2) begin
|
||||
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
if(old_ready2 ^ old_ready1) begin
|
||||
|
||||
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
|
||||
if(byte_cnt < 2) begin
|
||||
|
||||
if (cmd == 8'h19) sd_ack_conf <= 1;
|
||||
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
|
||||
mount_strobe <= 0;
|
||||
|
||||
if(cmd == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
// buttons and switches
|
||||
8'h01: but_sw <= spi_data_in;
|
||||
8'h02: joystick_0 <= spi_data_in;
|
||||
8'h03: joystick_1 <= spi_data_in;
|
||||
// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
|
||||
// store incoming ps2 mouse bytes
|
||||
8'h04: begin
|
||||
got_ps2 <= 1;
|
||||
case(byte_cnt)
|
||||
2: ps2_mouse[7:0] <= spi_data_in;
|
||||
3: ps2_mouse[15:8] <= spi_data_in;
|
||||
4: ps2_mouse[23:16] <= spi_data_in;
|
||||
endcase
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
8'h05: begin
|
||||
got_ps2 <= 1;
|
||||
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
|
||||
end
|
||||
|
||||
8'h15: status[7:0] <= spi_data_in;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
8'h19,
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
8'h17: begin
|
||||
sd_buff_dout <= spi_data_in;
|
||||
b_wr <= 1;
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
8'h1a: begin
|
||||
// first byte is joystick index
|
||||
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
|
||||
else if(byte_cnt == 3) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
|
||||
end else if(byte_cnt == 4) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
|
||||
end
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
|
||||
|
||||
// send image info
|
||||
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
|
||||
// status, 32bit version
|
||||
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// PS2 ///////////////////////////////
|
||||
// 8 byte fifos to store ps2 bytes
|
||||
localparam PS2_FIFO_BITS = 3;
|
||||
|
||||
reg clk_ps2;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt == PS2DIV) begin
|
||||
clk_ps2 <= ~clk_ps2;
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// keyboard
|
||||
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_kbd_tx_state;
|
||||
reg [7:0] ps2_kbd_tx_byte;
|
||||
reg ps2_kbd_parity;
|
||||
|
||||
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_kbd_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_kbd_r_inc <= 0;
|
||||
|
||||
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_kbd_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
|
||||
ps2_kbd_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_kbd_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_kbd_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_kbd_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
|
||||
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
|
||||
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
|
||||
if(ps2_kbd_tx_byte[0])
|
||||
ps2_kbd_parity <= !ps2_kbd_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
|
||||
else ps2_kbd_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// mouse
|
||||
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_mouse_tx_state;
|
||||
reg [7:0] ps2_mouse_tx_byte;
|
||||
reg ps2_mouse_parity;
|
||||
|
||||
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_mouse_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_mouse_r_inc <= 0;
|
||||
|
||||
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_mouse_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
|
||||
ps2_mouse_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_mouse_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_mouse_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_mouse_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
|
||||
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
|
||||
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
|
||||
if(ps2_mouse_tx_byte[0])
|
||||
ps2_mouse_parity <= !ps2_mouse_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
|
||||
else ps2_mouse_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// DOWNLOADING ///////////////////////////////
|
||||
|
||||
reg [7:0] data_w;
|
||||
reg [24:0] addr_w;
|
||||
reg rclk = 0;
|
||||
|
||||
localparam UIO_FILE_TX = 8'h53;
|
||||
localparam UIO_FILE_TX_DAT = 8'h54;
|
||||
localparam UIO_FILE_INDEX = 8'h55;
|
||||
|
||||
reg rdownload = 0;
|
||||
|
||||
// data_io has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg [24:0] addr;
|
||||
|
||||
if(SPI_SS2) cnt <= 0;
|
||||
else begin
|
||||
// don't shift in last bit. It is evaluated directly
|
||||
// when writing to ram
|
||||
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
|
||||
|
||||
// count 0-7 8-15 8-15 ...
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
// finished command byte
|
||||
if(cnt == 7) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
// prepare/end transmission
|
||||
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
|
||||
// prepare
|
||||
if(SPI_DI) begin
|
||||
case(ioctl_index[4:0])
|
||||
1: addr <= 25'h200000; // TRD buffer at 2MB
|
||||
2: addr <= 25'h400000; // tape buffer at 4MB
|
||||
default: addr <= 25'h150000; // boot rom
|
||||
endcase
|
||||
rdownload <= 1;
|
||||
end else begin
|
||||
addr_w <= addr;
|
||||
rdownload <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// command 0x54: UIO_FILE_TX
|
||||
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
|
||||
addr_w <= addr;
|
||||
data_w <= {sbuf, SPI_DI};
|
||||
addr <= addr + 1'd1;
|
||||
rclk <= ~rclk;
|
||||
end
|
||||
|
||||
// expose file (menu) index
|
||||
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
|
||||
end
|
||||
end
|
||||
|
||||
// transfer to ioctl_clk domain.
|
||||
// ioctl_index is set before ioctl_download, so it's stable already
|
||||
always@(posedge clk_sys) begin
|
||||
reg rclkD, rclkD2;
|
||||
|
||||
if(ioctl_ce) begin
|
||||
ioctl_download <= rdownload;
|
||||
|
||||
rclkD <= rclk;
|
||||
rclkD2 <= rclkD;
|
||||
ioctl_wr <= 0;
|
||||
|
||||
if(rclkD != rclkD2) begin
|
||||
ioctl_dout <= data_w;
|
||||
ioctl_addr <= addr_w;
|
||||
ioctl_wr <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
194
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/osd.sv
Normal file
194
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/osd.sv
Normal file
@@ -0,0 +1,194 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd (
|
||||
// OSDs pixel clock, should be synchronous to cores pixel clock to
|
||||
// avoid jitter.
|
||||
input clk_sys,
|
||||
|
||||
// SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
input [1:0] rotate, //[0] - rotate [1] - left or right
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] R_in,
|
||||
input [5:0] G_in,
|
||||
input [5:0] B_in,
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] R_out,
|
||||
output [5:0] G_out,
|
||||
output [5:0] B_out
|
||||
);
|
||||
|
||||
parameter OSD_X_OFFSET = 10'd0;
|
||||
parameter OSD_Y_OFFSET = 10'd0;
|
||||
parameter OSD_COLOR = 3'd0;
|
||||
|
||||
localparam OSD_WIDTH = 10'd256;
|
||||
localparam OSD_HEIGHT = 10'd128;
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg osd_enable;
|
||||
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
|
||||
|
||||
// the OSD has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS3) begin
|
||||
reg [4:0] cnt;
|
||||
reg [10:0] bcnt;
|
||||
reg [7:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
|
||||
if(SPI_SS3) begin
|
||||
cnt <= 0;
|
||||
bcnt <= 0;
|
||||
end else begin
|
||||
sbuf <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// 0:7 is command, rest payload
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
|
||||
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
|
||||
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
|
||||
bcnt <= bcnt + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// *********************************************************************************
|
||||
// video timing and sync polarity anaylsis
|
||||
// *********************************************************************************
|
||||
|
||||
// horizontal counter
|
||||
reg [9:0] h_cnt;
|
||||
reg [9:0] hs_low, hs_high;
|
||||
wire hs_pol = hs_high < hs_low;
|
||||
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
|
||||
|
||||
// vertical counter
|
||||
reg [9:0] v_cnt;
|
||||
reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
|
||||
|
||||
wire doublescan = (dsp_height>350);
|
||||
|
||||
reg ce_pix;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt = 0;
|
||||
integer pixsz, pixcnt;
|
||||
reg hs;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
hs <= HSync;
|
||||
|
||||
pixcnt <= pixcnt + 1;
|
||||
if(pixcnt == pixsz) pixcnt <= 0;
|
||||
ce_pix <= !pixcnt;
|
||||
|
||||
if(hs && ~HSync) begin
|
||||
cnt <= 0;
|
||||
pixsz <= (cnt >> 9) - 1;
|
||||
pixcnt <= 0;
|
||||
ce_pix <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg hsD, hsD2;
|
||||
reg vsD, vsD2;
|
||||
|
||||
if(ce_pix) begin
|
||||
// bring hsync into local clock domain
|
||||
hsD <= HSync;
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of HSync
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of HSync
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_low <= h_cnt;
|
||||
v_cnt <= v_cnt + 1'd1;
|
||||
end else begin
|
||||
h_cnt <= h_cnt + 1'd1;
|
||||
end
|
||||
|
||||
vsD <= VSync;
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of VSync
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of VSync
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// area in which OSD is being displayed
|
||||
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
|
||||
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
|
||||
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
|
||||
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
|
||||
wire [9:0] osd_hcnt = h_cnt - h_osd_start;
|
||||
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
wire [9:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
|
||||
wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
|
||||
|
||||
wire osd_de = osd_enable &&
|
||||
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
|
||||
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
|
||||
|
||||
reg [10:0] osd_buffer_addr;
|
||||
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
|
||||
reg osd_pixel;
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
if(ce_pix) begin
|
||||
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
|
||||
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
|
||||
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
|
||||
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
|
||||
|
||||
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
|
||||
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
|
||||
end
|
||||
end
|
||||
|
||||
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
|
||||
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
|
||||
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
365
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.v
Normal file
365
Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.v
Normal file
@@ -0,0 +1,365 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output locked;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire c2 = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire6),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 52,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 47,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 104,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 47,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 208,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 47,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "52"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "208"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.403847"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.201923"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.100962"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "47"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "47"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "47"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.39200000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.19600000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.09800000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "52"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "47"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "104"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "47"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "208"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "47"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -0,0 +1,195 @@
|
||||
//
|
||||
// scandoubler.v
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
// TODO: Delay vsync one line
|
||||
|
||||
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
// system interface
|
||||
input clk_sys,
|
||||
input ce_pix,
|
||||
input ce_pix_actual,
|
||||
|
||||
input hq2x,
|
||||
|
||||
// shifter video interface
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input line_start,
|
||||
|
||||
input [DWIDTH:0] r_in,
|
||||
input [DWIDTH:0] g_in,
|
||||
input [DWIDTH:0] b_in,
|
||||
input mono,
|
||||
|
||||
// output interface
|
||||
output reg hs_out,
|
||||
output vs_out,
|
||||
output [DWIDTH:0] r_out,
|
||||
output [DWIDTH:0] g_out,
|
||||
output [DWIDTH:0] b_out
|
||||
);
|
||||
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
assign vs_out = vs_in;
|
||||
|
||||
reg [2:0] phase;
|
||||
reg [2:0] ce_div;
|
||||
reg [7:0] pix_len = 0;
|
||||
wire [7:0] pl = pix_len + 1'b1;
|
||||
|
||||
reg ce_x1, ce_x4;
|
||||
reg req_line_reset;
|
||||
wire ls_in = hs_in | line_start;
|
||||
always @(negedge clk_sys) begin
|
||||
reg old_ce;
|
||||
reg [2:0] ce_cnt;
|
||||
|
||||
reg [7:0] pixsz2, pixsz4 = 0;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
if(~&pix_len) pix_len <= pix_len + 1'd1;
|
||||
|
||||
ce_x4 <= 0;
|
||||
ce_x1 <= 0;
|
||||
|
||||
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
|
||||
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
|
||||
phase <= phase + 1'd1;
|
||||
ce_x4 <= 1;
|
||||
end
|
||||
|
||||
if(~old_ce & ce_pix) begin
|
||||
pixsz2 <= {1'b0, pl[7:1]};
|
||||
pixsz4 <= {2'b00, pl[7:2]};
|
||||
ce_x1 <= 1;
|
||||
ce_x4 <= 1;
|
||||
pix_len <= 0;
|
||||
phase <= phase + 1'd1;
|
||||
|
||||
ce_cnt <= ce_cnt + 1'd1;
|
||||
if(ce_pix_actual) begin
|
||||
phase <= 0;
|
||||
ce_div <= ce_cnt + 1'd1;
|
||||
ce_cnt <= 0;
|
||||
req_line_reset <= 0;
|
||||
end
|
||||
|
||||
if(ls_in) req_line_reset <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg ce_sd;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: ce_sd = !phase[0];
|
||||
4: ce_sd = !phase[1:0];
|
||||
default: ce_sd <= 1;
|
||||
endcase
|
||||
end
|
||||
|
||||
`define BITS_TO_FIT(N) ( \
|
||||
N <= 2 ? 0 : \
|
||||
N <= 4 ? 1 : \
|
||||
N <= 8 ? 2 : \
|
||||
N <= 16 ? 3 : \
|
||||
N <= 32 ? 4 : \
|
||||
N <= 64 ? 5 : \
|
||||
N <= 128 ? 6 : \
|
||||
N <= 256 ? 7 : \
|
||||
N <= 512 ? 8 : \
|
||||
N <=1024 ? 9 : 10 )
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
|
||||
(
|
||||
.clk(clk_sys),
|
||||
.ce_x4(ce_x4 & ce_sd),
|
||||
.inputpixel({b_in,g_in,r_in}),
|
||||
.mono(mono),
|
||||
.disable_hq2x(~hq2x),
|
||||
.reset_frame(vs_in),
|
||||
.reset_line(req_line_reset),
|
||||
.read_y(sd_line),
|
||||
.read_x(sd_h_actual),
|
||||
.outpixel({b_out,g_out,r_out})
|
||||
);
|
||||
|
||||
reg [10:0] sd_h_actual;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: sd_h_actual = sd_h[10:1];
|
||||
4: sd_h_actual = sd_h[10:2];
|
||||
default: sd_h_actual = sd_h;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [10:0] sd_h;
|
||||
reg [1:0] sd_line;
|
||||
always @(posedge clk_sys) begin
|
||||
|
||||
reg [11:0] hs_max,hs_rise,hs_ls;
|
||||
reg [10:0] hcnt;
|
||||
reg [11:0] sd_hcnt;
|
||||
|
||||
reg hs, hs2, vs, ls;
|
||||
|
||||
if(ce_x1) begin
|
||||
hs <= hs_in;
|
||||
ls <= ls_in;
|
||||
|
||||
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
|
||||
|
||||
// falling edge of hsync indicates start of line
|
||||
if(hs && !hs_in) begin
|
||||
hs_max <= {hcnt,1'b1};
|
||||
hcnt <= 0;
|
||||
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
|
||||
end else begin
|
||||
hcnt <= hcnt + 1'd1;
|
||||
end
|
||||
|
||||
// save position of rising edge
|
||||
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
|
||||
|
||||
vs <= vs_in;
|
||||
if(vs && ~vs_in) sd_line <= 0;
|
||||
end
|
||||
|
||||
if(ce_x4) begin
|
||||
hs2 <= hs_in;
|
||||
|
||||
// output counter synchronous to input and at twice the rate
|
||||
sd_hcnt <= sd_hcnt + 1'd1;
|
||||
sd_h <= sd_h + 1'd1;
|
||||
if(hs2 && !hs_in) sd_hcnt <= hs_max;
|
||||
if(sd_hcnt == hs_max) sd_hcnt <= 0;
|
||||
|
||||
// replicate horizontal sync at twice the speed
|
||||
if(sd_hcnt == hs_max) hs_out <= 0;
|
||||
if(sd_hcnt == hs_rise) hs_out <= 1;
|
||||
|
||||
if(sd_hcnt == hs_ls) sd_h <= 0;
|
||||
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,131 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Video generator - Dar - Feb 2014
|
||||
---------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity video_gen is
|
||||
port(
|
||||
clock_12 : in std_logic;
|
||||
ena_pixel : in std_logic;
|
||||
hsync : out std_logic;
|
||||
vsync : out std_logic;
|
||||
csync : out std_logic;
|
||||
hblank : out std_logic;
|
||||
vblank : out std_logic;
|
||||
|
||||
is_sprite : out std_logic;
|
||||
sprite : out std_logic_vector(2 downto 0);
|
||||
x_tile : out std_logic_vector(4 downto 0);
|
||||
y_tile : out std_logic_vector(4 downto 0);
|
||||
x_pixel : out std_logic_vector(2 downto 0);
|
||||
y_pixel : out std_logic_vector(2 downto 0);
|
||||
|
||||
cpu_clock : out std_logic
|
||||
);
|
||||
end video_gen;
|
||||
|
||||
architecture struct of video_gen is
|
||||
signal hcnt : unsigned (8 downto 0) := to_unsigned(511,9);
|
||||
signal vcnt : unsigned (8 downto 0) := to_unsigned(511,9);
|
||||
signal vcnt_r : unsigned (8 downto 0) := to_unsigned(511,9);
|
||||
|
||||
signal hsync0 : std_logic;
|
||||
signal hsync1 : std_logic;
|
||||
signal hsync2 : std_logic;
|
||||
|
||||
signal enable_clk : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
cpu_clock <= not hcnt(0);
|
||||
is_sprite <= not hcnt(8);
|
||||
sprite <= std_logic_vector(hcnt(6 downto 4));
|
||||
x_tile <= std_logic_vector(hcnt(7 downto 3));
|
||||
y_tile <= std_logic_vector(vcnt_r(7 downto 3));
|
||||
x_pixel <= std_logic_vector(hcnt(2 downto 0));
|
||||
y_pixel <= std_logic_vector(vcnt_r(2 downto 0));
|
||||
|
||||
hsync <= hsync0;
|
||||
|
||||
-- Compteur horizontal : 511-128+1=384 pixels
|
||||
-- 128 à 175 : 48 pixels fin de ligne
|
||||
-- 176 à 255 : 80 pixels debut de ligne
|
||||
-- 256 à 511 : 256 pixels affichés (32 tiles)
|
||||
|
||||
-- Compteur vertical : 511-248+1=264 lignes
|
||||
-- 496 à 511 : 16 lignes fin de trame
|
||||
-- 248 à 271 : 24 lignes debut de trame
|
||||
-- 272 à 495 : 224 lignes affichées (28 tiles)
|
||||
|
||||
-- Synchro horizontale : hcnt=[176 à 207] (32 pixels)
|
||||
-- Synchro verticale : vcnt=[248 à 255] ( 8 lignes)
|
||||
|
||||
process(clock_12)
|
||||
begin
|
||||
|
||||
if rising_edge(clock_12) then
|
||||
|
||||
-- enable_clk <= not enable_clk;
|
||||
-- cpu_clock <= not hcnt(0);
|
||||
|
||||
if ena_pixel = '1' then
|
||||
|
||||
if hcnt = 511 then
|
||||
hcnt <= to_unsigned (128,9);
|
||||
vcnt_r <= vcnt;
|
||||
else
|
||||
hcnt <= hcnt + 1;
|
||||
end if;
|
||||
|
||||
if hcnt = 175 then
|
||||
if vcnt = 511 then
|
||||
vcnt <= to_unsigned(248,9);
|
||||
else
|
||||
vcnt <= vcnt + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if hcnt = (175+ 0) then hsync0 <= '0';
|
||||
elsif hcnt = (175+29) then hsync0 <= '1';
|
||||
end if;
|
||||
|
||||
if hcnt = (175) then hsync1 <= '0';
|
||||
elsif hcnt = (175+13) then hsync1 <= '1';
|
||||
elsif hcnt = (175 +192) then hsync1 <= '0';
|
||||
elsif hcnt = (175+13+192) then hsync1 <= '1';
|
||||
end if;
|
||||
|
||||
if hcnt = (175) then hsync2 <= '0';
|
||||
elsif hcnt = (175-28) then hsync2 <= '1';
|
||||
end if;
|
||||
|
||||
if vcnt = 509 then csync <= hsync1;
|
||||
elsif vcnt = 510 then csync <= hsync1;
|
||||
elsif vcnt = 511 then csync <= hsync1;
|
||||
elsif vcnt = 248 then csync <= hsync2;
|
||||
elsif vcnt = 249 then csync <= hsync2;
|
||||
elsif vcnt = 250 then csync <= hsync2;
|
||||
elsif vcnt = 251 then csync <= hsync1;
|
||||
elsif vcnt = 252 then csync <= hsync1;
|
||||
elsif vcnt = 253 then csync <= hsync1;
|
||||
else csync <= hsync0;
|
||||
end if;
|
||||
|
||||
if vcnt = 511 then vsync <= '0';
|
||||
elsif vcnt = 250 then vsync <= '1';--
|
||||
end if;
|
||||
|
||||
if hcnt = (127+8+1) then hblank <= '1'; -- +8 = retard du shift_register + 1 pixel--
|
||||
elsif hcnt = (255+8+1) then hblank <= '0'; -- +8 = retard du shift_register + 1 pixel--
|
||||
end if;
|
||||
|
||||
if vcnt = (495+1+0) then vblank <= '1';
|
||||
elsif vcnt = (271+1+1) then vblank <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
@@ -0,0 +1,243 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
// LINE_LENGTH: Length of display line in pixels
|
||||
// Usually it's length from HSync to HSync.
|
||||
// May be less if line_start is used.
|
||||
//
|
||||
// HALF_DEPTH: If =1 then color dept is 3 bits per component
|
||||
// For half depth 6 bits monochrome is available with
|
||||
// mono signal enabled and color = {G, R}
|
||||
|
||||
module video_mixer
|
||||
#(
|
||||
parameter LINE_LENGTH = 480,
|
||||
parameter HALF_DEPTH = 1,
|
||||
|
||||
parameter OSD_COLOR = 3'd4,
|
||||
parameter OSD_X_OFFSET = 10'd0,
|
||||
parameter OSD_Y_OFFSET = 10'd0
|
||||
)
|
||||
(
|
||||
// master clock
|
||||
// it should be multiple by (ce_pix*4).
|
||||
input clk_sys,
|
||||
|
||||
// Pixel clock or clock_enable (both are accepted).
|
||||
input ce_pix,
|
||||
|
||||
// Some systems have multiple resolutions.
|
||||
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
|
||||
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
|
||||
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
|
||||
input ce_pix_actual,
|
||||
|
||||
// OSD SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
// scanlines (00-none 01-25% 10-50% 11-75%)
|
||||
input [1:0] scanlines,
|
||||
|
||||
// 0 = HVSync 31KHz, 1 = CSync 15KHz
|
||||
input scandoublerD,
|
||||
|
||||
// High quality 2x scaling
|
||||
input hq2x,
|
||||
|
||||
// YPbPr always uses composite sync
|
||||
input ypbpr,
|
||||
|
||||
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
|
||||
input ypbpr_full,
|
||||
input [1:0] rotate, //[0] - rotate [1] - left or right
|
||||
// color
|
||||
input [DWIDTH:0] R,
|
||||
input [DWIDTH:0] G,
|
||||
input [DWIDTH:0] B,
|
||||
|
||||
// Monochrome mode (for HALF_DEPTH only)
|
||||
input mono,
|
||||
|
||||
// interlace sync. Positive pulses.
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// Falling of this signal means start of informative part of line.
|
||||
// It can be horizontal blank signal.
|
||||
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
|
||||
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
|
||||
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
|
||||
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
|
||||
// before first informative pixel.
|
||||
input line_start,
|
||||
|
||||
// MiST video output signals
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_VS,
|
||||
output VGA_HS
|
||||
);
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
wire [DWIDTH:0] R_sd;
|
||||
wire [DWIDTH:0] G_sd;
|
||||
wire [DWIDTH:0] B_sd;
|
||||
wire hs_sd, vs_sd;
|
||||
|
||||
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
|
||||
(
|
||||
.*,
|
||||
.hs_in(HSync),
|
||||
.vs_in(VSync),
|
||||
.r_in(R),
|
||||
.g_in(G),
|
||||
.b_in(B),
|
||||
|
||||
.hs_out(hs_sd),
|
||||
.vs_out(vs_sd),
|
||||
.r_out(R_sd),
|
||||
.g_out(G_sd),
|
||||
.b_out(B_sd)
|
||||
);
|
||||
|
||||
wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd);
|
||||
wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd);
|
||||
wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd);
|
||||
|
||||
generate
|
||||
if(HALF_DEPTH) begin
|
||||
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
|
||||
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
|
||||
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
|
||||
end else begin
|
||||
wire [5:0] r = rt;
|
||||
wire [5:0] g = gt;
|
||||
wire [5:0] b = bt;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire hs = (scandoublerD ? HSync : hs_sd);
|
||||
wire vs = (scandoublerD ? VSync : vs_sd);
|
||||
|
||||
reg scanline = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg old_hs, old_vs;
|
||||
|
||||
old_hs <= hs;
|
||||
old_vs <= vs;
|
||||
|
||||
if(old_hs && ~hs) scanline <= ~scanline;
|
||||
if(old_vs && ~vs) scanline <= 0;
|
||||
end
|
||||
|
||||
wire [5:0] r_out, g_out, b_out;
|
||||
always @(*) begin
|
||||
case(scanlines & {scanline, scanline})
|
||||
1: begin // reduce 25% = 1/2 + 1/4
|
||||
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
|
||||
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
|
||||
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
2: begin // reduce 50% = 1/2
|
||||
r_out = {1'b0, r[5:1]};
|
||||
g_out = {1'b0, g[5:1]};
|
||||
b_out = {1'b0, b[5:1]};
|
||||
end
|
||||
|
||||
3: begin // reduce 75% = 1/4
|
||||
r_out = {2'b00, r[5:2]};
|
||||
g_out = {2'b00, g[5:2]};
|
||||
b_out = {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
default: begin
|
||||
r_out = r;
|
||||
g_out = g;
|
||||
b_out = b;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
wire [5:0] red, green, blue;
|
||||
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
|
||||
(
|
||||
.*,
|
||||
|
||||
.R_in(r_out),
|
||||
.G_in(g_out),
|
||||
.B_in(b_out),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.rotate(rotate),
|
||||
|
||||
.R_out(red),
|
||||
.G_out(green),
|
||||
.B_out(blue)
|
||||
);
|
||||
|
||||
wire [5:0] yuv_full[225] = '{
|
||||
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
|
||||
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
|
||||
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
|
||||
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
|
||||
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
|
||||
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
|
||||
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
|
||||
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
|
||||
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
|
||||
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
|
||||
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
|
||||
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
|
||||
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
|
||||
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
|
||||
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
|
||||
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
|
||||
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
|
||||
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
|
||||
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
|
||||
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
|
||||
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
|
||||
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
|
||||
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
|
||||
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
|
||||
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
|
||||
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
|
||||
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
|
||||
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
|
||||
6'd63
|
||||
};
|
||||
|
||||
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
|
||||
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
|
||||
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
|
||||
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
|
||||
|
||||
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
|
||||
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
|
||||
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
|
||||
|
||||
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
|
||||
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
|
||||
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
|
||||
assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
|
||||
assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,645 @@
|
||||
--
|
||||
-- A simulation model of YM2149 (AY-3-8910 with bells on)
|
||||
|
||||
-- Copyright (c) MikeJ - Jan 2005
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- You are responsible for any legal issues arising from your use of this code.
|
||||
--
|
||||
-- The latest version of this file can be found at: www.fpgaarcade.com
|
||||
--
|
||||
-- Email support@fpgaarcade.com
|
||||
--
|
||||
-- Revision list
|
||||
--
|
||||
-- version 001 initial release
|
||||
--
|
||||
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
|
||||
--
|
||||
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
|
||||
-- vol 15 .. 0
|
||||
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
|
||||
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
|
||||
-- to produced all the required values.
|
||||
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
|
||||
--
|
||||
-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
|
||||
-- accurate for designs where the outputs are buffered and not simply wired together.
|
||||
-- The ouput level is more complex in that case and requires a larger table.
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity YM2149 is
|
||||
port (
|
||||
-- data bus
|
||||
I_DA : in std_logic_vector(7 downto 0);
|
||||
O_DA : out std_logic_vector(7 downto 0);
|
||||
O_DA_OE_L : out std_logic;
|
||||
-- control
|
||||
I_A9_L : in std_logic;
|
||||
I_A8 : in std_logic;
|
||||
I_BDIR : in std_logic;
|
||||
I_BC2 : in std_logic;
|
||||
I_BC1 : in std_logic;
|
||||
I_SEL_L : in std_logic;
|
||||
|
||||
O_AUDIO : out std_logic_vector(7 downto 0);
|
||||
-- port a
|
||||
I_IOA : in std_logic_vector(7 downto 0);
|
||||
O_IOA : out std_logic_vector(7 downto 0);
|
||||
O_IOA_OE_L : out std_logic;
|
||||
-- port b
|
||||
I_IOB : in std_logic_vector(7 downto 0);
|
||||
O_IOB : out std_logic_vector(7 downto 0);
|
||||
O_IOB_OE_L : out std_logic;
|
||||
|
||||
ENA : in std_logic; -- clock enable for higher speed operation
|
||||
RESET_L : in std_logic;
|
||||
CLK : in std_logic -- note 6 Mhz
|
||||
);
|
||||
end;
|
||||
|
||||
architecture RTL of YM2149 is
|
||||
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
|
||||
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
|
||||
|
||||
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
|
||||
signal noise_div : std_logic := '0';
|
||||
signal ena_div : std_logic;
|
||||
signal ena_div_noise : std_logic;
|
||||
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
|
||||
|
||||
-- registers
|
||||
signal addr : std_logic_vector(7 downto 0);
|
||||
signal busctrl_addr : std_logic;
|
||||
signal busctrl_we : std_logic;
|
||||
signal busctrl_re : std_logic;
|
||||
|
||||
signal reg : array_16x8 ; --:= (
|
||||
-- "00000000", -- R0 Period Tone A 8bits lsb
|
||||
-- "00000100", -- R1 Period Tone A 4bits msb
|
||||
-- "00000000", -- R2 Period Tone B 8bits lsb
|
||||
-- "00000010", -- R3 Period Tone B 4bits msb
|
||||
-- "00000000", -- R4 Period Tone C 8bits lsb
|
||||
-- "00000001", -- R5 Period Tone C 4bits msb
|
||||
-- "00001000", -- R6 Period Noise 5bits
|
||||
-- "00111000", -- R7 Mixer Noise CBA 3bits, Tone CBA 3bits
|
||||
-- "00000111", -- R8 Amplitude A Mode 1bit, Level 4bits
|
||||
-- "00000111", -- R9 Amplitude B Mode 1bit, Level 4bits
|
||||
-- "00000111", -- R10 Amplitude C Mode 1bit, Level 4bits
|
||||
-- "00000000", -- R11 Period Enveloppe 8bits lsb
|
||||
-- "00000000", -- R12 Period Enveloppe 8bits msb
|
||||
-- "00000000", -- R13 Shape Enveloppe 4bits
|
||||
-- "00000000", -- R14 Port A
|
||||
-- "00000000" -- R15 Port B
|
||||
-- );
|
||||
|
||||
signal env_reset : std_logic;
|
||||
signal ioa_inreg : std_logic_vector(7 downto 0);
|
||||
signal iob_inreg : std_logic_vector(7 downto 0);
|
||||
|
||||
signal noise_gen_cnt : std_logic_vector(4 downto 0);
|
||||
signal noise_gen_op : std_logic;
|
||||
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
|
||||
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
|
||||
|
||||
signal env_gen_cnt : std_logic_vector(15 downto 0);
|
||||
signal env_ena : std_logic;
|
||||
signal env_hold : std_logic;
|
||||
signal env_inc : std_logic;
|
||||
signal env_vol : std_logic_vector(4 downto 0);
|
||||
|
||||
signal tone_ena_l : std_logic;
|
||||
signal tone_src : std_logic;
|
||||
signal noise_ena_l : std_logic;
|
||||
signal chan_vol : std_logic_vector(4 downto 0);
|
||||
|
||||
signal dac_amp : std_logic_vector(7 downto 0);
|
||||
signal audio_mix : std_logic_vector(9 downto 0);
|
||||
signal audio_final : std_logic_vector(9 downto 0);
|
||||
begin
|
||||
-- cpu i/f
|
||||
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
|
||||
variable cs : std_logic;
|
||||
variable sel : std_logic_vector(2 downto 0);
|
||||
begin
|
||||
-- BDIR BC2 BC1 MODE
|
||||
-- 0 0 0 inactive
|
||||
-- 0 0 1 address
|
||||
-- 0 1 0 inactive
|
||||
-- 0 1 1 read
|
||||
-- 1 0 0 address
|
||||
-- 1 0 1 inactive
|
||||
-- 1 1 0 write
|
||||
-- 1 1 1 read
|
||||
busctrl_addr <= '0';
|
||||
busctrl_we <= '0';
|
||||
busctrl_re <= '0';
|
||||
|
||||
cs := '0';
|
||||
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
|
||||
cs := '1';
|
||||
end if;
|
||||
|
||||
sel := (I_BDIR & I_BC2 & I_BC1);
|
||||
case sel is
|
||||
when "000" => null;
|
||||
when "001" => busctrl_addr <= '1';
|
||||
when "010" => null;
|
||||
when "011" => busctrl_re <= cs;
|
||||
when "100" => busctrl_addr <= '1';
|
||||
when "101" => null;
|
||||
when "110" => busctrl_we <= cs;
|
||||
when "111" => busctrl_addr <= '1';
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
p_oe : process(busctrl_re)
|
||||
begin
|
||||
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
|
||||
O_DA_OE_L <= not (busctrl_re);
|
||||
end process;
|
||||
|
||||
--
|
||||
-- CLOCKED
|
||||
--
|
||||
p_waddr : process
|
||||
begin
|
||||
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
if (RESET_L = '0') then
|
||||
addr <= (others => '0');
|
||||
else
|
||||
if (busctrl_addr = '1') then
|
||||
addr <= I_DA;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_wdata : process
|
||||
begin
|
||||
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
|
||||
wait until rising_edge(CLK);
|
||||
env_reset <= '0';
|
||||
|
||||
if (RESET_L = '0') then
|
||||
reg <= (others => (others => '0'));
|
||||
env_reset <= '1';
|
||||
else
|
||||
env_reset <= '0';
|
||||
if (busctrl_we = '1') then
|
||||
case addr(3 downto 0) is
|
||||
when x"0" => reg(0) <= I_DA;
|
||||
when x"1" => reg(1) <= I_DA;
|
||||
when x"2" => reg(2) <= I_DA;
|
||||
when x"3" => reg(3) <= I_DA;
|
||||
when x"4" => reg(4) <= I_DA;
|
||||
when x"5" => reg(5) <= I_DA;
|
||||
when x"6" => reg(6) <= I_DA;
|
||||
when x"7" => reg(7) <= I_DA;
|
||||
when x"8" => reg(8) <= I_DA;
|
||||
when x"9" => reg(9) <= I_DA;
|
||||
when x"A" => reg(10) <= I_DA;
|
||||
when x"B" => reg(11) <= I_DA;
|
||||
when x"C" => reg(12) <= I_DA;
|
||||
when x"D" => reg(13) <= I_DA; env_reset <= '1';
|
||||
when x"E" => reg(14) <= I_DA;
|
||||
when x"F" => reg(15) <= I_DA;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--
|
||||
-- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
|
||||
--
|
||||
-- p_waddr : process(reset_l, busctrl_addr)
|
||||
-- begin
|
||||
-- -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
|
||||
-- if (RESET_L = '0') then
|
||||
-- addr <= (others => '0');
|
||||
-- elsif falling_edge(busctrl_addr) then -- yuk
|
||||
-- addr <= I_DA;
|
||||
-- end if;
|
||||
-- end process;
|
||||
--
|
||||
-- p_wdata : process(reset_l, busctrl_we, addr)
|
||||
-- begin
|
||||
-- if (RESET_L = '0') then
|
||||
-- reg <= (others => (others => '0'));
|
||||
-- elsif falling_edge(busctrl_we) then
|
||||
-- case addr(3 downto 0) is
|
||||
-- when x"0" => reg(0) <= I_DA;
|
||||
-- when x"1" => reg(1) <= I_DA;
|
||||
-- when x"2" => reg(2) <= I_DA;
|
||||
-- when x"3" => reg(3) <= I_DA;
|
||||
-- when x"4" => reg(4) <= I_DA;
|
||||
-- when x"5" => reg(5) <= I_DA;
|
||||
-- when x"6" => reg(6) <= I_DA;
|
||||
-- when x"7" => reg(7) <= I_DA;
|
||||
-- when x"8" => reg(8) <= I_DA;
|
||||
-- when x"9" => reg(9) <= I_DA;
|
||||
-- when x"A" => reg(10) <= I_DA;
|
||||
-- when x"B" => reg(11) <= I_DA;
|
||||
-- when x"C" => reg(12) <= I_DA;
|
||||
-- when x"D" => reg(13) <= I_DA;
|
||||
-- when x"E" => reg(14) <= I_DA;
|
||||
-- when x"F" => reg(15) <= I_DA;
|
||||
-- when others => null;
|
||||
-- end case;
|
||||
-- end if;
|
||||
--
|
||||
-- env_reset <= '0';
|
||||
-- if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
|
||||
-- env_reset <= '1';
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
--
|
||||
-- END LATCHED
|
||||
--
|
||||
|
||||
p_rdata : process(busctrl_re, addr, reg)
|
||||
begin
|
||||
O_DA <= (others => '0'); -- 'X'
|
||||
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
|
||||
case addr(3 downto 0) is
|
||||
when x"0" => O_DA <= reg(0) ;
|
||||
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
|
||||
when x"2" => O_DA <= reg(2) ;
|
||||
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
|
||||
when x"4" => O_DA <= reg(4) ;
|
||||
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
|
||||
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
|
||||
when x"7" => O_DA <= reg(7) ;
|
||||
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
|
||||
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
|
||||
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
|
||||
when x"B" => O_DA <= reg(11);
|
||||
when x"C" => O_DA <= reg(12);
|
||||
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
|
||||
when x"E" => if (reg(7)(6) = '0') then -- input
|
||||
O_DA <= ioa_inreg;
|
||||
else
|
||||
O_DA <= reg(14); -- read output reg
|
||||
end if;
|
||||
when x"F" => if (Reg(7)(7) = '0') then
|
||||
O_DA <= iob_inreg;
|
||||
else
|
||||
O_DA <= reg(15);
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
--
|
||||
p_divider : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
-- / 8 when SEL is high and /16 when SEL is low
|
||||
if (ENA = '1') then
|
||||
ena_div <= '0';
|
||||
ena_div_noise <= '0';
|
||||
if (cnt_div = "0000") then
|
||||
cnt_div <= (not I_SEL_L) & "111";
|
||||
ena_div <= '1';
|
||||
|
||||
noise_div <= not noise_div;
|
||||
if (noise_div = '1') then
|
||||
ena_div_noise <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt_div <= cnt_div - "1";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_noise_gen : process
|
||||
variable noise_gen_comp : std_logic_vector(4 downto 0);
|
||||
variable poly17_zero : std_logic;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
if (reg(6)(4 downto 0) = "00000") then
|
||||
noise_gen_comp := "00000";
|
||||
else
|
||||
noise_gen_comp := (reg(6)(4 downto 0) - "1");
|
||||
end if;
|
||||
|
||||
poly17_zero := '0';
|
||||
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
|
||||
|
||||
if (ENA = '1') then
|
||||
|
||||
if (ena_div_noise = '1') then -- divider ena
|
||||
|
||||
if (noise_gen_cnt >= noise_gen_comp) then
|
||||
noise_gen_cnt <= "00000";
|
||||
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
|
||||
else
|
||||
noise_gen_cnt <= (noise_gen_cnt + "1");
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
noise_gen_op <= poly17(0);
|
||||
|
||||
p_tone_gens : process
|
||||
variable tone_gen_freq : array_3x12;
|
||||
variable tone_gen_comp : array_3x12;
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
|
||||
-- looks like real chips count up - we need to get the Exact behaviour ..
|
||||
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
|
||||
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
|
||||
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
|
||||
-- period 0 = period 1
|
||||
for i in 1 to 3 loop
|
||||
if (tone_gen_freq(i) = x"000") then
|
||||
tone_gen_comp(i) := x"000";
|
||||
else
|
||||
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
if (ENA = '1') then
|
||||
for i in 1 to 3 loop
|
||||
if (ena_div = '1') then -- divider ena
|
||||
|
||||
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
|
||||
tone_gen_cnt(i) <= x"000";
|
||||
tone_gen_op(i) <= not tone_gen_op(i);
|
||||
else
|
||||
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_envelope_freq : process
|
||||
variable env_gen_freq : std_logic_vector(15 downto 0);
|
||||
variable env_gen_comp : std_logic_vector(15 downto 0);
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
env_gen_freq := reg(12) & reg(11);
|
||||
-- envelope freqs 1 and 0 are the same.
|
||||
if (env_gen_freq = x"0000") then
|
||||
env_gen_comp := x"0000";
|
||||
else
|
||||
env_gen_comp := (env_gen_freq - "1");
|
||||
end if;
|
||||
|
||||
if (ENA = '1') then
|
||||
env_ena <= '0';
|
||||
if (ena_div = '1') then -- divider ena
|
||||
if (env_gen_cnt >= env_gen_comp) then
|
||||
env_gen_cnt <= x"0000";
|
||||
env_ena <= '1';
|
||||
else
|
||||
env_gen_cnt <= (env_gen_cnt + "1");
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_envelope_shape : process(env_reset, CLK)
|
||||
variable is_bot : boolean;
|
||||
variable is_bot_p1 : boolean;
|
||||
variable is_top_m1 : boolean;
|
||||
variable is_top : boolean;
|
||||
begin
|
||||
-- envelope shapes
|
||||
-- C AtAlH
|
||||
-- 0 0 x x \___
|
||||
--
|
||||
-- 0 1 x x /___
|
||||
--
|
||||
-- 1 0 0 0 \\\\
|
||||
--
|
||||
-- 1 0 0 1 \___
|
||||
--
|
||||
-- 1 0 1 0 \/\/
|
||||
-- ___
|
||||
-- 1 0 1 1 \
|
||||
--
|
||||
-- 1 1 0 0 ////
|
||||
-- ___
|
||||
-- 1 1 0 1 /
|
||||
--
|
||||
-- 1 1 1 0 /\/\
|
||||
--
|
||||
-- 1 1 1 1 /___
|
||||
if (env_reset = '1') then
|
||||
-- load initial state
|
||||
if (reg(13)(2) = '0') then -- attack
|
||||
env_vol <= "11111";
|
||||
env_inc <= '0'; -- -1
|
||||
else
|
||||
env_vol <= "00000";
|
||||
env_inc <= '1'; -- +1
|
||||
end if;
|
||||
env_hold <= '0';
|
||||
|
||||
elsif rising_edge(CLK) then
|
||||
is_bot := (env_vol = "00000");
|
||||
is_bot_p1 := (env_vol = "00001");
|
||||
is_top_m1 := (env_vol = "11110");
|
||||
is_top := (env_vol = "11111");
|
||||
|
||||
if (ENA = '1') then
|
||||
if (env_ena = '1') then
|
||||
if (env_hold = '0') then
|
||||
if (env_inc = '1') then
|
||||
env_vol <= (env_vol + "00001");
|
||||
else
|
||||
env_vol <= (env_vol + "11111");
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- envelope shape control.
|
||||
if (reg(13)(3) = '0') then
|
||||
if (env_inc = '0') then -- down
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_top then env_hold <= '1'; end if;
|
||||
end if;
|
||||
else
|
||||
if (reg(13)(0) = '1') then -- hold = 1
|
||||
if (env_inc = '0') then -- down
|
||||
if (reg(13)(1) = '1') then -- alt
|
||||
if is_bot then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
end if;
|
||||
else
|
||||
if (reg(13)(1) = '1') then -- alt
|
||||
if is_top then env_hold <= '1'; end if;
|
||||
else
|
||||
if is_top_m1 then env_hold <= '1'; end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
elsif (reg(13)(1) = '1') then -- alternate
|
||||
if (env_inc = '0') then -- down
|
||||
if is_bot_p1 then env_hold <= '1'; end if;
|
||||
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
|
||||
else
|
||||
if is_top_m1 then env_hold <= '1'; end if;
|
||||
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
|
||||
begin
|
||||
tone_ena_l <= '1'; tone_src <= '1';
|
||||
noise_ena_l <= '1'; chan_vol <= "00000";
|
||||
case cnt_div(1 downto 0) is
|
||||
when "00" =>
|
||||
tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(3);
|
||||
when "01" =>
|
||||
tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(4);
|
||||
when "10" =>
|
||||
tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
|
||||
noise_ena_l <= reg(7)(5);
|
||||
when "11" => null; -- tone gen outputs become valid on this clock
|
||||
when others => null;
|
||||
end case;
|
||||
end process;
|
||||
|
||||
p_op_mixer : process
|
||||
variable chan_mixed : std_logic;
|
||||
variable chan_amp : std_logic_vector(4 downto 0);
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
if (ENA = '1') then
|
||||
|
||||
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
|
||||
|
||||
chan_amp := (others => '0');
|
||||
if (chan_mixed = '1') then
|
||||
if (chan_vol(4) = '0') then
|
||||
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
|
||||
chan_amp := "00000";
|
||||
else
|
||||
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
|
||||
end if;
|
||||
else
|
||||
chan_amp := env_vol(4 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
|
||||
dac_amp <= x"00";
|
||||
case chan_amp is
|
||||
when "11111" => dac_amp <= x"FF";
|
||||
when "11110" => dac_amp <= x"D9";
|
||||
when "11101" => dac_amp <= x"BA";
|
||||
when "11100" => dac_amp <= x"9F";
|
||||
when "11011" => dac_amp <= x"88";
|
||||
when "11010" => dac_amp <= x"74";
|
||||
when "11001" => dac_amp <= x"63";
|
||||
when "11000" => dac_amp <= x"54";
|
||||
when "10111" => dac_amp <= x"48";
|
||||
when "10110" => dac_amp <= x"3D";
|
||||
when "10101" => dac_amp <= x"34";
|
||||
when "10100" => dac_amp <= x"2C";
|
||||
when "10011" => dac_amp <= x"25";
|
||||
when "10010" => dac_amp <= x"1F";
|
||||
when "10001" => dac_amp <= x"1A";
|
||||
when "10000" => dac_amp <= x"16";
|
||||
when "01111" => dac_amp <= x"13";
|
||||
when "01110" => dac_amp <= x"10";
|
||||
when "01101" => dac_amp <= x"0D";
|
||||
when "01100" => dac_amp <= x"0B";
|
||||
when "01011" => dac_amp <= x"09";
|
||||
when "01010" => dac_amp <= x"08";
|
||||
when "01001" => dac_amp <= x"07";
|
||||
when "01000" => dac_amp <= x"06";
|
||||
when "00111" => dac_amp <= x"05";
|
||||
when "00110" => dac_amp <= x"04";
|
||||
when "00101" => dac_amp <= x"03";
|
||||
when "00100" => dac_amp <= x"03";
|
||||
when "00011" => dac_amp <= x"02";
|
||||
when "00010" => dac_amp <= x"02";
|
||||
when "00001" => dac_amp <= x"01";
|
||||
when "00000" => dac_amp <= x"00";
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
if (cnt_div(1 downto 0) = "10") then
|
||||
audio_mix <= (others => '0');
|
||||
audio_final <= audio_mix;
|
||||
else
|
||||
audio_mix <= audio_mix + ("00" & dac_amp);
|
||||
end if;
|
||||
|
||||
if (RESET_L = '0') then
|
||||
O_AUDIO(7 downto 0) <= "00000000";
|
||||
else
|
||||
if (audio_final(9) = '0') then
|
||||
O_AUDIO(7 downto 0) <= audio_final(8 downto 1);
|
||||
else -- clip
|
||||
O_AUDIO(7 downto 0) <= x"FF";
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
p_io_ports : process(reg)
|
||||
begin
|
||||
O_IOA <= reg(14);
|
||||
|
||||
O_IOA_OE_L <= not reg(7)(6);
|
||||
O_IOB <= reg(15);
|
||||
O_IOB_OE_L <= not reg(7)(7);
|
||||
end process;
|
||||
|
||||
p_io_ports_inreg : process
|
||||
begin
|
||||
wait until rising_edge(CLK);
|
||||
ioa_inreg <= I_IOA;
|
||||
iob_inreg <= I_IOB;
|
||||
end process;
|
||||
end architecture RTL;
|
||||
@@ -17,10 +17,13 @@ Aviable Arcade Cores
|
||||
#Custom Hardware
|
||||
Bagman
|
||||
Berzerk
|
||||
Crazy Climber
|
||||
Crazy Kong
|
||||
Galaga
|
||||
|
||||
#Crazy Climber Hardware
|
||||
Crazy Climber
|
||||
River Patrol
|
||||
|
||||
#Data East Burger Time Hardware
|
||||
#Setup 1
|
||||
Burnin Rubber
|
||||
|
||||
Reference in New Issue
Block a user