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add Commen Units

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Marcel
2019-07-22 23:42:05 +02:00
parent fa65ff3c9f
commit 462f0490bd
512 changed files with 133512 additions and 5 deletions
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32
common/CPU/6502_6510/aholme_6502.v Normal file
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module aholme_6502(
input clk,
input enable,
input reset,
output [15:0] ab,
input [7:0] dbi,
output [7:0] dbo,
output we,
input irq,
input nmi,
input ready
);
wire we_c;
chip_6502 aholme_cpu (
.clk(clk),
.phi(clk & enable),
.res(~reset),
.so(1'b0),
.rdy(ready),
.nmi(nmi_n),
.irq(irq_n),
.rw(we_c),
.dbi(dbi),
.dbo(dbo),
.ab(ab)
);
assign we = ~we_c;
endmodule

72
common/CPU/6502_6510/arlet_6502.v Normal file
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// Licensed to the Apache Software Foundation (ASF) under one
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
// to you under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// software distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//
// Description: A wrapper for Arlet Ottens 6502 CPU core
//
// Author.....: Alan Garfield
// Niels A. Moseley
// Date.......: 26-1-2018
//
module arlet_6502(
input clk, // clock signal
input enable, // clock enable strobe
input rst, // active high reset signal
output reg [15:0] ab, // address bus
input [7:0] dbi, // 8-bit data bus (input)
output reg [7:0] dbo, // 8-bit data bus (output)
output reg we, // active high write enable strobe
input irq_n, // active low interrupt request
input nmi_n, // active low non-maskable interrupt
input ready, // CPU updates when ready = 1
output [15:0] pc_monitor // program counter monitor signal for debugging
);
wire [7:0] dbo_c;
wire [15:0] ab_c;
wire we_c;
cpu arlet_cpu(
.clk(clk),
.reset(rst),
.AB(ab_c),
.DI(dbi),
.DO(dbo_c),
.WE(we_c),
.IRQ(~irq_n),
.NMI(~nmi_n),
.RDY(ready),
.PC_MONITOR(pc_monitor)
);
always @(posedge clk or posedge rst)
begin
if (rst)
begin
ab <= 16'd0;
dbo <= 8'd0;
we <= 1'b0;
end
else
if (enable)
begin
ab <= ab_c;
dbo <= dbo_c;
we <= we_c;
end
end
endmodule

66
common/CPU/6502_6510/chip_6502.v Normal file
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`include "../rtl/cpu/aholme/chip_6502_nodes.inc"
module LOGIC (
input [`NUM_NODES-1:0] i,
output [`NUM_NODES-1:0] o);
`include "chip_6502_logic.inc"
endmodule
module chip_6502 (
input clk, // FPGA clock
input phi, // 6502 clock
input res,
input so,
input rdy,
input nmi,
input irq,
input [7:0] dbi,
output [7:0] dbo,
output rw,
output sync,
output [15:0] ab);
// Node states
wire [`NUM_NODES-1:0] no;
reg [`NUM_NODES-1:0] ni;
reg [`NUM_NODES-1:0] q = 0;
LOGIC logic_00 (.i(ni), .o(no));
always @ (posedge clk)
q <= no;
always @* begin
ni = q;
ni[`NODE_vcc ] = 1'b1;
ni[`NODE_vss ] = 1'b0;
ni[`NODE_res ] = res;
ni[`NODE_clk0] = phi;
ni[`NODE_so ] = so;
ni[`NODE_rdy ] = rdy;
ni[`NODE_nmi ] = nmi;
ni[`NODE_irq ] = irq;
{ni[`NODE_db7],ni[`NODE_db6],ni[`NODE_db5],ni[`NODE_db4],
ni[`NODE_db3],ni[`NODE_db2],ni[`NODE_db1],ni[`NODE_db0]} = dbi[7:0];
end
assign dbo[7:0] = {
no[`NODE_db7],no[`NODE_db6],no[`NODE_db5],no[`NODE_db4],
no[`NODE_db3],no[`NODE_db2],no[`NODE_db1],no[`NODE_db0]
};
assign ab[15:0] = {
no[`NODE_ab15], no[`NODE_ab14], no[`NODE_ab13], no[`NODE_ab12],
no[`NODE_ab11], no[`NODE_ab10], no[`NODE_ab9], no[`NODE_ab8],
no[`NODE_ab7], no[`NODE_ab6], no[`NODE_ab5], no[`NODE_ab4],
no[`NODE_ab3], no[`NODE_ab2], no[`NODE_ab1], no[`NODE_ab0]
};
assign rw = no[`NODE_rw];
assign sync = no[`NODE_sync];
endmodule

10
common/CPU/6502_6510/chip_6502_mux.v Normal file
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module MUX #(
parameter N=1
) (
output wire o,
input wire i,
input wire [N-1:0] s,
input wire [N-1:0] d);
assign o = (|s) ? &(d|(~s)) : i;
endmodule

1598
common/CPU/6502_6510/cpu6502.vhd Normal file
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87
common/CPU/6502_6510/cpu65xx_e.vhd Normal file
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-- -----------------------------------------------------------------------
--
-- FPGA 64
--
-- A fully functional commodore 64 implementation in a single FPGA
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
--
-- Interface to 6502/6510 core
--
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity cpu65xx is
generic (
pipelineOpcode : boolean;
pipelineAluMux : boolean;
pipelineAluOut : boolean
);
port (
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
so_n : in std_logic := '1';
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic;
debugOpcode : out unsigned(7 downto 0);
debugPc : out unsigned(15 downto 0);
debugA : out unsigned(7 downto 0);
debugX : out unsigned(7 downto 0);
debugY : out unsigned(7 downto 0);
debugS : out unsigned(7 downto 0)
);
end cpu65xx;
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity cpu6502 is
port(
clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
nmi : in std_logic;
irq : in std_logic;
din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
we : out std_logic
);
end cpu6502;
architecture cpu6502 of cpu6502 is
begin
cpuInstance: entity work.cpu65xx(fast)
generic map (
pipelineOpcode => false,
pipelineAluMux => false,
pipelineAluOut => false
)
port map (
clk => clk,
enable=> ce,
reset => reset,
nmi_n => not nmi,
irq_n => not irq,
di => din,
do => dout,
addr => addr,
we => we
);
end architecture;

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common/CPU/6502_6510/cpu65xx_fast.vhd Normal file
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3962
common/CPU/6800/cpu68.vhd Normal file
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28
common/CPU/68000/FX68k/Rom.sv Normal file
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//
// microrom and nanorom instantiation
//
// There is bit of wasting of resources here. An extra registering pipeline happens that is not needed.
// This is just for the purpose of helping inferring block RAM using pure generic code. Inferring RAM is important for performance.
// Might be more efficient to use vendor specific features such as clock enable.
//
module uRom( input clk, input [UADDR_WIDTH-1:0] microAddr, output logic [UROM_WIDTH-1:0] microOutput);
reg [UROM_WIDTH-1:0] uRam[ UROM_DEPTH];
initial begin
$readmemb("microrom.mem", uRam);
end
always_ff @( posedge clk)
microOutput <= uRam[ microAddr];
endmodule
module nanoRom( input clk, input [NADDR_WIDTH-1:0] nanoAddr, output logic [NANO_WIDTH-1:0] nanoOutput);
reg [NANO_WIDTH-1:0] nRam[ NANO_DEPTH];
initial begin
$readmemb("nanorom.mem", nRam);
end
always_ff @( posedge clk)
nanoOutput <= nRam[ nanoAddr];
endmodule

35
common/CPU/68000/FX68k/aluCorf.sv Normal file
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// add bcd correction factor
// It would be more efficient to merge add/sub with main ALU !!!
module aluCorf( input [7:0] binResult, input bAdd, input cin, input hCarry,
output [7:0] bcdResult, output dC, output logic ov);
reg [8:0] htemp;
reg [4:0] hNib;
wire lowC = hCarry | (bAdd ? gt9( binResult[ 3:0]) : 1'b0);
wire highC = cin | (bAdd ? (gt9( htemp[7:4]) | htemp[8]) : 1'b0);
always_comb begin
if( bAdd) begin
htemp = { 1'b0, binResult} + (lowC ? 4'h6 : 4'h0);
hNib = htemp[8:4] + (highC ? 4'h6 : 4'h0);
ov = hNib[3] & ~binResult[7];
end
else begin
htemp = { 1'b0, binResult} - (lowC ? 4'h6 : 4'h0);
hNib = htemp[8:4] - (highC ? 4'h6 : 4'h0);
ov = ~hNib[3] & binResult[7];
end
end
assign bcdResult = { hNib[ 3:0], htemp[3:0]};
assign dC = hNib[4] | cin;
// Nibble > 9
function gt9 (input [3:0] nib);
begin
gt9 = nib[3] & (nib[2] | nib[1]);
end
endfunction
endmodule

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common/CPU/68000/FX68k/aluGetOp.sv Normal file
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// Get current OP from row & col
module aluGetOp( input [15:0] row, input [2:0] col, input isCorf,
output logic [4:0] aluOp);
always_comb begin
aluOp = 'X;
unique case( col)
1: aluOp = OP_AND;
5: aluOp = OP_EXT;
default:
unique case( 1'b1)
row[1]:
unique case( col)
2: aluOp = OP_SUB;
3: aluOp = OP_SUBC;
4,6: aluOp = OP_SLAA;
endcase
row[2]:
unique case( col)
2: aluOp = OP_ADD;
3: aluOp = OP_ADDC;
4: aluOp = OP_ASR;
endcase
row[3]:
unique case( col)
2: aluOp = OP_ADDX;
3: aluOp = isCorf ? OP_ABCD : OP_ADD;
4: aluOp = OP_ASL;
endcase
row[4]:
aluOp = ( col == 4) ? OP_LSL : OP_AND;
row[5],
row[6]:
unique case( col)
2: aluOp = OP_SUB;
3: aluOp = OP_SUBC;
4: aluOp = OP_LSR;
endcase
row[7]: // MUL
unique case( col)
2: aluOp = OP_SUB;
3: aluOp = OP_ADD;
4: aluOp = OP_ROXR;
endcase
row[8]:
// OP_AND For EXT.L
// But would be more efficient to change ucode and use column 1 instead of col3 at ublock extr1!
unique case( col)
2: aluOp = OP_EXT;
3: aluOp = OP_AND;
4: aluOp = OP_ROXR;
endcase
row[9]:
unique case( col)
2: aluOp = OP_SUBX;
3: aluOp = OP_SBCD;
4: aluOp = OP_ROL;
endcase
row[10]:
unique case( col)
2: aluOp = OP_SUBX;
3: aluOp = OP_SUBC;
4: aluOp = OP_ROR;
endcase
row[11]:
unique case( col)
2: aluOp = OP_SUB0;
3: aluOp = OP_SUB0;
4: aluOp = OP_ROXL;
endcase
row[12]: aluOp = OP_ADDX;
row[13]: aluOp = OP_EOR;
row[14]: aluOp = (col == 4) ? OP_EOR : OP_OR;
row[15]: aluOp = (col == 3) ? OP_ADD : OP_OR; // OP_ADD used by DBcc
endcase
endcase
end
endmodule

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common/CPU/68000/FX68k/aluShifter.sv Normal file
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module aluShifter( input [31:0] data,
input isByte, input isLong, swapWords,
input dir, input cin,
output logic [31:0] result);
// output reg cout
logic [31:0] tdata;
// size mux, put cin in position if dir == right
always_comb begin
tdata = data;
if( isByte & dir)
tdata[8] = cin;
else if( !isLong & dir)
tdata[16] = cin;
end
always_comb begin
// Reverse alu/alue position for MUL & DIV
// Result reversed again
if( swapWords & dir)
result = { tdata[0], tdata[31:17], cin, tdata[15:1]};
else if( swapWords)
result = { tdata[30:16], cin, tdata[14:0], tdata[31]};
else if( dir)
result = { cin, tdata[31:1]};
else
result = { tdata[30:0], cin};
end
endmodule

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common/CPU/68000/FX68k/busArbiter.sv Normal file
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//
// DMA/BUS Arbitration
//
module busArbiter( input s_clks Clks,
input BRi, BgackI, Halti, bgBlock,
output busAvail,
output logic BGn);
enum int unsigned { DRESET = 0, DIDLE, D1, D_BR, D_BA, D_BRA, D3, D2} dmaPhase, next;
always_comb begin
case(dmaPhase)
DRESET: next = DIDLE;
DIDLE: begin
if( bgBlock)
next = DIDLE;
else if( ~BgackI)
next = D_BA;
else if( ~BRi)
next = D1;
else
next = DIDLE;
end
D_BA: begin // Loop while only BGACK asserted, BG negated here
if( ~BRi & !bgBlock)
next = D3;
else if( ~BgackI & !bgBlock)
next = D_BA;
else
next = DIDLE;
end
D1: next = D_BR; // Loop while only BR asserted
D_BR: next = ~BRi & BgackI ? D_BR : D_BA; // No direct path to IDLE !
D3: next = D_BRA;
D_BRA: begin // Loop while both BR and BGACK asserted
case( {BgackI, BRi} )
2'b11: next = DIDLE; // Both deasserted
2'b10: next = D_BR; // BR asserted only
2'b01: next = D2; // BGACK asserted only
2'b00: next = D_BRA; // Stay here while both asserted
endcase
end
// Might loop here if both deasserted, should normally don't arrive here anyway?
// D2: next = (BgackI & BRi) | bgBlock ? D2: D_BA;
D2: next = D_BA;
default: next = DIDLE; // Should not reach here normally
endcase
end
logic granting;
always_comb begin
unique case( next)
D1, D3, D_BR, D_BRA: granting = 1'b1;
default: granting = 1'b0;
endcase
end
reg rGranted;
assign busAvail = Halti & BRi & BgackI & ~rGranted;
always_ff @( posedge Clks.clk) begin
if( Clks.extReset) begin
dmaPhase <= DRESET;
rGranted <= 1'b0;
end
else if( Clks.enPhi2) begin
dmaPhase <= next;
// Internal signal changed on PHI2
rGranted <= granting;
end
// External Output changed on PHI1
if( Clks.extReset)
BGn <= 1'b1;
else if( Clks.enPhi1)
BGn <= ~rGranted;
end
endmodule

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common/CPU/68000/FX68k/busControl.sv Normal file
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module busControl( input s_clks Clks, input enT1, input enT4,
input permStart, permStop, iStop,
input aob0,
input isWrite, isByte, isRmc,
input busAvail,
output bgBlock,
output busAddrErr,
output waitBusCycle,
output busStarting, // Asserted during S0
output logic addrOe, // Asserted from S1 to the end, whole bus cycle except S0
output bciWrite, // Used for SSW on bus/addr error
input rDtack, BeDebounced, Vpai,
output ASn, output LDSn, output UDSn, eRWn);
reg rAS, rLDS, rUDS, rRWn;
assign ASn = rAS;
assign LDSn = rLDS;
assign UDSn = rUDS;
assign eRWn = rRWn;
reg dataOe;
reg bcPend;
reg isWriteReg, bciByte, isRmcReg, wendReg;
assign bciWrite = isWriteReg;
reg addrOeDelay;
reg isByteT4;
wire canStart, busEnd;
wire bcComplete, bcReset;
wire isRcmReset = bcComplete & bcReset & isRmcReg;
assign busAddrErr = aob0 & ~bciByte;
// Bus retry not really supported.
// It's BERR and HALT and not address error, and not read-modify cycle.
wire busRetry = ~busAddrErr & 1'b0;
enum int unsigned { SRESET = 0, SIDLE, S0, S2, S4, S6, SRMC_RES} busPhase, next;
always_ff @( posedge Clks.clk) begin
if( Clks.extReset)
busPhase <= SRESET;
else if( Clks.enPhi1)
busPhase <= next;
end
always_comb begin
case( busPhase)
SRESET: next = SIDLE;
SRMC_RES: next = SIDLE; // Single cycle special state when read phase of RMC reset
S0: next = S2;
S2: next = S4;
S4: next = busEnd ? S6 : S4;
S6: next = isRcmReset ? SRMC_RES : (canStart ? S0 : SIDLE);
SIDLE: next = canStart ? S0 : SIDLE;
default: next = SIDLE;
endcase
end
// Idle phase of RMC bus cycle. Might be better to just add a new state
wire rmcIdle = (busPhase == SIDLE) & ~ASn & isRmcReg;
assign canStart = (busAvail | rmcIdle) & (bcPend | permStart) & !busRetry & !bcReset;
wire busEnding = (next == SIDLE) | (next == S0);
assign busStarting = (busPhase == S0);
// term signal (DTACK, BERR, VPA, adress error)
assign busEnd = ~rDtack | iStop;
// bcComplete asserted on raising edge of S6 (together with SNC).
assign bcComplete = (busPhase == S6);
// Clear bus info latch on completion (regular or aborted) and no bus retry (and not PHI1).
// bciClear asserted half clock later on PHI2, and bci latches cleared async concurrently
wire bciClear = bcComplete & ~busRetry;
// Reset on reset or (berr & berrDelay & (not halt or rmc) & not 6800 & in bus cycle) (and not PHI1)
assign bcReset = Clks.extReset | (addrOeDelay & BeDebounced & Vpai);
// Enable uclock only on S6 (S8 on Bus Error) or not bciPermStop
assign waitBusCycle = wendReg & !bcComplete;
// Block Bus Grant when starting new bus cycle. But No need if AS already asserted (read phase of RMC)
// Except that when that RMC phase aborted on bus error, it's asserted one cycle later!
assign bgBlock = ((busPhase == S0) & ASn) | (busPhase == SRMC_RES);
always_ff @( posedge Clks.clk) begin
if( Clks.extReset) begin
addrOe <= 1'b0;
end
else if( Clks.enPhi2 & ( busPhase == S0)) // From S1, whole bus cycle except S0
addrOe <= 1'b1;
else if( Clks.enPhi1 & (busPhase == SRMC_RES))
addrOe <= 1'b0;
else if( Clks.enPhi1 & ~isRmcReg & busEnding)
addrOe <= 1'b0;
if( Clks.enPhi1)
addrOeDelay <= addrOe;
if( Clks.extReset) begin
rAS <= 1'b1;
rUDS <= 1'b1;
rLDS <= 1'b1;
rRWn <= 1'b1;
dataOe <= '0;
end
else begin
if( Clks.enPhi2 & isWriteReg & (busPhase == S2))
dataOe <= 1'b1;
else if( Clks.enPhi1 & (busEnding | (busPhase == SIDLE)) )
dataOe <= 1'b0;
if( Clks.enPhi1 & busEnding)
rRWn <= 1'b1;
else if( Clks.enPhi1 & isWriteReg) begin
// Unlike LDS/UDS Asserted even in address error
if( (busPhase == S0) & isWriteReg)
rRWn <= 1'b0;
end
// AS. Actually follows addrOe half cycle later!
if( Clks.enPhi1 & (busPhase == S0))
rAS <= 1'b0;
else if( Clks.enPhi2 & (busPhase == SRMC_RES)) // Bus error on read phase of RMC. Deasserted one cycle later
rAS <= 1'b1;
else if( Clks.enPhi2 & bcComplete & ~SRMC_RES)
if( ~isRmcReg) // Keep AS asserted on the IDLE phase of RMC
rAS <= 1'b1;
if( Clks.enPhi1 & (busPhase == S0)) begin
if( ~isWriteReg & !busAddrErr) begin
rUDS <= ~(~bciByte | ~aob0);
rLDS <= ~(~bciByte | aob0);
end
end
else if( Clks.enPhi1 & isWriteReg & (busPhase == S2) & !busAddrErr) begin
rUDS <= ~(~bciByte | ~aob0);
rLDS <= ~(~bciByte | aob0);
end
else if( Clks.enPhi2 & bcComplete) begin
rUDS <= 1'b1;
rLDS <= 1'b1;
end
end
end
// Bus cycle info latch. Needed because uinstr might change if the bus is busy and we must wait.
// Note that urom advances even on wait states. It waits *after* updating urom and nanorom latches.
// Even without wait states, ublocks of type ir (init reading) will not wait for bus completion.
// Originally latched on (permStart AND T1).
// Bus cycle info latch: isRead, isByte, read-modify-cycle, and permStart (bus cycle pending). Some previously latched on T4?
// permStop also latched, but unconditionally on T1
// Might make more sense to register this outside this module
always_ff @( posedge Clks.clk) begin
if( enT4) begin
isByteT4 <= isByte;
end
end
// Bus Cycle Info Latch
always_ff @( posedge Clks.clk) begin
if( Clks.pwrUp) begin
bcPend <= 1'b0;
wendReg <= 1'b0;
isWriteReg <= 1'b0;
bciByte <= 1'b0;
isRmcReg <= 1'b0;
end
else if( Clks.enPhi2 & (bciClear | bcReset)) begin
bcPend <= 1'b0;
wendReg <= 1'b0;
end
else begin
if( enT1 & permStart) begin
isWriteReg <= isWrite;
bciByte <= isByteT4;
isRmcReg <= isRmc & ~isWrite; // We need special case the end of the read phase only.
bcPend <= 1'b1;
end
if( enT1)
wendReg <= permStop;
end
end
endmodule

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common/CPU/68000/FX68k/ccrTable.sv Normal file
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// Row/col CCR update table
module ccrTable(
input [2:0] col, input [15:0] row, input finish,
output logic [MASK_NBITS-1:0] ccrMask);
localparam
KNZ00 = 5'b01111, // ok coz operators clear them
KKZKK = 5'b00100,
KNZKK = 5'b01100,
KNZ10 = 5'b01111, // Used by OP_EXT on divison overflow
KNZ0C = 5'b01111, // Used by DIV. V should be 0, but it is ok:
// DIVU: ends with quotient - 0, so V & C always clear.
// DIVS: ends with 1i (AND), again, V & C always clear.
KNZVC = 5'b01111,
CUPDALL = 5'b11111,
CUNUSED = 5'bxxxxx;
logic [MASK_NBITS-1:0] ccrMask1;
always_comb begin
unique case( col)
1: ccrMask = ccrMask1;
2,3:
unique case( 1'b1)
row[1]: ccrMask = KNZ0C; // DIV, used as 3n in col3
row[2],
row[3], // ABCD
row[5],
row[9], // SBCD/NBCD
row[10], // SUBX/NEGX
row[12]: ccrMask = CUPDALL; // ADDX
row[6], // CMP
row[7], // MUL
row[11]: ccrMask = KNZVC; // NOT
row[4],
row[8], // Not used in col 3
row[13],
row[14]: ccrMask = KNZ00;
row[15]: ccrMask = 5'b0; // TAS/Scc, not used in col 3
// default: ccrMask = CUNUSED;
endcase
4:
unique case( row)
// 1: DIV, only n (4n & 6n)
// 14: BCLR 4n
// 6,12,13,15 // not used
`ALU_ROW_02,
`ALU_ROW_03, // ASL (originally ANZVA)
`ALU_ROW_04,
`ALU_ROW_05: ccrMask = CUPDALL; // Shifts (originally ANZ0A)
`ALU_ROW_07: ccrMask = KNZ00; // MUL (originally KNZ0A)
`ALU_ROW_09,
`ALU_ROW_10: ccrMask = KNZ00; // RO[lr] (originally KNZ0A)
`ALU_ROW_11: ccrMask = CUPDALL; // ROXL (originally ANZ0A)
default: ccrMask = CUNUSED;
endcase
5: ccrMask = row[1] ? KNZ10 : 5'b0;
default: ccrMask = CUNUSED;
endcase
end
// Column 1 (AND)
always_comb begin
if( finish)
ccrMask1 = row[7] ? KNZ00 : KNZKK;
else
ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00;
end
endmodule

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//
// Data bus I/O
// At a separate module because it is a bit complicated and the timing is special.
// Here we do the low/high byte mux and the special case of MOVEP.
//
// Original implementation is rather complex because both the internal and external buses are bidirectional.
// Input is latched async at the EDB register.
// We capture directly from the external data bus to the internal registers (IRC & DBIN) on PHI2, starting the external S7 phase, at a T4 internal period.
module dataIo( input s_clks Clks,
input enT1, enT2, enT3, enT4,
input s_nanod Nanod, input s_irdecod Irdecod,
input [15:0] iEdb,
input aob0,
input dobIdle,
input [15:0] dobInput,
output logic [15:0] Irc,
output logic [15:0] dbin,
output logic [15:0] oEdb
);
reg [15:0] dob;
// DBIN/IRC
// Timing is different than any other register. We can latch only on the next T4 (bus phase S7).
// We need to register all control signals correctly because the next ublock will already be started.
// Can't latch control on T4 because if there are wait states there might be multiple T4 before we latch.
reg xToDbin, xToIrc;
reg dbinNoLow, dbinNoHigh;
reg byteMux, isByte_T4;
always_ff @( posedge Clks.clk) begin
// Byte mux control. Can't latch at T1. AOB might be not ready yet.
// Must latch IRD decode at T1 (or T4). Then combine and latch only at T3.
// Can't latch at T3, a new IRD might be loaded already at T1.
// Ok to latch at T4 if combination latched then at T3
if( enT4)
isByte_T4 <= Irdecod.isByte; // Includes MOVEP from mem, we could OR it here
if( enT3) begin
dbinNoHigh <= Nanod.noHighByte;
dbinNoLow <= Nanod.noLowByte;
byteMux <= Nanod.busByte & isByte_T4 & ~aob0;
end
if( enT1) begin
// If on wait states, we continue latching until next T1
xToDbin <= 1'b0;
xToIrc <= 1'b0;
end
else if( enT3) begin
xToDbin <= Nanod.todbin;
xToIrc <= Nanod.toIrc;
end
// Capture on T4 of the next ucycle
// If there are wait states, we keep capturing every PHI2 until the next T1
if( xToIrc & Clks.enPhi2)
Irc <= iEdb;
if( xToDbin & Clks.enPhi2) begin
// Original connects both halves of EDB.
if( ~dbinNoLow)
dbin[ 7:0] <= byteMux ? iEdb[ 15:8] : iEdb[7:0];
if( ~dbinNoHigh)
dbin[ 15:8] <= ~byteMux & dbinNoLow ? iEdb[ 7:0] : iEdb[ 15:8];
end
end
// DOB
logic byteCycle;
always_ff @( posedge Clks.clk) begin
// Originaly on T1. Transfer to internal EDB also on T1 (stays enabled upto the next T1). But only on T4 (S3) output enables.
// It is safe to do on T3, then, but control signals if derived from IRD must be registered.
// Originally control signals are not registered.
// Wait states don't affect DOB operation that is done at the start of the bus cycle.
if( enT4)
byteCycle <= Nanod.busByte & Irdecod.isByte; // busIsByte but not MOVEP
// Originally byte low/high interconnect is done at EDB, not at DOB.
if( enT3 & ~dobIdle) begin
dob[7:0] <= Nanod.noLowByte ? dobInput[15:8] : dobInput[ 7:0];
dob[15:8] <= (byteCycle | Nanod.noHighByte) ? dobInput[ 7:0] : dobInput[15:8];
end
end
assign oEdb = dob;
endmodule

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common/CPU/68000/FX68k/excUnit.sv Normal file
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/*
Execution unit
Executes register transfers set by the microcode. Originally through a set of bidirectional buses.
Most sources are available at T3, but DBIN only at T4! CCR also might be updated at T4, but it is not connected to these buses.
We mux at T1 and T2, then transfer to the destination at T3. The exception is AOB that need to be updated earlier.
*/
module excUnit( input s_clks Clks,
input enT1, enT2, enT3, enT4,
input s_nanod Nanod, input s_irdecod Irdecod,
input [15:0] Ird, // ALU row (and others) decoder needs it
input pswS,
input [15:0] ftu,
input [15:0] iEdb,
output logic [7:0] ccr,
output [15:0] alue,
output prenEmpty, au05z,
output logic dcr4, ze,
output logic aob0,
output [15:0] AblOut,
output logic [15:0] Irc,
output logic [15:0] oEdb,
output logic [23:1] eab);
localparam REG_USP = 15;
localparam REG_SSP = 16;
localparam REG_DT = 17;
// Register file
reg [15:0] regs68L[ 18];
reg [15:0] regs68H[ 18];
// synthesis translate off
/*
It is bad practice to initialize simulation registers that the hardware doesn't.
There is risk that simulation would be different than the real hardware. But in this case is the other way around.
Some ROM uses something like sub.l An,An at powerup which clears the register
Simulator power ups the registers with 'X, as they are really undetermined at the real hardware.
But the simulator doesn't realize (it can't) that the same value is substracting from itself,
and that the result should be zero even when it's 'X - 'X.
*/
initial begin
for( int i = 0; i < 18; i++) begin
regs68L[i] <= '0;
regs68H[i] <= '0;
end
end
// For simulation display only
wire [31:0] SSP = { regs68H[REG_SSP], regs68L[REG_SSP]};
// synthesis translate on
wire [15:0] aluOut;
wire [15:0] dbin;
logic [15:0] dcrOutput;
reg [15:0] PcL, PcH;
reg [31:0] auReg, aob;
reg [15:0] Ath, Atl;
// Bus execution
reg [15:0] Dbl, Dbh;
reg [15:0] Abh, Abl;
reg [15:0] Abd, Dbd;
assign AblOut = Abl;
assign au05z = (~| auReg[5:0]);
logic [15:0] dblMux, dbhMux;
logic [15:0] abhMux, ablMux;
logic [15:0] abdMux, dbdMux;
logic abdIsByte;
logic Pcl2Dbl, Pch2Dbh;
logic Pcl2Abl, Pch2Abh;
// RX RY muxes
// RX and RY actual registers
logic [4:0] actualRx, actualRy;
logic [3:0] movemRx;
logic byteNotSpAlign; // Byte instruction and no sp word align
// IRD decoded signals must be latched. See comments on decoder
// But nanostore decoding can't be latched before T4.
//
// If we need this earlier we can register IRD decode on T3 and use nano async
logic [4:0] rxMux, ryMux;
logic [3:0] rxReg, ryReg;
logic rxIsSp, ryIsSp;
logic rxIsAreg, ryIsAreg;
always_comb begin
// Unique IF !!
if( Nanod.ssp) begin
rxMux = REG_SSP;
rxIsSp = 1'b1;
rxReg = 1'bX;
end
else if( Irdecod.rxIsUsp) begin
rxMux = REG_USP;
rxIsSp = 1'b1;
rxReg = 1'bX;
end
else if( Irdecod.rxIsDt & !Irdecod.implicitSp) begin
rxMux = REG_DT;
rxIsSp = 1'b0;
rxReg = 1'bX;
end
else begin
if( Irdecod.implicitSp)
rxReg = 15;
else if( Irdecod.rxIsMovem)
rxReg = movemRx;
else
rxReg = { Irdecod.rxIsAreg, Irdecod.rx};
if( (& rxReg)) begin
rxMux = pswS ? REG_SSP : 15;
rxIsSp = 1'b1;
end
else begin
rxMux = { 1'b0, rxReg};
rxIsSp = 1'b0;
end
end
// RZ has higher priority!
if( Irdecod.ryIsDt & !Nanod.rz) begin
ryMux = REG_DT;
ryIsSp = 1'b0;
ryReg = 'X;
end
else begin
ryReg = Nanod.rz ? Irc[15:12] : {Irdecod.ryIsAreg, Irdecod.ry};
ryIsSp = (& ryReg);
if( ryIsSp & pswS) // No implicit SP on RY
ryMux = REG_SSP;
else
ryMux = { 1'b0, ryReg};
end
end
always_ff @( posedge Clks.clk) begin
if( enT4) begin
byteNotSpAlign <= Irdecod.isByte & ~(Nanod.rxlDbl ? rxIsSp : ryIsSp);
actualRx <= rxMux;
actualRy <= ryMux;
rxIsAreg <= rxIsSp | rxMux[3];
ryIsAreg <= ryIsSp | ryMux[3];
end
if( enT4)
abdIsByte <= Nanod.abdIsByte & Irdecod.isByte;
end
// Set RX/RY low word to which bus segment is connected.
wire ryl2Abl = Nanod.ryl2ab & (ryIsAreg | Nanod.ablAbd);
wire ryl2Abd = Nanod.ryl2ab & (~ryIsAreg | Nanod.ablAbd);
wire ryl2Dbl = Nanod.ryl2db & (ryIsAreg | Nanod.dblDbd);
wire ryl2Dbd = Nanod.ryl2db & (~ryIsAreg | Nanod.dblDbd);
wire rxl2Abl = Nanod.rxl2ab & (rxIsAreg | Nanod.ablAbd);
wire rxl2Abd = Nanod.rxl2ab & (~rxIsAreg | Nanod.ablAbd);
wire rxl2Dbl = Nanod.rxl2db & (rxIsAreg | Nanod.dblDbd);
wire rxl2Dbd = Nanod.rxl2db & (~rxIsAreg | Nanod.dblDbd);
// Buses. Main mux
logic abhIdle, ablIdle, abdIdle;
logic dbhIdle, dblIdle, dbdIdle;
always_comb begin
{abhIdle, ablIdle, abdIdle} = '0;
{dbhIdle, dblIdle, dbdIdle} = '0;
unique case( 1'b1)
ryl2Dbd: dbdMux = regs68L[ actualRy];
rxl2Dbd: dbdMux = regs68L[ actualRx];
Nanod.alue2Dbd: dbdMux = alue;
Nanod.dbin2Dbd: dbdMux = dbin;
Nanod.alu2Dbd: dbdMux = aluOut;
Nanod.dcr2Dbd: dbdMux = dcrOutput;
default: begin dbdMux = 'X; dbdIdle = 1'b1; end
endcase
unique case( 1'b1)
rxl2Dbl: dblMux = regs68L[ actualRx];
ryl2Dbl: dblMux = regs68L[ actualRy];
Nanod.ftu2Dbl: dblMux = ftu;
Nanod.au2Db: dblMux = auReg[15:0];
Nanod.atl2Dbl: dblMux = Atl;
Pcl2Dbl: dblMux = PcL;
default: begin dblMux = 'X; dblIdle = 1'b1; end
endcase
unique case( 1'b1)
Nanod.rxh2dbh: dbhMux = regs68H[ actualRx];
Nanod.ryh2dbh: dbhMux = regs68H[ actualRy];
Nanod.au2Db: dbhMux = auReg[31:16];
Nanod.ath2Dbh: dbhMux = Ath;
Pch2Dbh: dbhMux = PcH;
default: begin dbhMux = 'X; dbhIdle = 1'b1; end
endcase
unique case( 1'b1)
ryl2Abd: abdMux = regs68L[ actualRy];
rxl2Abd: abdMux = regs68L[ actualRx];
Nanod.dbin2Abd: abdMux = dbin;
Nanod.alu2Abd: abdMux = aluOut;
default: begin abdMux = 'X; abdIdle = 1'b1; end
endcase
unique case( 1'b1)
Pcl2Abl: ablMux = PcL;
rxl2Abl: ablMux = regs68L[ actualRx];
ryl2Abl: ablMux = regs68L[ actualRy];
Nanod.ftu2Abl: ablMux = ftu;
Nanod.au2Ab: ablMux = auReg[15:0];
Nanod.aob2Ab: ablMux = aob[15:0];
Nanod.atl2Abl: ablMux = Atl;
default: begin ablMux = 'X; ablIdle = 1'b1; end
endcase
unique case( 1'b1)
Pch2Abh: abhMux = PcH;
Nanod.rxh2abh: abhMux = regs68H[ actualRx];
Nanod.ryh2abh: abhMux = regs68H[ actualRy];
Nanod.au2Ab: abhMux = auReg[31:16];
Nanod.aob2Ab: abhMux = aob[31:16];
Nanod.ath2Abh: abhMux = Ath;
default: begin abhMux = 'X; abhIdle = 1'b1; end
endcase
end
// Source starts driving the bus on T1. Bus holds data until end of T3. Destination latches at T3.
// These registers store the first level mux, without bus interconnections.
// Even when this uses almost to 100 registers, it saves a lot of comb muxing and it is much faster.
reg [15:0] preAbh, preAbl, preAbd;
reg [15:0] preDbh, preDbl, preDbd;
always_ff @( posedge Clks.clk) begin
// Register first level mux at T1
if( enT1) begin
{preAbh, preAbl, preAbd} <= { abhMux, ablMux, abdMux};
{preDbh, preDbl, preDbd} <= { dbhMux, dblMux, dbdMux};
end
// Process bus interconnection at T2. Many combinations only used on DIV
// We use a simple method. If a specific bus segment is not driven we know that it should get data from a neighbour segment.
// In some cases this is not true and the segment is really idle without any destination. But then it doesn't matter.
if( enT2) begin
if( Nanod.extAbh)
Abh <= { 16{ ablIdle ? preAbd[ 15] : preAbl[ 15] }};
else if( abhIdle)
Abh <= ablIdle ? preAbd : preAbl;
else
Abh <= preAbh;
if( ~ablIdle)
Abl <= preAbl;
else
Abl <= Nanod.ablAbh ? preAbh : preAbd;
Abd <= ~abdIdle ? preAbd : ablIdle ? preAbh : preAbl;
if( Nanod.extDbh)
Dbh <= { 16{ dblIdle ? preDbd[ 15] : preDbl[ 15] }};
else if( dbhIdle)
Dbh <= dblIdle ? preDbd : preDbl;
else
Dbh <= preDbh;
if( ~dblIdle)
Dbl <= preDbl;
else
Dbl <= Nanod.dblDbh ? preDbh : preDbd;
Dbd <= ~dbdIdle ? preDbd: dblIdle ? preDbh : preDbl;
/*
Dbl <= dblMux; Dbh <= dbhMux;
Abd <= abdMux; Dbd <= dbdMux;
Abh <= abhMux; Abl <= ablMux; */
end
end
// AOB
//
// Originally change on T1. We do on T2, only then the output is enabled anyway.
//
// AOB[0] is used for address error. But even when raises on T1, seems not actually used until T2 or possibly T3.
// It is used on T1 when deasserted at the BSER exception ucode. Probably deassertion timing is not critical.
// But in that case (at BSER), AOB is loaded from AU, so we can safely transfer on T1.
// We need to take directly from first level muxes that are updated and T1
wire au2Aob = Nanod.au2Aob | (Nanod.au2Db & Nanod.db2Aob);
always_ff @( posedge Clks.clk) begin
// UNIQUE IF !
if( enT1 & au2Aob) // From AU we do can on T1
aob <= auReg;
else if( enT2) begin
if( Nanod.db2Aob)
aob <= { preDbh, ~dblIdle ? preDbl : preDbd};
else if( Nanod.ab2Aob)
aob <= { preAbh, ~ablIdle ? preAbl : preAbd};
end
end
assign eab = aob[23:1];
assign aob0 = aob[0];
// AU
logic [31:0] auInpMux;
// `ifdef ALW_COMB_BUG
// Old Modelsim bug. Doesn't update ouput always. Need excplicit sensitivity list !?
// always @( Nanod.auCntrl) begin
always_comb begin
unique case( Nanod.auCntrl)
3'b000: auInpMux = 0;
3'b001: auInpMux = byteNotSpAlign | Nanod.noSpAlign ? 1 : 2; // +1/+2
3'b010: auInpMux = -4;
3'b011: auInpMux = { Abh, Abl};
3'b100: auInpMux = 2;
3'b101: auInpMux = 4;
3'b110: auInpMux = -2;
3'b111: auInpMux = byteNotSpAlign | Nanod.noSpAlign ? -1 : -2; // -1/-2
default: auInpMux = 'X;
endcase
end
// Simulation problem
// Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits counter testing if bits 5-0 are zero.
// But when adding something like 32'hXXXX0000, the simulator (incorrectly) will set *all the 32 bits* of the result as X.
// synthesis translate_off
`define SIMULBUGX32 1
wire [16:0] aulow = Dbl + auInpMux[15:0];
wire [31:0] auResult = {Dbh + auInpMux[31:16] + aulow[16], aulow[15:0]};
// synthesis translate_on
always_ff @( posedge Clks.clk) begin
if( Clks.pwrUp)
auReg <= '0;
else if( enT3 & Nanod.auClkEn)
`ifdef SIMULBUGX32
auReg <= auResult;
`else
auReg <= { Dbh, Dbl } + auInpMux;
`endif
end
// Main A/D registers
always_ff @( posedge Clks.clk) begin
if( enT3) begin
if( Nanod.dbl2rxl | Nanod.abl2rxl) begin
if( ~rxIsAreg) begin
if( Nanod.dbl2rxl) regs68L[ actualRx] <= Dbd;
else if( abdIsByte) regs68L[ actualRx][7:0] <= Abd[7:0];
else regs68L[ actualRx] <= Abd;
end
else
regs68L[ actualRx] <= Nanod.dbl2rxl ? Dbl : Abl;
end
if( Nanod.dbl2ryl | Nanod.abl2ryl) begin
if( ~ryIsAreg) begin
if( Nanod.dbl2ryl) regs68L[ actualRy] <= Dbd;
else if( abdIsByte) regs68L[ actualRy][7:0] <= Abd[7:0];
else regs68L[ actualRy] <= Abd;
end
else
regs68L[ actualRy] <= Nanod.dbl2ryl ? Dbl : Abl;
end
// High registers are easier. Both A & D on the same buses, and not byte ops.
if( Nanod.dbh2rxh | Nanod.abh2rxh)
regs68H[ actualRx] <= Nanod.dbh2rxh ? Dbh : Abh;
if( Nanod.dbh2ryh | Nanod.abh2ryh)
regs68H[ actualRy] <= Nanod.dbh2ryh ? Dbh : Abh;
end
end
// PC & AT
reg dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl;
always_ff @( posedge Clks.clk) begin
if( Clks.extReset) begin
{ dbl2Pcl, dbh2Pch, abh2Pch, abl2Pcl } <= '0;
Pcl2Dbl <= 1'b0;
Pch2Dbh <= 1'b0;
Pcl2Abl <= 1'b0;
Pch2Abh <= 1'b0;
end
else if( enT4) begin // Must latch on T4 !
dbl2Pcl <= Nanod.dbl2reg & Nanod.pcldbl;
dbh2Pch <= Nanod.dbh2reg & Nanod.pchdbh;
abh2Pch <= Nanod.abh2reg & Nanod.pchabh;
abl2Pcl <= Nanod.abl2reg & Nanod.pclabl;
Pcl2Dbl <= Nanod.reg2dbl & Nanod.pcldbl;
Pch2Dbh <= Nanod.reg2dbh & Nanod.pchdbh;
Pcl2Abl <= Nanod.reg2abl & Nanod.pclabl;
Pch2Abh <= Nanod.reg2abh & Nanod.pchabh;
end
// Unique IF !!!
if( enT1 & Nanod.au2Pc)
PcL <= auReg[15:0];
else if( enT3) begin
if( dbl2Pcl)
PcL <= Dbl;
else if( abl2Pcl)
PcL <= Abl;
end
// Unique IF !!!
if( enT1 & Nanod.au2Pc)
PcH <= auReg[31:16];
else if( enT3) begin
if( dbh2Pch)
PcH <= Dbh;
else if( abh2Pch)
PcH <= Abh;
end
// Unique IF !!!
if( enT3) begin
if( Nanod.dbl2Atl)
Atl <= Dbl;
else if( Nanod.abl2Atl)
Atl <= Abl;
end
// Unique IF !!!
if( enT3) begin
if( Nanod.abh2Ath)
Ath <= Abh;
else if( Nanod.dbh2Ath)
Ath <= Dbh;
end
end
// Movem reg mask priority encoder
wire rmIdle;
logic [3:0] prHbit;
logic [15:0] prenLatch;
// Invert reg order for predecrement mode
assign prenEmpty = (~| prenLatch);
pren rmPren( .mask( prenLatch), .hbit (prHbit));
always_ff @( posedge Clks.clk) begin
// Cheating: PREN always loaded from DBIN
// Must be on T1 to branch earlier if reg mask is empty!
if( enT1 & Nanod.abl2Pren)
prenLatch <= dbin;
else if( enT3 & Nanod.updPren) begin
prenLatch [prHbit] <= 1'b0;
movemRx <= Irdecod.movemPreDecr ? ~prHbit : prHbit;
end
end
// DCR
wire [15:0] dcrCode;
wire [3:0] dcrInput = abdIsByte ? { 1'b0, Abd[ 2:0]} : Abd[ 3:0];
onehotEncoder4 dcrDecoder( .bin( dcrInput), .bitMap( dcrCode));
always_ff @( posedge Clks.clk) begin
if( Clks.pwrUp)
dcr4 <= '0;
else if( enT3 & Nanod.abd2Dcr) begin
dcrOutput <= dcrCode;
dcr4 <= Abd[4];
end
end
// ALUB
reg [15:0] alub;
always_ff @( posedge Clks.clk) begin
if( enT3) begin
// UNIQUE IF !!
if( Nanod.dbd2Alub)
alub <= Dbd;
else if( Nanod.abd2Alub)
alub <= Abd; // abdIsByte affects this !!??
end
end
wire alueClkEn = enT3 & Nanod.dbd2Alue;
// DOB/DBIN/IRC
logic [15:0] dobInput;
wire dobIdle = (~| Nanod.dobCtrl);
always_comb begin
unique case (Nanod.dobCtrl)
NANO_DOB_ADB: dobInput = Abd;
NANO_DOB_DBD: dobInput = Dbd;
NANO_DOB_ALU: dobInput = aluOut;
default: dobInput = 'X;
endcase
end
dataIo dataIo( .Clks, .enT1, .enT2, .enT3, .enT4, .Nanod, .Irdecod,
.iEdb, .dobIdle, .dobInput, .aob0,
.Irc, .dbin, .oEdb);
fx68kAlu alu(
.clk( Clks.clk), .pwrUp( Clks.pwrUp), .enT1, .enT3, .enT4,
.ird( Ird),
.aluColumn( Nanod.aluColumn), .aluAddrCtrl( Nanod.aluActrl),
.init( Nanod.aluInit), .finish( Nanod.aluFinish), .aluIsByte( Irdecod.isByte),
.ftu2Ccr( Nanod.ftu2Ccr),
.alub, .ftu, .alueClkEn, .alue,
.aluDataCtrl( Nanod.aluDctrl), .iDataBus( Dbd), .iAddrBus(Abd),
.ze, .aluOut, .ccr);
endmodule

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//
// FX68K
//
// M68000 cycle accurate, fully synchronous
// Copyright (c) 2018 by Jorge Cwik
//
// TODO:
// - Everything except bus retry already implemented.
`timescale 1 ns / 1 ns
// Define this to run a self contained compilation test build
// `define FX68K_TEST
localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4, SF = 13;
localparam UADDR_WIDTH = 10;
localparam UROM_WIDTH = 17;
localparam UROM_DEPTH = 1024;
localparam NADDR_WIDTH = 9;
localparam NANO_WIDTH = 68;
localparam NANO_DEPTH = 336;
localparam BSER1_NMA = 'h003;
localparam RSTP0_NMA = 'h002;
localparam HALT1_NMA = 'h001;
localparam TRAC1_NMA = 'h1C0;
localparam ITLX1_NMA = 'h1C4;
localparam TVN_SPURIOUS = 12;
localparam TVN_AUTOVEC = 13;
localparam TVN_INTERRUPT = 15;
localparam NANO_DOB_DBD = 2'b01;
localparam NANO_DOB_ADB = 2'b10;
localparam NANO_DOB_ALU = 2'b11;
// Clocks, phases and resets
typedef struct {
logic clk;
logic extReset; // External sync reset on emulated system
logic pwrUp; // Asserted together with reset on emulated system coldstart
logic enPhi1, enPhi2; // Clock enables. Next cycle is PHI1 or PHI2
} s_clks;
// IRD decoded signals
typedef struct {
logic isPcRel;
logic isTas;
logic implicitSp;
logic toCcr;
logic rxIsDt, ryIsDt;
logic rxIsUsp, rxIsMovem, movemPreDecr;
logic isByte;
logic isMovep;
logic [2:0] rx, ry;
logic rxIsAreg, ryIsAreg;
logic [15:0] ftuConst;
logic [5:0] macroTvn;
logic inhibitCcr;
} s_irdecod;
// Nano code decoded signals
typedef struct {
logic permStart;
logic waitBusFinish;
logic isWrite;
logic busByte;
logic isRmc;
logic noLowByte, noHighByte;
logic updTpend, clrTpend;
logic tvn2Ftu, const2Ftu;
logic ftu2Dbl, ftu2Abl;
logic abl2Pren, updPren;
logic inl2psw, ftu2Sr, sr2Ftu, ftu2Ccr, pswIToFtu;
logic ird2Ftu, ssw2Ftu;
logic initST;
logic Ir2Ird;
logic auClkEn, noSpAlign;
logic [2:0] auCntrl;
logic todbin, toIrc;
logic dbl2Atl, abl2Atl, atl2Abl, atl2Dbl;
logic abh2Ath, dbh2Ath;
logic ath2Dbh, ath2Abh;
logic db2Aob, ab2Aob, au2Aob;
logic aob2Ab, updSsw;
// logic adb2Dob, dbd2Dob, alu2Dob;
logic [1:0] dobCtrl;
logic abh2reg, abl2reg;
logic reg2abl, reg2abh;
logic dbh2reg, dbl2reg;
logic reg2dbl, reg2dbh;
logic ssp, pchdbh, pcldbl, pclabl, pchabh;
logic rxh2dbh, rxh2abh;
logic dbl2rxl, dbh2rxh;
logic rxl2db, rxl2ab;
logic abl2rxl, abh2rxh;
logic dbh2ryh, abh2ryh;
logic ryl2db, ryl2ab;
logic ryh2dbh, ryh2abh;
logic dbl2ryl, abl2ryl;
logic rz;
logic rxlDbl;
logic [2:0] aluColumn;
logic [1:0] aluDctrl;
logic aluActrl;
logic aluInit, aluFinish;
logic abd2Dcr, dcr2Dbd;
logic dbd2Alue, alue2Dbd;
logic dbd2Alub, abd2Alub;
logic alu2Dbd, alu2Abd;
logic au2Db, au2Ab, au2Pc;
logic dbin2Abd, dbin2Dbd;
logic extDbh, extAbh;
logic ablAbd, ablAbh;
logic dblDbd, dblDbh;
logic abdIsByte;
} s_nanod;
module fx68k(
input clk,
// These two signals don't need to be registered. They are not async reset.
input extReset, // External sync reset on emulated system
input pwrUp, // Asserted together with reset on emulated system coldstart
input enPhi1, enPhi2, // Clock enables. Next cycle is PHI1 or PHI2
output eRWn, output ASn, output LDSn, output UDSn,
output logic E, output VMAn,
output FC0, output FC1, output FC2,
output BGn,
output oRESETn, output oHALTEDn,
input DTACKn, input VPAn,
input BERRn,
input BRn, BGACKn,
input IPL0n, input IPL1n, input IPL2n,
input [15:0] iEdb, output [15:0] oEdb,
output [23:1] eab
);
// wire clock = Clks.clk;
s_clks Clks;
assign Clks.clk = clk;
assign Clks.extReset = extReset;
assign Clks.pwrUp = pwrUp;
assign Clks.enPhi1 = enPhi1;
assign Clks.enPhi2 = enPhi2;
wire wClk;
// Internal sub clocks T1-T4
enum int unsigned { T0 = 0, T1, T2, T3, T4} tState;
wire enT1 = Clks.enPhi1 & (tState == T4) & ~wClk;
wire enT2 = Clks.enPhi2 & (tState == T1);
wire enT3 = Clks.enPhi1 & (tState == T2);
wire enT4 = Clks.enPhi2 & ((tState == T0) | (tState == T3));
// T4 continues ticking during reset and group0 exception.
// We also need it to erase ucode output latched on T4.
always_ff @( posedge Clks.clk) begin
if( Clks.pwrUp)
tState <= T0;
else begin
case( tState)
T0: if( Clks.enPhi2) tState <= T4;
T1: if( Clks.enPhi2) tState <= T2;
T2: if( Clks.enPhi1) tState <= T3;
T3: if( Clks.enPhi2) tState <= T4;
T4: if( Clks.enPhi1) tState <= wClk ? T0 : T1;
endcase
end
end
// The following signals are synchronized with 3 couplers, phi1-phi2-phi1.
// Will be valid internally one cycle later if changed at the rasing edge of the clock.
//
// DTACK, BERR
// DTACK valid at S6 if changed at the rasing edge of S4 to avoid wait states.
// SNC (sncClkEn) is deasserted together (unless DTACK asserted too early).
//
// We synchronize some signals half clock earlier. We compensate later
reg rDtack, rBerr;
reg [2:0] rIpl, iIpl;
reg Vpai, BeI, BRi, BgackI, BeiDelay;
// reg rBR;
wire BeDebounced = ~( BeI | BeiDelay);
always_ff @( posedge Clks.clk) begin
if( Clks.pwrUp) begin
rBerr <= 1'b0;
BeI <= 1'b0;
end
else if( Clks.enPhi2) begin
rDtack <= DTACKn;
rBerr <= BERRn;
rIpl <= ~{ IPL2n, IPL1n, IPL0n};
iIpl <= rIpl;
// rBR <= BRn; // Needed for cycle accuracy but only if BR is changed on the wrong edge of the clock
end
else if( Clks.enPhi1) begin
Vpai <= VPAn;
BeI <= rBerr;
BeiDelay <= BeI;
BRi <= BRn;
BgackI <= BGACKn;
// BRi <= rBR;
end
end
// Instantiate micro and nano rom
logic [NANO_WIDTH-1:0] nanoLatch;
logic [NANO_WIDTH-1:0] nanoOutput;
logic [UROM_WIDTH-1:0] microLatch;
logic [UROM_WIDTH-1:0] microOutput;
logic [UADDR_WIDTH-1:0] microAddr, nma;
logic [NADDR_WIDTH-1:0] nanoAddr, orgAddr;
wire rstUrom;
// For the time being, address translation is done for nanorom only.
microToNanoAddr microToNanoAddr(
.uAddr ( nma),
.orgAddr ( orgAddr)
);
// Output of these modules will be updated at T2 at the latest (depending on clock division)
nanoRom nanoRom(
.clk ( Clks.clk),
.nanoAddr (nanoAddr),
.nanoOutput (nanoOutput)
);
uRom uRom(
.clk ( Clks.clk),
.microAddr ( microAddr),
.microOutput( microOutput));
always_ff @( posedge Clks.clk) begin
// uaddr originally latched on T1, except bits 6 & 7, the conditional bits, on T2
// Seems we can latch whole address at either T1 or T2
// Originally it's invalid on hardware reset, and forced later when coming out of reset
if( Clks.pwrUp) begin
microAddr <= RSTP0_NMA;
nanoAddr <= RSTP0_NMA;
end
else if( enT1) begin
microAddr <= nma;
nanoAddr <= orgAddr; // Register translated uaddr to naddr
end
if( Clks.extReset) begin
microLatch <= '0;
nanoLatch <= '0;
end
else if( rstUrom) begin
// Originally reset these bits only. Not strictly needed like this.
// Can reset the whole register if it is important.
{ microLatch[16], microLatch[15], microLatch[0]} <= '0;
nanoLatch <= '0;
end
else if( enT3) begin
microLatch <= microOutput;
nanoLatch <= nanoOutput;
end
end
// Decoded nanocode signals
s_nanod Nanod;
// IRD decoded control signals
s_irdecod Irdecod;
//
reg Tpend;
reg intPend; // Interrupt pending
reg pswT, pswS;
reg [ 2:0] pswI;
wire [7:0] ccr;
wire [15:0] psw = { pswT, 1'b0, pswS, 2'b00, pswI, ccr};
reg [15:0] ftu;
reg [15:0] Irc, Ir, Ird;
wire [15:0] alue;
wire [15:0] Abl;
wire prenEmpty, au05z, dcr4, ze;
wire [UADDR_WIDTH-1:0] a1, a2, a3;
wire isPriv, isIllegal, isLineA, isLineF;
// IR & IRD forwarding
always_ff @( posedge Clks.clk) begin
if( enT1) begin
if( Nanod.Ir2Ird)
Ird <= Ir;
else if(microLatch[0]) // prevented by IR => IRD !
Ir <= Irc;
end
end
wire [3:0] tvn;
wire waitBusCycle, busStarting;
wire BusRetry = 1'b0;
wire busAddrErr;
wire bciWrite; // Last bus cycle was write
wire bgBlock, busAvail;
wire addrOe;
wire busIsByte = Nanod.busByte & (Irdecod.isByte | Irdecod.isMovep);
wire aob0;
reg iStop; // Internal signal for ending bus cycle
reg A0Err; // Force bus/address error ucode
reg excRst; // Signal reset exception to sequencer
reg BerrA;
reg Spuria, Avia;
wire Iac;
reg rAddrErr, iBusErr, Err6591;
wire iAddrErr = rAddrErr & addrOe; // To simulate async reset
wire enErrClk;
// Reset micro/nano latch after T4 of the current ublock.
assign rstUrom = Clks.enPhi1 & enErrClk;
uaddrDecode uaddrDecode( .opcode( Ir), .a1, .a2, .a3, .isPriv, .isIllegal, .isLineA, .isLineF, .lineBmap());
sequencer sequencer( .Clks, .enT3, .microLatch, .Ird,
.A0Err, .excRst, .BerrA, .busAddrErr, .Spuria, .Avia,
.Tpend, .intPend, .isIllegal, .isPriv, .isLineA, .isLineF,
.nma, .a1, .a2, .a3, .tvn,
.psw, .prenEmpty, .au05z, .dcr4, .ze, .alue01( alue[1:0]), .i11( Irc[ 11]) );
excUnit excUnit( .Clks, .Nanod, .Irdecod, .enT1, .enT2, .enT3, .enT4,
.Ird, .ftu, .iEdb, .pswS,
.prenEmpty, .au05z, .dcr4, .ze, .AblOut( Abl), .eab, .aob0, .Irc, .oEdb,
.alue, .ccr);
nDecoder3 nDecoder( .Clks, .Nanod, .Irdecod, .enT2, .enT4, .microLatch, .nanoLatch);
irdDecode irdDecode( .ird( Ird), .Irdecod);
busControl busControl( .Clks, .enT1, .enT4, .permStart( Nanod.permStart), .permStop( Nanod.waitBusFinish), .iStop,
.aob0, .isWrite( Nanod.isWrite), .isRmc( Nanod.isRmc), .isByte( busIsByte), .busAvail,
.bciWrite, .addrOe, .bgBlock, .waitBusCycle, .busStarting, .busAddrErr,
.rDtack, .BeDebounced, .Vpai,
.ASn, .LDSn, .UDSn, .eRWn);
busArbiter busArbiter( .Clks, .BRi, .BgackI, .Halti( 1'b1), .bgBlock, .busAvail, .BGn);
// Output reset & halt control
wire [1:0] uFc = microLatch[ 16:15];
logic oReset, oHalted;
assign oRESETn = !oReset;
assign oHALTEDn = !oHalted;
// FC without permStart is special, either reset or halt
always_ff @( posedge Clks.clk) begin
if( Clks.pwrUp) begin
oReset <= 1'b0;
oHalted <= 1'b0;
end
else if( enT1) begin
oReset <= (uFc == 2'b01) & !Nanod.permStart;
oHalted <= (uFc == 2'b10) & !Nanod.permStart;
end
end
logic [2:0] rFC;
assign { FC2, FC1, FC0} = rFC; // ~rFC;
assign Iac = {rFC == 3'b111}; // & Control output enable !!
always_ff @( posedge Clks.clk) begin
if( Clks.extReset)
rFC <= '0;
else if( enT1 & Nanod.permStart) begin // S0 phase of bus cycle
rFC[2] <= pswS;
// PC relativ access is marked as FC type 'n' (0) at ucode.
// We don't care about RZ in this case. Those uinstructions with RZ don't start a bus cycle.
rFC[1] <= microLatch[ 16] | ( ~microLatch[ 15] & ~Irdecod.isPcRel);
rFC[0] <= microLatch[ 15] | ( ~microLatch[ 16] & Irdecod.isPcRel);
end
end
// IPL interface
reg [2:0] inl; // Int level latch
reg updIll;
reg prevNmi;
wire nmi = (iIpl == 3'b111);
wire iplStable = (iIpl == rIpl);
wire iplComp = iIpl > pswI;
always_ff @( posedge Clks.clk) begin
if( Clks.extReset) begin
intPend <= 1'b0;
prevNmi <= 1'b0;
end
else begin
if( Clks.enPhi2)
prevNmi <= nmi;
// Originally async RS-Latch on PHI2, followed by a transparent latch on T2
// Tricky because they might change simultaneously
// Syncronous on PHI2 is equivalent as long as the output is read on T3!
// Set on stable & NMI edge or compare
// Clear on: NMI Iack or (stable & !NMI & !Compare)
if( Clks.enPhi2) begin
if( iplStable & ((nmi & ~prevNmi) | iplComp) )
intPend <= 1'b1;
else if( ((inl == 3'b111) & Iac) | (iplStable & !nmi & !iplComp) )
intPend <= 1'b0;
end
end
if( Clks.extReset) begin
inl <= '1;
updIll <= 1'b0;
end
else if( enT4)
updIll <= microLatch[0]; // Update on any IRC->IR
else if( enT1 & updIll)
inl <= iIpl; // Timing is correct.
// Spurious interrupt, BERR on Interrupt Ack.
// Autovector interrupt. VPA on IACK.
// Timing is tight. Spuria is deasserted just after exception exception is recorded.
if( enT4) begin
Spuria <= ~BeiDelay & Iac;
Avia <= ~Vpai & Iac;
end
end
assign enErrClk = iAddrErr | iBusErr;
assign wClk = waitBusCycle | ~BeI | iAddrErr | Err6591;
// E clock and counter, VMA
reg [3:0] eCntr;
reg rVma;
assign VMAn = rVma;
// Internal stop just one cycle before E falling edge
wire xVma = ~rVma & (eCntr == 8);
always_ff @( posedge Clks.clk) begin
if( Clks.pwrUp) begin
E <= 1'b0;
eCntr <='0;
rVma <= 1'b1;
end
if( Clks.enPhi2) begin
if( eCntr == 9)
E <= 1'b0;
else if( eCntr == 5)
E <= 1'b1;
if( eCntr == 9)
eCntr <= '0;
else
eCntr <= eCntr + 1'b1;
end
if( Clks.enPhi2 & addrOe & ~Vpai & (eCntr == 3))
rVma <= 1'b0;
else if( Clks.enPhi1 & eCntr == '0)
rVma <= 1'b1;
end
always_ff @( posedge Clks.clk) begin
// This timing is critical to stop the clock phases at the exact point on bus/addr error.
// Timing should be such that current ublock completes (up to T3 or T4).
// But T1 for the next ublock shouldn't happen. Next T1 only after resetting ucode and ncode latches.
if( Clks.extReset)
rAddrErr <= 1'b0;
else if( Clks.enPhi1) begin
if( busAddrErr & addrOe) // Not on T1 ?!
rAddrErr <= 1'b1;
else if( ~addrOe) // Actually async reset!
rAddrErr <= 1'b0;
end
if( Clks.extReset)
iBusErr <= 1'b0;
else if( Clks.enPhi1) begin
iBusErr <= ( BerrA & ~BeI & ~Iac & !BusRetry);
end
if( Clks.extReset)
BerrA <= 1'b0;
else if( Clks.enPhi2) begin
if( ~BeI & ~Iac & addrOe)
BerrA <= 1'b1;
// else if( BeI & addrOe) // Bad, async reset since addrOe raising edge
else if( BeI & busStarting) // So replaced with this that raises one cycle earlier
BerrA <= 1'b0;
end
// Signal reset exception to sequencer.
// Originally cleared on 1st T2 after permstart. Must keep it until TVN latched.
if( Clks.extReset)
excRst <= 1'b1;
else if( enT2 & Nanod.permStart)
excRst <= 1'b0;
if( Clks.extReset)
A0Err <= 1'b1; // A0 Reset
else if( enT3) // Keep set until new urom words are being latched
A0Err <= 1'b0;
else if( Clks.enPhi1 & enErrClk & (busAddrErr | BerrA)) // Check bus error timing
A0Err <= 1'b1;
if( Clks.extReset) begin
iStop <= 1'b0;
Err6591 <= 1'b0;
end
else if( Clks.enPhi1)
Err6591 <= enErrClk;
else if( Clks.enPhi2)
iStop <= xVma | (Vpai & (iAddrErr | ~rBerr));
end
// PSW
logic irdToCcr_t4;
always_ff @( posedge Clks.clk) begin
if( Clks.pwrUp) begin
Tpend <= 1'b0;
{pswT, pswS, pswI } <= '0;
irdToCcr_t4 <= '0;
end
else if( enT4) begin
irdToCcr_t4 <= Irdecod.toCcr;
end
else if( enT3) begin
// UNIQUE IF !!
if( Nanod.updTpend)
Tpend <= pswT;
else if( Nanod.clrTpend)
Tpend <= 1'b0;
// UNIQUE IF !!
if( Nanod.ftu2Sr & !irdToCcr_t4)
{pswT, pswS, pswI } <= { ftu[ 15], ftu[13], ftu[10:8]};
else begin
if( Nanod.initST) begin
pswS <= 1'b1;
pswT <= 1'b0;
end
if( Nanod.inl2psw)
pswI <= inl;
end
end
end
// FTU
reg [4:0] ssw;
reg [3:0] tvnLatch;
logic [15:0] tvnMux;
reg inExcept01;
// Seems CPU has a buglet here.
// Flagging group 0 exceptions from TVN might not work because some bus cycles happen before TVN is updated.
// But doesn't matter because a group 0 exception inside another one will halt the CPU anyway and won't save the SSW.
always_ff @( posedge Clks.clk) begin
// Updated at the start of the exception ucode
if( Nanod.updSsw & enT3) begin
ssw <= { ~bciWrite, inExcept01, rFC};
end
// Update TVN on T1 & IR=>IRD
if( enT1 & Nanod.Ir2Ird) begin
tvnLatch <= tvn;
inExcept01 <= (tvn != 1);
end
if( Clks.pwrUp)
ftu <= '0;
else if( enT3) begin
unique case( 1'b1)
Nanod.tvn2Ftu: ftu <= tvnMux;
// 0 on unused bits seem to come from ftuConst PLA previously clearing FBUS
Nanod.sr2Ftu: ftu <= {pswT, 1'b0, pswS, 2'b00, pswI, 3'b000, ccr[4:0] };
Nanod.ird2Ftu: ftu <= Ird;
Nanod.ssw2Ftu: ftu[4:0] <= ssw; // Undoc. Other bits must be preserved from IRD saved above!
Nanod.pswIToFtu: ftu <= { 12'hFFF, pswI, 1'b0}; // Interrupt level shifted
Nanod.const2Ftu: ftu <= Irdecod.ftuConst;
Nanod.abl2Pren: ftu <= Abl; // From ALU or datareg. Used for SR modify
default: ftu <= ftu;
endcase
end
end
always_comb begin
if( inExcept01) begin
// Unique IF !!!
if( tvnLatch == TVN_SPURIOUS)
tvnMux = {9'b0, 5'd24, 2'b00};
else if( tvnLatch == TVN_AUTOVEC)
tvnMux = {9'b0, 2'b11, pswI, 2'b00}; // Set TVN PLA decoder
else if( tvnLatch == TVN_INTERRUPT)
tvnMux = {6'b0, Ird[7:0], 2'b00}; // Interrupt vector was read and transferred to IRD
else
tvnMux = {10'b0, tvnLatch, 2'b00};
end
else
tvnMux = { 8'h0, Irdecod.macroTvn, 2'b00};
end
endmodule

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FX68K
68000 cycle accurate core
Copyright (c) 2018 by Jorge Cwik
fx68k@fxatari.com
FX68K is a 68K cycle exact compatible core. In theory at least, it should be impossible to distinguish functionally from a real 68K processor.
On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance.
The core is fully synchronous. Considerable effort was done to avoid any asynchronous logic.
Written in SystemVerilog.
The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal.
It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented.
Copyright
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
Developer Notes
The core receives a clock that must be at least twice the frequency of the desired nominal speed. The core also receives two signals for masking both phases of the clock (PHI1 and PHI2). These signals are implemented as simple clock enable for all the flip flops used by the core. This way, the original clock frequency can be any multiple and it doesn't even need to be regular or constant.
These two signals are enPhi1 and enPhi2. They must be a single cycle pulse, and they don't need to be registered. Because they are actually used as clock enable, the output signals change one cycle later.
enPhi1 should be asserted one cycle before the high phase of the nominal clock, and enPhi2 one cycle before the low phase.
E.g., during a bus cycle, AS is asserted one cycle after enPhi1 is asserted, and AS is deasserted one cycle after enPhi2 is asserted. This follows the original bus timing that specify AS being asserted on the raising edge of the clock, and deasserted on the falling edge one.
All signals follow the original polarity and then most are low active.
extReset is external reset and is synchronous and high active. Hence is doesn't have to be registered.
pwrUp qualifies external reset as being a cold power up reset. If it is asserted, then extReset must be asserted as well. Most system don't need to distinguish between a cold and a warm reset at the CPU level. Then both signals can be always asserted together. The core does expect pwrUp to be asserted initially because there is no true asynchronous reset. The signal is high active.
Timing analysis
Microcode access is one of the slowest paths on the core. But the microcode output is not needed immediately. Use the following constraints to get a more accurate timing analysis. Note that the full path might need to be modified:
# Altera/Intel
set_multicycle_path -start -setup -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|microAddr[*]] 2
set_multicycle_path -start -hold -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|microAddr[*]] 1
set_multicycle_path -start -setup -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|nanoAddr[*]] 2
set_multicycle_path -start -hold -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|nanoAddr[*]] 1
# For Xilinx Vivado
set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 2
set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 2
set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 1
set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 1

479
common/CPU/68000/FX68k/fx68kAlu.sv Normal file
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//
// FX 68K
//
// M68K cycle accurate, fully synchronous
// Copyright (c) 2018 by Jorge Cwik
//
// ALU
//
`timescale 1 ns / 1 ns
localparam MASK_NBITS = 5;
localparam
OP_AND = 1,
OP_SUB = 2, OP_SUBX = 3, OP_ADD = 4,
OP_EXT = 5, OP_SBCD = 6, OP_SUB0 = 7,
OP_OR = 8, OP_EOR = 9,
OP_SUBC = 10, OP_ADDC = 11, OP_ADDX = 12,
OP_ASL = 13,
OP_ASR = 14,
OP_LSL = 15,
OP_LSR = 16,
OP_ROL = 17,
OP_ROR = 18,
OP_ROXL = 19,
OP_ROXR = 20,
OP_SLAA = 21,
OP_ABCD = 22;
module fx68kAlu ( input clk, pwrUp, enT1, enT3, enT4,
input [15:0] ird,
input [2:0] aluColumn,
input [1:0] aluDataCtrl,
input aluAddrCtrl, alueClkEn, ftu2Ccr, init, finish, aluIsByte,
input [15:0] ftu,
input [15:0] alub,
input [15:0] iDataBus, input [15:0] iAddrBus,
output ze,
output reg [15:0] alue,
output reg [7:0] ccr,
output [15:0] aluOut);
`define ALU_ROW_01 16'h0002
`define ALU_ROW_02 16'h0004
`define ALU_ROW_03 16'h0008
`define ALU_ROW_04 16'h0010
`define ALU_ROW_05 16'h0020
`define ALU_ROW_06 16'h0040
`define ALU_ROW_07 16'h0080
`define ALU_ROW_08 16'h0100
`define ALU_ROW_09 16'h0200
`define ALU_ROW_10 16'h0400
`define ALU_ROW_11 16'h0800
`define ALU_ROW_12 16'h1000
`define ALU_ROW_13 16'h2000
`define ALU_ROW_14 16'h4000
`define ALU_ROW_15 16'h8000
// Bit positions for flags in CCR
localparam CF = 0, VF = 1, ZF = 2, NF = 3, XF = 4;
reg [15:0] aluLatch;
reg [4:0] pswCcr;
reg [4:0] ccrCore;
logic [15:0] result;
logic [4:0] ccrTemp;
reg coreH; // half carry latch
logic [15:0] subResult;
logic subHcarry;
logic subCout, subOv;
assign aluOut = aluLatch;
assign ze = ~ccrCore[ ZF]; // Check polarity !!!
//
// Control
// Signals derived from IRD *must* be registered on either T3 or T4
// Signals derived from nano rom can be registered on T4.
reg [15:0] row;
reg isArX; // Don't set Z
reg noCcrEn;
reg isByte;
reg [4:0] ccrMask;
reg [4:0] oper;
logic [15:0] aOperand, dOperand;
wire isCorf = ( aluDataCtrl == 2'b10);
wire [15:0] cRow;
wire cIsArX;
wire cNoCcrEn;
rowDecoder rowDecoder(
.ird ( ird),
.row ( cRow),
.noCcrEn ( cNoCcrEn),
.isArX ( cIsArX)
);
// Get Operation & CCR Mask from row/col
// Registering them on T4 increase performance. But slowest part seems to be corf !
wire [4:0] cMask;
wire [4:0] aluOp;
aluGetOp aluGetOp(
.row ( row),
.col ( aluColumn),
.isCorf ( isCorf),
.aluOp ( aluOp)
);
ccrTable ccrTable(
.col ( aluColumn),
.row ( row),
.finish ( finish),
.ccrMask ( cMask)
);
// Inefficient, uCode could help !
wire shftIsMul = row[7];
wire shftIsDiv = row[1];
wire [31:0] shftResult;
reg [7:0] bcdLatch;
reg bcdCarry, bcdOverf;
reg isLong;
reg rIrd8;
logic isShift;
logic shftCin, shftRight, addCin;
// Register some decoded signals
always_ff @( posedge clk) begin
if( enT3) begin
row <= cRow;
isArX <= cIsArX;
noCcrEn <= cNoCcrEn;
rIrd8 <= ird[8];
isByte <= aluIsByte;
end
if( enT4) begin
// Decode if long shift
// MUL and DIV are long (but special !)
isLong <= (ird[7] & ~ird[6]) | shftIsMul | shftIsDiv;
ccrMask <= cMask;
oper <= aluOp;
end
end
always_comb begin
// Dest (addr) operand source
// If aluCsr (depends on column/row) addrbus is shifted !!
aOperand = (aluAddrCtrl ? alub : iAddrBus);
// Second (data,source) operand mux
case( aluDataCtrl)
2'b00: dOperand = iDataBus;
2'b01: dOperand = 'h0000;
2'b11: dOperand = 'hffff;
// 2'b10: dOperand = bcdResult;
2'b10: dOperand = 'X;
endcase
end
// Execution
// shift operand MSB. Input in ASR/ROL. Carry in right.
// Can't be registered because uses bus operands that aren't available early !
wire shftMsb = isLong ? alue[15] : (isByte ? aOperand[7] : aOperand[15]);
aluShifter shifter(
.data ( { alue, aOperand}),
.swapWords ( shftIsMul | shftIsDiv),
.cin ( shftCin),
.dir ( shftRight),
.isByte ( isByte),
.isLong ( isLong),
.result ( shftResult)
);
wire [7:0] bcdResult;
wire bcdC, bcdV;
aluCorf aluCorf(
.binResult ( aluLatch[7:0]),
.hCarry ( coreH),
.bAdd ( (oper != OP_SBCD) ),
.cin ( pswCcr[ XF]),
.bcdResult ( bcdResult),
.dC ( bcdC),
.ov ( bcdV));
// BCD adjust is among the slowest processing on ALU !
// Precompute and register BCD result on T1
// We don't need to wait for execution buses because corf is always added to ALU previous result
always_ff @( posedge clk)
if( enT1) begin
bcdLatch <= bcdResult;
bcdCarry <= bcdC;
bcdOverf <= bcdV;
end
// Adder carry in selector
always_comb
begin
case( oper)
OP_ADD, OP_SUB: addCin = 1'b0;
OP_SUB0: addCin = 1'b1; // NOT = 0 - op - 1
OP_ADDC,OP_SUBC: addCin = ccrCore[ CF];
OP_ADDX,OP_SUBX: addCin = pswCcr[ XF];
default: addCin = 1'bX;
endcase
end
// Shifter carry in and direction selector
always_comb begin
case( oper)
OP_LSL, OP_ASL, OP_ROL, OP_ROXL, OP_SLAA: shftRight = 1'b0;
OP_LSR, OP_ASR, OP_ROR, OP_ROXR: shftRight = 1'b1;
default: shftRight = 1'bX;
endcase
case( oper)
OP_LSR,
OP_ASL,
OP_LSL: shftCin = 1'b0;
OP_ROL,
OP_ASR: shftCin = shftMsb;
OP_ROR: shftCin = aOperand[0];
OP_ROXL,
OP_ROXR:
if( shftIsMul)
shftCin = rIrd8 ? pswCcr[NF] ^ pswCcr[VF] : pswCcr[ CF];
else
shftCin = pswCcr[ XF];
OP_SLAA: shftCin = aluColumn[1]; // col4 -> 0, col 6-> 1
default: shftCin = 'X;
endcase
end
// ALU operation selector
always_comb begin
// sub is DATA - ADDR
mySubber( aOperand, dOperand, addCin,
(oper == OP_ADD) | (oper == OP_ADDC) | (oper == OP_ADDX),
isByte, subResult, subCout, subOv);
isShift = 1'b0;
case( oper)
OP_AND: result = aOperand & dOperand;
OP_OR: result = aOperand | dOperand;
OP_EOR: result = aOperand ^ dOperand;
OP_EXT: result = { {8{aOperand[7]}}, aOperand[7:0]};
OP_SLAA,
OP_ASL, OP_ASR,
OP_LSL, OP_LSR,
OP_ROL, OP_ROR,
OP_ROXL, OP_ROXR:
begin
result = shftResult[15:0];
isShift = 1'b1;
end
OP_ADD,
OP_ADDC,
OP_ADDX,
OP_SUB,
OP_SUBC,
OP_SUB0,
OP_SUBX: result = subResult;
OP_ABCD,
OP_SBCD: result = { 8'hXX, bcdLatch};
default: result = 'X;
endcase
end
task mySubber;
input [15:0] inpa, inpb;
input cin, bAdd, isByte;
output reg [15:0] result;
output cout, ov;
// Not very efficient!
logic [16:0] rtemp;
logic rm,sm,dm,tsm;
begin
if( isByte)
begin
rtemp = bAdd ? { 1'b0, inpb[7:0]} + { 1'b0, inpa[7:0]} + cin:
{ 1'b0, inpb[7:0] } - { 1'b0, inpa[7:0]} - cin;
result = { {8{ rtemp[7]}}, rtemp[7:0]};
cout = rtemp[8];
end
else begin
rtemp = bAdd ? { 1'b0, inpb } + { 1'b0, inpa} + cin:
{ 1'b0, inpb } - { 1'b0, inpa} - cin;
result = rtemp[ 15:0];
cout = rtemp[16];
end
rm = isByte ? rtemp[7] : rtemp[15];
dm = isByte ? inpb[ 7] : inpb[ 15];
tsm = isByte ? inpa[ 7] : inpa[ 15];
sm = bAdd ? tsm : ~tsm;
ov = (sm & dm & ~rm) | (~sm & ~dm & rm);
// Store half carry for bcd correction
subHcarry = inpa[4] ^ inpb[4] ^ rtemp[4];
end
endtask
// CCR flags process
always_comb begin
ccrTemp[XF] = pswCcr[XF]; ccrTemp[CF] = 0; ccrTemp[VF] = 0;
// Not on all operators !!!
ccrTemp[ ZF] = isByte ? ~(| result[7:0]) : ~(| result);
ccrTemp[ NF] = isByte ? result[7] : result[15];
unique case( oper)
OP_EXT:
// Division overflow.
if( aluColumn == 5) begin
ccrTemp[VF] = 1'b1; ccrTemp[NF] = 1'b1;
end
OP_SUB0, // used by NOT
OP_OR,
OP_EOR:
begin
ccrTemp[CF] = 0; ccrTemp[VF] = 0;
end
OP_AND:
begin
// ROXL/ROXR indeed copy X to C in column 1 (OP_AND), executed before entering the loop.
// Needed when rotate count is zero, the ucode with the ROX operator never reached.
// C must be set to the value of X, X remains unaffected.
if( (aluColumn == 1) & (row[11] | row[8]))
ccrTemp[CF] = pswCcr[XF];
else
ccrTemp[CF] = 0;
ccrTemp[VF] = 0;
end
// Assumes col 3 of DIV use C and not X !
// V will be set in other cols (2/3) of DIV
OP_SLAA: ccrTemp[ CF] = aOperand[15];
OP_LSL,OP_ROXL:
begin
ccrTemp[ CF] = shftMsb;
ccrTemp[ XF] = shftMsb;
ccrTemp[ VF] = 1'b0;
end
OP_LSR,OP_ROXR:
begin
// 0 Needed for mul, or carry gets in high word
ccrTemp[ CF] = shftIsMul ? 1'b0 : aOperand[0];
ccrTemp[ XF] = aOperand[0];
// Not relevant for MUL, we clear it at mulm6 (1f) anyway.
// Not that MUL can never overlow!
ccrTemp[ VF] = 0;
// Z is checking here ALU (low result is actually in ALUE).
// But it is correct, see comment above.
end
OP_ASL:
begin
ccrTemp[ XF] = shftMsb; ccrTemp[ CF] = shftMsb;
// V set if msb changed on any shift.
// Otherwise clear previously on OP_AND (col 1i).
ccrTemp[ VF] = pswCcr[VF] | (shftMsb ^
(isLong ? alue[15-1] : (isByte ? aOperand[7-1] : aOperand[15-1])) );
end
OP_ASR:
begin
ccrTemp[ XF] = aOperand[0]; ccrTemp[ CF] = aOperand[0];
ccrTemp[ VF] = 0;
end
// X not changed on ROL/ROR !
OP_ROL: ccrTemp[ CF] = shftMsb;
OP_ROR: ccrTemp[ CF] = aOperand[0];
OP_ADD,
OP_ADDC,
OP_ADDX,
OP_SUB,
OP_SUBC,
OP_SUBX:
begin
ccrTemp[ CF] = subCout;
ccrTemp[ XF] = subCout;
ccrTemp[ VF] = subOv;
end
OP_ABCD,
OP_SBCD:
begin
ccrTemp[ XF] = bcdCarry;
ccrTemp[ CF] = bcdCarry;
ccrTemp[ VF] = bcdOverf;
end
endcase
end
// Core and psw latched at the same cycle
// CCR filter
// CCR out mux for Z & C flags
// Z flag for 32-bit result
// Not described, but should be used also for instructions
// that clear but not set Z (ADDX/SUBX/ABCD, etc)!
logic [4:0] ccrMasked;
always_comb begin
ccrMasked = (ccrTemp & ccrMask) | (pswCcr & ~ccrMask);
if( finish | isCorf | isArX)
ccrMasked[ ZF] = ccrTemp[ ZF] & pswCcr[ ZF];
end
always_ff @( posedge clk) begin
if( enT3) begin
// Update latches from ALU operators
if( (| aluColumn)) begin
aluLatch <= result;
coreH <= subHcarry;
// Update CCR core
if( (| aluColumn))
ccrCore <= ccrTemp; // Most bits not really used
end
if( alueClkEn)
alue <= iDataBus;
else if( isShift & (| aluColumn))
alue <= shftResult[31:16];
end
// CCR
// Originally on T3-T4 edge pulse !!
// Might be possible to update on T4 (but not after T0) from partial result registered on T3, it will increase performance!
if( pwrUp)
pswCcr <= '0;
else if( enT3 & ftu2Ccr)
pswCcr <= ftu[4:0];
else if( enT3 & ~noCcrEn & (finish | init))
pswCcr <= ccrMasked;
end
assign ccr = { 3'b0, pswCcr};
endmodule

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common/CPU/68000/FX68k/fx68k_tb.sv Normal file
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//
// For compilation test only
//
module fx68k_tb( input clk32,
input extReset,
// input pwrUp,
input DTACKn, input VPAn,
input BERRn,
input BRn, BGACKn,
input IPL0n, input IPL1n, input IPL2n,
input [15:0] iEdb,
output [15:0] oEdb,
output eRWn, output ASn, output LDSn, output UDSn,
output logic E, output VMAn,
output FC0, output FC1, output FC2,
output BGn,
output oRESETn, output oHALTEDn,
output [23:1] eab
);
// Clock must be at least twice the desired frequency. A 32 MHz clock means a maximum 16 MHz effective frequency.
// In this example we divide the clock by 4. Resulting on an effective processor running at 8 MHz.
reg [1:0] clkDivisor = '0;
always @( posedge clk32) begin
clkDivisor <= clkDivisor + 1'b1;
end
/*
These two signals must be a single cycle pulse. They don't need to be registered.
Same signal can't be asserted twice in a row. Other than that there are no restrictions.
There can be any number of cycles, or none, even variable non constant cycles, between each pulse.
*/
wire enPhi1 = (clkDivisor == 2'b11);
wire enPhi2 = (clkDivisor == 2'b01);
fx68k fx68k( .clk( clk32),
.extReset, .pwrUp( extReset), .enPhi1, .enPhi2,
.DTACKn, .VPAn, .BERRn, .BRn, .BGACKn,
.IPL0n, .IPL1n, .IPL2n,
.iEdb,
.oEdb,
.eRWn, .ASn, .LDSn, .UDSn,
.E, .VMAn,
.FC0, .FC1, .FC2,
.BGn,
.oRESETn, .oHALTEDn, .eab);
endmodule

208
common/CPU/68000/FX68k/irdDecode.sv Normal file
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//
// IRD execution decoder. Complements nano code decoder
//
// IRD updated on T1, while ncode still executing. To avoid using the next IRD,
// decoded signals must be registered on T3, or T4 before using them.
//
module irdDecode( input [15:0] ird,
output s_irdecod Irdecod);
wire [3:0] line = ird[15:12];
logic [15:0] lineOnehot;
// This can be registered and pipelined from the IR decoder !
onehotEncoder4 irdLines( line, lineOnehot);
wire isRegShift = (lineOnehot['he]) & (ird[7:6] != 2'b11);
wire isDynShift = isRegShift & ird[5];
assign Irdecod.isPcRel = (& ird[ 5:3]) & ~isDynShift & !ird[2] & ird[1];
assign Irdecod.isTas = lineOnehot[4] & (ird[11:6] == 6'b101011);
assign Irdecod.rx = ird[11:9];
assign Irdecod.ry = ird[ 2:0];
wire isPreDecr = (ird[ 5:3] == 3'b100);
wire eaAreg = (ird[5:3] == 3'b001);
// rx is A or D
// movem
always_comb begin
unique case( 1'b1)
lineOnehot[1],
lineOnehot[2],
lineOnehot[3]:
// MOVE: RX always Areg except if dest mode is Dn 000
Irdecod.rxIsAreg = (| ird[8:6]);
lineOnehot[4]: Irdecod.rxIsAreg = (& ird[8:6]); // not CHK (LEA)
lineOnehot['h8]: Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7]; // SBCD
lineOnehot['hc]: Irdecod.rxIsAreg = eaAreg & ird[8] & ~ird[7]; // ABCD/EXG An,An
lineOnehot['h9],
lineOnehot['hb],
lineOnehot['hd]: Irdecod.rxIsAreg =
(ird[7] & ird[6]) | // SUBA/CMPA/ADDA
(eaAreg & ird[8] & (ird[7:6] != 2'b11)); // SUBX/CMPM/ADDX
default:
Irdecod.rxIsAreg = Irdecod.implicitSp;
endcase
end
// RX is movem
always_comb begin
Irdecod.rxIsMovem = lineOnehot[4] & ~ird[8] & ~Irdecod.implicitSp;
end
assign Irdecod.movemPreDecr = Irdecod.rxIsMovem & isPreDecr;
// RX is DT.
// but SSP explicit or pc explicit has higher priority!
// addq/subq (scc & dbcc also, but don't use rx)
// Immediate including static bit
assign Irdecod.rxIsDt = lineOnehot[5] | (lineOnehot[0] & ~ird[8]);
// RX is USP
assign Irdecod.rxIsUsp = lineOnehot[4] & (ird[ 11:4] == 8'he6);
// RY is DT
// rz or PC explicit has higher priority
wire eaImmOrAbs = (ird[5:3] == 3'b111) & ~ird[1];
assign Irdecod.ryIsDt = eaImmOrAbs & ~isRegShift;
// RY is Address register
always_comb begin
logic eaIsAreg;
// On most cases RY is Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
eaIsAreg = (ird[5:3] != 3'b000) & (ird[5:3] != 3'b111);
unique case( 1'b1)
// MOVE: RY always Areg expect if mode is 000 (DATA REG) or 111 (IMM, ABS,PC REL)
// Most lines, including misc line 4, also.
default: Irdecod.ryIsAreg = eaIsAreg;
lineOnehot[5]: // DBcc is an exception
Irdecod.ryIsAreg = eaIsAreg & (ird[7:3] != 5'b11001);
lineOnehot[6],
lineOnehot[7]: Irdecod.ryIsAreg = 1'b0;
lineOnehot['he]:
Irdecod.ryIsAreg = ~isRegShift;
endcase
end
// Byte sized instruction
// Original implementation sets this for some instructions that aren't really byte size
// but doesn't matter because they don't have a byte transfer enabled at nanocode, such as MOVEQ
wire xIsScc = (ird[7:6] == 2'b11) & (ird[5:3] != 3'b001);
wire xStaticMem = (ird[11:8] == 4'b1000) & (ird[5:4] == 2'b00); // Static bit to mem
always_comb begin
unique case( 1'b1)
lineOnehot[0]:
Irdecod.isByte =
( ird[8] & (ird[5:4] != 2'b00) ) | // Dynamic bit to mem
( (ird[11:8] == 4'b1000) & (ird[5:4] != 2'b00) ) | // Static bit to mem
( (ird[8:7] == 2'b10) & (ird[5:3] == 3'b001) ) | // Movep from mem only! For byte mux
( (ird[8:6] == 3'b000) & !xStaticMem ); // Immediate byte
lineOnehot[1]: Irdecod.isByte = 1'b1; // MOVE.B
lineOnehot[4]: Irdecod.isByte = (ird[7:6] == 2'b00) | Irdecod.isTas;
lineOnehot[5]: Irdecod.isByte = (ird[7:6] == 2'b00) | xIsScc;
lineOnehot[8],
lineOnehot[9],
lineOnehot['hb],
lineOnehot['hc],
lineOnehot['hd],
lineOnehot['he]: Irdecod.isByte = (ird[7:6] == 2'b00);
default: Irdecod.isByte = 1'b0;
endcase
end
// Need it for special byte size. Bus is byte, but whole register word is modified.
assign Irdecod.isMovep = lineOnehot[0] & ird[8] & eaAreg;
// rxIsSP implicit use of RX for actual SP transfer
//
// This logic is simple and will include some instructions that don't actually reference SP.
// But doesn't matter as long as they don't perform any RX transfer.
always_comb begin
unique case( 1'b1)
lineOnehot[6]: Irdecod.implicitSp = (ird[11:8] == 4'b0001); // BSR
lineOnehot[4]:
// Misc like RTS, JSR, etc
Irdecod.implicitSp = (ird[11:8] == 4'b1110) | (ird[11:6] == 6'b1000_01);
default: Irdecod.implicitSp = 1'b0;
endcase
end
// Modify CCR (and not SR)
// Probably overkill !! Only needs to distinguish SR vs CCR
// RTR, MOVE to CCR, xxxI to CCR
assign Irdecod.toCcr = ( lineOnehot[4] & ((ird[11:0] == 12'he77) | (ird[11:6] == 6'b010011)) ) |
( lineOnehot[0] & (ird[8:6] == 3'b000));
// FTU constants
// This should not be latched on T3/T4. Latch on T2 or not at all. FTU needs it on next T3.
// Note: Reset instruction gets constant from ALU not from FTU!
logic [15:0] ftuConst;
wire [3:0] zero28 = (ird[11:9] == 0) ? 4'h8 : { 1'b0, ird[11:9]}; // xltate 0,1-7 into 8,1-7
always_comb begin
unique case( 1'b1)
lineOnehot[6], // Bcc short
lineOnehot[7]: ftuConst = { { 8{ ird[ 7]}}, ird[ 7:0] }; // MOVEQ
lineOnehot['h5], // addq/subq/static shift double check this
lineOnehot['he]: ftuConst = { 12'b0, zero28};
// MULU/MULS DIVU/DIVS
lineOnehot['h8],
lineOnehot['hc]: ftuConst = 16'h0f;
lineOnehot[4]: ftuConst = 16'h80; // TAS
default: ftuConst = '0;
endcase
end
assign Irdecod.ftuConst = ftuConst;
//
// TRAP Vector # for group 2 exceptions
//
always_comb begin
if( lineOnehot[4]) begin
case ( ird[6:5])
2'b00,2'b01: Irdecod.macroTvn = 6; // CHK
2'b11: Irdecod.macroTvn = 7; // TRAPV
2'b10: Irdecod.macroTvn = {2'b10, ird[3:0]}; // TRAP
endcase
end
else
Irdecod.macroTvn = 5; // Division by zero
end
wire eaAdir = (ird[ 5:3] == 3'b001);
wire size11 = ird[7] & ird[6];
// Opcodes variants that don't affect flags
// ADDA/SUBA ADDQ/SUBQ MOVEA
assign Irdecod.inhibitCcr =
( (lineOnehot[9] | lineOnehot['hd]) & size11) | // ADDA/SUBA
( lineOnehot[5] & eaAdir) | // ADDQ/SUBQ to An (originally checks for line[4] as well !?)
( (lineOnehot[2] | lineOnehot[3]) & ird[8:6] == 3'b001); // MOVEA
endmodule

157
common/CPU/68000/FX68k/microToNanoAddr.sv Normal file
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// Translate uaddr to nanoaddr
module microToNanoAddr(
input [UADDR_WIDTH-1:0] uAddr,
output [NADDR_WIDTH-1:0] orgAddr);
wire [UADDR_WIDTH-1:2] baseAddr = uAddr[UADDR_WIDTH-1:2];
logic [NADDR_WIDTH-1:2] orgBase;
assign orgAddr = { orgBase, uAddr[1:0]};
always @( baseAddr)
begin
// nano ROM (136 addresses)
case( baseAddr)
'h00: orgBase = 7'h0 ;
'h01: orgBase = 7'h1 ;
'h02: orgBase = 7'h2 ;
'h03: orgBase = 7'h2 ;
'h08: orgBase = 7'h3 ;
'h09: orgBase = 7'h4 ;
'h0A: orgBase = 7'h5 ;
'h0B: orgBase = 7'h5 ;
'h10: orgBase = 7'h6 ;
'h11: orgBase = 7'h7 ;
'h12: orgBase = 7'h8 ;
'h13: orgBase = 7'h8 ;
'h18: orgBase = 7'h9 ;
'h19: orgBase = 7'hA ;
'h1A: orgBase = 7'hB ;
'h1B: orgBase = 7'hB ;
'h20: orgBase = 7'hC ;
'h21: orgBase = 7'hD ;
'h22: orgBase = 7'hE ;
'h23: orgBase = 7'hD ;
'h28: orgBase = 7'hF ;
'h29: orgBase = 7'h10 ;
'h2A: orgBase = 7'h11 ;
'h2B: orgBase = 7'h10 ;
'h30: orgBase = 7'h12 ;
'h31: orgBase = 7'h13 ;
'h32: orgBase = 7'h14 ;
'h33: orgBase = 7'h14 ;
'h38: orgBase = 7'h15 ;
'h39: orgBase = 7'h16 ;
'h3A: orgBase = 7'h17 ;
'h3B: orgBase = 7'h17 ;
'h40: orgBase = 7'h18 ;
'h41: orgBase = 7'h18 ;
'h42: orgBase = 7'h18 ;
'h43: orgBase = 7'h18 ;
'h44: orgBase = 7'h19 ;
'h45: orgBase = 7'h19 ;
'h46: orgBase = 7'h19 ;
'h47: orgBase = 7'h19 ;
'h48: orgBase = 7'h1A ;
'h49: orgBase = 7'h1A ;
'h4A: orgBase = 7'h1A ;
'h4B: orgBase = 7'h1A ;
'h4C: orgBase = 7'h1B ;
'h4D: orgBase = 7'h1B ;
'h4E: orgBase = 7'h1B ;
'h4F: orgBase = 7'h1B ;
'h54: orgBase = 7'h1C ;
'h55: orgBase = 7'h1D ;
'h56: orgBase = 7'h1E ;
'h57: orgBase = 7'h1F ;
'h5C: orgBase = 7'h20 ;
'h5D: orgBase = 7'h21 ;
'h5E: orgBase = 7'h22 ;
'h5F: orgBase = 7'h23 ;
'h70: orgBase = 7'h24 ;
'h71: orgBase = 7'h24 ;
'h72: orgBase = 7'h24 ;
'h73: orgBase = 7'h24 ;
'h74: orgBase = 7'h24 ;
'h75: orgBase = 7'h24 ;
'h76: orgBase = 7'h24 ;
'h77: orgBase = 7'h24 ;
'h78: orgBase = 7'h25 ;
'h79: orgBase = 7'h25 ;
'h7A: orgBase = 7'h25 ;
'h7B: orgBase = 7'h25 ;
'h7C: orgBase = 7'h25 ;
'h7D: orgBase = 7'h25 ;
'h7E: orgBase = 7'h25 ;
'h7F: orgBase = 7'h25 ;
'h84: orgBase = 7'h26 ;
'h85: orgBase = 7'h27 ;
'h86: orgBase = 7'h28 ;
'h87: orgBase = 7'h29 ;
'h8C: orgBase = 7'h2A ;
'h8D: orgBase = 7'h2B ;
'h8E: orgBase = 7'h2C ;
'h8F: orgBase = 7'h2D ;
'h94: orgBase = 7'h2E ;
'h95: orgBase = 7'h2F ;
'h96: orgBase = 7'h30 ;
'h97: orgBase = 7'h31 ;
'h9C: orgBase = 7'h32 ;
'h9D: orgBase = 7'h33 ;
'h9E: orgBase = 7'h34 ;
'h9F: orgBase = 7'h35 ;
'hA4: orgBase = 7'h36 ;
'hA5: orgBase = 7'h36 ;
'hA6: orgBase = 7'h37 ;
'hA7: orgBase = 7'h37 ;
'hAC: orgBase = 7'h38 ;
'hAD: orgBase = 7'h38 ;
'hAE: orgBase = 7'h39 ;
'hAF: orgBase = 7'h39 ;
'hB4: orgBase = 7'h3A ;
'hB5: orgBase = 7'h3A ;
'hB6: orgBase = 7'h3B ;
'hB7: orgBase = 7'h3B ;
'hBC: orgBase = 7'h3C ;
'hBD: orgBase = 7'h3C ;
'hBE: orgBase = 7'h3D ;
'hBF: orgBase = 7'h3D ;
'hC0: orgBase = 7'h3E ;
'hC1: orgBase = 7'h3F ;
'hC2: orgBase = 7'h40 ;
'hC3: orgBase = 7'h41 ;
'hC8: orgBase = 7'h42 ;
'hC9: orgBase = 7'h43 ;
'hCA: orgBase = 7'h44 ;
'hCB: orgBase = 7'h45 ;
'hD0: orgBase = 7'h46 ;
'hD1: orgBase = 7'h47 ;
'hD2: orgBase = 7'h48 ;
'hD3: orgBase = 7'h49 ;
'hD8: orgBase = 7'h4A ;
'hD9: orgBase = 7'h4B ;
'hDA: orgBase = 7'h4C ;
'hDB: orgBase = 7'h4D ;
'hE0: orgBase = 7'h4E ;
'hE1: orgBase = 7'h4E ;
'hE2: orgBase = 7'h4F ;
'hE3: orgBase = 7'h4F ;
'hE8: orgBase = 7'h50 ;
'hE9: orgBase = 7'h50 ;
'hEA: orgBase = 7'h51 ;
'hEB: orgBase = 7'h51 ;
'hF0: orgBase = 7'h52 ;
'hF1: orgBase = 7'h52 ;
'hF2: orgBase = 7'h52 ;
'hF3: orgBase = 7'h52 ;
'hF8: orgBase = 7'h53 ;
'hF9: orgBase = 7'h53 ;
'hFA: orgBase = 7'h53 ;
'hFB: orgBase = 7'h53 ;
default:
orgBase = 'X;
endcase
end
endmodule

1024
common/CPU/68000/FX68k/microrom.mem Normal file
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274
common/CPU/68000/FX68k/nDecoder3.sv Normal file
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// Nanorom (plus) decoder for die nanocode
module nDecoder3( input s_clks Clks, input s_irdecod Irdecod, output s_nanod Nanod,
input enT2, enT4,
input [UROM_WIDTH-1:0] microLatch,
input [NANO_WIDTH-1:0] nanoLatch);
localparam NANO_IR2IRD = 67;
localparam NANO_TOIRC = 66;
localparam NANO_ALU_COL = 63; // ALU operator column order is 63-64-65 !
localparam NANO_ALU_FI = 61; // ALU finish-init 62-61
localparam NANO_TODBIN = 60;
localparam NANO_ALUE = 57; // 57-59 shared with DCR control
localparam NANO_DCR = 57; // 57-59 shared with ALUE control
localparam NANO_DOBCTRL_1 = 56; // Input to control and permwrite
localparam NANO_LOWBYTE = 55; // Used by MOVEP
localparam NANO_HIGHBYTE = 54;
localparam NANO_DOBCTRL_0 = 53; // Input to control and permwrite
localparam NANO_ALU_DCTRL = 51; // 52-51 databus input mux control
localparam NANO_ALU_ACTRL = 50; // addrbus input mux control
localparam NANO_DBD2ALUB = 49;
localparam NANO_ABD2ALUB = 48;
localparam NANO_DBIN2DBD = 47;
localparam NANO_DBIN2ABD = 46;
localparam NANO_ALU2ABD = 45;
localparam NANO_ALU2DBD = 44;
localparam NANO_RZ = 43;
localparam NANO_BUSBYTE = 42; // If *both* this set and instruction is byte sized, then bus cycle is byte sized.
localparam NANO_PCLABL = 41;
localparam NANO_RXL_DBL = 40; // Switches RXL/RYL on DBL/ABL buses
localparam NANO_PCLDBL = 39;
localparam NANO_ABDHRECHARGE = 38;
localparam NANO_REG2ABL = 37; // register to ABL
localparam NANO_ABL2REG = 36; // ABL to register
localparam NANO_ABLABD = 35;
localparam NANO_DBLDBD = 34;
localparam NANO_DBL2REG = 33; // DBL to register
localparam NANO_REG2DBL = 32; // register to DBL
localparam NANO_ATLCTRL = 29; // 31-29
localparam NANO_FTUCONTROL = 25;
localparam NANO_SSP = 24;
localparam NANO_RXH_DBH = 22; // Switches RXH/RYH on DBH/ABH buses
localparam NANO_AUOUT = 20; // 21-20
localparam NANO_AUCLKEN = 19;
localparam NANO_AUCTRL = 16; // 18-16
localparam NANO_DBLDBH = 15;
localparam NANO_ABLABH = 14;
localparam NANO_EXT_ABH = 13;
localparam NANO_EXT_DBH = 12;
localparam NANO_ATHCTRL = 9; // 11-9
localparam NANO_REG2ABH = 8; // register to ABH
localparam NANO_ABH2REG = 7; // ABH to register
localparam NANO_REG2DBH = 6; // register to DBH
localparam NANO_DBH2REG = 5; // DBH to register
localparam NANO_AOBCTRL = 3; // 4-3
localparam NANO_PCH = 0; // 1-0 PchDbh PchAbh
localparam NANO_NO_SP_ALGN = 0; // Same bits as above when both set
localparam NANO_FTU_UPDTPEND = 1; // Also loads FTU constant according to IRD !
localparam NANO_FTU_INIT_ST = 15; // Set S, clear T (but not TPEND)
localparam NANO_FTU_CLRTPEND = 14;
localparam NANO_FTU_TVN = 13;
localparam NANO_FTU_ABL2PREN = 12; // ABL => FTU & ABL => PREN. Both transfers enabled, but only one will be used depending on uroutine.
localparam NANO_FTU_SSW = 11;
localparam NANO_FTU_RSTPREN = 10;
localparam NANO_FTU_IRD = 9;
localparam NANO_FTU_2ABL = 8;
localparam NANO_FTU_RDSR = 7;
localparam NANO_FTU_INL = 6;
localparam NANO_FTU_PSWI = 5; // Read Int Mask into FTU
localparam NANO_FTU_DBL = 4;
localparam NANO_FTU_2SR = 2;
localparam NANO_FTU_CONST = 1;
reg [3:0] ftuCtrl;
logic [2:0] athCtrl, atlCtrl;
assign athCtrl = nanoLatch[ NANO_ATHCTRL+2: NANO_ATHCTRL];
assign atlCtrl = nanoLatch[ NANO_ATLCTRL+2: NANO_ATLCTRL];
wire [1:0] aobCtrl = nanoLatch[ NANO_AOBCTRL+1:NANO_AOBCTRL];
wire [1:0] dobCtrl = {nanoLatch[ NANO_DOBCTRL_1], nanoLatch[NANO_DOBCTRL_0]};
always_ff @( posedge Clks.clk) begin
if( enT4) begin
// Reverse order!
ftuCtrl <= { nanoLatch[ NANO_FTUCONTROL+0], nanoLatch[ NANO_FTUCONTROL+1], nanoLatch[ NANO_FTUCONTROL+2], nanoLatch[ NANO_FTUCONTROL+3]} ;
Nanod.auClkEn <= !nanoLatch[ NANO_AUCLKEN];
Nanod.auCntrl <= nanoLatch[ NANO_AUCTRL+2 : NANO_AUCTRL+0];
Nanod.noSpAlign <= (nanoLatch[ NANO_NO_SP_ALGN + 1:NANO_NO_SP_ALGN] == 2'b11);
Nanod.extDbh <= nanoLatch[ NANO_EXT_DBH];
Nanod.extAbh <= nanoLatch[ NANO_EXT_ABH];
Nanod.todbin <= nanoLatch[ NANO_TODBIN];
Nanod.toIrc <= nanoLatch[ NANO_TOIRC];
// ablAbd is disabled on byte transfers (adbhCharge plus irdIsByte). Not sure the combination makes much sense.
// It happens in a few cases but I don't see anything enabled on abL (or abH) section anyway.
Nanod.ablAbd <= nanoLatch[ NANO_ABLABD];
Nanod.ablAbh <= nanoLatch[ NANO_ABLABH];
Nanod.dblDbd <= nanoLatch[ NANO_DBLDBD];
Nanod.dblDbh <= nanoLatch[ NANO_DBLDBH];
Nanod.dbl2Atl <= (atlCtrl == 3'b010);
Nanod.atl2Dbl <= (atlCtrl == 3'b011);
Nanod.abl2Atl <= (atlCtrl == 3'b100);
Nanod.atl2Abl <= (atlCtrl == 3'b101);
Nanod.aob2Ab <= (athCtrl == 3'b101); // Used on BSER1 only
Nanod.abh2Ath <= (athCtrl == 3'b001) | (athCtrl == 3'b101);
Nanod.dbh2Ath <= (athCtrl == 3'b100);
Nanod.ath2Dbh <= (athCtrl == 3'b110);
Nanod.ath2Abh <= (athCtrl == 3'b011);
Nanod.alu2Dbd <= nanoLatch[ NANO_ALU2DBD];
Nanod.alu2Abd <= nanoLatch[ NANO_ALU2ABD];
Nanod.abd2Dcr <= (nanoLatch[ NANO_DCR+1:NANO_DCR] == 2'b11);
Nanod.dcr2Dbd <= (nanoLatch[ NANO_DCR+2:NANO_DCR+1] == 2'b11);
Nanod.dbd2Alue <= (nanoLatch[ NANO_ALUE+2:NANO_ALUE+1] == 2'b10);
Nanod.alue2Dbd <= (nanoLatch[ NANO_ALUE+1:NANO_ALUE] == 2'b01);
Nanod.dbd2Alub <= nanoLatch[ NANO_DBD2ALUB];
Nanod.abd2Alub <= nanoLatch[ NANO_ABD2ALUB];
// Originally not latched. We better should because we transfer one cycle later, T3 instead of T1.
Nanod.dobCtrl <= dobCtrl;
// Nanod.adb2Dob <= (dobCtrl == 2'b10); Nanod.dbd2Dob <= (dobCtrl == 2'b01); Nanod.alu2Dob <= (dobCtrl == 2'b11);
end
end
// Update SSW at the start of Bus/Addr error ucode
assign Nanod.updSsw = Nanod.aob2Ab;
assign Nanod.updTpend = (ftuCtrl == NANO_FTU_UPDTPEND);
assign Nanod.clrTpend = (ftuCtrl == NANO_FTU_CLRTPEND);
assign Nanod.tvn2Ftu = (ftuCtrl == NANO_FTU_TVN);
assign Nanod.const2Ftu = (ftuCtrl == NANO_FTU_CONST);
assign Nanod.ftu2Dbl = (ftuCtrl == NANO_FTU_DBL) | ( ftuCtrl == NANO_FTU_INL);
assign Nanod.ftu2Abl = (ftuCtrl == NANO_FTU_2ABL);
assign Nanod.inl2psw = (ftuCtrl == NANO_FTU_INL);
assign Nanod.pswIToFtu = (ftuCtrl == NANO_FTU_PSWI);
assign Nanod.ftu2Sr = (ftuCtrl == NANO_FTU_2SR);
assign Nanod.sr2Ftu = (ftuCtrl == NANO_FTU_RDSR);
assign Nanod.ird2Ftu = (ftuCtrl == NANO_FTU_IRD); // Used on bus/addr error
assign Nanod.ssw2Ftu = (ftuCtrl == NANO_FTU_SSW);
assign Nanod.initST = (ftuCtrl == NANO_FTU_INL) | (ftuCtrl == NANO_FTU_CLRTPEND) | (ftuCtrl == NANO_FTU_INIT_ST);
assign Nanod.abl2Pren = (ftuCtrl == NANO_FTU_ABL2PREN);
assign Nanod.updPren = (ftuCtrl == NANO_FTU_RSTPREN);
assign Nanod.Ir2Ird = nanoLatch[ NANO_IR2IRD];
// ALU control better latched later after combining with IRD decoding
assign Nanod.aluDctrl = nanoLatch[ NANO_ALU_DCTRL+1 : NANO_ALU_DCTRL];
assign Nanod.aluActrl = nanoLatch[ NANO_ALU_ACTRL];
assign Nanod.aluColumn = { nanoLatch[ NANO_ALU_COL], nanoLatch[ NANO_ALU_COL+1], nanoLatch[ NANO_ALU_COL+2]};
wire [1:0] aluFinInit = nanoLatch[ NANO_ALU_FI+1:NANO_ALU_FI];
assign Nanod.aluFinish = (aluFinInit == 2'b10);
assign Nanod.aluInit = (aluFinInit == 2'b01);
// FTU 2 CCR encoded as both ALU Init and ALU Finish set.
// In theory this encoding allows writes to CCR without writing to SR
// But FTU 2 CCR and to SR are both set together at nanorom.
assign Nanod.ftu2Ccr = ( aluFinInit == 2'b11);
assign Nanod.abdIsByte = nanoLatch[ NANO_ABDHRECHARGE];
// Not being latched on T4 creates non unique case warning!
assign Nanod.au2Db = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b01);
assign Nanod.au2Ab = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b10);
assign Nanod.au2Pc = (nanoLatch[ NANO_AUOUT + 1: NANO_AUOUT] == 2'b11);
assign Nanod.db2Aob = (aobCtrl == 2'b10);
assign Nanod.ab2Aob = (aobCtrl == 2'b01);
assign Nanod.au2Aob = (aobCtrl == 2'b11);
assign Nanod.dbin2Abd = nanoLatch[ NANO_DBIN2ABD];
assign Nanod.dbin2Dbd = nanoLatch[ NANO_DBIN2DBD];
assign Nanod.permStart = (| aobCtrl);
assign Nanod.isWrite = ( | dobCtrl);
assign Nanod.waitBusFinish = nanoLatch[ NANO_TOIRC] | nanoLatch[ NANO_TODBIN] | Nanod.isWrite;
assign Nanod.busByte = nanoLatch[ NANO_BUSBYTE];
assign Nanod.noLowByte = nanoLatch[ NANO_LOWBYTE];
assign Nanod.noHighByte = nanoLatch[ NANO_HIGHBYTE];
// Not registered. Register at T4 after combining
// Might be better to remove all those and combine here instead of at execution unit !!
assign Nanod.abl2reg = nanoLatch[ NANO_ABL2REG];
assign Nanod.abh2reg = nanoLatch[ NANO_ABH2REG];
assign Nanod.dbl2reg = nanoLatch[ NANO_DBL2REG];
assign Nanod.dbh2reg = nanoLatch[ NANO_DBH2REG];
assign Nanod.reg2dbl = nanoLatch[ NANO_REG2DBL];
assign Nanod.reg2dbh = nanoLatch[ NANO_REG2DBH];
assign Nanod.reg2abl = nanoLatch[ NANO_REG2ABL];
assign Nanod.reg2abh = nanoLatch[ NANO_REG2ABH];
assign Nanod.ssp = nanoLatch[ NANO_SSP];
assign Nanod.rz = nanoLatch[ NANO_RZ];
// Actually DTL can't happen on PC relative mode. See IR decoder.
wire dtldbd = 1'b0;
wire dthdbh = 1'b0;
wire dtlabd = 1'b0;
wire dthabh = 1'b0;
wire dblSpecial = Nanod.pcldbl | dtldbd;
wire dbhSpecial = Nanod.pchdbh | dthdbh;
wire ablSpecial = Nanod.pclabl | dtlabd;
wire abhSpecial = Nanod.pchabh | dthabh;
//
// Combine with IRD decoding
// Careful that IRD is updated only on T1! All output depending on IRD must be latched on T4!
//
// PC used instead of RY on PC relative instuctions
assign Nanod.rxlDbl = nanoLatch[ NANO_RXL_DBL];
wire isPcRel = Irdecod.isPcRel & !Nanod.rz;
wire pcRelDbl = isPcRel & !nanoLatch[ NANO_RXL_DBL];
wire pcRelDbh = isPcRel & !nanoLatch[ NANO_RXH_DBH];
wire pcRelAbl = isPcRel & nanoLatch[ NANO_RXL_DBL];
wire pcRelAbh = isPcRel & nanoLatch[ NANO_RXH_DBH];
assign Nanod.pcldbl = nanoLatch[ NANO_PCLDBL] | pcRelDbl;
assign Nanod.pchdbh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b01) | pcRelDbh;
assign Nanod.pclabl = nanoLatch[ NANO_PCLABL] | pcRelAbl;
assign Nanod.pchabh = (nanoLatch[ NANO_PCH+1:NANO_PCH] == 2'b10) | pcRelAbh;
// Might be better not to register these signals to allow latching RX/RY mux earlier!
// But then must latch Irdecod.isPcRel on T3!
always_ff @( posedge Clks.clk) begin
if( enT4) begin
Nanod.rxl2db <= Nanod.reg2dbl & !dblSpecial & nanoLatch[ NANO_RXL_DBL];
Nanod.rxl2ab <= Nanod.reg2abl & !ablSpecial & !nanoLatch[ NANO_RXL_DBL];
Nanod.dbl2rxl <= Nanod.dbl2reg & !dblSpecial & nanoLatch[ NANO_RXL_DBL];
Nanod.abl2rxl <= Nanod.abl2reg & !ablSpecial & !nanoLatch[ NANO_RXL_DBL];
Nanod.rxh2dbh <= Nanod.reg2dbh & !dbhSpecial & nanoLatch[ NANO_RXH_DBH];
Nanod.rxh2abh <= Nanod.reg2abh & !abhSpecial & !nanoLatch[ NANO_RXH_DBH];
Nanod.dbh2rxh <= Nanod.dbh2reg & !dbhSpecial & nanoLatch[ NANO_RXH_DBH];
Nanod.abh2rxh <= Nanod.abh2reg & !abhSpecial & !nanoLatch[ NANO_RXH_DBH];
Nanod.dbh2ryh <= Nanod.dbh2reg & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH];
Nanod.abh2ryh <= Nanod.abh2reg & !abhSpecial & nanoLatch[ NANO_RXH_DBH];
Nanod.dbl2ryl <= Nanod.dbl2reg & !dblSpecial & !nanoLatch[ NANO_RXL_DBL];
Nanod.abl2ryl <= Nanod.abl2reg & !ablSpecial & nanoLatch[ NANO_RXL_DBL];
Nanod.ryl2db <= Nanod.reg2dbl & !dblSpecial & !nanoLatch[ NANO_RXL_DBL];
Nanod.ryl2ab <= Nanod.reg2abl & !ablSpecial & nanoLatch[ NANO_RXL_DBL];
Nanod.ryh2dbh <= Nanod.reg2dbh & !dbhSpecial & !nanoLatch[ NANO_RXH_DBH];
Nanod.ryh2abh <= Nanod.reg2abh & !abhSpecial & nanoLatch[ NANO_RXH_DBH];
end
// Originally isTas only delayed on T2 (and seems only a late mask rev fix)
// Better latch the combination on T4
if( enT4)
Nanod.isRmc <= Irdecod.isTas & nanoLatch[ NANO_BUSBYTE];
end
endmodule

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@@ -0,0 +1,336 @@
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000001000000110011100000000000000101001000001
00100001000000011000010001001000000110100000000001000000011001001001
00000001100000000010100000001000000110000000001001000000001001001001
00100000000000011000010001000000000101000000000010000000100001010000
11000001000000000000000000001000000100010000000001000000000001010001
00100001000000011000010000000000000000000000000101000000000000010000
01000001011000000000100000000110010001000000001100000000110100011000
01000001011000000000100000000110010001000000001100000001100100011000
00100001000000011000010000000000000100000000000001000000000001010000
10100100001000011000001000010000101001110000000001000100110010100001
01000000000000000000000010000000010100000000001000110001000000000000
00100001000000011000000000110010100100011111010001100000000001000000
00100010000000011000000000000000100010000100000000010100000100000011
00000001011000000000000001000110000000000000000010000000000100000000
00000000000000000000000000001000000100000000000001000000000001010001
00000001100000000010100000001000000110000000001001010000001001001001
00101000000000001000010000000000000000000000000010000000000000000000
01100010000000011000010010000000010100000000001000110001000000000000
00000000000000000000000010010010100000000000000100110010000000000000
00100000000000011000010001001000000110000000001001010000001001001001
00000000000000000000001000000000100100000000000000110010000001011000
00010010000000000100100000001000000100000000000010000000000001010001
00100010000000011100000000000000000001100000000010001000100000000000
00010010000000000100000000000000010001100000000010000000000000000000
00000000000000000000000000011001100110100000010001000000011011010001
10100010110000000000000000000000100000010000010010000100000100000000
10000000000000000000000000001000000100010000000001000000000001000001
00100000000000011001000000011010000110000000001001000000001001001001
00010011000000000000101000010000001001000000010101000000100000110000
00000001000000000001010000000000000000000000000101100000000000010000
00100010000000011000001000001000100110000000000001000000000001010001
00000001000000000010100001010000001001000000010110000000100000110000
01000001000000000000000000000000000001101010001100000000110000000000
00110100000000000100000100000000000000000000000010000000000000000000
00000000000100100000100000000000010000000000000000000001000000011000
01110101000000000100100000100010000001100000000000000000110100001010
00100010000000011010000100000000100010000100000000010100000100000011
11000001000000000000000000001000000100010000000001000000000001010001
01010011000000000100100000100010000001100000000000000000110100001010
11000001000000000000000000001001100110110000000001000000011011000001
01001001110000000000001000001000001000000000000101000000000000100001
00000000000000000000100000100010010000000000000000110001000100000010
00010000110000000001010000000000000000011100000010000000000000011000
01010001110000000001000000011010100100000000000001000000000001000001
00000000000000000000000001000000000100000000001100010000000001010000
00001000000000011001001000001000000110100000000001000100000011010001
01010001110000000001010000001000001000000000000101000000000000110001
10100010110100100100000001000000000001110000000010000000110000010000
00000000000100000000000000000010100001001010000101100000100000010000
00010000110000000001000000000000100000000000010010000100000100000000
10000000000000000000000000001000000100010000000001000000000001000001
00000001000000000000000001000000001001000000000101000000100000100000
00010010000000000000100000001010101000000000000101000000000000110001
10100000000100111000000000100001100010111010000101100000011010010010
00100000000000011000000000110010100110000000010000100000001101000010
00010010000000001100000000000000000000000000000010000000000000000000
11000001000000000000001000011101100100010000000001000000000001000001
00010100000000000100000100000000000000000000000010000000000000000000
10100010110000000100001000000000100000010000010010000100000010000000
00100000000100111000000000000000100000010010000101000100000100010010
00100010000000011000000000000000100010000100000000010100000100000011
00100010100000011001010000010000100100000000001110000100001000000000
00000000000100000000000000000010100000001010000101000000000000010000
00100010100000011001000000010010100100000000001110000100001000000000
00000001000000000000010000000000100000000000010101000100000010010000
00000000000100100000000000100010000000000100000000110001000100011010
00100000000000011000000000010000100110000000011000100000001001000000
00000000000100100000100000100010010000000000000000110001000100011010
00000000011000000000000000000110000000000000001110000000110100111000
00011000000000011001001000001000000100000000000001000000000001010001
00100010000000011100000000000000000001100000000010001000100000000000
00110000100000001000000100000000100000000000000010000100000100000000
00000000000100000000000000000010100001000000000101100000100000010000
10100010110000000100001000010001100000010000000010000000000000000000
01000001000000000000000000000000000000000000000101000000000000010000
10000000000000000000000000001000000100010000000001000000000001000001
00000000000000000000000000001000001000000000000101000000000000110001
00001000110000000000001000000000000000000000000010000000000000000000
00010010000000001100000000000000000000000000000010000000000000000000
00010000000000001010000100000000110001000000000010000100011000000000
01010001000000011000001000000000000001100000000000000000110000000000
00001100000000011000001000100001000010100000000101110000000000000011
01000000000000000000000010000000010100000000001000110000000001000000
11000001000000000000000000001000001000010000000101000000000000100001
00000000000000000000000000001000000100011100000001100000000001000001
00000000000000000000000000000000000000000000000101100000000000000000
00000000000100000000000000000000100000000000000101000100000100010000
11101011000000000000000000000000000000010000000010000000000000000000
01100001000000011001000000011010100100000000000001000000000001000001
01100010000000011000010010000000010100000000001000110000000001000000
00000000000000000000000010010010100000000000010100110000000100000000
01000001000000000000010000011001101000000000000101000100001000110001
00100000000100111100000000000000000010000010000100100010001000010000
00010010000000000000000000000010110100000000001110000000000000011000
00000000000000000000001000010000100100000000011100110010000001011000
00000000000100000000000000010000111000000000010101000100011000110000
00000000011000000010100000000110000100000000001101110000000101000000
00000000000000000000000000000000000000000000000010000000000000000000
00000001000000000000000000000000010101001010001101000000100001010000
00000001000000000000010000000000100000000000000101000100001000010000
01110101000000010000001000000000000001100000000000000000110000000000
01000001000000000000000010000000010100001010001000110001000000000000
00100010000000011000000000011010101010000000010101000000001100110001
00100001000000011000010001010000000100000000010000010000000001010000
01000001000000000000010000000000100000000110000101000000000000010000
01000001000000000000000010000000010100001010001000110001000000000000
00100000000000011000010001010001000000000000011010000000000010001000
00000001000000000000000001010000000100000000010001110000000001000000
00010010000000001000000000011010101000000000000101000000000000110001
00000000000000000000000000001000001000000000000101000000000000110001
00010010000000000001100000000010000000000000000101100000000000000000
00010010000000000001000000000010000100000000000101100000000000000000
00100010000000011100000000001000001000000000000101000000000000100001
00000001000000000001010000000000001010100000000110000000011000101000
00000001100000000000100000000000000000000000000101000000000000010000
00010010000000000000101000001001000100000000001001000000000011010001
11110101001000000100000000000000000000010000000010000000000000000000
00000000000000000000010000001001101000000000000101000010000010110001
00000000000000000000010000000000100000000110000101100000000000000000
00100010100000001001100000000010000010000100001000000000001000001000
00100010100000001001000000000010000110000100001000000000001000001000
00010010000000001000010000000000000000000000001110000000000000011000
00110100000100101100000000000000000001100000000001100000110000010000
01110101000000001000000100000000111000000000010010000100000100000000
01000000000000000000010000010000100110000000011100100000000001011000
11010011000000000000101000001001000100010000001001000000000011010001
11110101001000000000000000000000100000010000000010000100000100000000
01110101000000000100000000000000010000000000010010001000000001000000
01110101000000000000000000000000110000000000010010001100000101000000
01110101000000000000000000000000110000000000010010001100011001000000
01110000000000011100000000000000000001100000001101000000110000000000
00010000000000001000000000000010100000000000000010000000000000000000
00010010000000000100000100000000010001000000000010000000000000000000
01000000000000000000010000010000100110000000011100100010001001011000
00100000000000011000010000000000000100000000000000100000000001000000
00000001000000000000000000000000001000000000000101000000000000110000
00100001000000011100000001011001000110000000011000000000001011001001
01100001000000011000000000010010100110000000011100100000001101011000
01100001000000011000010000010010000010000000010101000000001100010000
00000000000000000000000100000000010010100000001100110001011000011000
01100001000000011000000000010000100110000000011000100000001001000000
00000000000000000000000000001000000100011100000001100000000001000001
00010010000000000000000000010010110110000000001110000010001000011000
01000001000000000000100000010010010000000000010000110001000100011000
00010010000000000000010000010000110110000000001110000010001000011000
01000001000000000000000010000000010100001010001000110000000001000000
01000001000000000000010000001000101000000110000101000000000000110001
00000001000000000000010000000000100000000000000101000100001000010000
00101000000000001000010000000000000000000000000010000000000000000000
00100010000000011000000000000000100000000000000010000100011000000000
00100010001000011010000000000000100000000000000010000100000100000000
11010011001000000100000000010000011000010000000010000000000000000000
00010010000000000100000000000000010000000000010010001000000001000000
00001000000000011000001000000000000000000000000101110000000000000011
00100010110000000000010000001000001000000000000101000000000000110001
00100010000000011000000000000000100010100000000010000000000000000000
00100000000000011000000000110001100100011111011001100000000011000010
00100000000000011000000000001000100110000000001001010000001001000001
01000001000000000000000000010000000100000000011100100000000001011000
00000000100000000010100000000000000001000000000101000000100000010000
00000001000000000000000000011001000100000000011001000000000011000001
00000000011000000010100001000110000101000000000000010000100101010000
00100001000000011100000001011001000100000000011001000000000011000001
01000000000000000000000000000000000101001010001101100000100001000000
00000000000100000000000000000000100001001010000101100100100100010000
00000000011000000000000000000010110110000000001100000000001101011000
01000001000000000000000000000001111001100000001010000000110010100000
00110010000000011000000000010010100010000000001110000010001000011000
11000001000000000000000000011001100110110000010001000000011011000001
00100000000000011010000000100001110000001100001010000000000010000010
00000000000000000000000000010000000100010101010001100000000001000000
01000000000000000000000000000000000010100000000010000000011000001000
00000001000000000000000000000000000001101010001101000000110000010000
10000000000000000000001000001101100100010000000001000000000001000001
01110101000000000000000000000000110000000000000010001100000101000000
11000001000000000000000000001000000100010000000001000000000001000001
00100010000000011000000000001001101000000010000101000010000010110001
00100010000100011000000000010010100000000000000101000000000000010000
11100101000000011100000000001001000100010000001001000000000011010001
00100100000100111000000000000000100000000000010101100100000100010000
00100010000100011000000000011010100100000000000000000000000001011001
00100000000000001000001000000000100000000000000010000100000010000000
00100010000000011100001000001000100100000000000001000100001001010001
00010010000000000100000100000000010001000000000010000000000000000000
10000000000000000000001000011101000100010000000001000000000001000001
00011000000000011000001000000000100010000000000010000000000000000000
01000000000000000000000000000000000100000000000001000000000001010000
01000000000000000000010000010000100110000000011100100000011001001000
00000000001000000010001000010001010000000000000010001000000000100000
11100101000000011100000000001000001000010000000101000000000000110001
01000001000000000000001000010001100000000000000010000000000000000000
00110100000000000000000000000000110000000000000010001100000101000000
10000000000000000000001000001000100100010000010001000100000011000001
01110101000000000100001000000001110000000000010010001000000001000000
10000000000000000000001000001000100100010000000001000100000011000001
00110100000000000000000000000000110000000000010010001100000101000000
00110100000000000000000000000000110000000000010010001100011001000000
01000000000000000000000000010000000110100000011100100000011001001000
00000000000100000000000000010000111000000000010101000100000100110010
00000000000100000000000000100010100001100000000001000000110000011000
01000000000000000000000000010010000110000000010000100000001101001000
00000000000000000000000000001000000110000000001001000000001001001001
01000000000000000000010000000001100000000000000101000010000010010000
01000000000000000000000000001000000110000000001001010000001001000001
00000001000000000000000000000000000001101010001101000000110000000000
11100101000000011000000000010000111001110000010010000100110100100000
00000000000000000000000000011010101010000000000101000010001000110001
11000001000000000000001000001101100100010000000001000000000001000001
00000000000000000000000100000000010000000000000001100001000000000000
00000000000000000000000000001001100100000000001001000000000011010001
11000001000000000000010000010001100000010000010010000000011010000000
00000000000000000000000000000000000000010110000010000000000000000000
00000000000000000000000000000000000000001100000000000001000000000000
00100010000000011000000000000000100010100000000010000000000000000000
00001000000000011000001000000000000000000000000101110000000000000011
10000000000000000000000000000000000000010000000010000000000000000000
00000000000000000000010000000000100010000000000010000010001000000000
00101000000000001000001000000000000000000000000010000000000000000000
01010011000000000000100000000010100001100000001100000000110000011000
00000001000010000000000001000000000000000000000101000000000000010000
00100010000000011000010000001101101000000000000101000000000000110001
00000000000000000000100000010010010000000000010000110001000100000000
01000000000000000000000000010000000100000000011100100000000001000000
00000000000000000000000100010010010000000000010000110001000100000000
01000000000000000000100000000000010000000000000001000000110000010000
01010011000000001000010000000000000001100000001100000000110000011000
01000001000000000000010000001001101000000000000101000000000000110001
00100100000100011001000000000000100000000000010101000100000100010000
01100010000000011000100000010010110010000000001100000000110000011000
00011000000000011000001000000000000000000000000101110000000000000011
00000000000000000000000000001000000100000000000001000000000001010001
00010010000000000100000100000000010001000000000010000000000000000000
00001010000000011000001000000000000000000000000101110000000000000011
00010010000000000000000000000001110100000010001110000010000010011000
01100010000000011000100000010010110010000000001100000001000000011000
01000000000000000000100000000010010000000000001100110001000100011000
00100010000100011000000001011010100100000000000001000000000001011001
00000001000000000000010000000001100001001010000101000000100000010000
00000000000000000000010000000000100101000110001110000000100001011000
00000000000000000000100000010010010000000000010000110001000100011000
01010011000000000000100000000001100001100010001100000010110010011000
01100011000000011000000000010010100100000000011101110000000001011000
00000000000100000001000000010000100100000000011101000100000101010000
00100010000100011000000001010010100100000000011100010000000001010000
00000001000000000000010000000000100000000001000101000100000010010000
00000001000000000000010000000001100000001111000101000000000000010000
00000000000000000000000000010010100000000110010101100000000100000000
00000111000000000000010000010000111000001000010110000100001000100000
01000000000000000000100000000001110000000000001001000000110010010000
01001011000000011000001000000000000001100000000000000000110000000000
00000000000000000000010000000000100010000000000101000000000000010000
10100100000000011100000000001000000100010000000001000000000001000001
00010000000000000000000000010000100100000010000010000000000000000000
00000000000000000000000000001000000100000010000000110010000001000001
01000000000000000000000000001001100100000000001001010000000011000001
00000000000000000000000000001001100100000000001001010000000011000001
00100000000000011000000000010010100010000000010101000000001100010000
00000000000100000000000000000000101000000000000101000100011000110000
00000000000100100000100000010010010000000000010000110001000100011000
01000000000000000000010000010001100000000000010101000010000010010000
00100001000000011100010100000000110010000000001110001000100000011000
00000000000000000000001000000000100000000110000101000000000000000000
00000110000000000000000000000000000000001000000010000000000000000000
01000000000000000000010000000000100100001010001100110010000001000000
01000000000000000000000000000000000100001010001100000000000001000000
01100001000000011000000000000000100001100010000000000000110000000000
01000001000000000000010000000000100000000110000101010000000000010000
00101000000000001000010000001000101010000000000101100000000000100001
10000110000000000000000000001000001000001000000101100000000000100001
00000000000000000000000000001000000100000000000001000000000001010001
00100010000100111000100000000000110010100000000001000000110000010000
00100100000100111100000000001000000100000000000001000000000001011001
00100011000000011000010100000000010000000000001110001000100000011000
00000000000000000000000000011001100110100000010001000000011011010001
00000000000000000000000000000000000000000000000010000000000000000000
00000000000100100000010001001000100100000000000001000000011001001001
00100100001000111100001000000000100010000000000101000000000000010000
01000001000000000000000000010001100000000010000010000000000000000000
00100010000000011010000000000000110100000000011110001100100100011000
11100101000000011100000100000000001000010000010101000000011010000000
00010000000000000000100000000000100001100010001100000000110000000000
00100010000100111000010001001000000100000000000000000000000001011001
00010000000000000010000000000000100100000010001110000000000000011000
11100011000000011100001000010101100000010000000101000000000000000000
00100000000000011000000000110010100100011111010001100000000001000000
10000000000100000000000000001000100110110000000001000000000001011001
11000001000000000000000000001001000100010000001001000000000011010001
00100100000100111100000000000000000000000000000101100000000000010000
10000000000100100000000001001001000100010000001001000000000011001001
11000001000000000000000000000000000000010000000010000000000000000000
00110100001100100000000000000000100000000000000101100100000100010000
00000001000001000000000001000000000000000000000101000000000000010000
00000001000010000000010001000000100000000000000101000100000010010000
00100000000100111000000000010000101000010111010101000100000100110010
11100101000000011100000000000000000000010000000010000000000000000000
11100101000000011000000000000000100000010000010010000100000100000000
00000000000000000000000000001000001000000000000101000000000000110001
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000000000000000000000000000000010000000000000000000
00000001000000000000000000001000001001100000000001000000110000110001
00000001000001000000000001001000000100000000000001010000000001011001
00100000000000001000001000000000100000000000000010000100000010000000
11000001000000000000010000001001001000010000000101000000000000110001
00000000000110000000000001000000100000000000000101000100000100010000
00000000000101000000000001000000100000000000000101000100000100010000
00000000000010100000000001010000000100000000000101000000000000010000
00000000000101000000000001001010000100000000000001010000000001011001
11100101001000011100000000000000010000010000010010001000000000100000
00100000000000001000000000001000001000000000000110000000000000110001
00100000000000011000000000000000100000000100011100000101000100011000
00100000000000011000000000010000110100000000011100000101000100011000
01100011100000011000000100010010000000000000000101110000000000000011
01100010000000011000010100000000010000000000001100000001000000011000
10000000000100100000000001001000000100010000000001000000000001011001
01100010000000011000010100000010010000000000001100110001000100011000
01100011000000011000010000010000000100000000011101110000000001011000
00000000000000000000010000000000100000000110000101000000000000010000
00000000000000000000000000000000000000011100001110000000000000011000
10100000000000001000010000001000101000000110000101000000000000100001
00100000000000011000000000110001100100001111011001100000000011000010
00000001000000000000010000000001100001001010000101000010100010010000
00100010001000111000010000010000000100000000011101000000000001010000
00100100000100111100000000000000000000000000000101000000000000010000
00100010000100011000010001010000000100000000011100010000000001010000
01000001000000000000000100010000011000000000000010000000000000000000
00000000000000000000010000000000100010000000000101000010001000010000
00100000000100111000000000000000100000000010000100100000000000010000
00100010000000011000010000001000001000000000000101000000000000110001
00000001000000000000010000000000100000000000000101000100000010010000
00000000000000000000000000000000000000000000000010000000000000000000
00000000000000000000001000000000100100000000000000110010000001011000
00000000011000000000000000000010110110000000001100000000001101011000

23
common/CPU/68000/FX68k/onehotEncoder4.sv Normal file
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@@ -0,0 +1,23 @@
// bin to one-hot, 4 bits to 16-bit bitmap
module onehotEncoder4( input [3:0] bin, output reg [15:0] bitMap);
always_comb begin
case( bin)
'b0000: bitMap = 16'h0001;
'b0001: bitMap = 16'h0002;
'b0010: bitMap = 16'h0004;
'b0011: bitMap = 16'h0008;
'b0100: bitMap = 16'h0010;
'b0101: bitMap = 16'h0020;
'b0110: bitMap = 16'h0040;
'b0111: bitMap = 16'h0080;
'b1000: bitMap = 16'h0100;
'b1001: bitMap = 16'h0200;
'b1010: bitMap = 16'h0400;
'b1011: bitMap = 16'h0800;
'b1100: bitMap = 16'h1000;
'b1101: bitMap = 16'h2000;
'b1110: bitMap = 16'h4000;
'b1111: bitMap = 16'h8000;
endcase
end
endmodule

25
common/CPU/68000/FX68k/pren.sv Normal file
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@@ -0,0 +1,25 @@
// priority encoder
// used by MOVEM regmask
// this might benefit from device specific features
// MOVEM doesn't need speed, will read the result 2 CPU cycles after each update.
module pren( mask, hbit);
parameter size = 16;
parameter outbits = 4;
input [size-1:0] mask;
output reg [outbits-1:0] hbit;
// output reg idle;
always @( mask) begin
integer i;
hbit = 0;
// idle = 1;
for( i = size-1; i >= 0; i = i - 1) begin
if( mask[ i]) begin
hbit = i;
// idle = 0;
end
end
end
endmodule

139
common/CPU/68000/FX68k/rowDecoder.sv Normal file
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@@ -0,0 +1,139 @@
// Decodes IRD into ALU row (1-15)
// Slow, but no need to optimize for speed since IRD is latched at least two CPU cycles before it is used
// We also register the result after combining with column from nanocode
//
// Many opcodes are not decoded because they either don't do any ALU op,
// or use only columns 1 and 5 that are the same for all rows.
module rowDecoder( input [15:0] ird,
output logic [15:0] row, output noCcrEn, output logic isArX);
// Addr or data register direct
wire eaRdir = (ird[ 5:4] == 2'b00);
// Addr register direct
wire eaAdir = (ird[ 5:3] == 3'b001);
wire size11 = ird[7] & ird[6];
always_comb begin
case( ird[15:12])
'h4,
'h9,
'hd:
isArX = row[10] | row[12];
default:
isArX = 1'b0;
endcase
end
always_comb begin
unique case( ird[15:12])
'h4: begin
if( ird[8])
row = `ALU_ROW_06; // chk (or lea)
else case( ird[11:9])
'b000: row = `ALU_ROW_10; // negx
'b001: row = `ALU_ROW_04; // clr
'b010: row = `ALU_ROW_05; // neg
'b011: row = `ALU_ROW_11; // not
'b100: row = (ird[7]) ? `ALU_ROW_08 : `ALU_ROW_09; // nbcd/swap/ext(or pea)
'b101: row = `ALU_ROW_15; // tst & tas
default: row = 0;
endcase
end
'h0: begin
if( ird[8]) // dynamic bit
row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13;
else case( ird[ 11:9])
'b000: row = `ALU_ROW_14; // ori
'b001: row = `ALU_ROW_04; // andi
'b010: row = `ALU_ROW_05; // subi
'b011: row = `ALU_ROW_02; // addi
'b100: row = ird[7] ? `ALU_ROW_14 : `ALU_ROW_13; // static bit
'b101: row = `ALU_ROW_13; // eori
'b110: row = `ALU_ROW_06; // cmpi
default: row = 0;
endcase
end
// MOVE
// move.b originally also rows 5 & 15. Only because IRD bit 14 is not decoded.
// It's the same for move the operations performed by MOVE.B
'h1,'h2,'h3: row = `ALU_ROW_02;
'h5:
if( size11)
row = `ALU_ROW_15; // As originally and easier to decode
else
row = ird[8] ? `ALU_ROW_05 : `ALU_ROW_02; // addq/subq
'h6: row = 0; //bcc/bra/bsr
'h7: row = `ALU_ROW_02; // moveq
'h8:
if( size11) // div
row = `ALU_ROW_01;
else if( ird[8] & eaRdir) // sbcd
row = `ALU_ROW_09;
else
row = `ALU_ROW_14; // or
'h9:
if( ird[8] & ~size11 & eaRdir)
row = `ALU_ROW_10; // subx
else
row = `ALU_ROW_05; // sub/suba
'hb:
if( ird[8] & ~size11 & ~eaAdir)
row = `ALU_ROW_13; // eor
else
row = `ALU_ROW_06; // cmp/cmpa/cmpm
'hc:
if( size11)
row = `ALU_ROW_07; // mul
else if( ird[8] & eaRdir) // abcd
row = `ALU_ROW_03;
else
row = `ALU_ROW_04; // and
'hd:
if( ird[8] & ~size11 & eaRdir)
row = `ALU_ROW_12; // addx
else
row = `ALU_ROW_02; // add/adda
'he:
begin
reg [1:0] stype;
if( size11) // memory shift/rotate
stype = ird[ 10:9];
else // register shift/rotate
stype = ird[ 4:3];
case( {stype, ird[8]})
0: row = `ALU_ROW_02; // ASR
1: row = `ALU_ROW_03; // ASL
2: row = `ALU_ROW_05; // LSR
3: row = `ALU_ROW_04; // LSL
4: row = `ALU_ROW_08; // ROXR
5: row = `ALU_ROW_11; // ROXL
6: row = `ALU_ROW_10; // ROR
7: row = `ALU_ROW_09; // ROL
endcase
end
default: row = 0;
endcase
end
// Decode opcodes that don't affect flags
// ADDA/SUBA ADDQ/SUBQ MOVEA
assign noCcrEn =
// ADDA/SUBA
( ird[15] & ~ird[13] & ird[12] & size11) |
// ADDQ/SUBQ to An
( (ird[15:12] == 4'h5) & eaAdir) |
// MOVEA
( (~ird[15] & ~ird[14] & ird[13]) & ird[8:6] == 3'b001);
endmodule

237
common/CPU/68000/FX68k/sequencer.sv Normal file
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@@ -0,0 +1,237 @@
// Microcode sequencer
module sequencer( input s_clks Clks, input enT3,
input [UROM_WIDTH-1:0] microLatch,
input A0Err, BerrA, busAddrErr, Spuria, Avia,
input Tpend, intPend, isIllegal, isPriv, excRst, isLineA, isLineF,
input [15:0] psw,
input prenEmpty, au05z, dcr4, ze, i11,
input [1:0] alue01,
input [15:0] Ird,
input [UADDR_WIDTH-1:0] a1, a2, a3,
output logic [3:0] tvn,
output logic [UADDR_WIDTH-1:0] nma);
logic [UADDR_WIDTH-1:0] uNma;
logic [UADDR_WIDTH-1:0] grp1Nma;
logic [1:0] c0c1;
reg a0Rst;
wire A0Sel;
wire inGrp0Exc;
// assign nma = Clks.extReset ? RSTP0_NMA : (A0Err ? BSER1_NMA : uNma);
// assign nma = A0Err ? (a0Rst ? RSTP0_NMA : BSER1_NMA) : uNma;
// word type I: 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
// NMA : .. .. 09 08 01 00 05 04 03 02 07 06 .. .. .. .. ..
wire [UADDR_WIDTH-1:0] dbNma = { microLatch[ 14:13], microLatch[ 6:5], microLatch[ 10:7], microLatch[ 12:11]};
// Group 0 exception.
// Separated block from regular NMA. Otherwise simulation might depend on order of assigments.
always_comb begin
if( A0Err) begin
if( a0Rst) // Reset
nma = RSTP0_NMA;
else if( inGrp0Exc) // Double fault
nma = HALT1_NMA;
else // Bus or address error
nma = BSER1_NMA;
end
else
nma = uNma;
end
always_comb begin
// Format II (conditional) or I (direct branch)
if( microLatch[1])
uNma = { microLatch[ 14:13], c0c1, microLatch[ 10:7], microLatch[ 12:11]};
else
case( microLatch[ 3:2])
0: uNma = dbNma; // DB
1: uNma = A0Sel ? grp1Nma : a1;
2: uNma = a2;
3: uNma = a3;
endcase
end
// Format II, conditional, NMA decoding
wire [1:0] enl = { Ird[6], prenEmpty}; // Updated on T3
wire [1:0] ms0 = { Ird[8], alue01[0]};
wire [3:0] m01 = { au05z, Ird[8], alue01};
wire [1:0] nz1 = { psw[ NF], psw[ ZF]};
wire [1:0] nv = { psw[ NF], psw[ VF]};
logic ccTest;
wire [4:0] cbc = microLatch[ 6:2]; // CBC bits
always_comb begin
unique case( cbc)
'h0: c0c1 = {i11, i11}; // W/L offset EA, from IRC
'h1: c0c1 = (au05z) ? 2'b01 : 2'b11; // Updated on T3
'h11: c0c1 = (au05z) ? 2'b00 : 2'b11;
'h02: c0c1 = { 1'b0, ~psw[ CF]}; // C used in DIV
'h12: c0c1 = { 1'b1, ~psw[ CF]};
'h03: c0c1 = {psw[ ZF], psw[ ZF]}; // Z used in DIVU
'h04: // nz1, used in DIVS
case( nz1)
'b00: c0c1 = 2'b10;
'b10: c0c1 = 2'b01;
'b01,'b11: c0c1 = 2'b11;
endcase
'h05: c0c1 = {psw[ NF], 1'b1}; // N used in CHK and DIV
'h15: c0c1 = {1'b1, psw[ NF]};
// nz2, used in DIVS (same combination as nz1)
'h06: c0c1 = { ~nz1[1] & ~nz1[0], 1'b1};
'h07: // ms0 used in MUL
case( ms0)
'b10, 'b00: c0c1 = 2'b11;
'b01: c0c1 = 2'b01;
'b11: c0c1 = 2'b10;
endcase
'h08: // m01 used in MUL
case( m01)
'b0000,'b0001,'b0100,'b0111: c0c1 = 2'b11;
'b0010,'b0011,'b0101: c0c1 = 2'b01;
'b0110: c0c1 = 2'b10;
default: c0c1 = 2'b00;
endcase
// Conditional
'h09: c0c1 = (ccTest) ? 2'b11 : 2'b01;
'h19: c0c1 = (ccTest) ? 2'b11 : 2'b10;
// DCR bit 4 (high or low word)
'h0c: c0c1 = dcr4 ? 2'b01: 2'b11;
'h1c: c0c1 = dcr4 ? 2'b10: 2'b11;
// DBcc done
'h0a: c0c1 = ze ? 2'b11 : 2'b00;
// nv, used in CHK
'h0b: c0c1 = (nv == 2'b00) ? 2'b00 : 2'b11;
// V, used in trapv
'h0d: c0c1 = { ~psw[ VF], ~psw[VF]};
// enl, combination of pren idle and word/long on IRD
'h0e,'h1e:
case( enl)
2'b00: c0c1 = 'b10;
2'b10: c0c1 = 'b11;
// 'hx1 result 00/01 depending on condition 0e/1e
2'b01,2'b11:
c0c1 = { 1'b0, microLatch[ 6]};
endcase
default: c0c1 = 'X;
endcase
end
// CCR conditional
always_comb begin
unique case( Ird[ 11:8])
'h0: ccTest = 1'b1; // T
'h1: ccTest = 1'b0; // F
'h2: ccTest = ~psw[ CF] & ~psw[ ZF]; // HI
'h3: ccTest = psw[ CF] | psw[ZF]; // LS
'h4: ccTest = ~psw[ CF]; // CC (HS)
'h5: ccTest = psw[ CF]; // CS (LO)
'h6: ccTest = ~psw[ ZF]; // NE
'h7: ccTest = psw[ ZF]; // EQ
'h8: ccTest = ~psw[ VF]; // VC
'h9: ccTest = psw[ VF]; // VS
'ha: ccTest = ~psw[ NF]; // PL
'hb: ccTest = psw[ NF]; // MI
'hc: ccTest = (psw[ NF] & psw[ VF]) | (~psw[ NF] & ~psw[ VF]); // GE
'hd: ccTest = (psw[ NF] & ~psw[ VF]) | (~psw[ NF] & psw[ VF]); // LT
'he: ccTest = (psw[ NF] & psw[ VF] & ~psw[ ZF]) |
(~psw[ NF] & ~psw[ VF] & ~psw[ ZF]); // GT
'hf: ccTest = psw[ ZF] | (psw[ NF] & ~psw[VF]) | (~psw[ NF] & psw[VF]); // LE
endcase
end
// Exception logic
logic rTrace, rInterrupt;
logic rIllegal, rPriv, rLineA, rLineF;
logic rExcRst, rExcAdrErr, rExcBusErr;
logic rSpurious, rAutovec;
wire grp1LatchEn, grp0LatchEn;
// Originally control signals latched on T4. Then exception latches updated on T3
assign grp1LatchEn = microLatch[0] & (microLatch[1] | !microLatch[4]);
assign grp0LatchEn = microLatch[4] & !microLatch[1];
assign inGrp0Exc = rExcRst | rExcBusErr | rExcAdrErr;
always_ff @( posedge Clks.clk) begin
if( grp0LatchEn & enT3) begin
rExcRst <= excRst;
rExcBusErr <= BerrA;
rExcAdrErr <= busAddrErr;
rSpurious <= Spuria;
rAutovec <= Avia;
end
// Update group 1 exception latches
// Inputs from IR decoder updated on T1 as soon as IR loaded
// Trace pending updated on T3 at the start of the instruction
// Interrupt pending on T2
if( grp1LatchEn & enT3) begin
rTrace <= Tpend;
rInterrupt <= intPend;
rIllegal <= isIllegal & ~isLineA & ~isLineF;
rLineA <= isLineA;
rLineF <= isLineF;
rPriv <= isPriv & !psw[ SF];
end
end
// exception priority
always_comb begin
grp1Nma = TRAC1_NMA;
if( rExcRst)
tvn = '0; // Might need to change that to signal in exception
else if( rExcBusErr | rExcAdrErr)
tvn = { 1'b1, rExcAdrErr};
// Seudo group 0 exceptions. Just for updating TVN
else if( rSpurious | rAutovec)
tvn = rSpurious ? TVN_SPURIOUS : TVN_AUTOVEC;
else if( rTrace)
tvn = 9;
else if( rInterrupt) begin
tvn = TVN_INTERRUPT;
grp1Nma = ITLX1_NMA;
end
else begin
unique case( 1'b1) // Can't happen more than one of these
rIllegal: tvn = 4;
rPriv: tvn = 8;
rLineA: tvn = 10;
rLineF: tvn = 11;
default: tvn = 1; // Signal no group 0/1 exception
endcase
end
end
assign A0Sel = rIllegal | rLineF | rLineA | rPriv | rTrace | rInterrupt;
always_ff @( posedge Clks.clk) begin
if( Clks.extReset)
a0Rst <= 1'b1;
else if( enT3)
a0Rst <= 1'b0;
end
endmodule

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// Provides ucode routine entries (A1/A3) for each opcode
// Also checks for illegal opcode and priv violation
// This is one of the slowest part of the processor.
// But no need to optimize or pipeline because the result is not needed until at least 4 cycles.
// IR updated at the least one microinstruction earlier.
// Just need to configure the timing analizer correctly.
module uaddrDecode(
input [15:0] opcode,
output [UADDR_WIDTH-1:0] a1, a2, a3,
output logic isPriv, isIllegal, isLineA, isLineF,
output [15:0] lineBmap);
wire [3:0] line = opcode[15:12];
logic [3:0] eaCol, movEa;
onehotEncoder4 irLineDecod( line, lineBmap);
assign isLineA = lineBmap[ 'hA];
assign isLineF = lineBmap[ 'hF];
pla_lined pla_lined( .movEa( movEa), .col( eaCol),
.opcode( opcode), .lineBmap( lineBmap),
.palIll( isIllegal), .plaA1( a1), .plaA2( a2), .plaA3( a3) );
// ea decoding
assign eaCol = eaDecode( opcode[ 5:0]);
assign movEa = eaDecode( {opcode[ 8:6], opcode[ 11:9]} );
// EA decode
function [3:0] eaDecode;
input [5:0] eaBits;
begin
unique case( eaBits[ 5:3])
3'b111:
case( eaBits[ 2:0])
3'b000: eaDecode = 7; // Absolute short
3'b001: eaDecode = 8; // Absolute long
3'b010: eaDecode = 9; // PC displacement
3'b011: eaDecode = 10; // PC offset
3'b100: eaDecode = 11; // Immediate
default: eaDecode = 12; // Invalid
endcase
default: eaDecode = eaBits[5:3]; // Register based EAs
endcase
end
endfunction
/*
Privileged instructions:
ANDI/EORI/ORI SR
MOVE to SR
MOVE to/from USP
RESET
RTE
STOP
*/
always_comb begin
unique case( lineBmap)
// ori/andi/eori SR
'h01: isPriv = ((opcode & 16'hf5ff) == 16'h007c);
'h10:
begin
// No priority !!!
if( (opcode & 16'hffc0) == 16'h46c0) // move to sr
isPriv = 1'b1;
else if( (opcode & 16'hfff0) == 16'h4e60) // move usp
isPriv = 1'b1;
else if( opcode == 16'h4e70 || // reset
opcode == 16'h4e73 || // rte
opcode == 16'h4e72) // stop
isPriv = 1'b1;
else
isPriv = 1'b0;
end
default: isPriv = 1'b0;
endcase
end
endmodule

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------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- --
-- Copyright (c) 2007-2008 Tobias Gubener <tobiflex@opencores.org> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.02 2008/01/23
-- bugfix Timing
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FDC Output
-- add odd Address test
-- add TRACE
-- Movem with regmask==x0000
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68 is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
dtack : in std_logic;
addr : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
drive_data : out std_logic --enable for data_out driver
);
end TG68;
ARCHITECTURE logic OF TG68 IS
COMPONENT TG68_fast
PORT (
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0);
test_IPL : in std_logic;
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
decodeOPC : buffer std_logic;
wr : out std_logic;
UDS, LDS : out std_logic
);
END COMPONENT;
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
SIGNAL n_clk : std_logic;
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
BEGIN
n_clk <= NOT clk;
TG68_fast_inst: TG68_fast
PORT MAP (
clk => n_clk, -- : in std_logic;
reset => reset, -- : in std_logic;
clkena_in => clkena, -- : in std_logic;
data_in => data_in, -- : in std_logic_vector(15 downto 0);
IPL => cpuIPL, -- : in std_logic_vector(2 downto 0);
test_IPL => '0', -- : in std_logic;
address => addr, -- : out std_logic_vector(31 downto 0);
data_write => data_out, -- : out std_logic_vector(15 downto 0);
state_out => state, -- : out std_logic_vector(1 downto 0);
decodeOPC => decode, -- : buffer std_logic;
wr => wr, -- : out std_logic;
UDS => uds_in, -- : out std_logic;
LDS => lds_in -- : out std_logic;
);
PROCESS (clk)
BEGIN
IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= as_s AND as_e;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
IF reset='0' THEN
S_state <= "11";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
IF state/="01" OR decode='1' THEN
CASE S_state IS
WHEN "00" => as_s <= '0';
rw_s <= wr;
IF wr='1' THEN
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
S_state <= "01";
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
WHEN "10" =>
rw_s <= wr;
IF waitm='0' THEN
S_state <= "11";
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END IF;
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
cpuIPL <= "111";
drive_data <= '0';
ELSIF falling_edge(clk) THEN
IF clkena_in='1' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
drive_data <= '0';
CASE S_state IS
WHEN "00" => null;
WHEN "01" => drive_data <= NOT wr;
WHEN "10" => as_e <= '0';
uds_e <= uds_in;
lds_e <= lds_in;
cpuIPL <= IPL;
drive_data <= NOT wr;
IF state="01" THEN
clkena_e <= '1';
waitm <= '0';
ELSE
clkena_e <= NOT dtack;
waitm <= dtack;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END PROCESS;
END;

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GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
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GNU LESSER GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
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------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This is the TOP-Level for TG68KdotC_Kernel to generate 68K Bus signals --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68K is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
IPL : in std_logic_vector(2 downto 0):="111";
dtack : in std_logic;
vpa : in std_logic:='1';
ein : in std_logic:='1';
addr : buffer std_logic_vector(31 downto 0);
data_read : in std_logic_vector(15 downto 0);
data_write : out std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
e : out std_logic;
vma : buffer std_logic:='1';
wrd : out std_logic;
ena7RDreg : in std_logic:='1';
ena7WRreg : in std_logic:='1';
enaWRreg : in std_logic:='1';
fromram : in std_logic_vector(15 downto 0);
ramready : in std_logic:='0';
cpu : in std_logic_vector(1 downto 0);
memcfg : in std_logic_vector(5 downto 0);
ramaddr : out std_logic_vector(31 downto 0);
cpustate : out std_logic_vector(5 downto 0);
nResetOut : out std_logic;
skipFetch : buffer std_logic;
cpuDMA : buffer std_logic;
ramlds : out std_logic;
ramuds : out std_logic
);
end TG68K;
ARCHITECTURE logic OF TG68K IS
COMPONENT TG68KdotC_Kernel
generic(
SR_Read : integer:= 2; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer:= 2; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer:= 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BitField : integer := 2 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only same parts - yet)
addr : buffer std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS, nLDS : out std_logic;
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
-- for debug
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
skipFetch : out std_logic;
regin : buffer std_logic_vector(31 downto 0)
);
END COMPONENT;
SIGNAL cpuaddr : std_logic_vector(31 downto 0);
SIGNAL t_addr : std_logic_vector(31 downto 0);
-- SIGNAL data_write : std_logic_vector(15 downto 0);
-- SIGNAL t_data : std_logic_vector(15 downto 0);
SIGNAL r_data : std_logic_vector(15 downto 0);
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
SIGNAL addr_akt_s : std_logic;
SIGNAL addr_akt_e : std_logic;
SIGNAL data_akt_s : std_logic;
SIGNAL data_akt_e : std_logic;
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL vpad : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL S_stated : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
-- SIGNAL n_clk : std_logic;
SIGNAL vmaena : std_logic;
SIGNAL vmaenad : std_logic;
SIGNAL state_ena : std_logic;
SIGNAL sync_state3 : std_logic;
SIGNAL eind : std_logic;
SIGNAL eindd : std_logic;
SIGNAL sel_autoconfig: std_logic;
SIGNAL autoconfig_out: std_logic;
SIGNAL autoconfig_data: std_logic_vector(3 downto 0);
SIGNAL sel_fast: std_logic;
SIGNAL slower : std_logic_vector(3 downto 0);
type sync_states is (sync0, sync1, sync2, sync3, sync4, sync5, sync6, sync7, sync8, sync9);
signal sync_state : sync_states;
SIGNAL datatg68 : std_logic_vector(15 downto 0);
SIGNAL ramcs : std_logic;
BEGIN
-- n_clk <= NOT clk;
-- wrd <= data_akt_e OR data_akt_s;
wrd <= wr;
addr <= cpuaddr;-- WHEN addr_akt_e='1' ELSE t_addr WHEN addr_akt_s='1' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-- data <= data_write WHEN data_akt_e='1' ELSE t_data WHEN data_akt_s='1' ELSE "ZZZZZZZZZZZZZZZZ";
-- datatg68 <= fromram WHEN sel_fast='1' ELSE r_data;
datatg68 <= fromram WHEN sel_fast='1' ELSE r_data WHEN sel_autoconfig='0' ELSE autoconfig_data&r_data(11 downto 0);
-- toram <= data_write;
sel_autoconfig <= '1' when cpuaddr(23 downto 19)="11101" AND autoconfig_out='1' ELSE '0'; --$E80000 - $EFFFFF
sel_fast <= '1' when state/="01" AND (cpuaddr(23 downto 21)="001" OR cpuaddr(23 downto 21)="010" OR cpuaddr(23 downto 21)="011" OR cpuaddr(23 downto 21)="100") ELSE '0'; --$200000 - $9FFFFF
-- sel_fast <= '1' when cpuaddr(23 downto 21)="001" OR cpuaddr(23 downto 21)="010" ELSE '0'; --$200000 - $5FFFFF
-- sel_fast <= '1' when cpuaddr(23 downto 19)="11111" ELSE '0'; --$F800000;
-- sel_fast <= '0'; --$200000 - $9FFFFF
-- sel_fast <= '1' when cpuaddr(24)='1' AND state/="01" ELSE '0'; --$1000000 - $1FFFFFF
ramcs <= NOT sel_fast;-- OR (state(0) AND NOT state(1));
-- cpuDMA <= NOT ramcs;
cpuDMA <= sel_fast;
cpustate <= clkena&slower(1 downto 0)&ramcs&state;
ramlds <= lds_in;
ramuds <= uds_in;
ramaddr(23 downto 0) <= cpuaddr(23 downto 0);
ramaddr(24) <= sel_fast;
ramaddr(31 downto 25) <= cpuaddr(31 downto 25);
pf68K_Kernel_inst: TG68KdotC_Kernel
generic map(
SR_Read => 2, --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe => 2, --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode => 2, --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode => 2, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode => 2 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
)
PORT MAP(
clk => clk, -- : in std_logic;
nReset => reset, -- : in std_logic:='1'; --low active
clkena_in => clkena, -- : in std_logic:='1';
-- data_in => r_data, -- : in std_logic_vector(15 downto 0);
-- data_in => data_read, -- : in std_logic_vector(15 downto 0);
data_in => datatg68, -- : in std_logic_vector(15 downto 0);
IPL => cpuIPL, -- : in std_logic_vector(2 downto 0):="111";
IPL_autovector => '1', -- : in std_logic:='0';
addr => cpuaddr, -- : buffer std_logic_vector(31 downto 0);
data_write => data_write, -- : out std_logic_vector(15 downto 0);
busstate => state, -- : buffer std_logic_vector(1 downto 0);
regin => open, -- : out std_logic_vector(31 downto 0);
nWr => wr, -- : out std_logic;
nUDS => uds_in,
nLDS => lds_in, -- : out std_logic;
nResetOut => nResetOut,
CPU => cpu,
skipFetch => skipFetch -- : out std_logic
);
PROCESS (clk)
BEGIN
autoconfig_data <= "1111";
IF memcfg(5 downto 4)/="00" THEN
CASE cpuaddr(6 downto 1) IS
WHEN "000000" => autoconfig_data <= "1110"; --normal card, add mem, no ROM
WHEN "000001" =>
CASE memcfg(5 downto 4) IS
WHEN "01" => autoconfig_data <= "0110"; --2MB
WHEN "10" => autoconfig_data <= "0111"; --4MB
WHEN OTHERS => autoconfig_data <= "0000"; --8MB
END CASE;
WHEN "001000" => autoconfig_data <= "1110"; --4626=icomp
WHEN "001001" => autoconfig_data <= "1101";
WHEN "001010" => autoconfig_data <= "1110";
WHEN "001011" => autoconfig_data <= "1101";
WHEN "010011" => autoconfig_data <= "1110"; --serial=1
WHEN OTHERS => null;
END CASE;
END IF;
IF rising_edge(clk) THEN
IF reset='0' THEN
autoconfig_out <= '1'; --autoconfig on
ELSIF enaWRreg='1' THEN
IF sel_autoconfig='1' AND state="11"AND uds_in='0' AND cpuaddr(6 downto 1)="100100" THEN
autoconfig_out <= '0'; --autoconfig off
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF reset='0' THEN
vmaena <= '0';
vmaenad <= '0';
sync_state3 <= '0';
ELSIF ena7RDreg='1' THEN
vmaena <= '0';
sync_state3 <= '0';
IF state/="01" OR state_ena='1' THEN
vmaenad <= vmaena;
END IF;
IF sync_state=sync5 THEN
e <= '1';
END IF;
IF sync_state=sync3 THEN
sync_state3 <= '1';
END IF;
IF sync_state=sync9 THEN
e <= '0';
vmaena <= NOT vma;
END IF;
END IF;
END IF;
IF rising_edge(clk) THEN
S_stated <= S_state;
IF ena7WRreg='1' THEN
eind <= ein;
eindd <= eind;
CASE sync_state IS
WHEN sync0 => sync_state <= sync1;
WHEN sync1 => sync_state <= sync2;
WHEN sync2 => sync_state <= sync3;
WHEN sync3 => sync_state <= sync4;
vma <= vpa;
WHEN sync4 => sync_state <= sync5;
WHEN sync5 => sync_state <= sync6;
WHEN sync6 => sync_state <= sync7;
WHEN sync7 => sync_state <= sync8;
WHEN sync8 => sync_state <= sync9;
WHEN OTHERS => sync_state <= sync0;
vma <= '1';
END CASE;
IF eind='1' AND eindd='0' THEN
sync_state <= sync7;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
state_ena <= '0';
IF clkena_in='1' AND enaWRreg='1' AND (state="01" OR (ena7RDreg='1' AND clkena_e='1') OR ramready='1') THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
IF state="01" THEN
state_ena <= '1';
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
slower <= "1000";
ELSE
slower(3 downto 0) <= enaWRreg&slower(3 downto 1);
-- slower(0) <= NOT slower(3) AND NOT slower(2);
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= (as_s AND as_e) OR sel_fast;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
IF reset='0' THEN
S_state <= "00";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
addr_akt_s <= '0';
data_akt_s <= '0';
ELSIF rising_edge(clk) THEN
IF ena7WRreg='1' THEN
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
addr_akt_s <= '0';
data_akt_s <= '0';
CASE S_state IS
WHEN "00" => IF state/="01" AND sel_fast='0' THEN
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "01";
END IF;
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
t_addr <= cpuaddr;
-- t_data <= data_write;
WHEN "10" =>
addr_akt_s <= '1';
data_akt_s <= NOT wr;
r_data <= data_read;
IF waitm='0' OR (vma='0' AND sync_state=sync9) THEN
S_state <= "11";
ELSE
as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
addr_akt_e <= '0';
data_akt_e <= '0';
ELSIF rising_edge(clk) THEN
IF ena7RDreg='1' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
addr_akt_e <= '0';
data_akt_e <= '0';
CASE S_state IS
WHEN "00" => addr_akt_e <= '1';
cpuIPL <= IPL;
IF sel_fast='0' THEN
IF state/="01" THEN
as_e <= '0';
END IF;
rw_e <= wr;
data_akt_e <= NOT wr;
IF wr='1' THEN
uds_e <= uds_in;
lds_e <= lds_in;
END IF;
END IF;
WHEN "01" => addr_akt_e <= '1';
data_akt_e <= NOT wr;
as_e <= '0';
rw_e <= wr;
uds_e <= uds_in;
lds_e <= lds_in;
WHEN "10" => rw_e <= wr;
addr_akt_e <= '1';
data_akt_e <= NOT wr;
cpuIPL <= IPL;
waitm <= dtack;
WHEN OTHERS => --null;
clkena_e <= '1';
END CASE;
END IF;
END IF;
END PROCESS;
END;

918
common/CPU/68000/tg68k/TG68K_ALU.vhd Normal file
View File

@@ -0,0 +1,918 @@
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.TG68K_Pack.all;
entity TG68K_ALU is
generic(
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port(clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in std_logic;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in std_logic;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end TG68K_ALU;
architecture logic of TG68K_ALU is
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- ALU and more
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
signal OP1in : std_logic_vector(31 downto 0);
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal notaddsub_b : std_logic_vector(33 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal opaddsub : bit;
signal c_in : std_logic_vector(3 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal bcd_a : std_logic_vector(8 downto 0);
signal bcd_s : std_logic_vector(8 downto 0);
signal result_mulu : std_logic_vector(63 downto 0);
signal result_div : std_logic_vector(63 downto 0);
signal set_mV_Flag : std_logic;
signal V_Flag : bit;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_X : std_logic;
signal rot_C : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal asl_VFlag : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal bchg : std_logic;
signal bset : std_logic;
signal mulu_sign : std_logic;
signal mulu_signext : std_logic_vector(16 downto 0);
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(63 downto 0);
signal FAsign : std_logic;
signal faktorA : std_logic_vector(31 downto 0);
signal faktorB : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(63 downto 0);
signal div_quot : std_logic_vector(63 downto 0);
signal div_ovl : std_logic;
signal div_neg : std_logic;
signal div_bit : std_logic;
signal div_sub : std_logic_vector(32 downto 0);
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
signal OP2_sign : std_logic;
signal OP2outext : std_logic_vector(15 downto 0);
signal in_offset : std_logic_vector(5 downto 0);
-- signal in_width : std_logic_vector(5 downto 0);
signal datareg : std_logic_vector(31 downto 0);
signal insert : std_logic_vector(31 downto 0);
-- signal bf_result : std_logic_vector(31 downto 0);
-- signal bf_offset : std_logic_vector(5 downto 0);
-- signal bf_width : std_logic_vector(5 downto 0);
-- signal bf_firstbit : std_logic_vector(5 downto 0);
signal bf_datareg : std_logic_vector(31 downto 0);
-- signal bf_out : std_logic_vector(31 downto 0);
signal result : std_logic_vector(39 downto 0);
signal result_tmp : std_logic_vector(39 downto 0);
signal sign : std_logic_vector(31 downto 0);
signal bf_set1 : std_logic_vector(39 downto 0);
signal inmux0 : std_logic_vector(39 downto 0);
signal inmux1 : std_logic_vector(39 downto 0);
signal inmux2 : std_logic_vector(39 downto 0);
signal inmux3 : std_logic_vector(31 downto 0);
signal copymux0 : std_logic_vector(39 downto 0);
signal copymux1 : std_logic_vector(39 downto 0);
signal copymux2 : std_logic_vector(39 downto 0);
signal copymux3 : std_logic_vector(31 downto 0);
signal bf_set2 : std_logic_vector(31 downto 0);
-- signal bf_set3 : std_logic_vector(31 downto 0);
signal shift : std_logic_vector(39 downto 0);
signal copy : std_logic_vector(39 downto 0);
-- signal offset : std_logic_vector(5 downto 0);
-- signal width : std_logic_vector(5 downto 0);
signal bf_firstbit : std_logic_vector(5 downto 0);
signal mux : std_logic_vector(3 downto 0);
signal bitnr : std_logic_vector(4 downto 0);
signal mask : std_logic_vector(31 downto 0);
signal bf_bset : std_logic;
signal bf_NFlag : std_logic;
signal bf_bchg : std_logic;
signal bf_ins : std_logic;
signal bf_exts : std_logic;
signal bf_fffo : std_logic;
signal bf_d32 : std_logic;
signal bf_s32 : std_logic;
signal index : std_logic_vector(4 downto 0);
-- signal i : integer range 0 to 31;
-- signal i : integer range 0 to 31;
-- signal i : std_logic_vector(5 downto 0);
BEGIN
-----------------------------------------------------------------------------
-- set OP1in
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_shift,
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
BEGIN
ALUout <= OP1in;
ALUout(7) <= OP1in(7) OR exec_tas;
IF exec(opcBFwb)='1' THEN
ALUout <= result(31 downto 0);
IF bf_fffo='1' THEN
ALUout <= (OTHERS =>'0');
ALUout(5 downto 0) <= bf_firstbit + bf_shift;
END IF;
END IF;
OP1in <= addsub_q;
IF exec(opcABCD)='1' THEN
OP1in(7 downto 0) <= bcd_a(7 downto 0);
ELSIF exec(opcSBCD)='1' THEN
OP1in(7 downto 0) <= bcd_s(7 downto 0);
ELSIF exec(opcMULU)='1' AND MUL_Mode/=3 THEN
IF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
OP1in <= result_mulu(31 downto 0);
ELSE
OP1in <= result_mulu(63 downto 32);
END IF;
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
-- IF exe_opcode(15)='1' THEN
OP1in <= result_div(47 downto 32)&result_div(15 downto 0);
ELSE --64bit
IF exec(write_reminder)='1' THEN
OP1in <= result_div(63 downto 32);
ELSE
OP1in <= result_div(31 downto 0);
END IF;
END IF;
ELSIF exec(opcOR)='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec(opcAND)='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec(opcScc)='1' THEN
OP1in(7 downto 0) <= (others=>exe_condition);
ELSIF exec(opcEOR)='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
OP1in <= OP2out;
ELSIF exec(opcROT)='1' THEN
OP1in <= rot_out;
ELSIF exec(opcSWAP)='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec(opcBITS)='1' THEN
OP1in <= bits_out;
ELSIF exec(opcBF)='1' THEN
OP1in <= bf_datareg;
ELSIF exec(opcMOVESR)='1' THEN
OP1in(7 downto 0) <= Flags;
IF exe_datatype="00" THEN
OP1in(15 downto 8) <= "00000000";
ELSE
OP1in(15 downto 8) <= FlagsSR;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, execOPC, datatype, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
notaddsub_b, add_result, c_in, sndOPC)
BEGIN
addsub_a <= OP1out;
IF exec(get_bfoffset)='1' THEN
IF sndOPC(11)='1' THEN
addsub_a <= OP1out(31)&OP1out(31)&OP1out(31)&OP1out(31 downto 3);
ELSE
addsub_a <= "000000000000000000000000000000"&sndOPC(10 downto 9);
END IF;
END IF;
IF exec(subidx)='1' THEN
opaddsub <= '1';
ELSE
opaddsub <= '0';
END IF;
c_in(0) <='0';
addsub_b <= OP2out;
IF execOPC='0' AND exec(OP2out_one)='0' AND exec(get_bfoffset)='0'THEN
IF long_start='0' AND datatype="00" AND exec(use_SP)='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF long_start='0' AND exe_datatype="10" AND (exec(presub) OR exec(postadd) OR movem_presub)='1' THEN
IF exec(movem_action)='1' THEN
addsub_b <= "00000000000000000000000000000110";
ELSE
addsub_b <= "00000000000000000000000000000100";
END IF;
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
c_in(0) <= '1';
END IF;
opaddsub <= exec(addsub);
END IF;
IF opaddsub='0' OR long_start='1' THEN --ADD
notaddsub_b <= '0'&addsub_b&c_in(0);
ELSE --SUB
notaddsub_b <= NOT ('0'&addsub_b&c_in(0));
END IF;
add_result <= (('0'&addsub_a&notaddsub_b(0))+notaddsub_b);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_q <= add_result(32 downto 1);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (OP1out, OP2out, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
bcd_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
bcd_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
bchg <= '0';
bset <= '0';
CASE opcode(7 downto 6) IS
WHEN "01" => --bchg
bchg <= '1';
WHEN "11" => --bset
bset <= '1';
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
IF exe_opcode(8)='0' THEN
IF exe_opcode(5 downto 4)="00" THEN
bit_number <= sndOPC(4 downto 0);
ELSE
bit_number <= "00"&sndOPC(2 downto 0);
END IF;
ELSE
IF exe_opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
bits_out <= OP1out;
bits_out(to_integer(unsigned(bit_Number))) <= (bchg AND NOT one_bit_in) OR bset ;
END PROCESS;
-----------------------------------------------------------------------------
-- Bit Field
-----------------------------------------------------------------------------
PROCESS (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
shift, datareg, bf_NFlag, result, reg_QB, sign, bf_d32, bf_s32, copy, bf_loffset, copymux0, copymux1, copymux2, copymux3, bf_width)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
bf_bset <= '0';
bf_bchg <= '0';
bf_ins <= '0';
bf_exts <= '0';
bf_fffo <= '0';
bf_d32 <= '0';
bf_s32 <= '0';
CASE opcode(10 downto 8) IS
WHEN "010" => bf_bchg <= '1'; --BFCHG
WHEN "011" => bf_exts <= '1'; --BFEXTS
-- WHEN "100" => insert <= (OTHERS =>'0'); --BFCLR
WHEN "101" => bf_fffo <= '1'; --BFFFO
WHEN "110" => bf_bset <= '1'; --BFSET
WHEN "111" => bf_ins <= '1'; --BFINS
bf_s32 <= '1';
WHEN OTHERS => NULL;
END CASE;
IF opcode(4 downto 3)="00" THEN
bf_d32 <= '1';
END IF;
bf_ext_out <= result(39 downto 32);
END IF;
END IF;
shift <= bf_ext_in&OP2out;
IF bf_s32='1' THEN
shift(39 downto 32) <= OP2out(7 downto 0);
END IF;
IF bf_shift(0)='1' THEN
inmux0 <= shift(0)&shift(39 downto 1);
ELSE
inmux0 <= shift;
END IF;
IF bf_shift(1)='1' THEN
inmux1 <= inmux0(1 downto 0)&inmux0(39 downto 2);
ELSE
inmux1 <= inmux0;
END IF;
IF bf_shift(2)='1' THEN
inmux2 <= inmux1(3 downto 0)&inmux1(39 downto 4);
ELSE
inmux2 <= inmux1;
END IF;
IF bf_shift(3)='1' THEN
inmux3 <= inmux2(7 downto 0)&inmux2(31 downto 8);
ELSE
inmux3 <= inmux2(31 downto 0);
END IF;
IF bf_shift(4)='1' THEN
bf_set2(31 downto 0) <= inmux3(15 downto 0)&inmux3(31 downto 16);
ELSE
bf_set2(31 downto 0) <= inmux3;
END IF;
IF bf_loffset(4)='1' THEN
copymux3 <= sign(15 downto 0)&sign(31 downto 16);
ELSE
copymux3 <= sign;
END IF;
IF bf_loffset(3)='1' THEN
copymux2(31 downto 0) <= copymux3(23 downto 0)&copymux3(31 downto 24);
ELSE
copymux2(31 downto 0) <= copymux3;
END IF;
IF bf_d32='1' THEN
copymux2(39 downto 32) <= copymux3(7 downto 0);
ELSE
copymux2(39 downto 32) <= "11111111";
END IF;
IF bf_loffset(2)='1' THEN
copymux1 <= copymux2(35 downto 0)&copymux2(39 downto 36);
ELSE
copymux1 <= copymux2;
END IF;
IF bf_loffset(1)='1' THEN
copymux0 <= copymux1(37 downto 0)&copymux1(39 downto 38);
ELSE
copymux0 <= copymux1;
END IF;
IF bf_loffset(0)='1' THEN
copy <= copymux0(38 downto 0)&copymux0(39);
ELSE
copy <= copymux0;
END IF;
result_tmp <= bf_ext_in&OP1out;
IF bf_ins='1' THEN
datareg <= reg_QB;
ELSE
datareg <= bf_set2;
END IF;
IF bf_ins='1' THEN
result(31 downto 0) <= bf_set2;
result(39 downto 32) <= bf_set2(7 downto 0);
ELSIF bf_bchg='1' THEN
result(31 downto 0) <= NOT OP1out;
result(39 downto 32) <= NOT bf_ext_in;
ELSE
result <= (OTHERS => '0');
END IF;
IF bf_bset='1' THEN
result <= (OTHERS => '1');
END IF;
sign <= (OTHERS => '0');
bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
FOR i in 0 to 31 LOOP
IF i>bf_width(4 downto 0) THEN
datareg(i) <= '0';
sign(i) <= '1';
END IF;
END LOOP;
FOR i in 0 to 39 LOOP
IF copy(i)='1' THEN
result(i) <= result_tmp(i);
END IF;
END LOOP;
IF bf_exts='1' AND bf_NFlag='1' THEN
bf_datareg <= datareg OR sign;
ELSE
bf_datareg <= datareg;
END IF;
-- bf_datareg <= copy(31 downto 0);
-- result(31 downto 0)<=datareg;
--BFFFO
mask <= datareg;
bf_firstbit <= '0'&bitnr;
bitnr <= "11111";
IF mask(31 downto 28)="0000" THEN
IF mask(27 downto 24)="0000" THEN
IF mask(23 downto 20)="0000" THEN
IF mask(19 downto 16)="0000" THEN
bitnr(4) <= '0';
IF mask(15 downto 12)="0000" THEN
IF mask(11 downto 8)="0000" THEN
bitnr(3) <= '0';
IF mask(7 downto 4)="0000" THEN
bitnr(2) <= '0';
mux <= mask(3 downto 0);
ELSE
mux <= mask(7 downto 4);
END IF;
ELSE
mux <= mask(11 downto 8);
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(15 downto 12);
END IF;
ELSE
mux <= mask(19 downto 16);
bitnr(3) <= '0';
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(23 downto 20);
bitnr(3) <= '0';
END IF;
ELSE
mux <= mask(27 downto 24);
bitnr(2) <= '0';
END IF;
ELSE
mux <= mask(31 downto 28);
END IF;
IF mux(3 downto 2)="00" THEN
bitnr(1) <= '0';
IF mux(1)='0' THEN
bitnr(0) <= '0';
END IF;
ELSE
IF mux(3)='0' THEN
bitnr(0) <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
BEGIN
CASE exe_opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => NULL;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => NULL;
END CASE;
IF exec(rot_nop)='1' THEN
rot_out <= OP1out;
rot_X <= Flags(4);
IF rot_bits="10" THEN --ROXL, ROXR
rot_C <= Flags(4);
ELSE
rot_C <= '0';
END IF;
ELSE
IF exe_opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_X <= rot_rot;
rot_C <= rot_rot;
ELSE --right
rot_X <= OP1out(0);
rot_C <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE exe_opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--CCR op
------------------------------------------------------------------------------
PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1IN, c_out, addsub_ofl,
bcd_s, bcd_a, exec)
BEGIN
IF exec(andiSR)='1' THEN
CCRin <= Flags AND last_data_read(7 downto 0);
ELSIF exec(eoriSR)='1' THEN
CCRin <= Flags XOR last_data_read(7 downto 0);
ELSIF exec(oriSR)='1' THEN
CCRin <= Flags OR last_data_read(7 downto 0);
ELSE
CCRin <= OP2out(7 downto 0);
END IF;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
flag_z <= "000";
IF exec(use_XZFlag)='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF exe_datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec(opcABCD)='1' THEN
set_flags(0) <= bcd_a(8);
ELSIF exec(opcSBCD)='1' THEN
set_flags(0) <= bcd_s(8);
END IF;
ELSIF exe_datatype="10" OR exec(opcCPMAW)='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
IF rising_edge(clk) THEN
IF clkena_lw = '1' THEN
IF exec(directSR)='1' OR set_stop='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF exec(directCCR)='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF exec(opcROT)='1' THEN
asl_VFlag <= ((set_flags(3) XOR rot_rot) OR asl_VFlag);
ELSE
asl_VFlag <= '0';
END IF;
IF exec(to_CCR)='1' THEN
Flags(7 downto 0) <= CCRin(7 downto 0); --CCR
ELSIF Z_error='1' THEN
IF exe_opcode(8)='0' THEN
Flags(3 downto 0) <= reg_QA(31)&"000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF exec(no_Flags)='0' THEN
IF exec(opcADD)='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
Flags(4) <= rot_X;
END IF;
IF (exec(opcADD) OR exec(opcCMP))='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2) AND Flags(2);
Flags(1) <= '0';
Flags(0) <= '0';
ELSIF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN -- flag MULU.l
Flags(3) <= set_flags(3);
Flags(2) <= set_flags(2);
Flags(1) <= set_mV_Flag; --V
Flags(0) <= '0';
ELSIF exec(opcOR)='1' OR exec(opcAND)='1' OR exec(opcEOR)='1' OR exec(opcMOVE)='1' OR exec(opcMOVEQ)='1' OR exec(opcSWAP)='1' OR exec(opcBF)='1' OR (exec(opcMULU)='1' AND MUL_Mode/=3) THEN
Flags(1 downto 0) <= "00";
Flags(3 downto 2) <= set_flags(3 downto 2);
IF exec(opcBF)='1' THEN
Flags(3) <= bf_NFlag;
END IF;
ELSIF exec(opcROT)='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_C;
IF rot_bits="00" AND ((set_flags(3) XOR rot_rot) OR asl_VFlag)='1' THEN --ASL/ASR
Flags(1) <= '1';
ELSE
Flags(1) <= '0';
END IF;
ELSIF exec(opcBITS)='1' THEN
Flags(2) <= NOT one_bit_in;
ELSIF exec(opcCHK)='1' THEN
IF exe_datatype="01" THEN --Word
Flags(3) <= OP1out(15);
ELSE
Flags(3) <= OP1out(31);
END IF;
IF OP1out(15 downto 0)=X"0000" AND (exe_datatype="01" OR OP1out(31 downto 16)=X"0000") THEN
Flags(2) <='1';
ELSE
Flags(2) <='0';
END IF;
Flags(1 downto 0) <= "00";
END IF;
END IF;
END IF;
Flags(7 downto 5) <= "000";
END IF;
END PROCESS;
-------------------------------------------------------------------------------
---- MULU/MULS
-------------------------------------------------------------------------------
PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
BEGIN
IF (signedOP='1' AND faktorB(31)='1') OR FAsign='1' THEN
muls_msb <= mulu_reg(63);
ELSE
muls_msb <= '0';
END IF;
IF signedOP='1' AND faktorB(31)='1' THEN
mulu_sign <= '1';
ELSE
mulu_sign <= '0';
END IF;
IF MUL_Mode=0 THEN -- 16 Bit
result_mulu(63 downto 32) <= muls_msb&mulu_reg(63 downto 33);
result_mulu(15 downto 0) <= 'X'&mulu_reg(15 downto 1);
IF mulu_reg(0)='1' THEN
IF FAsign='1' THEN
result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)-(mulu_sign&faktorB(31 downto 16)));
ELSE
result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)+(mulu_sign&faktorB(31 downto 16)));
END IF;
END IF;
ELSE -- 32 Bit
result_mulu <= muls_msb&mulu_reg(63 downto 1);
IF mulu_reg(0)='1' THEN
IF FAsign='1' THEN
result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)-(mulu_sign&faktorB));
ELSE
result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)+(mulu_sign&faktorB));
END IF;
END IF;
END IF;
IF exe_opcode(15)='1' OR MUL_Mode=0 THEN
faktorB(31 downto 16) <= OP2out(15 downto 0);
faktorB(15 downto 0) <= (OTHERS=>'0');
ELSE
faktorB <= OP2out;
END IF;
IF (result_mulu(63 downto 32)=X"00000000" AND (signedOP='0' OR result_mulu(31)='0')) OR
(result_mulu(63 downto 32)=X"FFFFFFFF" AND signedOP='1' AND result_mulu(31)='1') THEN
set_mV_Flag <= '0';
ELSE
set_mV_Flag <= '1';
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
IF micro_state=mul1 THEN
mulu_reg(63 downto 32) <= (OTHERS=>'0');
IF divs='1' AND ((exe_opcode(15)='1' AND reg_QA(15)='1') OR (exe_opcode(15)='0' AND reg_QA(31)='1')) THEN --MULS Neg faktor
FAsign <= '1';
mulu_reg(31 downto 0) <= 0-reg_QA;
ELSE
FAsign <= '0';
mulu_reg(31 downto 0) <= reg_QA;
END IF;
ELSIF exec(opcMULU)='0' THEN
mulu_reg <= result_mulu;
END IF;
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
---- DIVU/DIVS
-------------------------------------------------------------------------------
PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
signedOP, nozero, div_qsign, OP2outext)
BEGIN
divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
divisor(15 downto 0) <= (OTHERS=> '0');
divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
divisor(47 downto 16) <= reg_QA;
ELSE
divisor(31 downto 0) <= reg_QA;
IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
divisor(63 downto 32) <= reg_QB;
END IF;
END IF;
IF signedOP='1' OR opcode(15)='0' THEN
OP2outext <= OP2out(31 downto 16);
ELSE
OP2outext <= (OTHERS=> '0');
END IF;
IF signedOP='1' AND OP2out(31) ='1' THEN
div_sub <= (div_reg(63 downto 31))+('1'&OP2out(31 downto 0));
ELSE
div_sub <= (div_reg(63 downto 31))-('0'&OP2outext(15 downto 0)&OP2out(15 downto 0));
END IF;
IF DIV_Mode=0 THEN
div_bit <= div_sub(16);
ELSE
div_bit <= div_sub(32);
END IF;
IF div_bit='1' THEN
div_quot(63 downto 32) <= div_reg(62 downto 31);
ELSE
div_quot(63 downto 32) <= div_sub(31 downto 0);
END IF;
div_quot(31 downto 0) <= div_reg(30 downto 0)&NOT div_bit;
IF ((nozero='1' AND signedOP='1' AND (OP2out(31) XOR OP1_sign XOR div_neg XOR div_qsign)='1' ) --Overflow DIVS
OR (signedOP='0' AND div_over(32)='0')) AND DIV_Mode/=3 THEN --Overflow DIVU
set_V_Flag <= '1';
ELSE
set_V_Flag <= '0';
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
V_Flag <= set_V_Flag;
signedOP <= divs;
IF micro_state=div1 THEN
nozero <= '0';
IF divs='1' AND divisor(63)='1' THEN -- Neg divisor
OP1_sign <= '1';
div_reg <= 0-divisor;
ELSE
OP1_sign <= '0';
div_reg <= divisor;
END IF;
ELSE
div_reg <= div_quot;
nozero <= NOT div_bit OR nozero;
END IF;
IF micro_state=div2 THEN
div_qsign <= NOT div_bit;
div_neg <= signedOP AND (OP2out(31) XOR OP1_sign);
IF DIV_Mode=0 THEN
div_over(32 downto 16) <= ('0'&div_reg(47 downto 32))-('0'&OP2out(15 downto 0));
ELSE
div_over <= ('0'&div_reg(63 downto 32))-('0'&OP2out);
END IF;
END IF;
IF exec(write_reminder)='0' THEN
-- IF exec_DIVU='0' THEN
IF div_neg='1' THEN
result_div(31 downto 0) <= 0-div_quot(31 downto 0);
ELSE
result_div(31 downto 0) <= div_quot(31 downto 0);
END IF;
IF OP1_sign='1' THEN
result_div(63 downto 32) <= 0-div_quot(63 downto 32);
ELSE
result_div(63 downto 32) <= div_quot(63 downto 32);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;

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common/CPU/68000/tg68k/TG68K_Pack.vhd Normal file
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------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package TG68K_Pack is
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
andi, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3, trap0, trap1, trap2, trap3,
movec1, movep1, movep2, movep3, movep4, movep5, movep6, rota1, bf1,
mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2);
constant opcMOVE : integer := 0; --
constant opcMOVEQ : integer := 1; --
constant opcMOVESR : integer := 2; --
constant opcADD : integer := 3; --
constant opcADDQ : integer := 4; --
constant opcOR : integer := 5; --
constant opcAND : integer := 6; --
constant opcEOR : integer := 7; --
constant opcCMP : integer := 8; --
constant opcROT : integer := 9; --
constant opcCPMAW : integer := 10;
constant opcEXT : integer := 11; --
constant opcABCD : integer := 12; --
constant opcSBCD : integer := 13; --
constant opcBITS : integer := 14; --
constant opcSWAP : integer := 15; --
constant opcScc : integer := 16; --
constant andiSR : integer := 17; --
constant eoriSR : integer := 18; --
constant oriSR : integer := 19; --
constant opcMULU : integer := 20; --
constant opcDIVU : integer := 21; --
constant dispouter : integer := 22; --
constant rot_nop : integer := 23; --
constant ld_rot_cnt : integer := 24; --
constant writePC_add : integer := 25; --
constant ea_data_OP1 : integer := 26; --
constant ea_data_OP2 : integer := 27; --
constant use_XZFlag : integer := 28; --
constant get_bfoffset : integer := 29; --
constant save_memaddr : integer := 30; --
constant opcCHK : integer := 31; --
constant movec_rd : integer := 32; --
constant movec_wr : integer := 33; --
constant Regwrena : integer := 34; --
constant update_FC : integer := 35; --
constant linksp : integer := 36; --
constant movepl : integer := 37; --
constant update_ld : integer := 38; --
constant OP1addr : integer := 39; --
constant write_reg : integer := 40; --
constant changeMode : integer := 41; --
constant ea_build : integer := 42; --
constant trap_chk : integer := 43; --
constant store_ea_data : integer := 44; --
constant addrlong : integer := 45; --
constant postadd : integer := 46; --
constant presub : integer := 47; --
constant subidx : integer := 48; --
constant no_Flags : integer := 49; --
constant use_SP : integer := 50; --
constant to_CCR : integer := 51; --
constant to_SR : integer := 52; --
constant OP2out_one : integer := 53; --
constant OP1out_zero : integer := 54; --
constant mem_addsub : integer := 55; --
constant addsub : integer := 56; --
constant directPC : integer := 57; --
constant direct_delta : integer := 58; --
constant directSR : integer := 59; --
constant directCCR : integer := 60; --
constant exg : integer := 61; --
constant get_ea_now : integer := 62; --
constant ea_to_pc : integer := 63; --
constant hold_dwr : integer := 64; --
constant to_USP : integer := 65; --
constant from_USP : integer := 66; --
constant write_lowlong : integer := 67; --
constant write_reminder : integer := 68; --
constant movem_action : integer := 69; --
constant briefext : integer := 70; --
constant get_2ndOPC : integer := 71; --
constant mem_byte : integer := 72; --
constant longaktion : integer := 73; --
constant opcRESET : integer := 74; --
constant opcBF : integer := 75; --
constant opcBFwb : integer := 76; --
constant s2nd_hbits : integer := 77; --
-- constant : integer := 75; --
-- constant : integer := 76; --
-- constant : integer := 7; --
-- constant : integer := 7; --
-- constant : integer := 7; --
constant lastOpcBit : integer := 77;
component TG68K_ALU
generic(
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
);
port(
clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
execOPC : in bit;
exe_condition : in std_logic;
exec_tas : in std_logic;
long_start : in bit;
movem_presub : in bit;
set_stop : in bit;
Z_error : in bit;
rot_bits : in std_logic_vector(1 downto 0);
exec : in bit_vector(lastOpcBit downto 0);
OP1out : in std_logic_vector(31 downto 0);
OP2out : in std_logic_vector(31 downto 0);
reg_QA : in std_logic_vector(31 downto 0);
reg_QB : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(15 downto 0);
datatype : in std_logic_vector(1 downto 0);
exe_opcode : in std_logic_vector(15 downto 0);
exe_datatype : in std_logic_vector(1 downto 0);
sndOPC : in std_logic_vector(15 downto 0);
last_data_read : in std_logic_vector(15 downto 0);
data_read : in std_logic_vector(15 downto 0);
FlagsSR : in std_logic_vector(7 downto 0);
micro_state : in micro_states;
bf_ext_in : in std_logic_vector(7 downto 0);
bf_ext_out : out std_logic_vector(7 downto 0);
bf_shift : in std_logic_vector(5 downto 0);
bf_width : in std_logic_vector(5 downto 0);
bf_loffset : in std_logic_vector(4 downto 0);
set_V_Flag : buffer bit;
Flags : buffer std_logic_vector(7 downto 0);
c_out : buffer std_logic_vector(2 downto 0);
addsub_q : buffer std_logic_vector(31 downto 0);
ALUout : out std_logic_vector(31 downto 0)
);
end component;
end;

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CPU core original CPU unclear items:
- CMPM, MOVE, ADDX, SUBX, ABCD, SBCD: generally spoken all operations where a source and a destination location are given. The predecrement and the postincrement addressing modes are affected. Which result is calculated by addressing modes (ax)+,(ay)+ and -(ax),-(ay). The result depends on the time when the address registers are incremented or decremented and the order, the operands are loaded. I assume, that the addresws registers are incremented twice during these instructions and that the address registers are incremented during the operation in a way, that the second operand is already taken from the postincremented or the predecremented address.
MOVEM:
- If the addressing register is included in the register list, the initial value of the register should be written to the memory. For the 68K20+ the decremented value is written. Which value is the correct one? Decremented by the actual amount of already transfered registers or the decremented value for the total amount of decremented registers?
- If the register list mask is empty, the MOVEM does nothing and behaves like a NOP.
ROL, ROR, ROXL, ROXR, ROTL, ROTR:
- The operation (example) ROL d0,d0 takes the number of required rotations out of do, rotates d0 and copies afterwards the result to d0.
- If the immediate rotation register is zero, no shift operation results, the status flags are updated.
ILLEGAL: The address written on the stack is the address of the ILLEGAL statement. In the simulator, the address written is the address of the ILLEGAL statement plus two.
Other things to do:
Further reduction of the core size.
WF 20071224

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The CPU IP core has been improved during the last release. There are still open topics. For more information see the 68K00 quirks-and-squirrels.txt in this directory.
Main changes since the last release:
1. The CPU does now work with the SUSKA IP core to run the emutos operating system.
2. Reduced the size from 10200 LEs (Altera Cyclone II) to about 9400 LEs.
3. Simplified the data register section.
4. Some bug fixes in several modules.
Please send me an email to wf@inventronik.de if bugs are encountered or also for tips and
suggestions.
Known issues:
The function code outputs (FC) are coded in a way, that the patterns during the bus transfers meet the patterns of the original 68000 CPUs. If there is no bus transfer and the processor is the bus master, there results a funcion code of "000". If the processor has no control over the bus, the function code outputs are high impedant.
The deasserted bus control signals UDSn or LDSn produce during byte wide bus access and in the predecrement addressing mode short spikes. This behaviour does not affect the correct bus transfer.
The EXT operation in the operation type OP_68K00 is named EXTW due to compiler constraints with the Xilinx ISE.
WF - 20080418.

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library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PACE_WF68K00IP_TOP_SOC is
port
(
CLK : in std_logic;
RESET_COREn : in std_logic; -- Core reset.
-- Address and data:
ADR_OUT : out std_logic_vector(23 downto 1);
ADR_EN : out std_logic;
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
DATA_EN : out std_logic;
-- System control:
BERRn : in std_logic;
RESET_INn : in std_logic;
RESET_OUT_EN : out std_logic; -- Open drain.
HALT_INn : in std_logic;
HALT_OUT_EN : out std_logic; -- Open drain.
-- Processor status:
FC_OUT : out std_logic_vector(2 downto 0);
FC_OUT_EN : out std_logic;
-- Interrupt control:
AVECn : in std_logic; -- Originally 68Ks use VPAn.
IPLn : in std_logic_vector(2 downto 0);
-- Aynchronous bus control:
DTACKn : in std_logic;
AS_OUTn : out std_logic;
AS_OUT_EN : out std_logic;
RWn_OUT : out std_logic;
RW_OUT_EN : out std_logic;
UDS_OUTn : out std_logic;
UDS_OUT_EN : out std_logic;
LDS_OUTn : out std_logic;
LDS_OUT_EN : out std_logic;
-- Synchronous peripheral control:
E : out std_logic;
VMA_OUTn : out std_logic;
VMA_OUT_EN : out std_logic;
VPAn : in std_logic;
-- Bus arbitration control:
BRn : in std_logic;
BGn : out std_logic;
BGACKn : in std_logic
);
end entity PACE_WF68K00IP_TOP_SOC;
architecture SYN of PACE_WF68K00IP_TOP_SOC is
signal CLK_s : bit;
signal RESET_COREn_s : bit;
-- Address and data:
signal ADR_EN_s : bit;
signal DATA_EN_s : bit;
-- System control:
signal BERRn_s : bit;
signal RESET_INn_s : bit;
signal RESET_OUT_EN_s : bit; -- Open drain.
signal HALT_OUT_EN_s : bit; -- Open drain.
-- Processor status:
signal FC_OUT_EN_s : bit;
-- Interrupt control:
signal AVECn_s : bit; -- Originally 68Ks use VPAn.
signal IPLn_s : std_logic_vector(2 downto 0);
-- Aynchronous bus control:
signal DTACKn_s : bit;
signal AS_OUTn_s : bit;
signal AS_OUT_EN_s : bit;
signal RWn_OUT_s : bit;
signal RW_OUT_EN_s : bit;
signal UDS_OUTn_s : bit;
signal UDS_OUT_EN_s : bit;
signal LDS_OUTn_s : bit;
signal LDS_OUT_EN_s : bit;
-- Synchronous peripheral control:
signal E_s : bit;
signal VMA_OUTn_s : bit;
signal VMA_OUT_EN_s : bit;
signal VPAn_s : bit;
-- Bus arbitration control:
signal BRn_s : bit;
signal BGn_s : bit;
signal BGACKn_s : bit;
begin
CLK_s <= TO_BIT(CLK);
RESET_COREn_s <= TO_BIT(RESET_COREn);
-- Address and data:
ADR_EN <= TO_X01(ADR_EN_s);
DATA_EN <= TO_X01(DATA_EN_s);
-- System control:
BERRn_s <= TO_BIT(BERRn);
RESET_INn_s <= TO_BIT(RESET_INn);
RESET_OUT_EN <= TO_X01(RESET_OUT_EN_s);
HALT_OUT_EN <= TO_X01(HALT_OUT_EN_s);
-- Processor status:
FC_OUT_EN <= TO_X01(FC_OUT_EN_s);
-- Interrupt control:
AVECn_s <= TO_BIT(AVECn);
IPLn_s <= IPLn;
-- Aynchronous bus control:
DTACKn_s <= TO_BIT(DTACKn);
AS_OUTn <= TO_X01(AS_OUTn_s);
AS_OUT_EN <= TO_X01(AS_OUT_EN_s);
RWn_OUT <= TO_X01(RWn_OUT_s);
RW_OUT_EN <= TO_X01(RW_OUT_EN_s);
UDS_OUTn <= TO_X01(UDS_OUTn_s);
UDS_OUT_EN <= TO_X01(UDS_OUT_EN_s);
LDS_OUTn <= TO_X01(LDS_OUTn_s);
LDS_OUT_EN <= TO_X01(LDS_OUT_EN_s);
-- Synchronous peripheral control:
E <= TO_X01(E_s);
VMA_OUTn <= TO_X01(VMA_OUTn_s);
VMA_OUT_EN <= TO_X01(VMA_OUT_EN_s);
VPAn_s <= TO_BIT(VPAn);
-- Bus arbitration control:
BRn_s <= TO_BIT(BRn);
BGn <= TO_X01(BGn_s);
BGACKn_s <= TO_BIT(BGACKn);
WF68K00IP_TOP_SOC_inst : entity work.WF68K00IP_TOP_SOC
port map
(
CLK => CLK_s,
RESET_COREn => RESET_COREn_s,
-- Address and data:
ADR_OUT => ADR_OUT,
ADR_EN => ADR_EN_s,
DATA_IN => DATA_IN,
DATA_OUT => DATA_OUT,
DATA_EN => DATA_EN_s,
-- System control:
BERRn => BERRn_s,
RESET_INn => RESET_INn_s,
RESET_OUT_EN => RESET_OUT_EN_s,
HALT_INn => HALT_INn,
HALT_OUT_EN => HALT_OUT_EN_s,
-- Processor status:
FC_OUT => FC_OUT,
FC_OUT_EN => FC_OUT_EN_s,
-- Interrupt control:
AVECn => AVECn_s,
IPLn => IPLn_s,
-- Aynchronous bus control:
DTACKn => DTACKn_s,
AS_OUTn => AS_OUTn_s,
AS_OUT_EN => AS_OUT_EN_s,
RWn_OUT => RWn_OUT_s,
RW_OUT_EN => RW_OUT_EN_s,
UDS_OUTn => UDS_OUTn_s,
UDS_OUT_EN => UDS_OUT_EN_s,
LDS_OUTn => LDS_OUTn_s,
LDS_OUT_EN => LDS_OUT_EN_s,
-- Synchronous peripheral control:
E => E_s,
VMA_OUTn => VMA_OUTn_s,
VMA_OUT_EN => VMA_OUT_EN_s,
VPAn => VPAn_s,
-- Bus arbitration control:
BRn => BRn_s,
BGn => BGn_s,
BGACKn => BGACKn_s
);
end SYN;

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----------------------------------------------------------------------
---- ----
---- MC68000 compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- This model provides an opcode and bus timing compatible ip ----
---- core compared to Motorola's MC68000 microprocessor. ----
---- ----
---- This file contains the 68Ks address registers. ----
---- ----
---- ----
---- Description: ----
---- This file contains the 68K series data and address ----
---- registers, the user stack pointer (USP), the supervisor ----
---- stack pointer (SSP) and the 32-bit program counter (PC). ----
---- The required sign extensions for the INDEX and the DISPLACE- ----
---- ment are provided by this model. ----
---- ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, or (at your option) any later ----
---- version. ----
---- ----
---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, write to the Free ----
---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6B 2006/12/24 WF
-- Initial Release.
-- Revision 2K7A 2007/05/31 WF
-- Updated all modules.
-- Revision 2K7B 2007/12/24 WF
-- See the 68K00 top level file.
-- Revision 2K8A 2008/07/14 WF
-- See the 68K00 top level file.
--
use work.wf68k00ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity WF68K00IP_ADDRESS_REGISTERS is
port (
CLK : in bit;
RESETn : in bit;
-- Address and data:
DATA_IN : in std_logic_vector(15 downto 0); -- Extension word input.
ADATA_IN : in std_logic_vector(31 downto 0); -- Address register and USP, SSP and PC input.
REGSEL_B : in std_logic_vector(2 downto 0); -- Register number.
REGSEL_A : in std_logic_vector(2 downto 0); -- Register number.
ADR_REG_QB : out std_logic_vector(31 downto 0); -- Register selected by REGSEL_B.
ADR_REG_QA : out std_logic_vector(31 downto 0); -- Register selected by REGSEL_A.
USP_OUT : out std_logic_vector(31 downto 0); -- User stack pointer.
SSP_OUT : out std_logic_vector(31 downto 0); -- Supervisor stack pointer.
PC_OUT : out std_logic_vector(31 downto 0); -- Program counter.
-- Extension words:
EXWORD : in EXWORDTYPE;
DEST_EXWORD : in EXWORDTYPE;
-- Registers controls:
DR : in bit; -- Direction control.
USP_CPY : in bit; -- Copy among address registers.
AR_EXG : in bit; -- Exchange address register contents.
AR_WR : in bit; -- Address register write.
USP_INC : in bit; -- User stack pointer increment by 2.
USP_DEC : in bit; -- User stack pointer decrement by 2.
ADR_TMP_CLR : in bit; -- Temporary address offset clear.
ADR_TMP_INC : in bit; -- Address register increment temporarily.
AR_INC : in bit; -- Address register increment.
AR_DEC : in bit; -- Address register decrement.
SSP_INC : in bit; -- Supervisor stack pointer increment by 2.
SSP_DEC : in bit; -- Supervisor stack pointer decrement by 2.
SSP_INIT : in bit; -- Initialize SSP.
SP_ADD_DISPL : in bit; -- Forces the adding of the sign extended displacement to the SP.
USE_SP_ADR : in bit; -- Indicates the use of the stack (suer or supervisor).
USE_SSP_ADR : in bit; -- Indicates the use of the supervisor stack.
PC_WR : in bit; -- Program counter write.
PC_INC : in bit; -- Program counter increment.
PC_TMP_CLR : in bit; -- Clear temporary PC.
PC_TMP_INC : in bit; -- Increment temporary PC.
PC_INIT : in bit; -- Initialize the program counter.
PC_ADD_DISPL : in bit; -- Forces the adding of the sign extended displacement to the SP.
-- Misc controls:
SRC_DESTn : in bit; -- '1' for read operand from source, '0' store result to destination (MOVE).
SBIT : in bit; -- Superuser flag.
OP : in OP_68K00; -- the operations.
OP_SIZE : in OP_SIZETYPE; -- BYTE, WORD or LONG.
OP_MODE : in std_logic_vector(4 downto 0);
OP_START : in bit; -- Used for the MOVEM.
ADR_MODE : in std_logic_vector(2 downto 0); -- Address mode indicator.
MOVE_D_AM : in std_logic_vector(2 downto 0); -- Destination address mode for MOVE.
FORCE_BIW2 : in bit;
FORCE_BIW3 : in bit;
-- Displacement stuff:
EXT_DSIZE : in D_SIZETYPE;
SEL_DISPLACE_BIW : in bit;
DISPLACE_BIW : in std_logic_vector(31 downto 0); -- Displacement (8 or 16 bit).
-- Index and data register stuff:
REGSEL_INDEX : in std_logic_vector(2 downto 0); -- Index register address select.
INDEX_D_IN : in std_logic_vector(31 downto 0); -- Index from a data register.
-- Traps:
CHK_PC : in bit; -- Check program counter for TRAP_AERR.
CHK_ADR : in bit; -- Check effective address for TRAP_AERR.
TRAP_AERR : out bit; -- Address error indication.
-- Effective address (result of the address logic):
ADR_EFF : out std_logic_vector(31 downto 0) -- This is the effective address.
);
end entity WF68K00IP_ADDRESS_REGISTERS;
architecture BEHAVIOR of WF68K00IP_ADDRESS_REGISTERS is
type AR_TYPE is array(0 to 6) of std_logic_vector(31 downto 0);
signal AR : AR_TYPE; -- Address registers A0 to A6.
signal DATA_SIGNED : std_logic_vector(31 downto 0); -- Sign extended data.
signal USP : std_logic_vector(31 downto 0); -- User stack pointer (refers to A7 in the user mode.).
signal SSP : std_logic_vector(31 downto 0); -- Supervisor stack pointer (refers to A7' in the supervisor mode).
signal PC : std_logic_vector(31 downto 0); -- Program counter.
signal AREG_TMP : std_logic_vector(31 downto 0); -- Temporary address holding register.
signal ADR_MODE_I : std_logic_vector(2 downto 0);
signal DISPLACE : std_logic_vector(31 downto 0);
signal DISPL_EXT : std_logic_vector(31 downto 0);
signal I_D_A : bit;
signal I_W_L : bit;
signal I_SCALE : bit_vector(1 downto 0); -- Scale information for the index.
signal INDEX_SIGN : bit; -- Sign of the index.
signal INDEX_SCALED : std_logic_vector(31 downto 0);
signal ABS_ADDRESS : std_logic_vector(31 downto 0);
signal AR_NR_A : integer range 0 to 7;
signal AR_NR_B : integer range 0 to 7;
signal AR_NR_I : integer range 0 to 7;
signal ADR_EFF_I : std_logic_vector(31 downto 0);
signal ADR_TMP : std_logic_vector(5 downto 0);
signal PC_TMP : std_logic_vector(4 downto 0);
signal PC_OFFSET : std_logic_vector(3 downto 0); -- Used for PC relative addressing modes.
signal AR_STEP : std_logic_vector(2 downto 0);
begin
-- Address mode selector switch:
-- The default assignment is valid for source and destination access
-- regardless of the value of SRC_DESTn (e.g. ADD, ADDX).
ADR_MODE_I <= MOVE_D_AM when SRC_DESTn = '0' and OP = MOVE else ADR_MODE;
-- Address pointers:
AR_NR_A <= conv_integer(REGSEL_A);
AR_NR_B <= conv_integer(REGSEL_B);
AR_NR_I <= conv_integer(REGSEL_INDEX);
-- TRAP_AERR:
-- 1. If an operation is read from an odd adress.
-- 2. If the respective stack pointers in use are at an odd address.
-- 2. If there is a WORD oder LONG bus access at an odd address.
-- Note: Do not change the priority of these conditions!
TRAP_AERR <= '1' when CHK_PC = '1' and PC(0) = '1' else -- OP-Code at an odd address.
'1' when CHK_ADR = '1' and USE_SSP_ADR = '1' and SSP(0) = '1' else
'1' when CHK_ADR = '1' and USE_SP_ADR = '1' and SBIT = '1' and SSP(0) = '1' else
'1' when CHK_ADR = '1' and USE_SP_ADR = '1' and USP(0) = '1' else
'0' when CHK_ADR = '1' and (USE_SSP_ADR = '1' or USE_SP_ADR = '1') else -- Stack is correct.
-- MOVEP size is long or word but the acces is at byte boarders:
'1' when CHK_ADR = '1' and OP /= MOVEP and OP_SIZE = LONG and ADR_EFF_I(0) = '1' else -- LONG at an odd address.
'1' when CHK_ADR = '1' and OP /= MOVEP and OP_SIZE = WORD and ADR_EFF_I(0) = '1' else '0'; -- WORD at an odd address.
-- The address register increment and decrement values:
AR_STEP <= "100" when OP_SIZE = LONG else
"010" when OP_SIZE = WORD else
"010" when OP_SIZE = BYTE and AR_NR_B = 7 else "001";
-- Data outputs:
USP_OUT <= USP;
SSP_OUT <= SSP;
PC_OUT <= PC + PC_TMP; -- Plus offset.
ADR_REG_QA <= AREG_TMP when OP = MOVEM and ADR_MODE_I = "100" and REGSEL_A = REGSEL_B else -- See P_AREG_TMP, case A.
SSP when AR_NR_A = 7 and SBIT= '1' else -- Supervisor stack pointer.
USP when AR_NR_A = 7 and SBIT= '0' else -- User stack pointer.
AR(AR_NR_A);
ADR_REG_QB <= SSP when AR_NR_B = 7 and SBIT= '1' else -- Supervisor stack pointer.
USP when AR_NR_B = 7 and SBIT= '0' else -- User stack pointer.
AR(AR_NR_B);
P_AREG_TMP: process(RESETn, CLK)
-- This register holds a temporary copy of the desired address register
-- for the MOVEM operation. There are two special cases:
-- Case A: if the addressing register in the predecrement mode is
-- written to memory, the initial value (not decremented) is written out.
-- Case B: If the addressing register in the non postincrement
-- addressing mode is loaded from memory, the AREG_TMP holds the
-- old addressing register value until the end of the MOVEM.
begin
if RESETn = '0' then
AREG_TMP <= x"00000000";
elsif CLK = '1' and CLK' event then
if OP = MOVEM and OP_START = '1' then
case AR_NR_B is
when 7 =>
if SBIT= '1' then
AREG_TMP <= SSP;
else
AREG_TMP <= USP;
end if;
when others => AREG_TMP <= AR(AR_NR_B);
end case;
end if;
end if;
end process P_AREG_TMP;
SRC_SIGNEXT: process(OP, OP_SIZE, ADATA_IN, ADR_EFF_I)
-- The MOVEA and MOVEM require a sign extended source data
-- which is provided by this logic. The BYTE size is not
-- allowed for these operations and not taken into account.
begin
if (OP = MOVEA or OP = MOVEM) and OP_SIZE = WORD then
for i in 31 downto 16 loop
DATA_SIGNED(i) <= ADATA_IN(15);
end loop;
DATA_SIGNED(15 downto 0) <= ADATA_IN(15 downto 0);
elsif OP = JMP or OP = JSR or OP = LEA then
DATA_SIGNED <= ADR_EFF_I;
else
DATA_SIGNED <= ADATA_IN;
end if;
end process SRC_SIGNEXT;
I_D_A <= '1' when EXWORD(0)(15) = '1' and SRC_DESTn = '1' else
'1' when DEST_EXWORD(0)(15) = '1' and SRC_DESTn = '0' else '0';
I_W_L <= '1' when EXWORD(0)(11) = '1' and SRC_DESTn = '1' else
'1' when DEST_EXWORD(0)(11) = '1' and SRC_DESTn = '0' else '0';
-- The SCALE is not implemented in the original 68000. Nevertheless, the SCALE
-- is foreseen in this core because the OPCODE compatibility is given.
I_SCALE <= To_BitVector(EXWORD(0)(10 downto 9)) when SRC_DESTn = '1' else
To_BitVector(DEST_EXWORD(0)(10 downto 9));
-- The absolute address is valid for the absolute address modes 'WORD' and 'LONG'.
-- The sign extension is provided in the address mode process.
ABS_ADDRESS <= x"0000" & EXWORD(0) when ADR_MODE_I = "111" and REGSEL_B = "000" and SRC_DESTn = '1' else
x"0000" & DEST_EXWORD(0) when ADR_MODE_I = "111" and REGSEL_B = "000" and SRC_DESTn = '0' else
EXWORD(0) & EXWORD(1) when SRC_DESTn = '1' else DEST_EXWORD(0) & DEST_EXWORD(1);
EXTEND_INDEX: process(AR_NR_I, I_D_A, I_W_L, AR, INDEX_D_IN, I_SCALE)
-- This process selects the INDEX from one of the data
-- registers or from one of the address registers. Further-
-- more the index needs to be sign extended from 8 bit to 32
-- bit or from 16 bit to 32 bit dependent on the address mode.
-- In case of a long word operation, no extension is required.
-- The index is multiplied by 1, 2, 4 or 8. The ADR_EFF is the
-- scaled index for the address calculation.
variable INDEX : std_logic_vector(31 downto 0);
variable INDEX_EXT : std_logic_vector(31 downto 0);
begin
if I_D_A = '1' then
INDEX := AR(AR_NR_I);
else
INDEX := INDEX_D_IN;
end if;
case I_W_L is
when '0' => -- Sign extended word.
for i in 31 downto 16 loop
INDEX_EXT(i) := INDEX(15);
end loop;
INDEX_EXT(15 downto 0) := INDEX(15 downto 0);
when '1' => -- Long word.
INDEX_EXT := INDEX;
end case;
case I_SCALE is
when "00" => INDEX_SCALED <= INDEX_EXT; -- Multiple by 1.
when "01" => INDEX_SCALED <= INDEX_EXT(31 downto 1) & '0'; -- Multiple by 2.
when "10" => INDEX_SCALED <= INDEX_EXT(31 downto 2) & "00"; -- Multiple by 4.
when "11" => INDEX_SCALED <= INDEX_EXT(31 downto 3) & "000"; -- Multiple by 8.
end case;
end process EXTEND_INDEX;
-- Displacement multiplexer:
DISPLACE <= DISPLACE_BIW when SEL_DISPLACE_BIW = '1' else
x"0000" & EXWORD(0) when EXT_DSIZE = WORD and SRC_DESTn = '1' else
x"000000" & EXWORD(0)(7 downto 0) when EXT_DSIZE = BYTE and SRC_DESTn = '1' else
x"0000" & DEST_EXWORD(0) when EXT_DSIZE = WORD else
x"000000" & DEST_EXWORD(0)(7 downto 0);
EXTEND_DISPLACEMENT: process(DISPLACE, EXT_DSIZE)
-- The displacement needs to be sign extended from 8 bit to 32, from 16 bit to 32 bit or
-- not extended dependent on the address mode.
begin
case EXT_DSIZE is
when BYTE => -- 8 bit wide displacement.
for i in 31 downto 8 loop
DISPL_EXT(i) <= DISPLACE(7);
end loop;
DISPL_EXT(7 downto 0) <= DISPLACE(7 downto 0);
when WORD => -- 16 bit wide displacement.
for i in 31 downto 16 loop
DISPL_EXT(i) <= DISPLACE(15);
end loop;
DISPL_EXT(15 downto 0) <= DISPLACE(15 downto 0);
when LONG =>
DISPL_EXT <= DISPLACE;
end case;
end process EXTEND_DISPLACEMENT;
P_ADR_TMP: process(RESETn, CLK)
-- This process provides a temporary address offset during
-- bus access over several bytes. The 6 bits are used for
-- the MOVEM command in the non postincrement /predecrement mode.
-- Other commands requires a maximum of
-- 3 bits.
begin
if RESETn = '0' then
ADR_TMP <= "000000";
elsif CLK = '1' and CLK' event then
if ADR_TMP_CLR = '1' then
ADR_TMP <= "000000";
elsif ADR_TMP_INC = '1' and OP_SIZE = BYTE then
ADR_TMP <= ADR_TMP + "01";
elsif ADR_TMP_INC = '1' then
ADR_TMP <= ADR_TMP + "10";
end if;
end if;
end process P_ADR_TMP;
P_PC_TMP: process(RESETn, CLK)
-- This process provides a temporary program counter offset
-- during the 'fetch phase'.
variable PC_TMPVAR : std_logic_vector(3 downto 0);
begin
if RESETn = '0' then
PC_TMPVAR := x"0";
elsif CLK = '1' and CLK' event then
if PC_INC = '1' or PC_TMP_CLR = '1' then
PC_TMPVAR := x"0";
elsif PC_TMP_INC = '1' then
PC_TMPVAR := PC_TMPVAR + '1';
end if;
end if;
PC_TMP <= PC_TMPVAR & "0"; -- Increment always by two.
end process P_PC_TMP;
PC_OFFSET <= x"6" when FORCE_BIW3 = '1' and FORCE_BIW2 = '1' else
x"4" when FORCE_BIW2 = '1' else x"2";
ADDRESS_MODES: process(ADR_MODE_I, REGSEL_B, AR, AR_NR_B, SBIT, USP, SSP, DISPL_EXT, AREG_TMP,
ADR_TMP, OP, INDEX_SCALED, ABS_ADDRESS, PC, PC_OFFSET, ADR_EFF_I, DR)
-- The effective address calculation takes place in this process depending on the
-- chosen addressing mode.
variable ADR_EFF_TMP : std_logic_vector(31 downto 0);
variable AREG : std_logic_vector(31 downto 0);
begin
if OP = MOVEM and (ADR_MODE_I = "010" or ADR_MODE_I = "101" or ADR_MODE_I = "110") and DR = '1' then
AREG := AREG_TMP; -- See P_AREG_TMP, case B.
else
case AR_NR_B is
when 7 =>
if SBIT= '1' then
AREG := SSP;
else
AREG := USP;
end if;
when others => AREG := AR(AR_NR_B);
end case;
end if;
--
case ADR_MODE_I is
-- when "000" | "001" => Direct address modes: no effective address required.
when "010" | "011" | "100" =>
-- x"2": Address register indirect mode. Assembler syntax: (An).
-- x"3": Address register indirect with postincrement mode. Assembler syntax: (An)+.
-- x"4": Address register indirect with predecrement mode. Assembler syntax: -(An).
-- x"2": The ADR_EFF is the pointer to the operand.
-- x"3": The ADR_EFF is the pointer to the operand.
-- x"4": The ADR_EFF is the pointer to the operand.
ADR_EFF_TMP := AREG;
when "101" => -- Address register indirect with offset. Assembler syntax: (d16,An).
ADR_EFF_TMP := AREG + DISPL_EXT;
when "110" =>
-- The ADR_EFF is the pointer to the operand.
-- Assembler syntax: (d8,An,Xn.SIZE*SCALE).
ADR_EFF_TMP := AREG + DISPL_EXT + INDEX_SCALED;
when "111" =>
case REGSEL_B is
when "000" => -- Absolute short addressing mode.
-- Assembler syntax: (xxx).W
-- The ADR_EFF is the pointer to the operand.
for i in 31 downto 16 loop
ADR_EFF_TMP(i) := ABS_ADDRESS(15); -- Sign extension.
end loop;
ADR_EFF_TMP(15 downto 0) := ABS_ADDRESS(15 downto 0);
when "001" => -- Absolute long addressing mode.
-- Assembler syntax: (xxx).L
-- The ADR_EFF is the pointer to the operand.
ADR_EFF_TMP := ABS_ADDRESS;
when "010" => -- Program counter relative with offset.
-- Assembler syntax: (d16,PC).
-- The effective address during PC relative addressing
-- contains the PC offset plus two.
ADR_EFF_TMP := PC + PC_OFFSET + DISPL_EXT;
when "011" => -- Program counter relative with index and offset.
-- Assembler syntax: (d8,PC,Xn.SIZE*SCALE).
-- The effective address during PC relative addressing
-- contains the PC offset plus two.
ADR_EFF_TMP := PC + PC_OFFSET + DISPL_EXT + INDEX_SCALED;
when others =>
ADR_EFF_TMP := (others => '-'); -- Don't care, not used dummy.
end case;
when others =>
ADR_EFF_TMP := (others => '-'); -- Result not required.
end case;
ADR_EFF_I <= ADR_EFF_TMP;
-- Copy of the effective address plus offsets:
ADR_EFF <= ADR_EFF_I + ADR_TMP;
end process ADDRESS_MODES;
REG_WR_MODIFY: process(RESETn, CLK, OP, AR_NR_A, AR_NR_B)
-- This process provides data transfer to the respective registers (write).
-- Affected are the address registers (AR), the supervisor stack pointer (SSP),
-- the user stack pointer (USP) and the program counter (PC).
begin
--
if RESETn = '0' then
for i in 0 to 6 loop
AR(i) <= (others => '0');
end loop;
USP <= (others => '0');
SSP <= (others => '0');
PC <= (others => '0');
elsif CLK = '1' and CLK' event then
-- Write operations are always long:
if AR_WR = '1' then
if AR_NR_A < 7 then
AR(AR_NR_A) <= DATA_SIGNED; -- Load AREG.
elsif SBIT = '1' then
SSP <= DATA_SIGNED; -- Load SSP.
else
USP <= DATA_SIGNED; -- Load USP.
end if;
end if;
-- Predecrement and postincrement:
if AR_INC = '1' and AR_NR_B < 7 then
AR(AR_NR_B) <= AR(AR_NR_B) + AR_STEP;
elsif AR_INC = '1' and SBIT= '1' then
SSP <= SSP + AR_STEP;
elsif AR_INC = '1' then
USP <= USP + AR_STEP;
elsif AR_DEC = '1' and AR_NR_B < 7 then
AR(AR_NR_B) <= AR(AR_NR_B) - AR_STEP;
elsif AR_DEC = '1' and SBIT= '1' then
SSP <= SSP - AR_STEP;
elsif AR_DEC = '1' then
USP <= USP - AR_STEP;
end if;
-- Increment / decrement the stack:
if USP_INC = '1' then
USP <= USP + "10"; -- Increment 2 bytes.
elsif USP_DEC = '1' then
USP <= USP - "10"; -- Decrement 2 bytes.
elsif SSP_INIT = '1' then
SSP <= ADATA_IN;
elsif SSP_INC = '1' then
SSP <= SSP + "10"; -- Increment 2 bytes.
elsif SSP_DEC = '1' then
SSP <= SSP - "10"; -- Decrement 2 bytes.
end if;
-- Displacement operations (concurrent to AR_WR..., see LINK).
if SP_ADD_DISPL = '1' and SBIT = '1' then
SSP <= SSP + DISPL_EXT; -- Used for LINK.
elsif SP_ADD_DISPL = '1' then
USP <= USP + DISPL_EXT; -- Used for LINK.
end if;
-- Exchange the content of address registers:
if AR_EXG = '1' and OP_MODE = "01001" then -- Exchange two address registers.
AR(AR_NR_B) <= AR(AR_NR_A); -- Internal wired because there is no second data input.
AR(AR_NR_A) <= ADATA_IN;
elsif AR_EXG = '1' and OP_MODE = "10001" then -- Exchange a data and an address register.
AR(AR_NR_B) <= ADATA_IN;
end if;
-- Address Register copies:
if USP_CPY = '1' and DR = '0' then -- Copy the address register to user stack pointer.
if AR_NR_B < 7 then
USP <= AR(AR_NR_B);
elsif SBIT = '1' then
USP <= SSP;
end if;
elsif USP_CPY = '1' then -- Copy the user stack pointer to the address register.
if AR_NR_B < 7 then
AR(AR_NR_B) <= USP;
elsif SBIT = '1' then
SSP <= USP;
end if;
end if;
-- Program counter arithmetics:
if PC_WR = '1' then -- JMP, JSR.
PC <= DATA_SIGNED;
elsif PC_INIT = '1' then
PC <= ADATA_IN;
-- The PC_ADD_DISPL and the PC_INC are asserted simultaneously when the
-- operation is used for Bcc and BRA. Therefore the prioritization of
-- PC_ADD_DISPL over PC_INC is important.
-- When PC_INC is active, the program counter is increased by the
-- value of PC_TMP plus two when the following execution state after
-- a fetch phase is FETCH_BIW_1.
elsif PC_ADD_DISPL = '1' then -- Used for Bcc, BRA, BSR, DBcc.
PC <= PC + DISPL_EXT + "10";
elsif PC_INC = '1' then
PC <= PC + PC_TMP + "10";
end if;
end if;
end process REG_WR_MODIFY;
end BEHAVIOR;

850
common/CPU/68000/wf_68k00_ip/wf68k00ip_alu.vhd Normal file
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@@ -0,0 +1,850 @@
----------------------------------------------------------------------
---- ----
---- MC68000 compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- This model provides an opcode and bus timing compatible ip ----
---- core compared to Motorola's MC68000 microprocessor. ----
---- ----
---- This file contains the arithmetic logic unit (ALU). ----
---- ----
---- ----
---- Description: ----
---- Arithmetic Logic Unit performs the arithmetic and logic ----
---- operations during execution of an instruction. It contains ----
---- the accumulator and related logic such as arithmetic unit, ----
---- logic unit, multiplier and divider. BCD operation are exe- ----
---- cuted in this unit and condition code flags (N-negative, ----
---- Z-zero, C-carry V-overflow) for most instructions. ----
---- For a proper operation, the ALU requires sign extended ----
---- operands OP_IN_S, OP_IN_D_LO and OP_IN_D_HI. In case of the ----
---- OP_IN_D_HI a sign extension is required for the long ----
---- (DIVL) only. ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, or (at your option) any later ----
---- version. ----
---- ----
---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, write to the Free ----
---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6B 2006/12/24 WF
-- Initial Release.
-- Revision 2K7A 2007/05/31 WF
-- Updated all modules.
-- Revision 2K7B 2007/12/24 WF
-- See the 68K00 top level file.
-- Revision 2K8A 2008/07/14 WF
-- See the 68K00 top level file.
--
use work.WF68K00IP_PKG.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity WF68K00IP_ALU is
port (
RESETn : in bit;
CLK : in bit;
ADR_MODE : in std_logic_vector(2 downto 0);
OP_SIZE : in OP_SIZETYPE;
OP : in OP_68K00;
-- The Flags:
XNZVC_IN : in std_logic_vector(4 downto 0);
XNZVC_OUT : out std_logic_vector(4 downto 0);
-- Operands and result:
OP_IN_S : in std_logic_vector(31 downto 0);
OP_IN_D_HI : in std_logic_vector(31 downto 0);
OP_IN_D_LO : in std_logic_vector(31 downto 0);
RESULT_HI : out std_logic_vector(31 downto 0);
RESULT_LO : out std_logic_vector(31 downto 0);
-- Status and Control:
OP_START : in bit; -- 1 CLK cycle.
TRAP_CHK_EN : in bit; -- 1 CLK cycle.
DIV_MUL_32n64 : in bit; -- 1 for 64 bit long MUL or DIV, 0 for 32 bit long MUL or DIV.
OP_BUSY : out bit;
TRAP_CHK : out bit; -- Trap due to the CHK instruction.
TRAP_DIVZERO : out bit -- Trap due to divide by zero.
);
end entity WF68K00IP_ALU;
architecture BEHAVIOR of WF68K00IP_ALU is
type MUL_STATES is (MUL_IDLE, MUL_ADD, MUL_VERIFY_SHIFT);
type DIV_STATES is (DIV_IDLE, DIV_VERIFY, DIV_ADDSUB, DIV_SIGN);
signal MUL_STATE : MUL_STATES;
signal NEXT_MUL_STATE : MUL_STATES;
signal DIV_STATE : DIV_STATES;
signal NEXT_DIV_STATE : DIV_STATES;
signal OP_IN_S_SIGN : std_logic_vector(31 downto 0);
signal OP_IN_D_SIGN_LO : std_logic_vector(31 downto 0);
signal RESULT_LOGOP : std_logic_vector(31 downto 0);
signal RESULT_BCD : std_logic_vector(7 downto 0);
signal RESULT_INTOP : std_logic_vector(31 downto 0);
signal RESULT_SPECIAL : std_logic_vector(31 downto 0);
signal RESULT_I_DIV : std_logic_vector(31 downto 0);
signal RESULT_I : std_logic_vector(31 downto 0);
signal RESULT_II : std_logic_vector(32 downto 0);
signal DIVISOR : std_logic_vector(63 downto 0);
signal DIVIDEND : std_logic_vector(63 downto 0);
signal CB_BCD : std_logic;
signal OV_DIV : std_logic;
signal MUL_CYC_CNT : unsigned(5 downto 0);
signal OP_MUL : bit;
signal OP_DIV : bit;
signal MUL_DIV_OP_S : std_logic_vector(31 downto 0);
signal MUL_OP_D : std_logic_vector(31 downto 0);
signal DIV_VAR : std_logic_vector(31 downto 0);
signal DIV_OLD_MSB : std_logic;
signal DIV_SHIFT_EN : bit;
begin
OP_BUSY <= OP_MUL or OP_DIV;
-- Result multiplexers:
with OP select
RESULT_HI <= RESULT_II(31 downto 0) when DIVS | DIVU | MULS | MULU, x"00000000" when others;
with OP select
RESULT_LO <= RESULT_LOGOP when AND_B | ANDI | ANDI_TO_CCR | ANDI_TO_SR | EOR | EORI | EORI_TO_CCR,
RESULT_LOGOP when EORI_TO_SR | NOT_B | OR_B | ORI | ORI_TO_CCR | ORI_TO_SR,
RESULT_INTOP when ADD | ADDA | ADDI | ADDQ | ADDX | CLR | CMP | CMPA | CMPI | CMPM,
RESULT_INTOP when NEG | NEGX | SUB | SUBA | SUBI | SUBQ | SUBX,
RESULT_SPECIAL when EXTW | SWAP | TAS,
x"000000" & RESULT_BCD when ABCD | NBCD | SBCD, -- Byte only.
RESULT_I_DIV when DIVS | DIVU,
RESULT_I when MULS | MULU,
OP_IN_S when others; -- Default for CHK, MOVE, MOVEQ.
-- Use low bytes of RESULT_II and RESULT_I for word wide DIVS, DIVU:
RESULT_I_DIV <= RESULT_II(15 downto 0) & RESULT_I(15 downto 0) when OP_SIZE = WORD else RESULT_I;
SIGNEXT: process(OP, OP_IN_S, OP_IN_D_LO, OP_SIZE)
-- This module provides the required sign extensions.
begin
case OP_SIZE is
when LONG =>
OP_IN_S_SIGN <= OP_IN_S;
OP_IN_D_SIGN_LO <= OP_IN_D_LO;
when WORD =>
for i in 31 downto 16 loop
OP_IN_S_SIGN(i) <= OP_IN_S(15);
OP_IN_D_SIGN_LO(i) <= OP_IN_D_LO(15);
end loop;
OP_IN_S_SIGN(15 downto 0) <= OP_IN_S(15 downto 0);
OP_IN_D_SIGN_LO(15 downto 0) <= OP_IN_D_LO(15 downto 0);
when BYTE =>
for i in 31 downto 8 loop
OP_IN_S_SIGN(i) <= OP_IN_S(7);
OP_IN_D_SIGN_LO(i) <= OP_IN_D_LO(7);
end loop;
OP_IN_S_SIGN(7 downto 0) <= OP_IN_S(7 downto 0);
OP_IN_D_SIGN_LO(7 downto 0) <= OP_IN_D_LO(7 downto 0);
end case;
end process SIGNEXT;
TRAP_CHK <= '1' when TRAP_CHK_EN = '1' and OP_IN_D_SIGN_LO(31) = '1' else -- Negative destination.
'1' when TRAP_CHK_EN = '1' and RESULT_INTOP(31) = '0' else '0'; -- Destination > Source.
TRAP_DIVZERO <= '1' when OP = DIVU and DIV_STATE = DIV_IDLE and OP_START = '1' and OP_IN_S = x"00000000" else
'1' when OP = DIVS and DIV_STATE = DIV_IDLE and OP_START = '1' and OP_IN_S = x"00000000" else '0';
P_LOGOP: process(OP, OP_IN_S, OP_IN_D_LO)
-- This process provides the logic operations:
-- AND, OR, XOR and NOT.
-- The logic operations require no signed / unsigned
-- modelling.
begin
case OP is
when AND_B | ANDI | ANDI_TO_CCR | ANDI_TO_SR =>
RESULT_LOGOP <= OP_IN_S and OP_IN_D_LO;
when OR_B | ORI | ORI_TO_CCR | ORI_TO_SR =>
RESULT_LOGOP <= OP_IN_S or OP_IN_D_LO;
when EOR | EORI | EORI_TO_CCR | EORI_TO_SR =>
RESULT_LOGOP <= OP_IN_S xor OP_IN_D_LO;
when NOT_B =>
RESULT_LOGOP <= not OP_IN_D_LO;
when MOVE =>
RESULT_LOGOP <= OP_IN_S; -- Used for MOVE.
when others =>
RESULT_LOGOP <= OP_IN_D_LO; -- Used for TST.
end case;
end process P_LOGOP;
P_INTOP: process(OP, OP_IN_S, OP_IN_S_SIGN, OP_IN_D_LO, OP_IN_D_SIGN_LO, ADR_MODE, XNZVC_IN, OP_SIZE, RESULT_INTOP)
-- The integer arithmetics ADD, SUB, NEG and CMP in their different variations are modelled here.
variable X_IN_I : Std_Logic_Vector(0 downto 0);
variable RESULT : unsigned(31 downto 0);
begin
X_IN_I(0) := XNZVC_IN(4); -- Extended Flag.
case OP is
when ADDA =>
RESULT := unsigned(OP_IN_D_LO) + unsigned(OP_IN_S_SIGN); -- No sign extension for the destination.
when ADDQ =>
case ADR_MODE is
when "001" => RESULT := unsigned(OP_IN_D_LO) + unsigned(OP_IN_S_SIGN); -- No sign extension for address destination.
when others => RESULT := unsigned(OP_IN_D_SIGN_LO) + unsigned(OP_IN_S_SIGN);
end case;
when ADD | ADDI =>
RESULT := unsigned(OP_IN_D_SIGN_LO) + unsigned(OP_IN_S_SIGN);
when ADDX =>
RESULT := unsigned(OP_IN_D_SIGN_LO) + unsigned(OP_IN_S_SIGN) + unsigned(X_IN_I);
when CMPA | SUBA =>
RESULT := unsigned(OP_IN_D_LO) - unsigned(OP_IN_S_SIGN); -- No sign extension for the destination.
when SUBQ =>
case ADR_MODE is
when "001" => RESULT := unsigned(OP_IN_D_LO) - unsigned(OP_IN_S_SIGN); -- No sign extension for address destination.
when others => RESULT := unsigned(OP_IN_D_SIGN_LO) - unsigned(OP_IN_S_SIGN);
end case;
when CHK | CMP | CMPI | CMPM | SUB | SUBI =>
RESULT := unsigned(OP_IN_D_SIGN_LO) - unsigned(OP_IN_S_SIGN);
when SUBX =>
RESULT := unsigned(OP_IN_D_SIGN_LO) - unsigned(OP_IN_S_SIGN) - unsigned(X_IN_I);
when NEG =>
RESULT := unsigned(OP_IN_S_SIGN) - unsigned(OP_IN_D_SIGN_LO);
when NEGX =>
RESULT := unsigned(OP_IN_S_SIGN) - unsigned(OP_IN_D_SIGN_LO) - unsigned(X_IN_I);
when CLR =>
RESULT := (others => '0');
when others =>
RESULT := (others => '0'); -- Don't care.
end case;
RESULT_INTOP <= std_logic_vector(RESULT);
end process P_INTOP;
P_SPECIAL: process(OP, OP_IN_S, OP_IN_D_LO, OP_SIZE, RESULT_INTOP)
-- This process provides the calculation for special operations.
variable RESULT : unsigned(31 downto 0);
begin
case OP is
when EXTW =>
case OP_SIZE is
when LONG =>
for i in 31 downto 16 loop
RESULT(i) := OP_IN_S(15);
end loop;
RESULT(15 downto 0) := unsigned(OP_IN_S(15 downto 0));
when others => -- Word.
for i in 15 downto 8 loop
RESULT(i) := OP_IN_S(7);
end loop;
RESULT(31 downto 16) := unsigned(OP_IN_S(31 downto 16));
RESULT(7 downto 0) := unsigned(OP_IN_S(7 downto 0));
end case;
when SWAP =>
RESULT := unsigned(OP_IN_S(15 downto 0)) & unsigned(OP_IN_S(31 downto 16));
when TAS =>
RESULT := x"000000" & '1' & unsigned(OP_IN_D_LO(6 downto 0)); -- Set the MSB.
when others =>
RESULT := (others => '0'); -- Don't care.
end case;
RESULT_SPECIAL <= std_logic_vector(RESULT);
end process P_SPECIAL;
P_BCDOP: process(OP, XNZVC_IN, OP_IN_S, OP_IN_D_LO)
-- The BCD operations are all byte wide and unsigned.
variable X_IN_I : unsigned(0 downto 0);
variable TEMP0 : unsigned(4 downto 0);
variable TEMP1 : unsigned(4 downto 0);
variable Z_0 : unsigned(3 downto 0);
variable C_0 : unsigned(0 downto 0);
variable Z_1 : unsigned(3 downto 0);
variable C_1 : std_logic;
variable S_0 : unsigned(3 downto 0);
variable S_1 : unsigned(3 downto 0);
begin
X_IN_I(0) := XNZVC_IN(4); -- Inverted extended Flag.
case OP is
when ABCD =>
TEMP0 := unsigned('0' & OP_IN_D_LO(3 downto 0)) + unsigned('0' & OP_IN_S(3 downto 0)) + ("0000" & X_IN_I);
TEMP1 := unsigned('0' & OP_IN_D_LO(7 downto 4)) + unsigned('0' & OP_IN_S(7 downto 4)) + ("0000" & C_0);
when NBCD =>
TEMP0 := "00000" - unsigned('0' & OP_IN_D_LO(3 downto 0)) - ("0000" & X_IN_I);
TEMP1 := "00000" - unsigned('0' & OP_IN_D_LO(7 downto 4)) - ("0000" & C_0);
when others => -- Valid for SBCD.
TEMP0 := unsigned('0' & OP_IN_D_LO(3 downto 0)) - unsigned('0' & OP_IN_S(3 downto 0)) - ("0000" & X_IN_I);
TEMP1 := unsigned('0' & OP_IN_D_LO(7 downto 4)) - unsigned('0' & OP_IN_S(7 downto 4)) - ("0000" & C_0);
end case;
if std_logic_vector(TEMP0) > "01001" then
Z_0 := "0110";
C_0 := "1";
else
Z_0 := "0000";
C_0 := "0";
end if;
if std_logic_vector(TEMP1) > "01001" then
Z_1 := "0110";
C_1 := '1';
else
Z_1 := "0000";
C_1 := '0';
end if;
case OP is
when ABCD =>
S_1 := TEMP1(3 downto 0) + Z_1;
S_0 := TEMP0(3 downto 0) + Z_0;
when others => -- Valid for SBCD, NBCD.
S_1 := TEMP1(3 downto 0) - Z_1;
S_0 := TEMP0(3 downto 0) - Z_0;
end case;
--
CB_BCD <= C_1;
RESULT_BCD(7 downto 4) <= std_logic_vector(S_1);
RESULT_BCD(3 downto 0) <= std_logic_vector(S_0);
end process P_BCDOP;
COND_CODES: process(OP, RESULT_BCD, CB_BCD, RESULT_LOGOP, RESULT_INTOP, OP_SIZE, XNZVC_IN, RESULT_SPECIAL,
OP_IN_D_SIGN_LO, OP_IN_S_SIGN, RESULT_I, RESULT_II, MUL_STATE, DIV_MUL_32n64, OV_DIV)
-- In this process all the condition codes X (eXtended), N (Negative)
-- Z (Zero), V (oVerflow) and C (Carry / borrow) are calculated for
-- all integer operations. Except for the MULS, MULU, DIVS, DIVU the
-- new conditions are valid one clock cycle after the operation starts.
-- For the multiplication and the division, the codes are valid after
-- BUSY is released.
-- Although MOVE, MOVEQ and CHK does not require any data processing by the ALU,
-- the condition codes are computated here.
variable Z, RM, SM, DM : std_logic;
begin
-- Concerning Z,V,C Flags:
case OP is
when ADD | ADDI | ADDQ | ADDX | CMP | CMPA | CMPI | CMPM | NEG | NEGX | SUB | SUBI | SUBQ | SUBX =>
RM := RESULT_INTOP(31);
SM := OP_IN_S_SIGN(31);
DM := OP_IN_D_SIGN_LO(31);
when others =>
RM := '-'; SM := '-'; DM := '-';
end case;
-- Concerning Z Flag:
case OP is
when ADD | ADDI | ADDQ | ADDX | CMP | CMPA | CMPI | CMPM | NEG | NEGX | SUB | SUBI | SUBQ | SUBX =>
if RESULT_INTOP = x"00000000" then
Z := '1';
else
Z := '0';
end if;
when others =>
Z := '0';
end case;
--
case OP is
when ABCD | NBCD | SBCD =>
if RESULT_BCD = x"00" then -- N and V are undefined, don't care.
XNZVC_OUT <= CB_BCD & '-' & XNZVC_IN(2) & '-' & CB_BCD;
else
XNZVC_OUT <= CB_BCD & '-' & '0' & '-' & CB_BCD;
end if;
when ADD | ADDI | ADDQ | ADDX =>
if Z = '1' then
if OP = ADDX then
XNZVC_OUT(3 downto 2) <= '0' & XNZVC_IN(2);
else
XNZVC_OUT(3 downto 2) <= "01";
end if;
else
XNZVC_OUT(3 downto 2) <= RM & '0';
end if;
--
case To_Bit(RM) & To_Bit(SM) & To_Bit(DM) is
when "011" => XNZVC_OUT(1) <= '1';
when "100" => XNZVC_OUT(1) <= '1';
when others => XNZVC_OUT(1) <= '0';
end case;
if (SM = '1' and DM = '1') or (RM = '0' and SM = '1') or (RM = '0' and DM = '1') then
XNZVC_OUT(4) <= '1'; XNZVC_OUT(0) <= '1';
else
XNZVC_OUT(4) <= '0'; XNZVC_OUT(0) <= '0';
end if;
when CLR =>
XNZVC_OUT <= XNZVC_IN(4) & "0100";
when SUB | SUBI | SUBQ | SUBX =>
if Z = '1' then
if OP = SUBX then
XNZVC_OUT(3 downto 2) <= '0' & XNZVC_IN(2);
else
XNZVC_OUT(3 downto 2) <= "01";
end if;
else
XNZVC_OUT(3 downto 2) <= RM & '0';
end if;
--
case To_Bit(RM) & To_Bit(SM) & To_Bit(DM) is
when "001" => XNZVC_OUT(1) <= '1';
when "110" => XNZVC_OUT(1) <= '1';
when others => XNZVC_OUT(1) <= '0';
end case;
if (SM = '1' and DM = '0') or (RM = '1' and SM = '1') or (RM = '1' and DM = '0') then
XNZVC_OUT(4) <= '1'; XNZVC_OUT(0) <= '1';
else
XNZVC_OUT(4) <= '0'; XNZVC_OUT(0) <= '0';
end if;
when CMP | CMPA | CMPI | CMPM =>
XNZVC_OUT(4) <= XNZVC_IN(4);
if Z = '1' then
XNZVC_OUT(3 downto 2) <= "01";
else
XNZVC_OUT(3 downto 2) <= RM & '0';
end if;
--
case To_Bit(RM) & To_Bit(SM) & To_Bit(DM) is
when "001" => XNZVC_OUT(1) <= '1';
when "110" => XNZVC_OUT(1) <= '1';
when others => XNZVC_OUT(1) <= '0';
end case;
if (SM = '1' and DM = '0') or (RM = '1' and SM = '1') or (RM = '1' and DM = '0') then
XNZVC_OUT(0) <= '1';
else
XNZVC_OUT(0) <= '0';
end if;
when NEG | NEGX =>
if Z = '1' then
if OP = NEGX then
XNZVC_OUT(3 downto 2) <= '0' & XNZVC_IN(2);
else
XNZVC_OUT(3 downto 2) <= "01";
end if;
else
XNZVC_OUT(3 downto 2) <= RM & '0';
end if;
XNZVC_OUT(4) <= DM or RM;
XNZVC_OUT(1) <= DM and RM;
XNZVC_OUT(0) <= DM or RM;
when AND_B | ANDI | EOR | EORI | OR_B | ORI | MOVE | NOT_B | TST =>
case OP_SIZE is
when LONG =>
if RESULT_LOGOP = x"00000000" then
XNZVC_OUT <= XNZVC_IN(4) & "0100";
else
XNZVC_OUT <= XNZVC_IN(4) & RESULT_LOGOP(31) &"000";
end if;
when WORD =>
if RESULT_LOGOP(15 downto 0) = x"0000" then
XNZVC_OUT <= XNZVC_IN(4) & "0100";
else
XNZVC_OUT <= XNZVC_IN(4) & RESULT_LOGOP(15) &"000";
end if;
when others => -- Byte.
if RESULT_LOGOP(7 downto 0) = x"00" then
XNZVC_OUT <= XNZVC_IN(4) & "0100";
else
XNZVC_OUT <= XNZVC_IN(4) & RESULT_LOGOP(7) &"000";
end if;
end case;
-- The ANDI_TO_CCR, ANDI_TO_SR, EORI_TO_CCR, EORI_TO_SR, ORI_TO_CCR, ORI_TO_SR
-- are determined in the LOGOP process.
when CHK =>
if OP_IN_D_SIGN_LO(31) = '1' then
XNZVC_OUT <= XNZVC_IN(4) & '1' & "---";
elsif RESULT_INTOP(31) = '0' then
XNZVC_OUT <= XNZVC_IN(4) & '0' & "---";
else
XNZVC_OUT <= XNZVC_IN(4 downto 3) & "---";
end if;
when DIVS | DIVU =>
if OP_SIZE = WORD and RESULT_I(15) = '1' then
XNZVC_OUT <= XNZVC_IN(4) & '1' & '0' & OV_DIV & '0'; -- Negative number.
elsif RESULT_I(31) = '1' then
XNZVC_OUT <= XNZVC_IN(4) & '1' & '0' & OV_DIV & '0'; -- Negative number.
elsif RESULT_I = x"00000000" then
XNZVC_OUT <= XNZVC_IN(4) & '0' & '1' & OV_DIV & '0'; -- Zero.
else
XNZVC_OUT <= XNZVC_IN(4) & '0' & '0' & OV_DIV & '0';
end if;
when EXTW =>
case OP_SIZE is
when LONG =>
if RESULT_SPECIAL = x"00000000" then
XNZVC_OUT <= XNZVC_IN(4) & "0100";
else
XNZVC_OUT <= XNZVC_IN(4) & RESULT_SPECIAL(31) & "000";
end if;
when others => -- Word.
if RESULT_SPECIAL(15 downto 0) = x"0000" then
XNZVC_OUT <= XNZVC_IN(4) & "0100";
else
XNZVC_OUT <= XNZVC_IN(4) & RESULT_SPECIAL(15) & "000";
end if;
end case;
when MOVEQ =>
if OP_IN_S_SIGN(7 downto 0) = x"00" then
XNZVC_OUT <= XNZVC_IN(4) & "0100";
else
XNZVC_OUT <= XNZVC_IN(4) & OP_IN_S_SIGN(7) & "000";
end if;
when MULS | MULU =>
-- X is unaffected, C is always zero.
-- The sign flag is stored in the end of the operation. The Z and V flags
-- are valid after the operation, when the MULU or the MULS is not BUSY.
--
XNZVC_OUT <= XNZVC_IN(4) & '0' & '0' & '0' & '0'; -- Default...
--
if RESULT_I = x"00000000" and RESULT_II(31 downto 0) = x"00000000" then
XNZVC_OUT <= XNZVC_IN(4) & '0' & '1' & '0' & '0'; -- Result is zero.
elsif OP_SIZE = WORD and RESULT_I(31) = '1' then
XNZVC_OUT <= XNZVC_IN(4) & '1' & '0' & '0' & '0'; -- Negative result.
elsif OP_SIZE = LONG and DIV_MUL_32n64 = '0' then
if RESULT_I(31) = '1' and RESULT_II(31 downto 0) /= x"00000000" then -- Negative and overflow.
XNZVC_OUT <= XNZVC_IN(4) & '1' & '0' & '1' & '0';
elsif RESULT_I(31) = '1' then -- Negative.
XNZVC_OUT <= XNZVC_IN(4) & '1' & '0' & '0' & '0';
elsif RESULT_II(31 downto 0) /= x"00000000" then -- Overflow.
XNZVC_OUT <= XNZVC_IN(4) & '0' & '0' & '1' & '0';
end if;
elsif OP_SIZE = LONG and RESULT_II(31) = '1' then -- Long64 form: negative result, no overflow.
XNZVC_OUT <= XNZVC_IN(4) & '1' & '0' & '0' & '0';
end if;
when SWAP =>
-- The FLAGS are calculated 'look ahead' for the register and the
-- condition code register is written simultaneously.
-- The OP_IN(15) is the swapped bit 31.
if RESULT_SPECIAL = x"00000000" then
XNZVC_OUT <= XNZVC_IN(4) & "0100";
else
XNZVC_OUT <= XNZVC_IN(4) & RESULT_SPECIAL(31) & "000";
end if;
when TAS => -- TAS is Byte only.
if OP_IN_D_SIGN_LO(7 downto 0) = x"00" then
XNZVC_OUT <= XNZVC_IN(4) & "0100";
else
XNZVC_OUT <= XNZVC_IN(4) & OP_IN_D_SIGN_LO(7) &"000";
end if;
when others => XNZVC_OUT <= "-----";
end case;
end process COND_CODES;
-- For the source and destination operands it is necessary to distinguish between WORD and LONG format and between
-- signed and unsigned operations:
MUL_DIV_OP_S <= x"FFFF" & OP_IN_S(15 downto 0) when OP_SIZE = WORD and OP_IN_S(15) = '1' and (OP = MULS or OP = DIVS) else
x"0000" & OP_IN_S(15 downto 0) when OP_SIZE = WORD else OP_IN_S;
MUL_OP_D <= x"FFFF" & OP_IN_D_LO(15 downto 0) when OP_SIZE = WORD and OP_IN_D_LO(15) = '1' and OP = MULS else
x"0000" & OP_IN_D_LO(15 downto 0) when OP_SIZE = WORD else OP_IN_D_LO;
MUL_DIV_BUFFER: process(RESETn, CLK)
-- The Result is stored in two 32 bit wide registers. If a register is not used in an
-- operation, it remains unchanged. If parts of a register are not used, the respective
-- bits also remain unchanged.
begin
if RESETn = '0' then
RESULT_I <= (others => '0');
RESULT_II <= (others => '0');
elsif CLK = '1' and CLK' event then
-- The MULS, MULU, DIVS, DIVU require a definite start condition in form
-- of a start strobe.
if OP_START = '1' then
case OP is
when MULS | MULU => -- Load operands.
RESULT_II <= (others => '0');
if OP_IN_D_LO = x"00000000" or OP_IN_S = x"00000000" then
-- The result is zero if any of the operands is zero.
RESULT_I <= x"00000000";
else
RESULT_I <= MUL_OP_D;
end if;
when DIVU =>
-- Register function: see DIV_STATE_DEC process.
if OP_SIZE = LONG and DIV_MUL_32n64 = '1' then
DIVIDEND <= OP_IN_D_HI & OP_IN_D_LO;
else
DIVIDEND <= x"00000000" & OP_IN_D_LO;
end if;
DIVISOR <= x"00000000" & MUL_DIV_OP_S;
RESULT_I <= (others => '0'); -- Initialize.
RESULT_II <= (others => '0'); -- Initialize.
DIV_VAR <= x"00000001"; -- Shift variable.
when DIVS =>
-- Register function: see DIV_STATE_DEC process.
if OP_SIZE = LONG and DIV_MUL_32n64 = '1' and OP_IN_D_HI(31) = '0' then
DIVIDEND <= OP_IN_D_HI & OP_IN_D_LO; -- Positive.
elsif OP_SIZE = LONG and DIV_MUL_32n64 = '1' then
DIVIDEND <= unsigned(not(OP_IN_D_HI & OP_IN_D_LO)) + '1';
elsif OP_IN_D_LO(31) = '0' then
DIVIDEND <= x"00000000" & OP_IN_D_LO; -- Positive.
else
DIVIDEND <= x"00000000" & unsigned(not(OP_IN_D_LO)) + '1'; -- Negative, load twos complement.
end if;
--
if MUL_DIV_OP_S(31) = '1' then
DIVISOR <= x"00000000" & unsigned(not(MUL_DIV_OP_S)) + '1'; -- Negative, load twos complement.
else
DIVISOR <= x"00000000" & MUL_DIV_OP_S;
end if;
RESULT_I <= (others => '0'); -- Initialize.
RESULT_II <= (others => '0'); -- Initialize.
DIV_VAR <= x"00000001"; -- Shift variable.
when others =>
null;
end case;
elsif MUL_STATE = MUL_ADD then
-- Use sign extended value of source operand for MULS.
-- The RESULT_II(32) is the carry bit of the adder.
RESULT_II <= unsigned(RESULT_II) + unsigned(MUL_DIV_OP_S);
elsif MUL_STATE = MUL_VERIFY_SHIFT then -- Right shift.
-- Special case:
-- The MULS algorithm works fine, if we sign extend the operands and shift over a bit width of the result width.
-- This is done for the WORD format. In case of the LONG format, we shift 32 times (time efficient multiplication).
-- The algorithm delivers a wrong result in case of the signed multiplikation, when one or both operand are
-- negative. This error does not take any effect in the first LONG form, where the wrong high register result is
-- discarded. In case of the second long form, the high register result must be corrected by the addition of the
-- twos complements of the respective operands. The correction takes place during the last shift step.
case MUL_CYC_CNT is
when "000000" =>
if OP = MULS and OP_SIZE = LONG and MUL_DIV_OP_S(31) = '1' and OP_IN_D_LO(31) = '1' then
RESULT_II <= unsigned('0' & RESULT_II(32 downto 1)) + unsigned(not(OP_IN_D_LO)) + '1'
+ unsigned(not(MUL_DIV_OP_S)) + '1';
elsif OP = MULS and OP_SIZE = LONG and MUL_DIV_OP_S(31) = '1' then
RESULT_II <= unsigned('0' & RESULT_II(32 downto 1)) + unsigned(not(OP_IN_D_LO)) + '1';
elsif OP = MULS and OP_SIZE = LONG and OP_IN_D_LO(31) = '1' then
RESULT_II <= unsigned('0' & RESULT_II(32 downto 1)) + unsigned(not(MUL_DIV_OP_S)) + '1';
else
RESULT_II <= '0' & RESULT_II(32 downto 1); -- Carry Bit at MSB.
end if;
when others => RESULT_II <= '0' & RESULT_II(32 downto 1);
end case;
RESULT_I <= RESULT_II(0) & RESULT_I(31 downto 1);
elsif DIV_SHIFT_EN = '1' then -- Shift the DIVIDEND left.
-- Shift the DIVIDEND and the shift variable:
DIVISOR <= DIVISOR(62 downto 0) & '0';
DIV_VAR <= DIV_VAR(30 downto 0) & '0';
elsif DIV_STATE = DIV_ADDSUB then
-- The subtraction is unsigned for DIVS and DIVU.
DIVIDEND <= unsigned(DIVIDEND) - unsigned(DIVISOR); -- Remainder's register.
RESULT_I <= unsigned(RESULT_I) + unsigned(DIV_VAR); -- Quotient's register.
-- Reset the shift variable and reload the DIVISOR:
DIV_VAR <= x"00000001";
if OP = DIVS and MUL_DIV_OP_S(31) = '1' then
DIVISOR <= x"00000000" & unsigned(not(MUL_DIV_OP_S)) + '1'; -- Negative, load twos complement.
else
DIVISOR <= x"00000000" & MUL_DIV_OP_S;
end if;
elsif DIV_STATE = DIV_SIGN then
case OP_SIZE is
when LONG =>
if DIV_MUL_32n64 = '1' and OP = DIVS and ((OP_IN_D_HI(31) xor OP_IN_S(31)) = '1') then -- 64 bit dividend.
RESULT_I <= unsigned(not(RESULT_I)) + '1'; -- Negative, change sign.
elsif OP = DIVS and ((OP_IN_D_LO(31) xor OP_IN_S(31)) = '1') then -- 32 bit dividend.
RESULT_I <= unsigned(not(RESULT_I)) + '1'; -- Negative, change sign.
end if;
when others => -- WORD.
if OP = DIVS and ((OP_IN_D_LO(31) xor OP_IN_S(15)) = '1') then
RESULT_I <= unsigned(not(RESULT_I)) + '1'; -- Negative, change sign.
end if;
end case;
--
-- Remainder's sign = DIVISOR's sign:
if OP = DIVS and OP_SIZE = LONG and DIV_MUL_32n64 = '1' and OP_IN_D_HI(31) = '1' then
RESULT_II(31 downto 0) <= unsigned(not(DIVIDEND(31 downto 0))) + '1';
elsif OP = DIVS and DIV_MUL_32n64 = '0' and OP_IN_D_LO(31) = '1' then
RESULT_II(31 downto 0) <= unsigned(not(DIVIDEND(31 downto 0))) + '1';
else
RESULT_II(31 downto 0) <= DIVIDEND(31 downto 0);
end if;
end if;
end if;
end process MUL_DIV_BUFFER;
MUL_REGs: process(RESETn, CLK, MUL_CYC_CNT, MUL_STATE)
-- This unit provides on the one hand the state register for the
-- multiplier state machine and on the other hand the progress
-- control in form of the cycle counter MUL_CYC_CNT.
begin
if RESETn = '0' then
MUL_CYC_CNT <= "000000";
MUL_STATE <= MUL_IDLE;
elsif CLK = '1' and CLK' event then
--
MUL_STATE <= NEXT_MUL_STATE;
--
-- Cycle counter arithmetic:
if (OP = MULS or OP = MULU) and OP_START = '1' then
MUL_CYC_CNT <= "100000";
elsif MUL_STATE = MUL_VERIFY_SHIFT and (OP_IN_D_LO = x"00000000" or OP_IN_S = x"00000000") then
MUL_CYC_CNT <= "000000";
elsif MUL_STATE = MUL_VERIFY_SHIFT then
case MUL_CYC_CNT is
when "000000" => null;
when others => MUL_CYC_CNT <= MUL_CYC_CNT - '1';
end case;
end if;
end if;
--
case MUL_CYC_CNT is
when "000000" =>
if MUL_STATE = MUL_IDLE then
OP_MUL <= '0';
else
OP_MUL <= '1';
end if;
when others => OP_MUL <= '1';
end case;
end process MUL_REGs;
MUL_DEC: process(MUL_STATE, OP_START, OP, RESULT_I, MUL_CYC_CNT, OP_IN_D_LO, OP_IN_S)
--This is the process for the MULU and MULS operation.
-- This multiplier provides the WORD format as also the LONG formats of the 68K20+.
-- The algorithm for this multiplication is partly taken from:
-- http://mandalex.manderby.com/i/integerarithmetik.php?id=94, dated September, 2006.
-- The site is in German language.
begin
case MUL_STATE is
when MUL_IDLE =>
if (OP = MULS or OP = MULU) and OP_START = '1' then
NEXT_MUL_STATE <= MUL_VERIFY_SHIFT;
else
NEXT_MUL_STATE <= MUL_IDLE;
end if;
when MUL_VERIFY_SHIFT =>
if OP_IN_D_LO = x"00000000" or OP_IN_S = x"00000000" then
NEXT_MUL_STATE <= MUL_IDLE; -- Product is zero.
elsif RESULT_I(0) = '1' then
NEXT_MUL_STATE <= MUL_ADD;
else
case MUL_CYC_CNT is
when "000000" =>
NEXT_MUL_STATE <= MUL_IDLE; -- Finished.
when others =>
NEXT_MUL_STATE <= MUL_VERIFY_SHIFT; -- Go on.
end case;
end if;
when MUL_ADD =>
NEXT_MUL_STATE <= MUL_VERIFY_SHIFT;
end case;
end process MUL_DEC;
DIV_REGs: process(RESETn, CLK)
-- This unit provides the state register for the divider
-- state machine.
begin
if RESETn = '0' then
DIV_STATE <= DIV_IDLE;
elsif CLK = '1' and CLK' event then
DIV_STATE <= NEXT_DIV_STATE;
-- MSB for overflow check:
-- During adding a value to the RESULT_I, one operand is ADR_VAR and the other
-- one is RESULT_I itself. For overflow checking, it is therefore required to store
-- the old RESULT_I operand's MSB.
if OP_START = '1' then
DIV_OLD_MSB <= '0';
elsif DIV_STATE = DIV_ADDSUB and OP = DIVS then
case OP_SIZE is
when LONG =>
DIV_OLD_MSB <= RESULT_I(30);
when others => -- Word.
DIV_OLD_MSB <= RESULT_I(14);
end case;
elsif DIV_STATE = DIV_ADDSUB then
case OP_SIZE is
when LONG =>
DIV_OLD_MSB <= RESULT_I(31);
when others => -- Word.
DIV_OLD_MSB <= RESULT_I(15);
end case;
end if;
end if;
end process DIV_REGs;
DIV_DEC: process(DIV_STATE, OP_START, OP, OP_IN_S, DIVIDEND, DIVISOR, RESULT_I, OP_SIZE, DIV_VAR, DIV_OLD_MSB)
-- This is the process for the DIVU and DIVS operation. The division is always done
-- with the positive operands by loading the positive value or the 2s complement of the
-- negative value. After the last computation step, the sign is taken into account to get
-- the correct result.
-- This divider provides the WORD format as also the LONG formats of the 68K20+.
--
-- The Registers are used as follows:
-- Word:
-- The DIVIDEND is located in the DIVIDEND register.
-- The DIVISOR is located in lowest word of the DIVISOR register.
-- The quotient is located in RESULT_I(15 downto 0).
-- The remainder is located in RESULT_II(15 downto 0).
-- The shift variable is located in DIV_VAR.
-- LONG:
-- The DIVIDEND is located in the DIVIDEND register (lower Word for 32 bit DIVIDEND).
-- The DIVISOR is located in the lower half of the DIVISOR register.
-- The quotient is located in RESULT_I
-- The remainder is located in RESULT_II
-- The shift variable is located in DIV_VAR.
begin
-- Default assignments:
DIV_SHIFT_EN <= '0';
OP_DIV <= '1';
case DIV_STATE is
when DIV_IDLE =>
if (OP = DIVS or OP = DIVU) and OP_START = '1' and OP_IN_S = x"00000000" then
NEXT_DIV_STATE <= DIV_IDLE; -- Divide by zero -> Trap.
elsif (OP = DIVS or OP = DIVU) and OP_START = '1' then
NEXT_DIV_STATE <= DIV_VERIFY;
else
NEXT_DIV_STATE <= DIV_IDLE;
end if;
OP_DIV <= '0';
when DIV_VERIFY =>
-- Check overflow:
-- The variable ADR_VAR carries only one bit with a value of '1' at the same time.
-- Therefore the overflow can be detected by looking at the old MSB and the new one.
if OP_SIZE = LONG and OP = DIVS and DIV_OLD_MSB = '1' and RESULT_I(30) = '0' then
NEXT_DIV_STATE <= DIV_IDLE; -- Break due to overflow.
elsif OP_SIZE = WORD and OP = DIVS and DIV_OLD_MSB = '1' and RESULT_I(14) = '0' then
NEXT_DIV_STATE <= DIV_IDLE; -- Break due to overflow.
elsif OP_SIZE = LONG and OP = DIVU and DIV_OLD_MSB = '1' and RESULT_I(31) = '0' then
NEXT_DIV_STATE <= DIV_IDLE; -- Break due to overflow.
elsif OP_SIZE = WORD and OP = DIVU and DIV_OLD_MSB = '1' and RESULT_I(15) = '0' then
NEXT_DIV_STATE <= DIV_IDLE; -- Break due to overflow.
elsif DIVIDEND < DIVISOR then
NEXT_DIV_STATE <= DIV_SIGN;
--
-- A ADDSUB operation takes place, when the shifted result
-- would be greater than the current remainder. Otherwise, there
-- takes place a shift operation.
elsif DIVISOR(63 downto 0) & '0' > '0' & DIVIDEND then
NEXT_DIV_STATE <= DIV_ADDSUB;
else -- Shift condition:
if OP_SIZE = LONG and DIV_VAR(31) = '1' then
NEXT_DIV_STATE <= DIV_IDLE; -- Break due to DIV_VAR overflow.
elsif OP_SIZE = WORD and DIV_VAR(15) = '1' then
NEXT_DIV_STATE <= DIV_IDLE; -- Break due to DIV_VAR overflow.
else
NEXT_DIV_STATE <= DIV_VERIFY;
DIV_SHIFT_EN <= '1'; -- Shift operation enabled.
end if;
end if;
when DIV_ADDSUB =>
NEXT_DIV_STATE <= DIV_VERIFY;
when DIV_SIGN =>
-- Set the sign and computate the 2s complement of the quotient and the
-- remainder, when necessary. See result buffer.
NEXT_DIV_STATE <= DIV_IDLE;
end case;
end process DIV_DEC;
OV_DIV <= '1' when OP_SIZE = LONG and DIV_VAR(31) = '1' else
'1' when OP_SIZE = WORD and DIV_VAR(15) = '1' else
'1' when OP_SIZE = LONG and OP = DIVS and DIV_OLD_MSB = '1' and RESULT_I(30) = '0' else
'1' when OP_SIZE = WORD and OP = DIVS and DIV_OLD_MSB = '1' and RESULT_I(14) = '0' else
'1' when OP_SIZE = LONG and OP = DIVU and DIV_OLD_MSB = '1' and RESULT_I(31) = '0' else
'1' when OP_SIZE = WORD and OP = DIVU and DIV_OLD_MSB = '1' and RESULT_I(15) = '0' else '0';
end BEHAVIOR;

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----------------------------------------------------------------------
---- ----
---- MC68000 compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- This model provides an opcode and bus timing compatible ip ----
---- core compared to Motorola's MC68000 microprocessor. ----
---- ----
---- This file contains the 68Ks bus interface unit. ----
---- ----
---- Description: ----
---- This module provides bus control during read cycles, write ----
---- cycles and read modify write cycles. It also provides 2 and ----
---- 3 wire bus arbitration control, halt and rerun operation, ----
---- bus and address error generation, wait state insertion and ----
---- synchronous bus operation (68000). ----
---- In the following there are some remarks on the working ----
---- principle of this core. ----
---- ----
---- Bus cycle operation: ----
---- A bus cycle is released by either asserting RD_BUS for ----
---- entering a read cycle, WR_BUS for entering a write cycle or ----
---- RDWR_BUS for entering the read modify write cycle. There ----
---- must not be asserted two or three of these signals at the ----
---- same time. Once the bus cycle is started, the RD_BUS, WR_BUS ----
---- or RDWR_BUS must be asserted until the cycle finishes. This ----
---- is indicated by the signal BUS_CYC_RDY, which is valid ----
---- for one clock cycle after the bus operation finished. ----
---- ----
---- Synchronous timing topics: ----
---- During the synchronous timing, the DTACKn must not be ----
---- asserted and due to asynchronous timing, the VPAn must not ----
---- be asserted, otherwise unpredictable behavior will result. ----
---- ----
---- Bus arbitration topics: ----
---- No bus arbitration during read modify write cycle. ----
---- In the case of a 2 wire bus arbitration, no re-entry for ----
---- another device is possible. ----
---- ----
---- Bus error topics: ----
---- During a bus error, the bus cycle finishes also asserting ----
---- the BUS_CYC_RDY signal during S9 for read, write and the ----
---- read portion of the read modify write cycle and during S19 ----
---- for the write portion of a read modify write cycle. ----
---- ----
---- Bus re-run topics: ----
---- During a re-run condition, the bus cycle finishes also ----
---- asserting the BUS_CYC_RDY signal during S7 for read and ----
---- write cycle and during S19 for the read modify write cycle. ----
---- ----
---- RESET topics: ----
---- When a reset is released by the CPU due to the RESET_EN ----
---- control, the RESET_RDY indicates the finishing of the reset ----
---- cycle 124 clock cycles later. The RESET_EN may be asserted ----
---- until RESET_RDY indicates 'ready'. The RESET_RDY is a strobe ----
---- and therefore valid for one clock cycle. ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, or (at your option) any later ----
---- version. ----
---- ----
---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, write to the Free ----
---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6B 2006/12/24 WF
-- Initial Release.
-- Revision 2K7A 2007/05/31 WF
-- Updated all modules.
-- Revision 2K7B 2007/12/24 WF
-- See the 68K00 top level file.
-- Revision 2K8A 2008/07/14 WF
-- See the 68K00 top level file.
--
library work;
use work.wf68k00ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity WF68K00IP_BUS_INTERFACE is
port (
-- System control:
CLK : in bit; -- System clock.
RESETn : in bit; -- Core reset.
RESET_INn : in bit; -- System's reset input.
RESET_OUT_EN : out bit; -- System's reset output open drain enable.
RESET_CPUn : out bit; -- Internal reset used for CPU initialization.
RESET_EN : in bit; -- Force reset control.
RESET_RDY : out bit; -- Indicates the end of a forced reset cycle (strobe).
-- Data lines:
DATA_IN : in std_logic_vector(15 downto 0); -- Data bus input lines.
-- Receive buffers:
SEL_A_HI : in bit; -- Select data A buffer high byte.
SEL_A_MIDHI : in bit; -- Select data A buffer midhigh byte.
SEL_A_MIDLO : in bit; -- Select data A buffer midlow byte.
SEL_A_LO : in bit; -- Select data A buffer low byte.
SEL_BUFF_A_LO : in bit; -- Select data A buffer low word.
SEL_BUFF_A_HI : in bit; -- Select data A buffer high word.
SEL_BUFF_B_LO : in bit; -- Select data B buffer low word.
SEL_BUFF_B_HI : in bit; -- Select data B buffer high word.
SYS_INIT : in bit; -- Indicates the system initialisation (PC, SSP).
OP_SIZE : in OP_SIZETYPE; -- Used for the input multiplexer (buffers).
BUFFER_A : out std_logic_vector(31 downto 0); -- Receive buffer A.
BUFFER_B : out std_logic_vector(31 downto 0); -- Receive buffer B.
DATA_CORE_OUT : out std_logic_vector(15 downto 0); -- Data buffer.
-- Control signals:
RD_BUS : in bit; -- Read bus request.
WR_BUS : in bit; -- Wriyte request.
RDWR_BUS : in bit; -- Read modify write request.
A0 : in std_logic; -- Least significant bit of the address counter.
BYTEn_WORD : in bit; -- Byte or Word format for read or write bus cycles.
EXEC_ABORT : in bit; -- Skip the current bus cycle, if '1'.
BUS_CYC_RDY : out bit; -- Indicates 'Ready' (strobe).
DATA_VALID : out bit;
-- Bus control signals:
DTACKn : in bit;
BERRn : in bit;
AVECn : in bit;
HALTn : in std_logic;
ADR_EN : out bit;
WR_HI : in bit;
HI_WORD_EN : out bit;
HI_BYTE_EN : out bit;
LO_BYTE_EN : out bit;
FC_EN : out bit;
ASn : out bit;
AS_EN : out bit;
UDSn : out bit;
UDS_EN : out bit;
LDSn : out bit;
LDS_EN : out bit;
RWn : out bit;
RW_EN : out bit;
-- Synchronous Bus controls:
VPAn : in bit;
VMAn : out bit;
VMA_EN : out bit;
E : out bit;
-- Bus arbitration:
BRn : in bit;
BGACKn : in bit;
BGn : out bit
);
end entity WF68K00IP_BUS_INTERFACE;
architecture BEHAVIOR of WF68K00IP_BUS_INTERFACE is
type ARB_STATES is(IDLE, GRANT, WAIT_RELEASE_3WIRE, WAIT_RELEASE_2WIRE);
type TIME_SLICES is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20);
signal RESET_OUT_EN_I : bit;
signal RESET_CPU_In : bit;
signal ARB_STATE : ARB_STATES;
signal NEXT_ARB_STATE : ARB_STATES;
signal T_SLICE : TIME_SLICES;
signal SLICE_CNT : std_logic_vector(3 downto 0);
signal BERR : bit;
signal FC_ENAB : bit;
signal VMA_In : bit;
signal UDS_RD_EN_N : bit;
signal UDS_RD_EN_P : bit;
signal UDS_RD_EN : bit;
signal LDS_RD_EN_N : bit;
signal LDS_RD_EN_P : bit;
signal LDS_RD_EN : bit;
signal UDS_WR_EN_N : bit;
signal UDS_WR_EN_P : bit;
signal UDS_WR_EN : bit;
signal LDS_WR_EN_N : bit;
signal LDS_WR_EN_P : bit;
signal LDS_WR_EN : bit;
signal UDS_RDWR_EN_N : bit; -- For read modify write;
signal UDS_RDWR_EN_P : bit; -- For read modify write;
signal UDS_RDWR_EN : bit; -- For read modify write;
signal LDS_RDWR_EN_N : bit; -- For read modify write;
signal LDS_RDWR_EN_P : bit; -- For read modify write;
signal LDS_RDWR_EN : bit; -- For read modify write;
signal AS_ENAB_N : bit;
signal AS_ENAB_P : bit;
signal AS_ENAB : bit;
signal AS_RDWR_INH : bit; -- For read modify write;
signal DATA_EN_N : bit;
signal DATA_EN_P : bit;
signal DATA_EN : bit;
signal DATA_RDWR_EN_N : bit; -- For read modify write;
signal DATA_RDWR_EN_P : bit; -- For read modify write;
signal DATA_RDWR_EN : bit; -- For read modify write;
signal WR_ENAB_P : bit;
signal WR_ENAB : bit;
signal WR_EN_RDWR_P : bit; -- For read modify write;
signal WR_RDWR_EN : bit; -- For read modify write;
signal ADR_INH : bit;
signal ADR_RDWR_INH : bit; -- For read modify write;
signal WAITSTATES : bit;
signal HALTED : bit;
signal SYNCn : bit;
begin
-- Three state controls:
UDS_EN <= '1' when BGACKn = '1' else '0'; -- Hi-Z during arbitration.
LDS_EN <= '1' when BGACKn = '1' else '0'; -- Hi-Z during arbitration.
AS_EN <= '1' when BGACKn = '1' else '0'; -- Hi-Z during arbitration.
RW_EN <= '1' when BGACKn = '1' else '0'; -- Hi-Z during arbitration.
DATA_VALID <= '1' when T_SLICE = S6 else '0'; -- Sample the data during S6.
BUS_BUFFER: process(RESETn, CLK)
-- This process samples the data from the data bus during the bus phase S6.
-- During S6 the received data from the bus is valid depending on the selection
-- of UDSn and LDSn. This means that the respective byte (high or low) is valid,
-- if wether UDSn or LDSn is asserted. If both are asserted, both bytes are valid.
-- For S6 is followed by a falling clock edge, the process reacts on it.
begin
if RESETn = '0' then
BUFFER_A <= (others => '0');
BUFFER_B <= (others => '0');
elsif CLK = '0' and CLK' event then
if T_SLICE = S6 and SEL_A_HI = '1' and A0 = '0' and RD_BUS = '1' then -- Read Byte from even address.
BUFFER_A(31 downto 24) <= DATA_IN(15 downto 8);
elsif T_SLICE = S6 and SEL_A_HI = '1' and RD_BUS = '1' then -- Read Byte from odd address.
BUFFER_A(31 downto 24) <= DATA_IN(7 downto 0);
elsif T_SLICE = S6 and SEL_A_MIDHI = '1' and A0 = '0' and RD_BUS = '1' then
BUFFER_A(23 downto 16) <= DATA_IN(15 downto 8);
elsif T_SLICE = S6 and SEL_A_MIDHI = '1' and RD_BUS = '1' then
BUFFER_A(23 downto 16) <= DATA_IN(7 downto 0);
elsif T_SLICE = S6 and SEL_A_MIDLO = '1' and A0 = '0' and RD_BUS = '1' then
BUFFER_A(15 downto 8) <= DATA_IN(15 downto 8);
elsif T_SLICE = S6 and SEL_A_MIDLO = '1' and RD_BUS = '1' then
BUFFER_A(15 downto 8) <= DATA_IN(7 downto 0);
elsif T_SLICE = S6 and SEL_A_LO = '1' and A0 = '0' and RD_BUS = '1' then
BUFFER_A(7 downto 0) <= DATA_IN(15 downto 8);
elsif T_SLICE = S6 and SEL_A_LO = '1' and RD_BUS = '1' then
BUFFER_A(7 downto 0) <= DATA_IN(7 downto 0);
--
elsif T_SLICE = S6 and SYS_INIT = '1' and SEL_BUFF_A_HI = '1' then -- During system startup.
BUFFER_A(31 downto 16) <= DATA_IN;
elsif T_SLICE = S6 and SYS_INIT = '1' and SEL_BUFF_A_LO = '1' then -- During system startup.
BUFFER_A(15 downto 0) <= DATA_IN;
elsif T_SLICE = S6 and SEL_BUFF_A_LO = '1' and OP_SIZE = BYTE and A0 = '0' then -- Byte from an even address.
BUFFER_A <= x"000000" & DATA_IN(15 downto 8);
elsif T_SLICE = S6 and SEL_BUFF_A_LO = '1' and OP_SIZE = BYTE then -- Byte from an odd address.
BUFFER_A <= x"000000" & DATA_IN(7 downto 0);
elsif T_SLICE = S6 and SEL_BUFF_A_LO = '1' then -- Word or long access.
BUFFER_A(15 downto 0) <= DATA_IN;
elsif T_SLICE = S6 and SEL_BUFF_A_HI = '1' then -- Long access.
BUFFER_A(31 downto 16) <= DATA_IN;
--
elsif T_SLICE = S6 and SEL_BUFF_B_LO = '1' and OP_SIZE = BYTE and A0 = '0' then -- Byte from an even address.
BUFFER_B <= x"000000" & DATA_IN(15 downto 8);
elsif T_SLICE = S6 and SEL_BUFF_B_LO = '1' and OP_SIZE = BYTE then -- Byte from an odd address.
BUFFER_B <= x"000000" & DATA_IN(7 downto 0);
elsif T_SLICE = S6 and SEL_BUFF_B_LO = '1' then -- Word or long access.
BUFFER_B(15 downto 0) <= DATA_IN;
elsif T_SLICE = S6 and SEL_BUFF_B_HI = '1' then -- Long access.
BUFFER_B(31 downto 16) <= DATA_IN;
end if;
if T_SLICE = S6 then
DATA_CORE_OUT <= DATA_IN; -- Transparent buffer.
end if;
end if;
end process BUS_BUFFER;
-- For the condition of the bus error see the 68K family user manual.
-- Bus errors during S0, S1 and S2 cannot occur.
-- There are no retry cycles in the read modify write mode.
BERR <= '1' when BERRn = '0' and HALTn = '1' and DTACKn = '1' and T_SLICE /= S0 and T_SLICE /= S1 and T_SLICE /= S2 else
'1' when BERRn = '0' and HALTn = '0' and RDWR_BUS = '1' and T_SLICE /= S0 and T_SLICE /= S1 and T_SLICE /= S2 else '0';
BUS_CYC_RDY <= '0' when BERRn = '0' and HALTn = '0' else -- Force a retry cycle.
'1' when HALTED = '1' and HALTn = '1' else -- Release immediately after the halt.
'1' when (RD_BUS = '1' or WR_BUS = '1') and T_SLICE = S7 else
'1' when RDWR_BUS = '1' and T_SLICE = S19 else '0';
FC_EN <= '1' when FC_ENAB = '1' else '0';
ADR_EN <= '1' when (RD_BUS = '1' or WR_BUS = '1') and ADR_INH = '0' else
'1' when RDWR_BUS = '1' and ADR_RDWR_INH = '0' else '0';
ASn <= '0' when (RD_BUS = '1' or WR_BUS = '1') and AS_ENAB = '1' else
'0' when RDWR_BUS = '1' and AS_RDWR_INH = '0' else '1';
UDSn <= '0' when RD_BUS = '1' and UDS_RD_EN = '1' and A0 = '0' and BYTEn_WORD = '0' else
'0' when WR_BUS = '1' and UDS_WR_EN = '1' and A0 = '0' and BYTEn_WORD = '0' else
'0' when RD_BUS = '1' and UDS_RD_EN = '1' and BYTEn_WORD = '1' else
'0' when WR_BUS = '1' and UDS_WR_EN = '1' and BYTEn_WORD = '1' else
-- Read modify write is always byte wide:
'0' when RDWR_BUS = '1' and UDS_RDWR_EN = '1' and A0 = '0' else '1';
LDSn <= '0' when RD_BUS = '1' and LDS_RD_EN = '1' and A0 = '1' and BYTEn_WORD = '0' else
'0' when WR_BUS = '1' and LDS_WR_EN = '1' and A0 = '1' and BYTEn_WORD = '0' else
'0' when RD_BUS = '1' and LDS_RD_EN = '1' and BYTEn_WORD = '1' else
'0' when WR_BUS = '1' and LDS_WR_EN = '1' and BYTEn_WORD = '1' else
-- Read modify write is always byte wide:
'0' when RDWR_BUS = '1' and LDS_RDWR_EN = '1' and A0 = '1' else '1';
RWn <= '0' when WR_BUS = '1' and WR_ENAB = '1' else
'0' when RDWR_BUS = '1' and WR_RDWR_EN = '1' else '1';
-- To meet the behavior of the bus during bus error, the HI_WORD_EN must have higher priority than
-- HI_BYTE_EN or LOW_BYTE_EN (using these signals for the bus drivers).
-- Nevertheless during bus error, there will be written invalid data via the HI_WORD_EN signal to the bus.
-- Read modify write is always byte wide due to used exclusively by the TAS operation.
HI_WORD_EN <= '1' when WR_BUS = '1' and DATA_EN = '1' and WR_HI = '1' else '0';
HI_BYTE_EN <= '1' when WR_BUS = '1' and DATA_EN = '1' and A0 = '0' and BYTEn_WORD = '0' else
'1' when WR_BUS = '1' and DATA_EN = '1' and BYTEn_WORD = '1' else
'1' when RDWR_BUS = '1' and DATA_RDWR_EN = '1' and A0 = '0' else '0';
LO_BYTE_EN <= '1' when WR_BUS = '1' and DATA_EN = '1' and A0 = '1' and BYTEn_WORD = '0' else
'1' when WR_BUS = '1' and DATA_EN = '1' and BYTEn_WORD = '1' else
'1' when RDWR_BUS = '1' and DATA_RDWR_EN = '1' and A0 = '1' else '0';
P_WAITSTATES: process
-- During read, write or read modify write processes, the read access is delayed by wait
-- states (slow read, slow write) if there is no DTACKn asserted until the end of S4 and
-- until the end of S16 (during read modify write). This is done by stopping the slice
-- counter. After the halt, in principle a S5, S17 bwould be possible. This is not correct
-- for not asserted DTACKn. This process provides a locking of this forbidden case and the
-- stop control for the slice counter. For more information see the 68000 processor data
-- sheet (bus cycles).
-- In case of a buss error, the bus cycle is finished by realeasing the WAITSTATES via BERR.
-- The SYNCn controls the synchronous bus timing. This is not valid for read modify write
-- cycles.
-- The AVECn ends the bus cycle in case of an autovector interrupt acknowledge cycle.
begin
wait until CLK = '0' and CLK' event;
if T_SLICE = S4 then
WAITSTATES <= DTACKn and SYNCn and AVECn and not BERR;
elsif T_SLICE = S16 then
WAITSTATES <= DTACKn and not BERR; -- For read modify write.
else
WAITSTATES <= '0';
end if;
end process P_WAITSTATES;
HALTSTATE: process
-- This is a flag to control the halted state of a bus cycle
-- and to release the BUS_CYC_RDY in the halted state.
begin
wait until CLK = '1' and CLK' event;
if HALTn = '0' and BERRn = '1' then
HALTED <= '1';
elsif SLICE_CNT = "0000" and HALTn = '1' then
HALTED <= '0';
end if;
end process HALTSTATE;
SLICES: process(RESETn, CLK)
-- This process provides the central timing for the read, write and read modify write cycle
-- as also for the bus arbitration procedure.
begin
if RESETn = '0' then
SLICE_CNT <= "1111";
elsif CLK = '1' and CLK' event then
-- Cycle reset:
if RESET_CPU_In = '0' then
SLICE_CNT <= "0000"; -- Abort current bus cycle.
elsif ARB_STATE /= IDLE and SLICE_CNT = "0000" then -- Do not start a bus sequence when the bus is granted.
SLICE_CNT <= "1111";
elsif ARB_STATE /= IDLE and SLICE_CNT = "1111" then -- Stay until the bus is released.
SLICE_CNT <= "1111";
-- Initialization:
elsif RD_BUS = '0' and WR_BUS = '0' and RDWR_BUS = '0' then
SLICE_CNT <= "0000"; -- Init.
elsif SLICE_CNT = "0000" and HALTn = '0' then
SLICE_CNT <= "0000"; -- Wait in retry or halt operation until HALTn is released.
-- Counting:
elsif (RD_BUS = '1' or WR_BUS = '1') and SLICE_CNT = "0011" then
SLICE_CNT <= "0000"; -- Finish the read or write cycle.
elsif RDWR_BUS = '1' and SLICE_CNT = "1001" then
SLICE_CNT <= "0000"; -- Finish the read modify write cycle.
elsif (RD_BUS = '1' or WR_BUS = '1' or RDWR_BUS = '1') and WAITSTATES = '0' and HALTED = '0' then
SLICE_CNT <= SLICE_CNT + '1'; -- Cycle active.
end if;
end if;
end process SLICES;
T_SLICE <= S0 when RD_BUS = '0' and WR_BUS = '0' and RDWR_BUS = '0' else -- IDLE Mode.
S0 when SLICE_CNT = "0000" and CLK = '1' else
S0 when SLICE_CNT = "0000" and CLK = '0' and HALTn = '0' else -- Stay in IDLE during retry with HALTn asserted.
S1 when SLICE_CNT = "0000" and CLK = '0' else
S2 when SLICE_CNT = "0001" and CLK = '1' else
S3 when SLICE_CNT = "0001" and CLK = '0' else
S4 when SLICE_CNT = "0010" and CLK = '1' else
S4 when WAITSTATES = '1' and SLICE_CNT = "0010" and CLK = '0' else
S5 when WAITSTATES = '0' and SLICE_CNT = "0010" and CLK = '0' else
S6 when SLICE_CNT = "0011" and CLK = '1' else
S7 when SLICE_CNT = "0011" and CLK = '0' else
S8 when SLICE_CNT = "0100" and CLK = '1' else
S9 when SLICE_CNT = "0100" and CLK = '0' else
S10 when SLICE_CNT = "0101" and CLK = '1' else
S11 when SLICE_CNT = "0101" and CLK = '0' else
S12 when SLICE_CNT = "0110" and CLK = '1' else
S13 when SLICE_CNT = "0110" and CLK = '0' else
S14 when SLICE_CNT = "0111" and CLK = '1' else
S15 when SLICE_CNT = "0111" and CLK = '0' else
S16 when SLICE_CNT = "1000" and CLK = '1' else
S16 when WAITSTATES = '1' and SLICE_CNT = "1000" and CLK = '0' else
S17 when WAITSTATES = '0' and SLICE_CNT = "1000" and CLK = '0' else
S18 when SLICE_CNT = "1001" and CLK = '1' else
S19 when SLICE_CNT = "1001" and CLK = '0' else S20; -- S20 is the Bus arbitration state.
-- The modelling with the two processes working on the positive and negative clock edge
-- is a bit complicated. But it results in rather 'clean' (glitch free) bus control
-- signals. Every signal is modelled with it's own timing to give the core a high degree
-- of freedom.
N: process
begin
wait until CLK = '0' and CLK' event;
case T_SLICE is
when S4 => UDS_WR_EN_N <= '1';
when others => UDS_WR_EN_N <= '0';
end case;
case T_SLICE is
when S4 => LDS_WR_EN_N <= '1';
when others => LDS_WR_EN_N <= '0';
end case;
case T_SLICE is
when S2 | S4 => UDS_RD_EN_N <= '1';
when others => UDS_RD_EN_N <= '0';
end case;
case T_SLICE is
when S2 | S4 => LDS_RD_EN_N <= '1';
when others => LDS_RD_EN_N <= '0';
end case;
case T_SLICE is
when S2 | S4 => AS_ENAB_N <= '1';
when others => AS_ENAB_N <= '0';
end case;
case T_SLICE is
when S2 | S4 | S16 => UDS_RDWR_EN_N <= '1';
when others => UDS_RDWR_EN_N <= '0';
end case;
case T_SLICE is
when S2 | S4 | S16 => LDS_RDWR_EN_N <= '1';
when others => LDS_RDWR_EN_N <= '0';
end case;
case T_SLICE is
when S2 => DATA_EN_N <= '1';
when others => DATA_EN_N <= '0';
end case;
case T_SLICE is
when S14 => DATA_RDWR_EN_N <= '1';
when others => DATA_RDWR_EN_N <= '0';
end case;
end process N;
P: process
begin
wait until CLK = '1' and CLK' event;
case T_SLICE is
when S1 | S3 => AS_ENAB_P <= '1';
when others => AS_ENAB_P <= '0';
end case;
case T_SLICE is
when S3 => UDS_WR_EN_P <= '1';
when others => UDS_WR_EN_P <= '0';
end case;
case T_SLICE is
when S1 | S3 | S15 => UDS_RDWR_EN_P <= '1';
when others => UDS_RDWR_EN_P <= '0';
end case;
case T_SLICE is
when S1 | S3 | S15 => LDS_RDWR_EN_P <= '1';
when others => LDS_RDWR_EN_P <= '0';
end case;
case T_SLICE is
when S3 => LDS_WR_EN_P <= '1';
when others => LDS_WR_EN_P <= '0';
end case;
case T_SLICE is
when S1 | S3 => UDS_RD_EN_P <= '1';
when others => UDS_RD_EN_P <= '0';
end case;
case T_SLICE is
when S1 | S3 => LDS_RD_EN_P <= '1';
when others => LDS_RD_EN_P <= '0';
end case;
case T_SLICE is
when S1 | S3 | S4 | S5 => WR_ENAB_P <= '1'; -- S4 due to wait states.
when others => WR_ENAB_P <= '0';
end case;
case T_SLICE is
when S13 | S15 | S16 | S17 => WR_EN_RDWR_P <= '1'; -- S16 due to wait states.
when others => WR_EN_RDWR_P <= '0';
end case;
case T_SLICE is
when S3 | S4 | S5 => DATA_EN_P <= '1'; -- S4 due to wait states.
when others => DATA_EN_P <= '0';
end case;
case T_SLICE is
when S15 | S16 | S17 => DATA_RDWR_EN_P <= '1'; -- S16 due to wait states.
when others => DATA_RDWR_EN_P <= '0';
end case;
end process P;
-- Read and write timing:
UDS_WR_EN <= UDS_WR_EN_N or UDS_WR_EN_P; -- '1' when S4 | S5 | S6.
LDS_WR_EN <= LDS_WR_EN_N or LDS_WR_EN_P; -- '1' when S4 | S5 | S6.
UDS_RD_EN <= UDS_RD_EN_N or UDS_RD_EN_P; -- '1' when S2 | S3 | S4 | S5 | S6.
LDS_RD_EN <= LDS_RD_EN_N or LDS_RD_EN_P; -- '1' when S2 | S3 | S4 | S5 | S6.
AS_ENAB <= AS_ENAB_N or AS_ENAB_P; -- '1' when S2 | S3 | S4 | S5 | S6.
WR_ENAB <= WR_ENAB_P; -- '1' when S2 | S3 | S4 | S5 | S6 | S7.
DATA_EN <= DATA_EN_N or DATA_EN_P; -- '1' when S3 | S4 | S5 | S6 | S7.
ADR_INH <= '1' when T_SLICE = S0 else '0';
-- Read modify write timing:
UDS_RDWR_EN <= UDS_RDWR_EN_N or UDS_RDWR_EN_P; -- '1' when S2 | S3 | S4 | S5 | S6 | S16 | S17 | S18.
LDS_RDWR_EN <= LDS_RDWR_EN_N or LDS_RDWR_EN_P; -- '1' when S2 | S3 | S4 | S5 | S6 | S16 | S17 | S18.
AS_RDWR_INH <= '1' when T_SLICE = S0 else '0';
WR_RDWR_EN <= WR_EN_RDWR_P; -- '1' when S14 | S15 | S16 | S17 | S18 | S19.
DATA_RDWR_EN <= DATA_RDWR_EN_N or DATA_RDWR_EN_P; -- '1' when S3 | S4 | S5 | S6 | S7 | S15 | S16 | S17 | S18 | S19.
ADR_RDWR_INH <= '1' when T_SLICE = S0 else '0';
-- Timing valid for all modes:
FC_ENAB <= '0' when T_SLICE = S0 and HALTn = '0' else -- During halt.
'0' when RD_BUS = '0' and WR_BUS = '0' and RDWR_BUS = '0' and T_SLICE = S0 else -- Normal operation.
'0' when BGACKn = '0' else '1'; -- During arbitration.
-- Synchronous bus timing:
E_TIMER: process(RESETn, CLK)
-- The E clock is a free running clock with a period of 10 times
-- the CLK period. The pulse ratio is 4 CLK high and 6 CLK low.
variable TMP : std_logic_vector(3 downto 0);
begin
if RESETn = '0' then
TMP := x"0";
VMA_In <= '1';
SYNCn <= '1';
E <= '1';
elsif CLK = '1' and CLK' event then
if TMP < x"9" then
TMP := TMP + '1';
else
TMP := x"0";
end if;
-- E logic:
if TMP = x"0" then
E <= '1';
elsif TMP = x"4" then
E <= '0';
end if;
-- VMA logic:
if VPAn = '0' and TMP >= x"4" then -- Switch, when E is low.
VMA_In <= '0';
elsif T_SLICE = S7 then
VMA_In <= '1';
end if;
-- SYNCn logic (wait states controlling):
if VPAn = '0' and VMA_In = '0' and TMP = x"0" then -- Switch, when E is just high.
SYNCn <= '0';
elsif VPAn = '1' or VMA_In = '1' then
SYNCn <= '1';
end if;
end if;
end process E_TIMER;
VMA_EN <= '0' when BGACKn = '0' else '1';
VMAn <= VMA_In;
-- Bus arbitration:
ARB_REG: process(RESETn, CLK)
begin
if RESETn = '0' then
ARB_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
ARB_STATE <= NEXT_ARB_STATE;
end if;
end process ARB_REG;
ARB_DEC: process(ARB_STATE, RDWR_BUS, BRn, RD_BUS, WR_BUS, T_SLICE, BGACKn)
-- The state machine for the bus grant works on the positive clock edge. Therefore it is
-- sufficient to control on the odd time slices (S1, S3, S5, S7). In the case, that the
-- bus request is asserted early, the bus grant is asserted during S4 otherwise one clock
-- later (S6 or IDLE).
begin
case ARB_STATE is
when IDLE =>
if RDWR_BUS = '1' then
NEXT_ARB_STATE <= IDLE; -- No bus arbitration during read modify write cycle.
elsif BRn = '0' and T_SLICE /= S1 then
NEXT_ARB_STATE <= GRANT; -- Bus grant delayed in case of S1, otherwise immediately.
else
NEXT_ARB_STATE <= IDLE;
end if;
when GRANT =>
if BGACKn = '0' then
NEXT_ARB_STATE <= WAIT_RELEASE_2WIRE;
elsif BRn = '1' then
NEXT_ARB_STATE <= IDLE; -- Re-initialize.
else
NEXT_ARB_STATE <= GRANT;
end if;
when WAIT_RELEASE_2WIRE =>
-- In the case of a 2 wire bus arbitration, no re-entry for another
-- device is possible.
if BGACKn = '1' and BRn = '1' then
NEXT_ARB_STATE <= IDLE;
elsif BGACKn = '0' then
NEXT_ARB_STATE <= WAIT_RELEASE_3WIRE; -- BGACKn = '0' indicates 3 wire arbitration.
else
NEXT_ARB_STATE <= WAIT_RELEASE_2WIRE;
end if;
when WAIT_RELEASE_3WIRE =>
if BGACKn = '1' and BRn = '0' then
NEXT_ARB_STATE <= GRANT; -- Re-enter new arbitration.
elsif BGACKn = '1' then
NEXT_ARB_STATE <= IDLE;
else
NEXT_ARB_STATE <= WAIT_RELEASE_3WIRE;
end if;
end case;
end process ARB_DEC;
BGn <= '0' when ARB_STATE = GRANT else -- 3 wire and 2 wire arbitration.
'0' when ARB_STATE = WAIT_RELEASE_2WIRE else '1'; -- 2 wire arbitration.
-- RESET logic:
RESET_FILTER: process(RESETn, CLK)
-- This process filters the incoming reset pin.
-- If RESET_INn and HALTn are asserted together for longer
-- than 10 clock cycles over the execution of a CPU reset
-- command, the CPU reset is released.
variable TMP : std_logic_vector(3 downto 0);
begin
if RESETn = '0' then
TMP := x"F"; -- For correct startup.
RESET_CPU_In <= '0';
elsif CLK = '1' and CLK' event then
if RESET_INn = '0' and HALTn = '0' and RESET_OUT_EN_I = '0' and TMP < x"F" then
TMP := TMP + '1';
elsif RESET_INn = '1' or HALTn = '1' or RESET_OUT_EN_I = '1' then
TMP := x"0";
end if;
if TMP > x"A" then
RESET_CPU_In <= '0'; -- Release internal reset.
else
RESET_CPU_In <= '1';
end if;
end if;
end process RESET_FILTER;
RESET_TIMER: process(RESETn, CLK)
-- This logic is responsible for the assertion of the
-- reset output for 124 clock cycles, during the reset
-- command. The LOCK variable avoids re-initialisation
-- of the counter in the case that the RESET_EN is no
-- strobe.
variable TMP : std_logic_vector(6 downto 0);
variable LOCK : boolean;
begin
if RESETn = '0' then
TMP := (others => '0');
LOCK := false;
elsif CLK = '1' and CLK' event then
if RESET_EN = '1' and LOCK = false then
TMP := "1111100"; -- 124 initial value.
LOCK := true; -- Lock the counter initialisation.
elsif TMP > "0000000" then
TMP := TMP - '1';
elsif RESET_EN = '0' then
LOCK := false; -- Unlock the counter initialisation.
end if;
if TMP = "0000001" then
RESET_OUT_EN_I <= '0';
RESET_RDY <= '1';
elsif TMP <= "0000011" then
RESET_OUT_EN_I <= '0';
RESET_RDY <= '0';
else
RESET_OUT_EN_I <= '1';
RESET_RDY <= '0';
end if;
end if;
end process RESET_TIMER;
RESET_OUT_EN <= RESET_OUT_EN_I;
RESET_CPUn <= RESET_CPU_In;
end BEHAVIOR;

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----------------------------------------------------------------------
---- ----
---- MC68000 compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- This model provides an opcode and bus timing compatible ip ----
---- core compared to Motorola's MC68000 microprocessor. ----
---- ----
---- This file contains the 68Ks data registers. ----
---- ----
---- ----
---- Description: ----
---- Contains the 68K00 data registers D0 to D7 and related logic ----
---- to perform byte, word and long data operations. ----
---- ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, or (at your option) any later ----
---- version. ----
---- ----
---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, write to the Free ----
---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6B 2006/12/24 WF
-- Initial Release.
-- Revision 2K7A 2007/05/31 WF
-- Updated all modules.
-- Revision 2K7B 2007/12/24 WF
-- See the 68K00 top level file.
-- Revision 2K8A 2008/07/14 WF
-- See the 68K00 top level file.
--
use work.wf68k00ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity WF68K00IP_DATA_REGISTERS is
port (
CLK : in bit;
RESETn : in bit;
-- Data lines:
DATA_IN_A : in std_logic_vector(31 downto 0);
DATA_IN_B : in std_logic_vector(31 downto 0);
-- Registers controls:
REGSEL_A : in std_logic_vector(2 downto 0);
REGSEL_B : in std_logic_vector(2 downto 0);
REGSEL_C : in std_logic_vector(2 downto 0);
DIV_MUL_32n64 : in bit;
-- Data outputs A and B:
DATA_OUT_A : out std_logic_vector(31 downto 0);
DATA_OUT_B : out std_logic_vector(31 downto 0);
DATA_OUT_C : out std_logic_vector(31 downto 0);
DR_EXG : in bit; -- Exchange a data register.
DR_DEC : in bit; -- Decrement by 1.
DR_WR : in bit; -- Data register write control.
OP : in OP_68K00;
OP_SIZE : in OP_SIZETYPE;
OP_MODE : in std_logic_vector(4 downto 0);
-- Miscellaneous:
DBcc_COND : out boolean -- Condition is true for Dn = -1.
);
end entity WF68K00IP_DATA_REGISTERS;
architecture BEHAVIOR of WF68K00IP_DATA_REGISTERS is
type DR_TYPE is array(0 to 7) of std_logic_vector(31 downto 0);
signal DR : DR_TYPE; -- Data registers D0 to D7.
signal DR_NR_A : integer range 0 to 7;
signal DR_NR_B : integer range 0 to 7;
signal DR_NR_C : integer range 0 to 7;
begin
-- Address pointers:
DR_NR_A <= conv_integer(REGSEL_A);
DR_NR_B <= conv_integer(REGSEL_B);
DR_NR_C <= conv_integer(REGSEL_C);
-- Output Multiplexer A and B:
DATA_OUT_A <= DR(DR_NR_A);
DATA_OUT_B <= DR(DR_NR_B);
DATA_OUT_C <= DR(DR_NR_C);
REGISTERS: process(RESETn, CLK, DR_NR_B, DR)
-- This process provides data transfer to the respective registers (write).
-- The MOVEM and MOVEQ require a sign extended source data.
-- The BYTE size is not allowed for MOVEM .
begin
if RESETn = '0' then
for i in 0 to 7 loop
DR(i) <= (others => '0');
end loop;
elsif CLK = '1' and CLK' event then
if DR_WR = '1' then
if OP = DIVS or OP = DIVU then
case OP_SIZE is
when WORD =>
DR(DR_NR_A) <= DATA_IN_A;
when others => -- LONG.
if DIV_MUL_32n64 = '0' and DR(DR_NR_A) = DR(DR_NR_B) then -- Long 1.
DR(DR_NR_A) <= DATA_IN_A; -- Quotient returned.
else -- Long 2, 3.
DR(DR_NR_A) <= DATA_IN_A;
DR(DR_NR_B) <= DATA_IN_B;
end if;
end case;
elsif OP = MULS or OP = MULU then
if OP_SIZE = WORD then
DR(DR_NR_A) <= DATA_IN_A;
elsif DIV_MUL_32n64 = '0' then -- Long 1.
DR(DR_NR_A) <= DATA_IN_A;
else -- Long 2.
DR(DR_NR_A) <= DATA_IN_A;
DR(DR_NR_B) <= DATA_IN_B;
end if;
elsif OP = MOVE or OP = MOVEP then
case OP_SIZE is
when LONG => DR(DR_NR_A) <= DATA_IN_A;
when WORD => DR(DR_NR_A)(15 downto 0) <= DATA_IN_A(15 downto 0);
when BYTE => DR(DR_NR_A)(7 downto 0) <= DATA_IN_A(7 downto 0);
end case;
elsif OP = MOVEQ then -- Sign extended.
for i in 31 downto 8 loop
DR(DR_NR_B)(i) <= DATA_IN_B(7);
end loop;
DR(DR_NR_B)(7 downto 0) <= DATA_IN_B(7 downto 0);
elsif OP = MOVEM then -- Sign extended.
if OP_SIZE = WORD then
for i in 31 downto 16 loop
DR(DR_NR_B)(i) <= DATA_IN_B(15);
end loop;
DR(DR_NR_B)(15 downto 0) <= DATA_IN_B(15 downto 0);
else
DR(DR_NR_B) <= DATA_IN_B;
end if;
elsif OP = EXTW or OP = SWAP then
DR(DR_NR_B) <= DATA_IN_B;
else
-- Depending on the size to be written, not all bits of a register
-- are affected.
case OP_SIZE is
when LONG => DR(DR_NR_B) <= DATA_IN_B;
when WORD => DR(DR_NR_B)(15 downto 0) <= DATA_IN_B(15 downto 0);
when Byte => DR(DR_NR_B)(7 downto 0) <= DATA_IN_B(7 downto 0);
end case;
end if;
-- Exchange the content of data registers:
elsif DR_EXG = '1' and OP_MODE = "01000" then -- Exchange two data registers.
DR(DR_NR_B) <= DATA_IN_A;
DR(DR_NR_A) <= DATA_IN_B;
elsif DR_EXG = '1' and OP_MODE = "10001" then -- Exchange a data and an address register.
DR(DR_NR_A) <= DATA_IN_A;
-- And decrement:
elsif DR_DEC = '1' then
DR(DR_NR_B)(15 downto 0) <= DR(DR_NR_B)(15 downto 0) - '1'; -- Used by the DBcc operation.
end if;
end if;
-- Test condition for the DBcc operation:
case DR(DR_NR_B)(15 downto 0) is
when x"FFFF" => DBcc_COND <= true; -- This is signed -1.
when others => DBcc_COND <= false;
end case;
end process REGISTERS;
end BEHAVIOR;

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----------------------------------------------------------------------
---- ----
---- MC68000 compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- This model provides an opcode and bus timing compatible ip ----
---- core compared to Motorola's MC68000 microprocessor. ----
---- ----
---- This file contains the interrupt control unit. ----
---- ----
---- ----
---- Description: ----
---- The interrupt control module is responsible for the inter- ----
---- rupt management of the external and internal interrupts and ----
---- for EXCEPTIONs processing. It manages auto-vectored inter- ----
---- rupt cycles, priority resolving and correct vector numbers ----
---- creation. ----
---- There are different kinds of interrupt sources which require ----
---- some special treatment: the RESET_CPU is released by exter- ----
---- nal logic. The exception state machine therefore has to ----
---- wait, once released, until this interrupt is released again. ----
---- Interrupts, allowing the operation processing to finish the ----
---- current operation, have to wait for the CTRL_RDY signal. ----
---- The bus error exception starts the exception handler state ----
---- machine. In this case, there is no need to wait for the bus ----
---- error to withdrawn. It is assumed, that the bus error is ----
---- released by the bus interface logic during the exception ----
---- processing takes place. Double bus errors / address errors ----
---- cause the processor to enter the 'HALT' state. ----
---- ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, or (at your option) any later ----
---- version. ----
---- ----
---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, write to the Free ----
---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6B 2006/12/24 WF
-- Initial Release.
-- Revision 2K7A 2007/05/31 WF
-- Updated all modules.
-- Revision 2K7B 2007/12/24 WF
-- See the 68K00 top level file.
-- Revision 2K8A 2008/07/14 WF
-- See the 68K00 top level file.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity WF68K00IP_INTERRUPT_CONTROL is
port (
CLK : in bit;
RESETn : in bit; -- Core reset.
RESET_CPUn : in bit; -- Internal reset used for CPU initialization.
BERR : in bit; -- Bus error detection.
HALTn : in std_logic;
-- Data and address bus:
ADR_IN : in std_logic_vector(31 downto 0);
USE_SSP_ADR : out bit;
ADR_EN_VECTOR : out bit;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
DATA_EN : out bit;
-- Bus interface controls:
RWn : in bit_vector(0 downto 0);
RD_BUS : out bit;
WR_BUS : out bit;
HALT_EN : out bit;
FC_IN : in std_logic_vector(2 downto 0);
FC_OUT : out std_logic_vector(2 downto 0);
FC_EN : out bit;
SEL_BUFF_A_LO : out bit; -- Select data A buffer low word.
SEL_BUFF_A_HI : out bit; -- Select data A buffer high word.
-- Address register controls
-- (Address reisters, status register and program counter):
STATUS_REG_IN : in std_logic_vector(15 downto 0);
PC : in std_logic_vector(31 downto 0);
INIT_STATUS : out bit;
PRESET_IRQ_MASK : out bit;
SSP_DEC : out bit;
SSP_INIT : out bit;
PC_INIT : out bit;
-- Operation decoder stuff:
BIW_0 : in std_logic_vector(15 downto 0); -- First instruction word.
-- Control state machine signals:
BUS_CYC_RDY : in bit;
CTRL_RDY : in bit; -- Main controller finished an execution.
CTRL_EN : out bit; -- Enable main controller.
EXEC_ABORT : out bit; -- Abort the current execution.
EXEC_RESUME : out bit; -- Resume operation processing (STOP).
-- Interrupt controls:
IRQ : in std_logic_vector(2 downto 0);
AVECn : in bit; -- Originally 68Ks use VPAn.
IRQ_SAVE : out bit;
INT_VECT : out std_logic_vector(9 downto 0); -- Interrupt vector number.
USE_INT_VECT : out bit;
-- Trap signals:
TRAP_AERR : in bit; -- Address error indication.
TRAP_OP : in bit; -- TRAP instruction.
TRAP_VECTOR : in std_logic_vector(3 downto 0); -- Vector of the TRAP instruction.
TRAP_V : in bit; -- TRAPV instruction.
TRAP_CHK : in bit;
TRAP_DIVZERO : in bit;
TRAP_ILLEGAL : in bit;
TRAP_1010 : in bit; -- Unimplemented instructions.
TRAP_1111 : in bit; -- Unimplemented instructions.
TRAP_TRACE : in bit;
TRAP_PRIV : in bit
);
end entity WF68K00IP_INTERRUPT_CONTROL;
architecture BEHAVIOR of WF68K00IP_INTERRUPT_CONTROL is
type EX_STATES is (IDLE, WAIT_CTRL_RDY, INIT, VECT_NR, GET_VECTOR, STACK_MISC, STACK_ACCESS_ADR_HI,
STACK_ACCESS_ADR_LO, STACK_INSTRUCTION, STACK_STATUS, STACK_PC_HI, STACK_PC_LO,
UPDATE_SSP_HI, UPDATE_SSP_LO, UPDATE_PC_HI, UPDATE_PC_LO, HALT);
type EXCEPTIONS is (EX_RESET, EX_BUS_ERR, EX_ADR_ERR, EX_ILLEGAL, EX_DIVZERO, EX_CHK, EX_TRAPV,
EX_PRIV, EX_TRACE, EX_1010, EX_1111, EX_TRAP, EX_INT, EX_NONE);
signal EX_STATE : EX_STATES;
signal NEXT_EX_STATE : EX_STATES;
signal EXCEPTION_Q : EXCEPTIONS; -- Currently executed exception.
signal TMP_CPY : bit;
signal STATUS_REG_TMP : std_logic_vector(15 downto 0);
signal RWn_TMP : std_logic_vector(0 downto 0);
signal FC_TMP : std_logic_vector(2 downto 0);
signal INSTRn : std_logic;
signal ADR_TMP : std_logic_vector(31 downto 0);
signal INC_TMP_VECTOR : bit;
signal EX_P_RESET : bit; -- ..._P are the pending exceptions.
signal EX_P_ADR_ERR : bit;
signal EX_P_BUS_ERR : bit;
signal EX_P_TRACE : bit;
signal EX_P_INT : bit;
signal EX_P_ILLEGAL : bit;
signal EX_P_1010 : bit;
signal EX_P_1111 : bit;
signal EX_P_PRIV : bit;
signal EX_P_TRAP : bit;
signal EX_P_TRAPV : bit;
signal EX_P_CHK : bit;
signal EX_P_DIVZERO : bit;
signal FORCE_HALT : boolean;
begin
-- The processor gets halted, if a bus error occurs in the stacking or updating states during
-- the exception processing of a bus error, an address error or a reset.
HALT_EN <= '1' when EX_STATE = HALT else '0';
FORCE_HALT <= true when EX_STATE /= IDLE and (BERR = '1' or TRAP_AERR = '1') and
(EXCEPTION_Q = EX_RESET or EXCEPTION_Q = EX_ADR_ERR or EXCEPTION_Q = EX_BUS_ERR) else false;
-- This is the flag which enables the main execution processing state machine. It is enabled, if there
-- is no pending interrupt and if the interrupt exception handler state machine is inactive.
CTRL_EN <= '1' when EX_STATE = IDLE and
EX_P_RESET = '0' and EX_P_ADR_ERR = '0' and EX_P_BUS_ERR = '0' and
EX_P_TRACE = '0' and EX_P_INT = '0' and EX_P_ILLEGAL = '0' and EX_P_1010 = '0' and
EX_P_1111 = '0' and EX_P_PRIV = '0' and EX_P_TRAP = '0' and EX_P_TRAPV = '0' and
EX_P_CHK = '0' and EX_P_DIVZERO = '0' else '0';
-- Flag, if the processor is executing an instruction or a type 0 or 1 exception.
-- 0: instruction, 1: exception.
with EXCEPTION_Q select
INSTRn <= '1' when EX_RESET | EX_ADR_ERR | EX_BUS_ERR,
'0' when others;
-- IACK cycle resides in the CPU space, the RESET resides in the supervisor
-- program space and all others reside in the supervisor data space.
FC_OUT <= "111" when EX_STATE = GET_VECTOR else -- IACK space cycle.
"110" when EX_STATE = UPDATE_SSP_HI or EX_STATE = UPDATE_SSP_LO else
"110" when EX_STATE = UPDATE_PC_HI or EX_STATE = UPDATE_PC_LO else
"101";
FC_EN <= '0' when EX_STATE = IDLE else
'0' when EX_STATE = WAIT_CTRL_RDY else
'0' when EX_STATE = INIT else
'0' when EX_STATE = VECT_NR else '1';
USE_SSP_ADR <= '1' when EX_STATE = STACK_MISC else
'1' when EX_STATE = STACK_ACCESS_ADR_HI else
'1' when EX_STATE = STACK_ACCESS_ADR_LO else
'1' when EX_STATE = STACK_INSTRUCTION else
'1' when EX_STATE = STACK_STATUS else
'1' when EX_STATE = STACK_PC_HI else
'1' when EX_STATE = STACK_PC_LO else '0';
SEL_BUFF_A_LO <= '1' when EX_STATE = UPDATE_SSP_LO else
'1' when EX_STATE = UPDATE_PC_LO else '0';
SEL_BUFF_A_HI <= '1' when EX_STATE = UPDATE_SSP_HI else
'1' when EX_STATE = UPDATE_PC_HI else '0';
ADR_EN_VECTOR <= '1' when EX_STATE = GET_VECTOR else '0'; -- IACK space cycle.
with EX_STATE select
RD_BUS <= '1' when GET_VECTOR | UPDATE_SSP_HI | UPDATE_SSP_LO | UPDATE_PC_HI | UPDATE_PC_LO, '0' when others;
with EX_STATE select
WR_BUS <= '1' when STACK_MISC | STACK_ACCESS_ADR_HI | STACK_ACCESS_ADR_LO | STACK_INSTRUCTION,
'1' when STACK_STATUS | STACK_PC_HI | STACK_PC_LO, '0' when others;
DATA_OUT <= "00000000000" & RWn_TMP & INSTRn & FC_TMP when EX_STATE = STACK_MISC else
ADR_TMP(31 downto 16) when EX_STATE = STACK_ACCESS_ADR_HI else
ADR_TMP(15 downto 0) when EX_STATE = STACK_ACCESS_ADR_LO else
BIW_0 when EX_STATE = STACK_INSTRUCTION else
STATUS_REG_TMP when EX_STATE = STACK_STATUS else
PC(31 downto 16) when EX_STATE = STACK_PC_HI else
PC(15 downto 0) when EX_STATE = STACK_PC_LO else (others => '-'); -- Dummy, don't care.
DATA_EN <= '1' when EX_STATE = STACK_MISC else
'1' when EX_STATE = STACK_ACCESS_ADR_HI else
'1' when EX_STATE = STACK_ACCESS_ADR_LO else
'1' when EX_STATE = STACK_INSTRUCTION else
'1' when EX_STATE = STACK_STATUS else
'1' when EX_STATE = STACK_PC_HI else
'1' when EX_STATE = STACK_PC_LO else '0';
-- Resume the STOP operation, when an external interrupt is going
-- to be processed.
EXEC_RESUME <= '1' when EX_P_INT = '1' else '0';
PENDING: process(RESETn, CLK)
-- The exceptions which occurs are stored in this pending register until the
-- interrupt handler handled the respective exception.
-- The TRAP_PRIV, TRAP_1010, TRAP_1111, TRAP_ILLEGAL, TRAP_OP and TRAP_V may be a strobe
-- of 1 clock period. All others must be strobes of 1 clock period.
begin
if RESETn = '0' then
EX_P_RESET <= '0';
EX_P_ADR_ERR <= '0';
EX_P_BUS_ERR <= '0';
EX_P_TRACE <= '0';
EX_P_INT <= '0';
EX_P_ILLEGAL <= '0';
EX_P_1010 <= '0';
EX_P_1111 <= '0';
EX_P_PRIV <= '0';
EX_P_TRAP <= '0';
EX_P_TRAPV <= '0';
EX_P_CHK <= '0';
EX_P_DIVZERO <= '0';
elsif CLK = '1' and CLK' event then
if RESET_CPUn = '0' then
EX_P_RESET <= '1';
elsif EX_STATE = UPDATE_PC_HI and BUS_CYC_RDY = '1' and EXCEPTION_Q = EX_RESET then
EX_P_RESET <= '0';
end if;
--
if TRAP_AERR = '1' then
EX_P_ADR_ERR <= '1';
elsif EX_STATE = UPDATE_PC_HI and BUS_CYC_RDY = '1' and EXCEPTION_Q = EX_ADR_ERR then
EX_P_ADR_ERR <= '0';
elsif RESET_CPUn = '0' then
EX_P_ADR_ERR <= '0';
end if;
--
if BERR = '1' and HALTn = '1' and EX_STATE /= GET_VECTOR then
-- Do not store the bus error during the interrupt acknowledge
-- cycle (GET_VECTOR).
EX_P_BUS_ERR <= '1';
elsif EX_STATE = UPDATE_PC_HI and BUS_CYC_RDY = '1' and EXCEPTION_Q = EX_BUS_ERR then
EX_P_BUS_ERR <= '0';
elsif RESET_CPUn = '0' then
EX_P_BUS_ERR <= '0';
end if;
--
if TRAP_TRACE = '1' then
EX_P_TRACE <= '1';
elsif EX_STATE = UPDATE_PC_HI and BUS_CYC_RDY = '1' and EXCEPTION_Q = EX_TRACE then
EX_P_TRACE <= '0';
elsif RESET_CPUn = '0' then
EX_P_TRACE <= '0';
end if;
--
if IRQ = "111" then -- Level 7 is nonmaskable ...
EX_P_INT <= '1';
elsif STATUS_REG_IN(10 downto 8) < IRQ then
EX_P_INT <= '1';
elsif EX_STATE = GET_VECTOR then
EX_P_INT <= '0';
elsif RESET_CPUn = '0' then
EX_P_INT <= '0';
end if;
--
-- The following six traps never appear at the same time:
if TRAP_1010 = '1' then
EX_P_1010 <= '1';
elsif TRAP_1111 = '1' then
EX_P_1111 <= '1';
elsif TRAP_ILLEGAL = '1' then
EX_P_ILLEGAL <= '1';
elsif TRAP_PRIV = '1' then
EX_P_PRIV <= '1';
elsif TRAP_OP = '1' then
EX_P_TRAP <= '1';
elsif TRAP_V = '1' then
EX_P_TRAPV <= '1';
elsif (EX_STATE = UPDATE_PC_HI and BUS_CYC_RDY = '1') or RESET_CPUn = '0' then
case EXCEPTION_Q is
when EX_PRIV | EX_1010 | EX_1111 | EX_ILLEGAL | EX_TRAP | EX_TRAPV =>
EX_P_PRIV <= '0';
EX_P_1010 <= '0';
EX_P_1111 <= '0';
EX_P_ILLEGAL <= '0';
EX_P_TRAP <= '0';
EX_P_TRAPV <= '0';
when others =>
null;
end case;
end if;
--
if TRAP_CHK = '1' then
EX_P_CHK <= '1';
elsif EX_STATE = UPDATE_PC_HI and BUS_CYC_RDY = '1' and EXCEPTION_Q = EX_CHK then
EX_P_CHK <= '0';
elsif RESET_CPUn = '0' then
EX_P_CHK <= '0';
end if;
--
if TRAP_DIVZERO = '1' then
EX_P_DIVZERO <= '1';
elsif EX_STATE = UPDATE_PC_HI and BUS_CYC_RDY = '1' and EXCEPTION_Q = EX_DIVZERO then
EX_P_DIVZERO <= '0';
elsif RESET_CPUn = '0' then
EX_P_DIVZERO <= '0';
end if;
end if;
end process PENDING;
STORE_CURRENT_EXCEPTION: process(RESETn, CLK)
-- The exceptions which occurs are stored in the following flags until the
-- interrupt handler handled the respective exception.
-- This process also stores the current processed exception for further use.
-- The update takes place in the IDLE EX_STATE.
begin
if RESETn = '0' then
EXCEPTION_Q <= EX_NONE;
elsif CLK = '1' and CLK' event then
if EX_STATE = IDLE and EX_P_RESET = '1' then
EXCEPTION_Q <= EX_RESET;
elsif EX_STATE = IDLE and EX_P_ADR_ERR = '1' then
EXCEPTION_Q <= EX_ADR_ERR;
elsif EX_STATE = IDLE and EX_P_BUS_ERR = '1' and BERR = '1' then
EXCEPTION_Q <= EX_NONE; -- Wait until BERR is negated.
elsif EX_STATE = IDLE and EX_P_BUS_ERR = '1' then
EXCEPTION_Q <= EX_BUS_ERR;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_ILLEGAL = '1' then
EXCEPTION_Q <= EX_ILLEGAL;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_1010 = '1' then
EXCEPTION_Q <= EX_1010;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_1111 = '1' then
EXCEPTION_Q <= EX_1111;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_PRIV = '1' then
EXCEPTION_Q <= EX_PRIV;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_TRAP = '1' then
EXCEPTION_Q <= EX_TRAP;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_TRAPV = '1' then
EXCEPTION_Q <= EX_TRAPV;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_CHK = '1' then
EXCEPTION_Q <=EX_CHK;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_DIVZERO = '1' then
EXCEPTION_Q <= EX_DIVZERO;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_TRACE = '1' then
EXCEPTION_Q <= EX_TRACE;
elsif EX_STATE = WAIT_CTRL_RDY and CTRL_RDY = '1' and EX_P_INT = '1' then
EXCEPTION_Q <= EX_INT;
elsif NEXT_EX_STATE = IDLE then
EXCEPTION_Q <= EX_NONE;
end if;
end if;
end process STORE_CURRENT_EXCEPTION;
P_TMP_CPY: process (CLK)
-- For the most interrupts, a status register copy is necessary.
-- This is the register for a temporary copy of the status register
-- made in the first step of the exception processing. This copy is
-- in the third step written to the stack pointer, together with the
-- other information.
-- In the same manner the read write, the function code and the
-- address information is saved.
-- The temporary copies are necessary to give the bus controller in
-- case of a bus error enough time to terminate the current bus cycle,
-- means, no other bus access like status register stacking should
-- appear immediately after the bus error occurs.
variable SR_MEM: std_logic_vector(9 downto 0);
begin
if CLK = '1' and CLK' event then
if TMP_CPY = '1' then
SR_MEM := STATUS_REG_IN(15) & STATUS_REG_IN(13) & STATUS_REG_IN(10 downto 8) & STATUS_REG_IN(4 downto 0);
RWn_TMP <= To_StdLogicVector(RWn);
FC_TMP <= FC_IN;
ADR_TMP <= ADR_IN;
end if;
end if;
STATUS_REG_TMP <= SR_MEM(9) & '0' & SR_MEM(8) & "00" & SR_MEM(7 downto 5) & "000" & SR_MEM(4 downto 0);
end process P_TMP_CPY;
INT_VECTOR: process(RESETn, CLK)
variable VECTOR_No : std_logic_vector(7 downto 0);
variable VECT_TMP : std_logic_vector(1 downto 0);
-- This process provides the interrupt vector number INT_VECT, which
-- is determined during interrupt processing.
begin
if RESETn = '0' then
VECTOR_No := (others => '0'); -- Dummy assignement.
elsif CLK = '1' and CLK' event then
if EX_STATE = VECT_NR or EX_STATE = GET_VECTOR then
case EXCEPTION_Q is
when EX_RESET => VECTOR_No := x"00";
when EX_BUS_ERR => VECTOR_No := x"02";
when EX_ADR_ERR => VECTOR_No := x"03";
when EX_ILLEGAL => VECTOR_No := x"04";
when EX_DIVZERO => VECTOR_No := x"05";
when EX_CHK => VECTOR_No := x"06";
when EX_TRAPV => VECTOR_No := x"07";
when EX_PRIV => VECTOR_No := x"08";
when EX_TRACE => VECTOR_No := x"09";
when EX_1010 => VECTOR_No := x"0A";
when EX_1111 => VECTOR_No := x"0B";
-- The uninitialized interrupt vector number x"0F"
-- is provided by the peripheral interrupt source
-- during the auto vector bus cycle.
when EX_INT =>
if BUS_CYC_RDY = '1' and BERR = '1' then
VECTOR_No := x"18"; -- Spurious interrupt.
elsif BUS_CYC_RDY = '1' and AVECn = '0' then
VECTOR_No := x"18" + STATUS_REG_IN(10 downto 8); -- Autovector.
elsif BUS_CYC_RDY = '1' then
-- This is the vector number provided by the device.
-- If the returned Vector Number is x"0F" then it is the
-- uninitialized interrupt vector due to non initia-
-- lized vector register of the peripheral device.
VECTOR_No := DATA_IN; -- Non autovector.
end if;
when EX_TRAP => VECTOR_No := x"2" & TRAP_VECTOR;
when others => VECTOR_No := (others => '-'); -- Don't care.
end case;
VECT_TMP := "00";
elsif INC_TMP_VECTOR = '1' then
-- Offset for the next two initial bytes during system initialisation.
VECT_TMP := VECT_TMP + '1'; -- Increment.
end if;
end if;
--
INT_VECT <= (VECTOR_No & "00") + (VECT_TMP & '0');
end process INT_VECTOR;
EXCEPTION_HANDLER_REG: process(RESETn, CLK)
-- This is the register portion of the exception control state machine.
begin
if RESETn = '0' then
EX_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
if RESET_CPUn = '0' then
EX_STATE <= IDLE;
elsif FORCE_HALT = true then
EX_STATE <= HALT;
else
EX_STATE <= NEXT_EX_STATE;
end if;
end if;
end process EXCEPTION_HANDLER_REG;
EXCEPTION_HANDLER_DEC: process(EX_STATE, EX_P_RESET, EX_P_ADR_ERR, EX_P_BUS_ERR, EX_P_TRACE, EX_P_INT, EX_P_ILLEGAL,
EX_P_1010, EX_P_1111, EX_P_PRIV, EX_P_TRAP, EX_P_TRAPV, EX_P_CHK, EX_P_DIVZERO, EXCEPTION_Q,
BUS_CYC_RDY, CTRL_RDY, BERR)
-- This is the decoder portion of the exception control state machine.
begin
-- Default assignements:
EXEC_ABORT <= '0';
TMP_CPY <= '0';
IRQ_SAVE <= '0';
INIT_STATUS <= '0';
PRESET_IRQ_MASK <= '0';
SSP_INIT <= '0';
PC_INIT <= '0';
SSP_DEC <= '0';
USE_INT_VECT <= '0';
INC_TMP_VECTOR <= '0';
case EX_STATE is
when IDLE =>
-- The priority of the exception execution is given by the
-- following construct. Although type 3 commands do not require
-- a prioritization, there is no drawback using these conditions.
-- The spurious interrupt and uninitialized interrupt never appear
-- as basic interrupts and therefore are not an interrupt source.
-- During IDLE, when an interrupt occurs, the status register copy
-- control is asserted and the current interrupt controll is given
-- to the STORE_EXCEPTION process. During bus or address errors,
-- the status register must be copied immediately to recognize
-- the current status for RWn etc. (before the faulty bus cycle is
-- finished).
if EX_P_RESET = '1' then
EXEC_ABORT <= '1';
NEXT_EX_STATE <= INIT;
elsif EX_P_ADR_ERR = '1' then
EXEC_ABORT <= '1';
TMP_CPY <= '1'; -- Immediate copy of the status register.
NEXT_EX_STATE <= INIT;
elsif EX_P_BUS_ERR = '1' and BERR = '1' then -- Wait until BERR is negated.
NEXT_EX_STATE <= IDLE;
elsif EX_P_BUS_ERR = '1' then -- Enter after BERR is negated.
EXEC_ABORT <= '1';
TMP_CPY <= '1'; -- Immediate copy of the status register.
NEXT_EX_STATE <= INIT;
elsif EX_P_TRAP = '1' or EX_P_TRAPV = '1' or EX_P_CHK = '1' or EX_P_DIVZERO = '1' or EX_P_TRACE = '1' then
NEXT_EX_STATE <= WAIT_CTRL_RDY;
elsif EX_P_INT = '1' or EX_P_ILLEGAL = '1' or EX_P_1010 = '1' or EX_P_1111 = '1' or EX_P_PRIV = '1' then
NEXT_EX_STATE <= WAIT_CTRL_RDY;
else -- No exception.
NEXT_EX_STATE <= IDLE;
end if;
when WAIT_CTRL_RDY =>
-- In this state, the interrupt machine waits until the current
-- operation execution has finished. The copy of the status register
-- is made after the excecution has finished.
if CTRL_RDY = '1' then
TMP_CPY <= '1'; -- Copy the status register.
NEXT_EX_STATE <= INIT;
else
NEXT_EX_STATE <= WAIT_CTRL_RDY;
end if;
when INIT =>
-- In this state, the supervisor mode is switched on (the S bit is set)
-- and the trace mode is switched off (the T bit is cleared).
INIT_STATUS <= '1';
case EXCEPTION_Q is
when EX_RESET =>
PRESET_IRQ_MASK <= '1';
NEXT_EX_STATE <= VECT_NR;
when EX_INT =>
IRQ_SAVE <= '1';
NEXT_EX_STATE <= GET_VECTOR;
when others => NEXT_EX_STATE <= VECT_NR;
end case;
when VECT_NR =>
-- This state is introduced to control the generation of the vector number
-- for all exceptions except the external interrupts.
case EXCEPTION_Q is
when EX_RESET =>
NEXT_EX_STATE <= UPDATE_SSP_HI; -- Do not stack anything but update the SSP and PC.
when others =>
SSP_DEC <= '1';
NEXT_EX_STATE <= STACK_PC_LO;
end case;
when GET_VECTOR =>
-- This state is intended to determine the vector number for the current process.
-- See also the process EX_VECTOR for the handling of the vector determination.
if BUS_CYC_RDY = '1' then
SSP_DEC <= '1';
NEXT_EX_STATE <= STACK_PC_LO;
else
NEXT_EX_STATE <= GET_VECTOR;
end if;
-- The following states provide writing to the stack pointer or reading
-- the exception vector address from the memory. If there is a bus error
-- or an address error during the read or write cycles, the processor
-- proceeds in two different ways:
-- If the errors occur during a reset, bus error or address error
-- exception processing, there is the case of a double bus fault. In
-- consequence, the processor halts due to catastrophic system failure.
-- If the errors occur during other exception processings, the current
-- processing is aborted and this exception handler state machine will
-- immediately begin with the bus error exception handling.
when STACK_PC_LO =>
if BUS_CYC_RDY = '1' then
SSP_DEC <= '1';
NEXT_EX_STATE <= STACK_PC_HI;
else
NEXT_EX_STATE <= STACK_PC_LO;
end if;
when STACK_PC_HI =>
if BUS_CYC_RDY = '1' then
SSP_DEC <= '1';
NEXT_EX_STATE <= STACK_STATUS;
else
NEXT_EX_STATE <= STACK_PC_HI;
end if;
when STACK_STATUS =>
if BUS_CYC_RDY = '1' then
case EXCEPTION_Q is
when EX_BUS_ERR | EX_ADR_ERR =>
SSP_DEC <= '1';
NEXT_EX_STATE <= STACK_INSTRUCTION;
when others =>
NEXT_EX_STATE <= UPDATE_PC_HI;
end case;
else
NEXT_EX_STATE <= STACK_STATUS;
end if;
when STACK_INSTRUCTION =>
if BUS_CYC_RDY = '1' then
SSP_DEC <= '1';
NEXT_EX_STATE <= STACK_ACCESS_ADR_LO;
else
NEXT_EX_STATE <= STACK_INSTRUCTION;
end if;
when STACK_ACCESS_ADR_LO =>
if BUS_CYC_RDY = '1' then
SSP_DEC <= '1';
NEXT_EX_STATE <= STACK_ACCESS_ADR_HI;
else
NEXT_EX_STATE <= STACK_ACCESS_ADR_LO;
end if;
when STACK_ACCESS_ADR_HI =>
if BUS_CYC_RDY = '1' then
SSP_DEC <= '1';
NEXT_EX_STATE <= STACK_MISC;
else
NEXT_EX_STATE <= STACK_ACCESS_ADR_HI;
end if;
when STACK_MISC =>
if BUS_CYC_RDY = '1' then
NEXT_EX_STATE <= UPDATE_PC_HI;
else
NEXT_EX_STATE <= STACK_MISC;
end if;
when UPDATE_SSP_HI =>
if BUS_CYC_RDY = '1' then
INC_TMP_VECTOR <= '1';
NEXT_EX_STATE <= UPDATE_SSP_LO;
else
NEXT_EX_STATE <= UPDATE_SSP_HI;
end if;
USE_INT_VECT <= '1';
when UPDATE_SSP_LO =>
if BUS_CYC_RDY = '1' then
INC_TMP_VECTOR <= '1';
SSP_INIT <= '1';
NEXT_EX_STATE <= UPDATE_PC_HI;
else
NEXT_EX_STATE <= UPDATE_SSP_LO;
end if;
USE_INT_VECT <= '1';
when UPDATE_PC_HI =>
if BUS_CYC_RDY = '1' then
INC_TMP_VECTOR <= '1';
NEXT_EX_STATE <= UPDATE_PC_LO;
else
NEXT_EX_STATE <= UPDATE_PC_HI;
end if;
USE_INT_VECT <= '1';
when UPDATE_PC_LO =>
if BUS_CYC_RDY = '1' then
PC_INIT <= '1';
NEXT_EX_STATE <= IDLE;
else
NEXT_EX_STATE <= UPDATE_PC_LO;
end if;
USE_INT_VECT <= '1';
when HALT =>
-- Processor halted, Double bus error!
NEXT_EX_STATE <= HALT;
end case;
end process EXCEPTION_HANDLER_DEC;
end BEHAVIOR;

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----------------------------------------------------------------------
---- ----
---- MC68000 compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- This model provides an opcode and bus timing compatible ip ----
---- core compared to Motorola's MC68000 microprocessor. ----
---- ----
---- This file is the package file of the ip core. ----
---- ----
---- ----
---- ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, or (at your option) any later ----
---- version. ----
---- ----
---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, write to the Free ----
---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6B 2006/12/24 WF
-- Initial Release.
-- Revision 2K7A 2007/05/31 WF
-- Updated all modules.
-- Revision 2K8A 2008/07/14 WF
-- See the 68K00 top level file.
--
library ieee;
use ieee.std_logic_1164.all;
package WF68K00IP_PKG is
type EXWORDTYPE is array(0 to 1) of std_logic_vector(15 downto 0);
type OP_SIZETYPE is (LONG, WORD, BYTE); -- Default is Byte.
type D_SIZETYPE is (LONG, WORD, BYTE); -- Displacement size.
-- The OPCODES AND, NOT, OR, ROR and ROL are defined keywords in VHDL. Therefore the assignment is
-- AND_B, NOT_B, OR_B, ROTR and ROTL.
type OP_68K00 is (ABCD, ADD, ADDA, ADDI, ADDQ, ADDX, AND_B, ANDI, ANDI_TO_CCR, ANDI_TO_SR, ASL, ASR, Bcc, BCHG, BCLR,
BRA, BSET, BSR, BTST, CHK, CLR, CMP, CMPA, CMPI, CMPM, DBcc, DIVS, DIVU, EOR, EORI, EORI_TO_CCR,
EORI_TO_SR, EXG, EXTW, ILLEGAL, JMP, JSR, LEA, LINK, LSL, LSR, MOVE, MOVEA, MOVE_FROM_CCR, MOVE_TO_CCR,
MOVE_FROM_SR, MOVE_TO_SR, MOVE_USP, MOVEM, MOVEP, MOVEQ, MULS, MULU, NBCD, NEG, NEGX, NOP, NOT_B,
OR_B, ORI, ORI_TO_CCR, ORI_TO_SR, PEA, RESET, ROTL, ROTR, ROXL, ROXR, RTE, RTR, RTS, SBCD, Scc, STOP,
SUB, SUBA, SUBI, SUBQ, SUBX, SWAP, TAS, TRAP, TRAPV, TST, UNLK, RESERVED, UNIMPLEMENTED);
component WF68K00IP_CONTROL
port (
CLK : in bit;
RESETn : in bit;
SR_CCR_IN : in std_logic_vector(15 downto 0);
C_CODE : in bit_vector(3 downto 0);
REGLISTMASK : in std_logic_vector(15 downto 0);
CTRL_EN : in bit;
EXEC_ABORT : in bit;
DATA_VALID : in bit;
BUS_CYC_RDY : in bit;
CTRL_RDY : out bit;
INIT_STATUS : in bit;
PRESET_IRQ_MASK : in bit;
IRQ : in std_logic_vector(2 downto 0);
IRQ_SAVE : in bit;
XNZVC_IN : in std_logic_vector(4 downto 0);
STATUS_REG_OUT : out std_logic_vector(15 downto 0);
FORCE_BIW2 : in bit;
FORCE_BIW3 : in bit;
EXT_CNT : in integer range 0 to 2;
DEST_EXT_CNT : in integer range 0 to 2;
REGSEL_20 : in std_logic_vector(2 downto 0);
IW_ADR : out integer range 0 to 2;
IW_WR : out bit;
SRC_DESTn : out bit;
EW_WR : out bit;
EW_ADR : out integer range 0 to 1;
RD_BUS : out bit;
WR_BUS : out bit;
RDWR_BUS : out bit;
WR_HI : out bit;
SEL_A_HI : out bit;
SEL_A_MIDHI : out bit;
SEL_A_MIDLO : out bit;
SEL_A_LO : out bit;
SEL_BUFF_A_LO : out bit;
SEL_BUFF_A_HI : out bit;
SEL_BUFF_B_LO : out bit;
SEL_BUFF_B_HI : out bit;
FC_OUT : out std_logic_vector(2 downto 0);
FC_EN : out bit;
PC_INIT : out bit;
PC_WR : out bit;
PC_INC : out bit;
PC_TMP_CLR : out bit;
PC_TMP_INC : out bit;
PC_ADD_DISPL : out bit;
USP_INC : out bit;
SSP_INC : out bit;
USP_DEC : out bit;
SSP_DEC : out bit;
USP_CPY : out bit;
SP_ADD_DISPL : out bit;
ADR_TMP_CLR : out bit;
ADR_TMP_INC : out bit;
AR_INC : out bit;
AR_DEC : out bit;
AR_WR : out bit;
AR_DR_EXG : out bit;
DR_WR : out bit;
DR_DEC : out bit;
SCAN_TRAPS : out bit;
TRAP_PRIV : in bit;
TRAP_TRACE : out bit;
OP : in OP_68K00;
OP_MODE : in std_logic_vector(2 downto 0);
OP_SIZE : in OP_SIZETYPE;
ADR_MODE : in std_logic_vector(2 downto 0);
MOVE_D_AM : in std_logic_vector(2 downto 0);
RESET_RDY : in bit;
OP_BUSY : in bit;
MEM_SHFT : in bit;
SHFT_BUSY : in bit;
DR : in bit;
RM : in bit;
DIV_MUL_32n64 : in bit;
EXEC_RESUME : in bit;
DBcc_COND : in boolean;
USE_SP_ADR : out bit;
OP_START : out bit;
TRAP_CHK_EN : out bit;
MOVEM_REGSEL : out std_logic_vector(2 downto 0);
MOVEM_ADn : out bit;
Scc_COND : out boolean;
SHIFTER_LOAD : out bit;
CHK_PC : out bit;
CHK_ADR : out bit;
SBIT : out bit;
UNLK_SP_An : out bit;
RESET_EN : out bit
);
end component;
component WF68K00IP_OPCODE_DECODER
port (
CLK : in bit;
RESETn : in bit;
DATA_IN : in std_logic_vector(15 downto 0);
SBIT : in bit;
OV : in std_logic;
IW_ADR : in integer range 0 to 2;
IW_WR : in bit;
FORCE_BIW2 : out bit;
FORCE_BIW3 : out bit;
EXT_CNT : out integer range 0 to 2;
DEST_EXT_CNT : out integer range 0 to 2;
DR : out bit;
RM : out bit;
IR : out bit;
OP : out OP_68K00;
OP_SIZE : out OP_SIZETYPE;
OP_MODE : out std_logic_vector(4 downto 0);
BIW_0 : out std_logic_vector(15 downto 0);
REGSEL_20 : out std_logic_vector(2 downto 0);
REGSEL_119 : out std_logic_vector(2 downto 0);
REGSEL_INDEX : out std_logic_vector(2 downto 0);
DATA_IMMEDIATE : out std_logic_vector(31 downto 0);
TRAP_VECTOR : out std_logic_vector(3 downto 0);
C_CODE : out bit_vector(3 downto 0);
MEM_SHFT : out bit;
REGLISTMASK : out std_logic_vector(15 downto 0);
BITPOS_IM : out bit;
BIT_POS : out std_logic_vector(4 downto 0);
DIV_MUL_32n64 : out bit;
REG_Dlq : out std_logic_vector(2 downto 0);
REG_Dhr : out std_logic_vector(2 downto 0);
SCAN_TRAPS : in bit;
TRAP_ILLEGAL : out bit;
TRAP_1010 : out bit;
TRAP_1111 : out bit;
TRAP_PRIV : out bit;
TRAP_OP : out bit;
TRAP_V : out bit;
EW_WR : in bit;
EW_ADR : in integer range 0 to 1;
SRC_DESTn : in bit;
EXWORD : out EXWORDTYPE;
DEST_EXWORD : out EXWORDTYPE;
ADR_MODE : out std_logic_vector(2 downto 0);
MOVE_D_AM : out std_logic_vector(2 downto 0);
EXT_DSIZE : out D_SIZETYPE;
SEL_DISPLACE_BIW : out bit;
DISPLACE_BIW : out std_logic_vector(31 downto 0)
);
end component;
component WF68K00IP_ADDRESS_REGISTERS
port (
CLK : in bit;
RESETn : in bit;
ADATA_IN : in std_logic_vector(31 downto 0);
REGSEL_B : in std_logic_vector(2 downto 0);
REGSEL_A : in std_logic_vector(2 downto 0);
ADR_REG_QB : out std_logic_vector(31 downto 0);
ADR_REG_QA : out std_logic_vector(31 downto 0);
USP_OUT : out std_logic_vector(31 downto 0);
SSP_OUT : out std_logic_vector(31 downto 0);
PC_OUT : out std_logic_vector(31 downto 0);
EXWORD : in EXWORDTYPE;
DEST_EXWORD : in EXWORDTYPE;
DR : in bit;
USP_CPY : in bit;
AR_EXG : in bit;
AR_WR : in bit;
USP_INC : in bit;
USP_DEC : in bit;
ADR_TMP_CLR : in bit;
ADR_TMP_INC : in bit;
AR_INC : in bit;
AR_DEC : in bit;
SSP_INC : in bit;
SSP_DEC : in bit;
SSP_INIT : in bit;
SP_ADD_DISPL : in bit;
USE_SP_ADR : in bit;
USE_SSP_ADR : in bit;
PC_WR : in bit;
PC_INC : in bit;
PC_TMP_CLR : in bit;
PC_TMP_INC : in bit;
PC_INIT : in bit;
PC_ADD_DISPL : in bit;
SRC_DESTn : in bit;
SBIT : in bit;
OP : in OP_68K00;
OP_SIZE : in OP_SIZETYPE;
OP_MODE : in std_logic_vector(4 downto 0);
OP_START : in bit;
ADR_MODE : in std_logic_vector(2 downto 0);
MOVE_D_AM : in std_logic_vector(2 downto 0);
FORCE_BIW2 : in bit;
FORCE_BIW3 : in bit;
EXT_DSIZE : in D_SIZETYPE;
SEL_DISPLACE_BIW : in bit;
DISPLACE_BIW : in std_logic_vector(31 downto 0);
REGSEL_INDEX : in std_logic_vector(2 downto 0);
INDEX_D_IN : in std_logic_vector(31 downto 0);
CHK_PC : in bit;
CHK_ADR : in bit;
TRAP_AERR : out bit;
ADR_EFF : out std_logic_vector(31 downto 0)
);
end component;
component WF68K00IP_DATA_REGISTERS
port (
CLK : in bit;
RESETn : in bit;
DATA_IN_A : in std_logic_vector(31 downto 0);
DATA_IN_B : in std_logic_vector(31 downto 0);
REGSEL_A : in std_logic_vector(2 downto 0);
REGSEL_B : in std_logic_vector(2 downto 0);
REGSEL_C : in std_logic_vector(2 downto 0);
DIV_MUL_32n64 : in bit;
DATA_OUT_A : out std_logic_vector(31 downto 0);
DATA_OUT_B : out std_logic_vector(31 downto 0);
DATA_OUT_C : out std_logic_vector(31 downto 0);
DR_EXG : in bit;
DR_DEC : in bit;
DR_WR : in bit;
OP : in OP_68K00;
OP_SIZE : in OP_SIZETYPE;
OP_MODE : in std_logic_vector(4 downto 0);
DBcc_COND : out boolean
);
end component;
component WF68K00IP_ALU
port (
RESETn : in bit;
CLK : in bit;
ADR_MODE : in std_logic_vector(2 downto 0);
OP_SIZE : in OP_SIZETYPE;
OP : in OP_68K00;
XNZVC_IN : in std_logic_vector(4 downto 0);
XNZVC_OUT : out std_logic_vector(4 downto 0);
OP_IN_S : in std_logic_vector(31 downto 0);
OP_IN_D_HI : in std_logic_vector(31 downto 0);
OP_IN_D_LO : in std_logic_vector(31 downto 0);
RESULT_HI : out std_logic_vector(31 downto 0);
RESULT_LO : out std_logic_vector(31 downto 0);
OP_START : in bit;
TRAP_CHK_EN : in bit;
DIV_MUL_32n64 : in bit;
OP_BUSY : out bit;
TRAP_CHK : out bit;
TRAP_DIVZERO : out bit
);
end component;
component WF68K00IP_SHIFTER
port (
CLK : in bit;
RESETn : in bit;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
OP : in OP_68K00;
OP_SIZE : in OP_SIZETYPE;
BIT_POS : in std_logic_vector(4 downto 0);
CNT_NR : in std_logic_vector(5 downto 0);
SHFT_BREAKn : in bit;
SHIFTER_LOAD : in bit;
SHFT_BUSY : out bit;
XNZVC_IN : in std_logic_vector(4 downto 0);
XNZVC_OUT : out std_logic_vector(4 downto 0)
);
end component;
component WF68K00IP_INTERRUPT_CONTROL
port (
CLK : in bit;
RESETn : in bit;
RESET_CPUn : in bit;
BERR : in bit;
HALTn : in std_logic;
ADR_IN : in std_logic_vector(31 downto 0);
USE_SSP_ADR : out bit;
ADR_EN_VECTOR : out bit;
DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
DATA_EN : out bit;
RWn : in bit_vector(0 downto 0);
RD_BUS : out bit;
WR_BUS : out bit;
HALT_EN : out bit;
FC_IN : in std_logic_vector(2 downto 0);
FC_OUT : out std_logic_vector(2 downto 0);
FC_EN : out bit;
SEL_BUFF_A_LO : out bit;
SEL_BUFF_A_HI : out bit;
STATUS_REG_IN : in std_logic_vector(15 downto 0);
PC : in std_logic_vector(31 downto 0);
INIT_STATUS : out bit;
PRESET_IRQ_MASK : out bit;
SSP_DEC : out bit;
SSP_INIT : out bit;
PC_INIT : out bit;
BIW_0 : in std_logic_vector(15 downto 0);
BUS_CYC_RDY : in bit;
CTRL_RDY : in bit;
CTRL_EN : out bit;
EXEC_ABORT : out bit;
EXEC_RESUME : out bit;
IRQ : in std_logic_vector(2 downto 0);
AVECn : in bit;
IRQ_SAVE : out bit;
INT_VECT : out std_logic_vector(9 downto 0);
USE_INT_VECT : out bit;
TRAP_AERR : in bit;
TRAP_OP : in bit;
TRAP_VECTOR : in std_logic_vector(3 downto 0);
TRAP_V : in bit;
TRAP_CHK : in bit;
TRAP_DIVZERO : in bit;
TRAP_ILLEGAL : in bit;
TRAP_1010 : in bit;
TRAP_1111 : in bit;
TRAP_TRACE : in bit;
TRAP_PRIV : in bit
);
end component;
component WF68K00IP_BUS_INTERFACE
port (
CLK : in bit;
RESETn : in bit;
RESET_INn : in bit;
RESET_OUT_EN : out bit;
RESET_CPUn : out bit;
RESET_EN : in bit;
RESET_RDY : out bit;
DATA_IN : in std_logic_vector(15 downto 0);
SEL_A_HI : in bit;
SEL_A_MIDHI : in bit;
SEL_A_MIDLO : in bit;
SEL_A_LO : in bit;
SEL_BUFF_A_LO : in bit;
SEL_BUFF_A_HI : in bit;
SEL_BUFF_B_LO : in bit;
SEL_BUFF_B_HI : in bit;
SYS_INIT : in bit;
OP_SIZE : in OP_SIZETYPE;
BUFFER_A : out std_logic_vector(31 downto 0);
BUFFER_B : out std_logic_vector(31 downto 0);
DATA_CORE_OUT : out std_logic_vector(15 downto 0);
RD_BUS : in bit;
WR_BUS : in bit;
RDWR_BUS : in bit;
A0 : in std_logic;
BYTEn_WORD : in bit;
EXEC_ABORT : in bit;
BUS_CYC_RDY : out bit;
DATA_VALID : out bit;
DTACKn : in bit;
BERRn : in bit;
AVECn : in bit;
HALTn : in std_logic;
ADR_EN : out bit;
WR_HI : in bit;
HI_WORD_EN : out bit;
HI_BYTE_EN : out bit;
LO_BYTE_EN : out bit;
FC_EN : out bit;
ASn : out bit;
AS_EN : out bit;
UDSn : out bit;
UDS_EN : out bit;
LDSn : out bit;
LDS_EN : out bit;
RWn : out bit;
RW_EN : out bit;
VPAn : in bit;
VMAn : out bit;
VMA_EN : out bit;
E : out bit;
BRn : in bit;
BGACKn : in bit;
BGn : out bit
);
end component;
end WF68K00IP_PKG;

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----------------------------------------------------------------------
---- ----
---- MC68000 compatible IP Core ----
---- ----
---- This file is part of the SUSKA ATARI clone project. ----
---- http://www.experiment-s.de ----
---- ----
---- Description: ----
---- This model provides an opcode and bus timing compatible ip ----
---- core compared to Motorola's MC68000 microprocessor. ----
---- ----
---- This file contains the 68Ks shifter unit. ----
---- ----
---- ----
---- Description: ----
---- This module performs the shifting operations ASL, ASR, LSL, ----
---- LSR, ROL, ROR, ROXL and ROXR as also the bit manipulation ----
---- and test operations BCHG, BCLR, BSET and BTST. ----
---- The timing of the core is as follows: ----
---- All bit manipulation operations are performed by concurrent ----
---- statement modelling which results in immediate bit process- ----
---- ing. Thus, the result is valid one clock cycle after the ----
---- settings for the operands are stable.
---- The shift and rotate operations start with SHIFTER_LOAD. ----
---- The data processing time is depending on the selected number ----
---- of bits and is indicated by the SHFT_BUSY flag. During ----
---- SHFT_BUSY is asserted, the data calculation is in progress. ----
---- The execution time for these operations is n clock ----
---- cycles +2 where n is the desired number of shifts or rotates.----
---- ----
---- ----
---- Author(s): ----
---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2006 - 2008 Wolfgang Foerster ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU General Public ----
---- License as published by the Free Software Foundation; either ----
---- version 2 of the License, or (at your option) any later ----
---- version. ----
---- ----
---- This program is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, write to the Free ----
---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ----
---- Boston, MA 02110-1301, USA. ----
---- ----
----------------------------------------------------------------------
--
-- Revision History
--
-- Revision 2K6B 2006/12/24 WF
-- Initial Release.
-- Revision 2K7A 2007/05/31 WF
-- Updated all modules.
-- Revision 2K7B 2007/12/24 WF
-- See the 68K00 top level file.
-- Revision 2K8A 2008/07/14 WF
-- See the 68K00 top level file.
--
use work.wf68k00ip_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity WF68K00IP_SHIFTER is
port (
CLK : in bit;
RESETn : in bit;
DATA_IN : in std_logic_vector(31 downto 0); -- Operand data.
DATA_OUT : out std_logic_vector(31 downto 0); -- Shifted operand.
OP : in OP_68K00;
OP_SIZE : in OP_SIZETYPE; -- The operand's size.
BIT_POS : in std_logic_vector(4 downto 0); -- Bit position control.
CNT_NR : in std_logic_vector(5 downto 0); -- Count control.
-- Progress controls:
SHFT_BREAKn : in bit;
SHIFTER_LOAD : in bit; -- Strobe of 1 clock pulse.
SHFT_BUSY : out bit;
-- The FLAGS:
XNZVC_IN : in std_logic_vector(4 downto 0);
XNZVC_OUT : out std_logic_vector(4 downto 0)
);
end entity WF68K00IP_SHIFTER;
architecture BEHAVIOR of WF68K00IP_SHIFTER is
type SHIFT_STATES is (IDLE, RUN);
signal SHIFT_STATE : SHIFT_STATES;
signal BIT_OP : std_logic_vector(31 downto 0);
signal SHFT_OP : std_logic_vector(31 downto 0);
signal SHFT_EN : bit;
signal SHFT_X : std_logic;
begin
-- Output multiplexer:
with OP select
DATA_OUT <= BIT_OP when BCHG | BCLR | BSET | BTST,
SHFT_OP when others; -- Valid for ASL | ASR | LSL | LSR | ROTL | ROTR | ROXL | ROXR.
BIT_PROC: process(BIT_POS, OP, BIT_OP, DATA_IN)
-- Bit manipulation operations.
variable BIT_POSITION : integer range 0 to 31;
begin
BIT_POSITION := Conv_Integer(BIT_POS);
--
BIT_OP <= DATA_IN; -- The default is the unmanipulated data.
--
case OP is
when BCHG =>
BIT_OP(BIT_POSITION) <= not DATA_IN(BIT_POSITION);
when BCLR =>
BIT_OP(BIT_POSITION) <= '0';
when BSET =>
BIT_OP(BIT_POSITION) <= '1';
when others =>
BIT_OP <= DATA_IN; -- Dummy, no result required for BTST.
end case;
end process BIT_PROC;
SHIFTER: process(RESETn, CLK)
begin
if RESETn = '0' then
SHFT_OP <= (others => '0');
elsif CLK = '1' and CLK' event then
if SHIFTER_LOAD = '1' then -- Load data in the shifter unit.
SHFT_OP <= DATA_IN; -- Load data for the shift or rotate operations.
elsif SHFT_EN = '1' then -- Shift and rotate operations:
case OP is
when ASL =>
if OP_SIZE = LONG then
SHFT_OP <= SHFT_OP(30 downto 0) & '0';
elsif OP_SIZE = WORD then
SHFT_OP <= x"0000" & SHFT_OP(14 downto 0) & '0';
else -- OP_SIZE = BYTE.
SHFT_OP <= x"000000" & SHFT_OP(6 downto 0) & '0';
end if;
when ASR =>
if OP_SIZE = LONG then
SHFT_OP <= SHFT_OP(31) & SHFT_OP(31 downto 1);
elsif OP_SIZE = WORD then
SHFT_OP <= x"0000" & SHFT_OP(15) & SHFT_OP(15 downto 1);
else -- OP_SIZE = BYTE.
SHFT_OP <= x"000000" & SHFT_OP(7) & SHFT_OP(7 downto 1);
end if;
when LSL =>
if OP_SIZE = LONG then
SHFT_OP <= SHFT_OP(30 downto 0) & '0';
elsif OP_SIZE = WORD then
SHFT_OP <= x"0000" & SHFT_OP(14 downto 0) & '0';
else -- OP_SIZE = BYTE.
SHFT_OP <= x"000000" & SHFT_OP(6 downto 0) & '0';
end if;
when LSR =>
if OP_SIZE = LONG then
SHFT_OP <= '0' & SHFT_OP(31 downto 1);
elsif OP_SIZE = WORD then
SHFT_OP <= x"0000" & '0' & SHFT_OP(15 downto 1);
else -- OP_SIZE = BYTE.
SHFT_OP <= x"000000" & '0' & SHFT_OP(7 downto 1);
end if;
when ROTL =>
if OP_SIZE = LONG then
SHFT_OP <= SHFT_OP(30 downto 0) & SHFT_OP(31);
elsif OP_SIZE = WORD then
SHFT_OP <= x"0000" & SHFT_OP(14 downto 0) & SHFT_OP(15);
else -- OP_SIZE = BYTE.
SHFT_OP <= x"000000" & SHFT_OP(6 downto 0) & SHFT_OP(7);
end if;
-- X not affected;
when ROTR =>
if OP_SIZE = LONG then
SHFT_OP <= SHFT_OP(0) & SHFT_OP(31 downto 1);
elsif OP_SIZE = WORD then
SHFT_OP <= x"0000" & SHFT_OP(0) & SHFT_OP(15 downto 1);
else -- OP_SIZE = BYTE.
SHFT_OP <= x"000000" & SHFT_OP(0) & SHFT_OP(7 downto 1);
end if;
-- X not affected;
when ROXL =>
if OP_SIZE = LONG then
SHFT_OP <= SHFT_OP(30 downto 0) & SHFT_X;
elsif OP_SIZE = WORD then
SHFT_OP <= x"0000" & SHFT_OP(14 downto 0) & SHFT_X;
else -- OP_SIZE = BYTE.
SHFT_OP <= x"000000" & SHFT_OP(6 downto 0) & SHFT_X;
end if;
when ROXR =>
if OP_SIZE = LONG then
SHFT_OP <= SHFT_X & SHFT_OP(31 downto 1);
elsif OP_SIZE = WORD then
SHFT_OP <= x"0000" & SHFT_X & SHFT_OP(15 downto 1);
else -- OP_SIZE = BYTE.
SHFT_OP <= x"000000" & SHFT_X & SHFT_OP(7 downto 1);
end if;
when others => null; -- Unaffected, forbidden.
end case;
end if;
end if;
end process SHIFTER;
P_SHFT_CTRL: process(RESETn, CLK, OP)
-- The variable shift or rotate length requires a control
-- to achieve the correct OPERAND manipulation. This
-- process controls the shift process and asserts the
-- SHFT_BUSY flag during shift or rotation.
variable BIT_CNT : std_logic_vector(5 downto 0);
begin
if RESETn = '0' then
SHIFT_STATE <= IDLE;
BIT_CNT := (others => '0');
SHFT_EN <= '0';
SHFT_BUSY <= '0';
elsif CLK = '1' and CLK' event then
if SHIFT_STATE = IDLE then
if SHIFTER_LOAD = '1' and CNT_NR /= "000000" then
SHIFT_STATE <= RUN;
BIT_CNT := CNT_NR;
SHFT_EN <= '1';
SHFT_BUSY <= '1';
else
SHIFT_STATE <= IDLE;
BIT_CNT := (others => '0');
SHFT_EN <= '0';
SHFT_BUSY <= '0';
end if;
elsif SHIFT_STATE = RUN then
-- A break condition for SHFT_BREAKn = '0'
-- occurs e.g. during interrupt handling.
if BIT_CNT = "000001" or SHFT_BREAKn = '0' then
SHIFT_STATE <= IDLE;
BIT_CNT := CNT_NR;
SHFT_EN <= '0';
SHFT_BUSY <= '0';
else
SHIFT_STATE <= RUN;
BIT_CNT := BIT_CNT - '1';
SHFT_EN <= '1';
SHFT_BUSY <= '1';
end if;
end if;
end if;
end process P_SHFT_CTRL;
COND_CODES: process(BIT_POS, OP, XNZVC_IN, DATA_IN, OP_SIZE, SHFT_OP, SHFT_X, CNT_NR, RESETn, CLK)
-- This process provides the flags for the shifter and the bit operations.
-- The flags for the shifter are valid after the shift operation, when the
-- SHFT_BUSY flag is not asserted. The flags of the bit operations are
-- valid immediately due to the one clock cycle process time.
variable BIT_POSITION : integer range 0 to 31;
variable SHFT_V : std_logic;
begin
BIT_POSITION := Conv_Integer(BIT_POS); -- Valid during the bit manipulation operations:
-- Negative and Zero flags:
case OP is
when BCHG | BCLR | BSET | BTST =>
XNZVC_OUT(3 downto 2) <= XNZVC_IN(3) & not DATA_IN(BIT_POSITION);
when ASL | ASR | LSL | LSR | ROTL | ROTR | ROXL | ROXR =>
-- Negative flag:
case OP_SIZE is
when LONG =>
XNZVC_OUT(3) <= SHFT_OP(31);
when WORD =>
XNZVC_OUT(3) <= SHFT_OP(15);
when others =>
XNZVC_OUT(3) <= SHFT_OP(7); -- Byte.
end case;
-- Zero flag:
if OP_SIZE = LONG and SHFT_OP = x"00000000" then
XNZVC_OUT(2) <= '1';
elsif OP_SIZE = WORD and SHFT_OP(15 downto 0) = x"0000" then
XNZVC_OUT(2) <= '1';
elsif OP_SIZE = BYTE and SHFT_OP(7 downto 0) = x"00" then
XNZVC_OUT(2) <= '1';
else
XNZVC_OUT(2) <= '0';
end if;
when others =>
XNZVC_OUT(3 downto 2) <= XNZVC_IN(3 downto 2);
end case;
-- Extended, Overflow and Carry flags:
if OP = BCHG or OP = BCLR or OP = BSET or OP = BTST then
XNZVC_OUT(4) <= XNZVC_IN(4);
XNZVC_OUT(1 downto 0) <= XNZVC_IN(1 downto 0);
elsif (OP = ROXL or OP = ROXR) and CNT_NR = "000000" then
XNZVC_OUT(4) <= XNZVC_IN(4);
XNZVC_OUT(1 downto 0) <= '0' & XNZVC_IN(4);
elsif CNT_NR = "000000" then
XNZVC_OUT(4) <= XNZVC_IN(4);
XNZVC_OUT(1 downto 0) <= "00";
else
-- Extended flag:
case OP is
when ASL | ASR | LSL | LSR | ROXL | ROXR =>
XNZVC_OUT(4) <= SHFT_X;
when others => -- Valid for ROTL, ROTR.
XNZVC_OUT(4) <= XNZVC_IN(4); -- Unaffected.
end case;
-- Overflow flag:
case OP is
when ASL | ASR =>
XNZVC_OUT(1) <= SHFT_V;
when others => -- Valid for LSL,LSR, ROL, ROR, ROXL, ROXR.
XNZVC_OUT(1) <= '0'; -- Unaffected.
end case;
-- Carry flag:
XNZVC_OUT(0) <= SHFT_X;
end if;
--
-- This register is a mirror for the X flag during the shift operation:
-- It is used as X flag for the ASL, ASR, LSL, LSR, ROXL and ROXR operations
-- as also as the C flag for all shift operations.
if RESETn = '0' then
SHFT_X <= '0';
elsif CLK = '1' and CLK' event then
if SHIFTER_LOAD = '1' then -- Load data in the shifter unit.
SHFT_X <= XNZVC_IN(4);
elsif SHFT_EN = '1' then -- Shift and rotate operations:
case OP is
when ASL | LSL | ROTL | ROXL =>
case OP_SIZE is
when LONG =>
SHFT_X <= SHFT_OP(31);
when WORD =>
SHFT_X <= SHFT_OP(15);
when BYTE =>
SHFT_X <= SHFT_OP(7);
end case;
when others =>
SHFT_X <= SHFT_OP(0);
end case;
end if;
end if;
--
if RESETn = '0' then
-- This process provides a detection of any toggling of the most significant
-- bit of the shifter unit during the ASL shift process. For all other shift
-- operations, the V flag is always zero.
SHFT_V := '0';
elsif CLK = '1' and CLK' event then
if SHIFTER_LOAD = '1' then
SHFT_V := '0';
elsif SHFT_EN = '1' then
case OP is
when ASL => -- ASR MSB is always unchanged.
if OP_SIZE = LONG then
SHFT_V := (SHFT_OP(31) xor SHFT_OP(30)) or SHFT_V;
elsif OP_SIZE = WORD then
SHFT_V := (SHFT_OP(15) xor SHFT_OP(14)) or SHFT_V;
else -- OP_SIZE = BYTE.
SHFT_V := (SHFT_OP(7) xor SHFT_OP(6)) or SHFT_V;
end if;
when others =>
SHFT_V := '0';
end case;
end if;
end if;
end process COND_CODES;
end BEHAVIOR;

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//
// Z80 Compatible Bus wrapper for fz80 ver.0.52
//
// Version 0.52a
//
// Copyright (c) 2004 Tatsuyuki Sato
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
note:
It should be necessary to set "`define M1" inf fz80.
---------------------------------------------------
-----------------------------
non-compatible spesification.
-----------------------------
1.no internal cycle
A internal cycle without bus cycle doesn't exist.
So some instruction is faster than Z80.
2.ealy tristate after reset
The "at" and "dt" assert after 1cycle from reset.
The Z80 is after 2cycles from reset.
3.busreq/busack timming are not checked yet.
4.halt always output 1(no supported).
-------------
state changes
-------------
+------+---+---+---+---+---+---+
|state |t1w|t1 |t2w|t2 |t3 |t4 |
+------+---+---+---+---+---+---+
| M1 | - | O | - | O*| O | O |
| MEM | - | O | - | O*| x | O |
| IO | - | O | - | O*| x | O |
| SpM1 | O | O | O | O | O | O |
+------+---+---+---+---+---+---+
*:sense wait (wait cycle)
histry:
2004. 9.16 ver.0.52a
bugfix power on reset error.
halt_n output always 1 (do not supported yet)
change `MREQ_INSIDE_RD logic.
2004. 9.10 ver.0.52
added power on reset
bugfix mreq inside rd mode
2004. 9. 9 ver.0.51
1st test version
*/
//`define FZ80C_NGC_LINK // xilinx XST link synthesized fz80c.v
//`define DEBUG_OUTPUT
// ----- design option -----
`define MREQ_INSIDE_RD // for wr = (rfsh & ~mreq_n & rd_n);
//`define FZ80C_POWER_ON_RESET // power on self reset
//`define DISABLE_BUSREQ_SYNC // bypass busreq/busack syncronize.
//`define DISABLE_REFRESH_CYCLE // no rfsh cycle & inst code fetch t4 raise
//`define NMI_SYNC_SENSE // nmi fall sense with clk
//`define DO_VAL_IF_DT 8'h00 // "do" set fixed value when output disable
module fz80c (/*AUTOARG*/
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di,
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n,
`ifdef DEBUG_OUTPUT
ts,
wait_window,
`endif
A, At,
do,dt
);
input reset_n,clk;
input wait_n , busrq_n;
input int_n,nmi_n;
input [7:0] di;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n; // (enable controll : mreq_n,iorq_n,rd_n,wr_n,rfsh_n)
output [15:0] A; // Address Bus
output [7:0] do; // Data Bus
output dt; // tristate controll : do
output At; // tristate controll : A
`ifdef DEBUG_OUTPUT
output [3:0] ts;
output wait_window;
`endif
`ifndef FZ80C_NGC_LINK
// internal register
reg [15:0] A;
reg [7:0] dinst_r;
reg [7:0] do_r;
reg [3:0] ts;
reg reset_s;
reg m1_r;
`ifndef DISABLE_REFRESH_CYCLE
reg rfsh_r;
`endif
reg mreq_r;
reg iorq_r;
reg wr_r;
reg rd_r;
reg wait_r;
reg dt_r,dt_t4;
`ifndef DISABLE_BUSREQ_SYNC
reg at_r;
reg busack_r;
reg busreq_r;
`endif
//reg halt_r;
`ifdef NMI_SYNC_SENSE
reg nmi_r1,nmi_r2;
`endif
// auto wait
reg tw1,tw2;
// gate signal base
reg t3l;
reg t04l;
`ifdef FZ80C_POWER_ON_RESET
reg por_n = 0;
reg por2_n = 0;
`endif
//////////////////////////////////////////////////////////////
// FZ80
//////////////////////////////////////////////////////////////
wire start;
wire mreq;
wire iorq;
wire rd;
wire wr;
wire busack;
wire waitreq;
reg intreq;
reg nmireq;
wire busreq;
wire m1;
//wire [7:0] data_in = m1 ? dinst_r : di;
wire [7:0] data_in = ~rfsh_n ? dinst_r : di;
wire [7:0] data_out;
wire [15:0] adr ,radr;
wire nmiack;
//wire halt;
// mreq,iorq inside in rd_wr
//wire req_mask =
fz80 fz80(
.data_in(data_in),
.reset_in(reset_s),
.clk(~clk),
.adr(adr),
.intreq(intreq),
.nmireq(nmireq),
.busreq(busreq),
.start(start),
.mreq(mreq),
.iorq(iorq),
.rd(rd),
.wr(wr),
.data_out(data_out),
.busack_out(busack),
.intack_out(),
.mr(),
.m1(m1),
// .halt(halt),
.radr(radr),
.nmiack_out(nmiack),
.waitreq(waitreq)
);
///////////////////////////////////////////////////////
// wires
///////////////////////////////////////////////////////
// state value
wire t0 = ts[3:0]==0; // t0 : reset cycle
wire t1 = ts[0]; // t1 : spM1 = t1&t2
wire t2 = ts[1]; // t2 : spM1 = tw(1,2)
wire t3 = ts[2]; // M1.t3
wire t4 = ts[3]; // M1.t4 or MEM/IO.t3
wire t04 = ~t1 & ~t2 & ~t3; // T0 or T4
`ifdef DEBUG_OUTPUT
// wait input window
assign wait_window = t2 & ~wait_r;
`endif
// RFSH assert timming
`ifdef DISABLE_REFRESH_CYCLE
wire nxt_rfsh = 1'b0;
`else
wire nxt_rfsh = (m1&t2&wait_r)|t3; // T3 and T4
`endif
///////////////////////////////////////////////////////
// NMI eddge sense
///////////////////////////////////////////////////////
`ifndef NMI_SYNC_SENSE
wire nmi_clr = nmiack | reset_s;
always @(negedge nmi_n or posedge nmi_clr)
begin
if(nmi_clr) nmireq <= #1 1'b0;
else nmireq <= #1 1'b1;
end
`endif
///////////////////////////////////////////////////////
// Timming state controll
///////////////////////////////////////////////////////
`ifdef FZ80C_POWER_ON_RESET
always @(negedge clk)
begin
por_n <= #1 por2_n;
por2_n <= #1 1'b1;
end
// with por
always @(negedge clk or negedge por_n)
if(~por_n) reset_s <= #1 1'b1;
else reset_s <= #1 ~reset_n;
`else
// without por
always @(negedge clk) reset_s <= #1 ~reset_n;
`endif
always @(posedge clk)
begin
if (reset_s)
begin
dinst_r <= #1 8'h00;
ts <= #1 4'b0000; // reset cycle;
A <= #1 16'h0000;
m1_r <= #1 1'b1;
`ifndef DISABLE_REFRESH_CYCLE
rfsh_r <= #1 1'b1;
`endif
intreq <= #1 1'b0;
`ifdef NMI_SYNC_SENSE
nmireq <= #1 1'b0;
nmi_r2 <= #1 1'b0;
nmi_r1 <= #1 1'b0;
`endif
tw1 <= #1 1'b0;
tw2 <= #1 1'b0;
dt_t4 <= #1 1'b1;
`ifndef DISABLE_BUSREQ_SYNC
busreq_r <= #1 1'b1;
busack_r <= #1 1'b1;
at_r <= #1 1'b1;
`endif
iorq_r <= #1 1'b1;
rd_r <= #1 1'b1;
mreq_r <= #1 1'b1;
// halt_r <= #1 1'b1;
end else begin
// T1 T2 on , T3 T4 off
m1_r <= #1 ~m1 | nxt_rfsh;
`ifndef DISABLE_REFRESH_CYCLE
// T3 T4 on , T1 T2 off
rfsh_r <= #1 ~nxt_rfsh;
`endif
// T1(M1),T2,T4(IO) on , T1(IO),T3,T4(M1) off
iorq_r <= #1 ~iorq | t04 | tw1 | nxt_rfsh;
// T1(MEM),T2,T4(MEM) on,T1(IO),T3,T4(M1) off
rd_r <= #1 ~rd | (iorq&t04) | nxt_rfsh;
// T1,T2,T4(MEM) on T3,T4(M1) off
mreq_r <= #1 ~mreq | nxt_rfsh;
// timming state controll
ts[0] <= #1 (t1&tw1) | t04; // t1
ts[1] <= #1 (t2& ~wait_r) | (t1&~tw1); // t2
ts[2] <= #1 (t2& wait_r& m1); // t3
ts[3] <= #1 (t2& wait_r&~m1) | t3; // t4
// auto wait state
tw1 <= #1 ~t1 & (m1&iorq); // TW for SpecialM1
tw2 <= #1 t1 & iorq; // TW for IO and SpecialM1
// address / refresh address
A <= #1 nxt_rfsh ? radr : adr;
// IRQ (T4 raise)
intreq <= #1 ~int_n;
// NMI eddge sense
`ifdef NMI_SYNC_SENSE
nmi_r2 <= #1 nmi_r1;
nmi_r1 <= #1 ~nmi_n;
if(nmiack) nmireq <= #1 1'b0;
else if(~nmi_r2 & nmi_r1) nmireq <= #1 1'b1;
`endif
// Opcode Latch = T3 raise
if(t2) dinst_r <= #1 di;
// data outpot tristate , HOLD half clock in T4
dt_t4 <= #1 dt_r;
// busreq / busack & Address tristate
`ifndef DISABLE_BUSREQ_SYNC
busreq_r <= #1 ~busrq_n;
busack_r <= #1 ~busack;
at_r <= #1 ~busack;
`endif
// halt fetch
// if(m1&t4) halt_r <= #1 ~halt;
end
end
// clk fall event
always @(negedge clk)
begin
if (reset_s)
begin
t3l <= #1 1'b0;
t04l <= #1 1'b1;
wait_r <= #1 1'b1;
wr_r <= #1 1'b1;
dt_r <= #1 1'b1;
do_r <= #1 8'h00;
end else begin
// gate controll
t3l <= #1 t3;
// t4l-t0l | specialM1.t1l
t04l <= #1 t04 | (t1&m1&iorq);
// DataOutput
do_r <= #1 data_out;
// wait sense (T2 raise)
wait_r <= #1 (wait_n | (m1&iorq)) & ~tw2;
// data bus enable , T1,T2 on , T4 off
dt_r <= #1 ~wr | t04;
// T1(IO),T2 on , T1(MEM),T4 off
wr_r <= #1 ~wr | t4 | (mreq&t1);
end
end
/////////////////////////////////////////////////////////////////////////////
// fz80 input
/////////////////////////////////////////////////////////////////////////////
assign waitreq = ~t4;
`ifdef DISABLE_BUSREQ_SYNC
assign busreq = ~busrq_n;
`else
assign busreq = busreq_r;
`endif
/////////////////////////////////////////////////////////////////////////////
// output signal
/////////////////////////////////////////////////////////////////////////////
// MREQ glidge mask
`ifdef MREQ_INSIDE_RD
reg mreq_dly;
always @(posedge clk or negedge rd_n)
begin
if(~rd_n) mreq_dly <= #1 1'b0;
else if(t04) mreq_dly <= #1 rd;
end
reg rd_hold_n;
always @(posedge clk or posedge mreq_n)
begin
if(mreq_n) rd_hold_n <= #1 1'b1;
else rd_hold_n <= #1 mreq_n | rd_n;
end
`else
wire mreq_dly = 0;
wire rd_hold_n = 1;
`endif
assign m1_n = m1_r;
`ifndef DISABLE_REFRESH_CYCLE
assign rfsh_n = rfsh_r;
`else
assign rfsh_n = 1'b1;
`endif
assign mreq_n = (mreq_r| t04l | mreq_dly) & (~t3l | rfsh_n);
assign iorq_n = iorq_r | t04l;
assign rd_n = (rd_r | t04l) & rd_hold_n;
assign wr_n = wr_r | t1;
assign dt = dt_r & dt_t4;
`ifndef DISABLE_BUSREQ_SYNC
assign At = at_r;
assign busak_n = busack_r;
`else
assign At = busack | reset_s;
assign busak_n = busack;
`endif
`ifdef DO_VAL_IF_DT
assign do = dt ? `DO_VAL_IF_DT : do_r;
`else
assign do = do_r;
`endif
//assign halt_n = halt_r;
assign halt_n = 1'b1;
`endif // FZ80C_USER_NGC_LINK
endmodule

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`timescale 1ns / 1ps
module mc6809
(
input CLK,
input CLKEN,
input nRESET,
input CPU,
output reg E,
output reg riseE,
output reg fallE, // everything except interrupts/dma registered/latched here
output reg Q,
output reg riseQ,
output reg fallQ, // NMI,IRQ,FIRQ,DMA,HALT registered here
input [7:0] Din,
output [7:0] Dout,
output [15:0] ADDR,
output RnW,
input nIRQ,
input nFIRQ,
input nNMI,
input nHALT
);
cpu09 cpu1
(
.clk(CLK),
.ce(fallE),
.rst(~nRESET | CPU),
.addr(ADDR1),
.rw(RnW1),
.data_out(Dout1),
.data_in(Din),
.irq(~nIRQ),
.firq(~nFIRQ),
.nmi(~nNMI),
.halt(~nHALT)
);
mc6809is cpu2
(
.CLK(CLK),
.D(Din),
.DOut(Dout2),
.ADDR(ADDR2),
.RnW(RnW2),
.fallE_en(fallE),
.fallQ_en(fallQ),
.nIRQ(nIRQ),
.nFIRQ(nFIRQ),
.nNMI(nNMI),
.nHALT(nHALT),
.nRESET(nRESET & CPU),
.nDMABREQ(1)
);
wire [7:0] Dout1,Dout2;
wire [15:0] ADDR1,ADDR2;
wire RnW1,RnW2;
assign Dout = CPU ? Dout2 : Dout1;
assign ADDR = CPU ? ADDR2 : ADDR1;
assign RnW = CPU ? RnW2 : RnW1;
always @(posedge CLK)
begin
reg [1:0] clk_phase =0;
fallE <= 0;
fallQ <= 0;
riseE <= 0;
riseQ <= 0;
if (CLKEN) begin
clk_phase <= clk_phase + 1'd1;
case (clk_phase)
2'b00: begin E <= 0; fallE <= 1; end
2'b01: begin Q <= 1; riseQ <= 1; end
2'b10: begin E <= 1; riseE <= 1; end
2'b11: begin Q <= 0; fallQ <= 1; end
endcase
end
end
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the NextZ80 project
// http://www.opencores.org/cores/nextz80/
//
// Filename: NextZ80ALU.v
// Description: Implementation of Z80 compatible CPU - ALU
// Version 1.0
// Creation date: 28Jan2011 - 18Mar2011
//
// Author: Nicolae Dumitrache
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 Nicolae Dumitrache
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
///////////////////////////////////////////////////////////////////////////////////
//FLAGS: S Z X1 N X2 PV N C
// OP[4:0]
// 00000 - ADD D0,D1
// 00001 - ADC D0,D1
// 00010 - SUB D0,D1
// 00011 - SBC D0,D1
// 00100 - AND D0,D1
// 00101 - XOR D0,D1
// 00110 - OR D0,D1
// 00111 - CP D0,D1
// 01000 - INC D0
// 01001 - CPL D0
// 01010 - DEC D0
// 01011 - RRD
// 01100 - RLD
// 01101 - DAA
// 01110 - INC16
// 01111 - DEC16
// 10000 - ADD16LO
// 10001 - ADD16HI
// 10010 -
// 10011 -
// 10100 - CCF, pass D0
// 10101 - SCF, pass D0
// 10110 -
// 10111 -
// 11000 - RLCA D0
// 11001 - RRCA D0
// 11010 - RLA D0
// 11011 - RRA D0
// 11100 - {ROT, BIT, SET, RES} D0,EXOP
// RLC D0 C <-- D0 <-- D0[7]
// RRC D0 D0[0] --> D0 --> C
// RL D0 C <-- D0 <-- C
// RR D0 C --> D0 --> C
// SLA D0 C <-- D0 <-- 0
// SRA D0 D0[7] --> D0 --> C
// SLL D0 C <-- D0 <-- 1
// SRL D0 0 --> D0 --> C
// 11101 - IN, pass D1
// 11110 - FLAGS <- D0
// 11111 - NEG D1
///////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ALU8(
input [7:0] D0,
input [7:0] D1,
input [7:0] FIN,
output reg[7:0] FOUT,
output reg [15:0] ALU8DOUT,
input [4:0] OP,
input [5:0] EXOP, // EXOP[5:4] = 2'b11 for CPI/D/R
input LDIFLAGS, // zero HF and NF on inc/dec16
input DSTHI // destination lo
);
wire [7:0] daaadjust;
wire cdaa, hdaa;
daa daa_adjust(.flags(FIN), .val(D0), .adjust(daaadjust), .cdaa(cdaa), .hdaa(hdaa));
wire parity = ~^ALU8DOUT[15:8];
wire zero = ALU8DOUT[15:8] == 0;
reg csin, cin;
wire [7:0]d0mux = OP[4:1] == 4'b1111 ? 0 : D0;
reg [7:0]_d1mux;
wire [7:0]d1mux = OP[1] ? ~_d1mux : _d1mux;
wire [8:0]sum;
wire hf;
assign {hf, sum[3:0]} = d0mux[3:0] + d1mux[3:0] + cin;
assign sum[8:4] = d0mux[7:4] + d1mux[7:4] + hf;
wire overflow = (d0mux[7] & d1mux[7] & !sum[7]) | (!d0mux[7] & !d1mux[7] & sum[7]);
reg [7:0]dbit;
always @* begin
ALU8DOUT = 16'hxxxx;
FOUT = 8'hxx;
case({OP[4:2]})
0,1,4,7: _d1mux = D1;
2: _d1mux = 1;
3: _d1mux = daaadjust; // DAA
6,5: _d1mux = 8'hxx;
endcase
case({OP[2:0], FIN[0]})
0,1,2,7,8,9,10,11,12,13: cin = 0;
3,4,5,6,14,15: cin = 1;
endcase
case(EXOP[3:0])
0: dbit = 8'b11111110;
1: dbit = 8'b11111101;
2: dbit = 8'b11111011;
3: dbit = 8'b11110111;
4: dbit = 8'b11101111;
5: dbit = 8'b11011111;
6: dbit = 8'b10111111;
7: dbit = 8'b01111111;
8: dbit = 8'b00000001;
9: dbit = 8'b00000010;
10: dbit = 8'b00000100;
11: dbit = 8'b00001000;
12: dbit = 8'b00010000;
13: dbit = 8'b00100000;
14: dbit = 8'b01000000;
15: dbit = 8'b10000000;
endcase
case(OP[3] ? EXOP[2:0] : OP[2:0])
0,5: csin = D0[7];
1: csin = D0[0];
2,3: csin = FIN[0];
4,7: csin = 0;
6: csin = 1;
endcase
case(OP[4:0])
0,1,2,3,8,10: begin // ADD, ADC, SUB, SBC, INC, DEC
ALU8DOUT[15:8] = sum[7:0];
ALU8DOUT[7:0] = sum[7:0];
FOUT[0] = OP[3] ? FIN[0] : (sum[8] ^ OP[1]); // inc/dec
FOUT[1] = OP[1];
FOUT[2] = overflow;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = hf ^ OP[1];
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero & (FIN[6] | ~EXOP[5] | ~DSTHI | OP[3]); //(EXOP[5] & DSTHI) ? (zero & FIN[6]) : zero; // adc16/sbc16
FOUT[7] = ALU8DOUT[15];
end
16,17: begin // ADD16LO, ADD16HI
ALU8DOUT[15:8] = sum[7:0];
ALU8DOUT[7:0] = sum[7:0];
FOUT[0] = sum[8];
FOUT[1] = OP[1];
FOUT[2] = FIN[2];
FOUT[3] = ALU8DOUT[11];
FOUT[4] = hf ^ OP[1];
FOUT[5] = ALU8DOUT[13];
FOUT[6] = FIN[6];
FOUT[7] = FIN[7];
end
7: begin // CP
ALU8DOUT[15:8] = sum[7:0];
FOUT[0] = EXOP[5] ? FIN[0] : !sum[8]; // CPI/D/R
FOUT[1] = OP[1];
FOUT[2] = overflow;
FOUT[3] = D1[3];
FOUT[4] = !hf;
FOUT[5] = D1[5];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
31: begin // NEG
ALU8DOUT[15:8] = sum[7:0];
FOUT[0] = !sum[8];
FOUT[1] = OP[1];
FOUT[2] = overflow;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = !hf;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
4: begin // AND
ALU8DOUT[15:8] = D0 & D1;
FOUT[0] = 0;
FOUT[1] = 0;
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 1;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
5,6: begin //XOR, OR
ALU8DOUT[15:8] = OP[0] ? (D0 ^ D1) : (D0 | D1);
FOUT[0] = 0;
FOUT[1] = 0;
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 0;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
9: begin // CPL
ALU8DOUT[15:8] = ~D0;
FOUT[0] = FIN[0];
FOUT[1] = 1;
FOUT[2] = FIN[2];
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 1;
FOUT[5] = ALU8DOUT[13];
FOUT[7:6] = FIN[7:6];
end
11,12: begin // RLD, RRD
if(OP[0]) ALU8DOUT = {D0[7:4], D1[3:0], D0[3:0], D1[7:4]};
else ALU8DOUT = {D0[7:4], D1[7:0], D0[3:0]};
FOUT[0] = FIN[0];
FOUT[1] = 0;
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 0;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
13: begin // DAA
ALU8DOUT[15:8] = sum[7:0];
FOUT[0] = cdaa;
FOUT[1] = FIN[1];
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = hdaa;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
14,15: begin // inc/dec 16
ALU8DOUT = {D0, D1} + (OP[0] ? 16'hffff : 16'h0001);
FOUT[0] = FIN[0];
FOUT[1] = LDIFLAGS ? 1'b0 : FIN[1];
FOUT[2] = ALU8DOUT != 0;
FOUT[3] = FIN[3];
FOUT[4] = LDIFLAGS ? 1'b0 : FIN[4];
FOUT[5] = FIN[5];
FOUT[6] = FIN[6];
FOUT[7] = FIN[7];
end
20,21: begin // CCF, SCF
ALU8DOUT[15:8] = D0;
FOUT[0] = OP[0] ? 1'b1 : !FIN[0];
FOUT[1] = 1'b0;
FOUT[2] = FIN[2];
FOUT[3] = ALU8DOUT[11];
FOUT[4] = OP[0] ? 1'b0 : FIN[0];
FOUT[5] = ALU8DOUT[13];
FOUT[6] = FIN[6];
FOUT[7] = FIN[7];
end
24,25,26,27, 28: begin // ROT, BIT, RES, SET
case({OP[2], EXOP[4:3]})
0,1,2,3,4: // rot - shift
if(OP[2] ? EXOP[0] : OP[0]){ALU8DOUT[15:8], FOUT[0]} = {csin, D0}; // right
else {FOUT[0], ALU8DOUT[15:8]} = {D0, csin}; // left
5,6: begin // BIT, RES
FOUT[0] = FIN[0];
ALU8DOUT[15:8] = D0 & dbit;
end
7: begin // SET
FOUT[0] = FIN[0];
ALU8DOUT[15:8] = D0 | dbit;
end
endcase
ALU8DOUT[7:0] = ALU8DOUT[15:8];
FOUT[1] = 0;
FOUT[2] = OP[2] ? (EXOP[3] ? zero : parity) : FIN[2];
FOUT[3] = ALU8DOUT[11];
FOUT[4] = OP[2] & EXOP[3];
FOUT[5] = ALU8DOUT[13];
FOUT[6] = OP[2] ? zero : FIN[6];
FOUT[7] = OP[2] ? ALU8DOUT[15] : FIN[7];
end
29: begin // IN, pass D1
ALU8DOUT = {D1, D1};
FOUT[0] = FIN[0];
FOUT[1] = 0;
FOUT[2] = parity;
FOUT[3] = ALU8DOUT[11];
FOUT[4] = 0;
FOUT[5] = ALU8DOUT[13];
FOUT[6] = zero;
FOUT[7] = ALU8DOUT[15];
end
30: FOUT = D0; // FLAGS <- D0
default:;
endcase
end
endmodule
module daa (
input [7:0]flags,
input [7:0]val,
output wire [7:0]adjust,
output reg cdaa,
output reg hdaa
);
wire h08 = val[7:4] < 9;
wire h09 = val[7:4] < 10;
wire l05 = val[3:0] < 6;
wire l09 = val[3:0] < 10;
reg [1:0]aa;
assign adjust = ({1'b0, aa[1], aa[1], 2'b0, aa[0], aa[0], 1'b0} ^ {8{flags[1]}}) + flags[1];
always @* begin
case({flags[0], h08, h09, flags[4], l09})
5'b00101, 5'b01101: aa = 0;
5'b00111, 5'b01111, 5'b01000, 5'b01010, 5'b01100, 5'b01110: aa = 1;
5'b00001, 5'b01001, 5'b10001, 5'b10101, 5'b11001, 5'b11101: aa = 2;
default: aa = 3;
endcase
case({flags[0], h08, h09, l09})
4'b0011, 4'b0111, 4'b0100, 4'b0110: cdaa = 0;
default: cdaa = 1;
endcase
case({flags[1], flags[4], l05, l09})
4'b0000, 4'b0010, 4'b0100, 4'b0110, 4'b1110, 4'b1111: hdaa = 1;
default: hdaa = 0;
endcase
end
endmodule
module ALU16(
input [15:0] D0,
input [7:0] D1,
output wire[15:0] DOUT,
input [2:0]OP // 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
);
reg [15:0] mux;
always @*
case(OP)
0: mux = 0; // post inc
1: mux = 1; // post inc
2: mux = 2; // post inc
3: mux = {D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7:0]}; // post inc
4: mux = 0; // no post inc
5: mux = 16'hffff; // no post inc
6: mux = 16'hfffe; // no post inc
default: mux = 16'hxxxx;
endcase
assign DOUT = D0 + mux;
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the NextZ80 project
// http://www.opencores.org/cores/nextz80/
//
// Filename: NextZ80Regs.v
// Description: Implementation of Z80 compatible CPU - registers
// Version 1.0
// Creation date: 28Jan2011 - 18Mar2011
//
// Author: Nicolae Dumitrache
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 Nicolae Dumitrache
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
///////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module Z80Reg(
input wire [7:0]rstatus, // 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy, 6=IFF1, 7=IFF2
input wire M1,
input wire [5:0]WE, // 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
input wire CLK,
input wire [15:0]ALU8OUT, // CPU data out bus (output of alu8)
input wire [7:0]DI, // CPU data in bus
output reg [7:0]DO, // CPU data out bus
input wire [15:0]ADDR, // CPU addr bus
input wire [7:0]CONST,
output reg [7:0]ALU80,
output reg [7:0]ALU81,
output reg [15:0]ALU160,
output wire[7:0]ALU161,
input wire [7:0]ALU8FLAGS,
output wire [7:0]FLAGS,
input wire [1:0]DO_SEL, // select DO betwen ALU8OUT lo and th register
input wire ALU160_sel, // 0=REG_RSEL, 1=PC
input wire [3:0]REG_WSEL, // rdow: [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-x ----- [0] = 0HI,1LO
input wire [3:0]REG_RSEL, // mux_rdor: [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-R, 5=SP, 7=tmpSP ----- [0] = 0HI, 1LO
input wire DINW_SEL, // select RAM write data between (0)ALU8OUT, and 1(DI)
input wire XMASK, // 0 if REG_WSEL should not use IX, IY, even if rstatus[4] == 1
input wire [2:0]ALU16OP, // ALU16OP
input wire WAIT // wait
);
// latch registers
reg [15:0]pc=0; // program counter
reg [15:0]sp; // stack pointer
reg [7:0]r; // refresh
reg [15:0]flg = 0;
reg [7:0]th; // temp high
// internal wires
wire [15:0]rdor; // R out from RAM
wire [15:0]rdow; // W out from RAM
wire [3:0]SELW; // RAM W port sel
wire [3:0]SELR; // RAM R port sel
reg [15:0]DIN; // RAM W in data
reg [15:0]mux_rdor; // (3)A reversed mixed with TL, (4)I mixed with R (5)SP
//------------------------------------ RAM block registers ----------------------------------
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero
RAM16X8D_regs regs_lo (
.DPO(rdor[7:0]), // Read-only data output
.SPO(rdow[7:0]), // R/W data output
.A(SELW), // R/W address
.D(DIN[7:0]), // Write data input
.DPRA(SELR), // Read-only address
.WCLK(CLK), // Write clock input
.WE(WE[0] & !WAIT) // Write enable input
);
RAM16X8D_regs regs_hi (
.DPO(rdor[15:8]), // Read-only data output
.SPO(rdow[15:8]), // R/W data output
.A(SELW), // R/W address
.D(DIN[15:8]), // Write data input
.DPRA(SELR), // Read-only address
.WCLK(CLK), // Write clock input
.WE(WE[1] & !WAIT) // Write enable input
);
wire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment
wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]}; // LD A, I/R IFF2 flag on parity
always @(posedge CLK)
if(!WAIT) begin
if(WE[2]) th <= DI;
if(WE[3]) sp <= ADDR1;
if(WE[4]) pc <= ADDR1;
if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0];
else if(M1) r[6:0] <= r[6:0] + 1;
if(WE[5])
if(rstatus[0]) flg[15:8] <= flgmux;
else flg[7:0] <= flgmux;
end
assign ALU161 = th;
assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
always @* begin
DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
ALU160 = ALU160_sel ? pc : mux_rdor;
case({REG_WSEL[3], DO_SEL})
0: DO = ALU80;
1: DO = th;
2: DO = FLAGS;
3: DO = ALU8OUT[7:0];
4: DO = pc[15:8];
5: DO = pc[7:0];
6: DO = sp[15:8];
7: DO = sp[7:0];
endcase
case({ALU16OP == 4, REG_RSEL[3:0]})
5'b01001, 5'b11001: mux_rdor = {rdor[15:8], r};
5'b01010, 5'b01011: mux_rdor = sp;
5'b01100, 5'b01101, 5'b11100, 5'b11101: mux_rdor = {8'b0, CONST};
default: mux_rdor = rdor;
endcase
end
RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));
endmodule
module RegSelect(
input [2:0]SEL,
output reg [3:0]RAMSEL,
input [5:0]rstatus // 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy
);
always @* begin
RAMSEL = 4'bxxxx;
case(SEL)
0: RAMSEL = {rstatus[1], 3'b000}; // BC
1: //DE
if(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010}; // HL
else RAMSEL = {rstatus[1], 3'b001}; // DE
2: // HL
case({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})
0,4: RAMSEL = {rstatus[1], 3'b010}; // HL
1,5: RAMSEL = {rstatus[1], 3'b001}; // DE
2,3: RAMSEL = 4'b0101; // IX
6,7: RAMSEL = 4'b0110; // IY
endcase
3: RAMSEL = {rstatus[0], 3'b011}; // A-TL
4: RAMSEL = 4; // I-R
5: RAMSEL = 12; // tmp SP
6: RAMSEL = 13; // zero
7: RAMSEL = 7; // temp reg for BIT/SET/RES
endcase
end
endmodule
module RAM16X8D_regs(
output [7:0]DPO, // Read-only data output
output [7:0]SPO, // R/W data output
input [3:0]A, // R/W address
input [7:0]D, // Write data input
input [3:0]DPRA, // Read-only address
input WCLK, // Write clock
input WE // Write enable
);
reg [7:0]data[15:0];
assign DPO = data[DPRA];
assign SPO = data[A];
always @(posedge WCLK)
if(WE) data[A] <= D;
endmodule

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package pack_t65 is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_t65.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "000" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
-- assert false report "Chargement A" severity warning;
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
P(Flag_B) <= '1';
end if;
if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
P(Flag_I) <= '1';
P(Flag_B) <= B_o;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_t65.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
begin
C := P_In(Flag_C) or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op(3 downto 0) is
when "0000" =>
-- ORA
Q_t := BusA or BusB;
when "0001" =>
-- AND
Q_t := BusA and BusB;
when "0010" =>
-- EOR
Q_t := BusA xor BusB;
when "0011" =>
-- ADC
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when "0101" | "1101" =>
-- LDA
when "0110" =>
-- CMP
P_Out(Flag_C) <= SBC_C;
when "0111" =>
-- SBC
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when "1000" =>
-- ASL
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when "1001" =>
-- ROL
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when "1010" =>
-- LSR
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1011" =>
-- ROR
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1100" =>
-- BIT
P_Out(Flag_V) <= BusB(6);
when "1110" =>
-- DEC
Q_t := std_logic_vector(unsigned(BusA) - 1);
when "1111" =>
-- INC
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
end case;
case Op(3 downto 0) is
when "0011" =>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when "0110" | "0111" =>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when "0100" =>
when "1100" =>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;

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common/CPU/cpu86/a_table.vhd Normal file
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@@ -0,0 +1,720 @@
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity a_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end a_table;
architecture rtl of a_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "001";
when "1110100100000000" => dout <= "010";
when "1111111111100000" => dout <= "000";
when "1111111100100110" => dout <= "100";
when "1111111100100000" => dout <= "000";
when "1111111101100000" => dout <= "011";
when "1111111110100000" => dout <= "100";
when "1110101000000000" => dout <= "010";
when "1111111100101110" => dout <= "100";
when "1111111100101000" => dout <= "000";
when "1111111101101000" => dout <= "011";
when "1111111110101000" => dout <= "100";
when "1110100000000000" => dout <= "010";
when "1111111111010000" => dout <= "000";
when "1111111100010110" => dout <= "100";
when "1111111100010000" => dout <= "000";
when "1111111101010000" => dout <= "011";
when "1111111110010000" => dout <= "100";
when "1001101000000000" => dout <= "010";
when "1111111100011110" => dout <= "100";
when "1111111100011000" => dout <= "000";
when "1111111101011000" => dout <= "011";
when "1111111110011000" => dout <= "100";
when "1100001100000000" => dout <= "000";
when "1100001000000000" => dout <= "000";
when "1100101100000000" => dout <= "000";
when "1100101000000000" => dout <= "000";
when "0111010000000000" => dout <= "001";
when "0111110000000000" => dout <= "001";
when "0111111000000000" => dout <= "001";
when "0111001000000000" => dout <= "001";
when "0111011000000000" => dout <= "001";
when "0111101000000000" => dout <= "001";
when "0111000000000000" => dout <= "001";
when "0111100000000000" => dout <= "001";
when "0111010100000000" => dout <= "001";
when "0111110100000000" => dout <= "001";
when "0111111100000000" => dout <= "001";
when "0111001100000000" => dout <= "001";
when "0111011100000000" => dout <= "001";
when "0111101100000000" => dout <= "001";
when "0111000100000000" => dout <= "001";
when "0111100100000000" => dout <= "001";
when "1110001100000000" => dout <= "001";
when "1110001000000000" => dout <= "001";
when "1110000100000000" => dout <= "001";
when "1110000000000000" => dout <= "001";
when "1100110100000000" => dout <= "101";
when "1100110000000000" => dout <= "110";
when "1100111000000000" => dout <= "111";
when "1100111100000000" => dout <= "000";
when "1111100000000000" => dout <= "000";
when "1111010100000000" => dout <= "000";
when "1111100100000000" => dout <= "000";
when "1111110000000000" => dout <= "000";
when "1111110100000000" => dout <= "000";
when "1111101000000000" => dout <= "000";
when "1111101100000000" => dout <= "000";
when "1111010000000000" => dout <= "000";
when "1001101100000000" => dout <= "000";
when "1111000000000000" => dout <= "000";
when "1001000000000000" => dout <= "000";
when "0010011000000000" => dout <= "000";
when "0010111000000000" => dout <= "000";
when "0011011000000000" => dout <= "000";
when "0011111000000000" => dout <= "000";
when "1000100011000000" => dout <= "000";
when "1000100000000000" => dout <= "000";
when "1000100001000000" => dout <= "011";
when "1000100010000000" => dout <= "100";
when "1000100000000110" => dout <= "100";
when "1000100111000000" => dout <= "000";
when "1000100100000000" => dout <= "000";
when "1000100101000000" => dout <= "011";
when "1000100110000000" => dout <= "100";
when "1000100100000110" => dout <= "100";
when "1000101011000000" => dout <= "000";
when "1000101000000000" => dout <= "000";
when "1000101001000000" => dout <= "011";
when "1000101010000000" => dout <= "100";
when "1000101000000110" => dout <= "100";
when "1000101111000000" => dout <= "000";
when "1000101100000000" => dout <= "000";
when "1000101101000000" => dout <= "011";
when "1000101110000000" => dout <= "100";
when "1000101100000110" => dout <= "100";
when "1100011000000000" => dout <= "000";
when "1100011001000000" => dout <= "011";
when "1100011010000000" => dout <= "100";
when "1100011000000110" => dout <= "100";
when "1100011100000000" => dout <= "000";
when "1100011101000000" => dout <= "011";
when "1100011110000000" => dout <= "100";
when "1100011100000110" => dout <= "100";
when "1011000000000000" => dout <= "000";
when "1011000100000000" => dout <= "000";
when "1011001000000000" => dout <= "000";
when "1011001100000000" => dout <= "000";
when "1011010000000000" => dout <= "000";
when "1011010100000000" => dout <= "000";
when "1011011000000000" => dout <= "000";
when "1011011100000000" => dout <= "000";
when "1011100000000000" => dout <= "000";
when "1011100100000000" => dout <= "000";
when "1011101000000000" => dout <= "000";
when "1011101100000000" => dout <= "000";
when "1011110000000000" => dout <= "000";
when "1011110100000000" => dout <= "000";
when "1011111000000000" => dout <= "000";
when "1011111100000000" => dout <= "000";
when "1010000000000000" => dout <= "010";
when "1010000100000000" => dout <= "010";
when "1010001000000000" => dout <= "010";
when "1010001100000000" => dout <= "010";
when "1000111011000000" => dout <= "000";
when "1000111000000000" => dout <= "000";
when "1000111001000000" => dout <= "011";
when "1000111010000000" => dout <= "100";
when "1000111000000110" => dout <= "100";
when "1000110011000000" => dout <= "000";
when "1000110000000000" => dout <= "000";
when "1000110001000000" => dout <= "011";
when "1000110010000000" => dout <= "100";
when "1000110000000110" => dout <= "100";
when "1111111100110000" => dout <= "000";
when "1111111101110000" => dout <= "011";
when "1111111110110000" => dout <= "100";
when "1111111100110110" => dout <= "100";
when "0101000000000000" => dout <= "000";
when "0101000100000000" => dout <= "000";
when "0101001000000000" => dout <= "000";
when "0101001100000000" => dout <= "000";
when "0101010000000000" => dout <= "000";
when "0101010100000000" => dout <= "000";
when "0101011000000000" => dout <= "000";
when "0101011100000000" => dout <= "000";
when "0000011000000000" => dout <= "000";
when "0000111000000000" => dout <= "000";
when "0001011000000000" => dout <= "000";
when "0001111000000000" => dout <= "000";
when "1000111100000000" => dout <= "000";
when "1000111101000000" => dout <= "011";
when "1000111110000000" => dout <= "100";
when "1000111100000110" => dout <= "100";
when "1000111111000000" => dout <= "000";
when "0101100000000000" => dout <= "000";
when "0101100100000000" => dout <= "000";
when "0101101000000000" => dout <= "000";
when "0101101100000000" => dout <= "000";
when "0101110000000000" => dout <= "000";
when "0101110100000000" => dout <= "000";
when "0101111000000000" => dout <= "000";
when "0101111100000000" => dout <= "000";
when "0000011100000000" => dout <= "000";
when "0001011100000000" => dout <= "000";
when "0001111100000000" => dout <= "000";
when "1000011011000000" => dout <= "000";
when "1000011000000000" => dout <= "000";
when "1000011001000000" => dout <= "011";
when "1000011010000000" => dout <= "100";
when "1000011000000110" => dout <= "100";
when "1000011111000000" => dout <= "000";
when "1000011100000000" => dout <= "000";
when "1000011101000000" => dout <= "011";
when "1000011110000000" => dout <= "100";
when "1000011100000110" => dout <= "100";
when "1001000100000000" => dout <= "000";
when "1001001000000000" => dout <= "000";
when "1001001100000000" => dout <= "000";
when "1001010000000000" => dout <= "000";
when "1001010100000000" => dout <= "000";
when "1001011000000000" => dout <= "000";
when "1001011100000000" => dout <= "000";
when "1110010000000000" => dout <= "101";
when "1110010100000000" => dout <= "101";
when "1110110000000000" => dout <= "000";
when "1110110100000000" => dout <= "000";
when "1110011000000000" => dout <= "101";
when "1110011100000000" => dout <= "101";
when "1110111100000000" => dout <= "000";
when "1110111000000000" => dout <= "000";
when "1101011100000000" => dout <= "000";
when "1001111100000000" => dout <= "000";
when "1001111000000000" => dout <= "000";
when "1001110000000000" => dout <= "000";
when "1001110100000000" => dout <= "000";
when "1000110100000110" => dout <= "100";
when "1000110111000000" => dout <= "000";
when "1000110100000000" => dout <= "000";
when "1000110101000000" => dout <= "011";
when "1000110110000000" => dout <= "100";
when "1100010100000110" => dout <= "100";
when "1100010100000000" => dout <= "000";
when "1100010101000000" => dout <= "011";
when "1100010110000000" => dout <= "100";
when "1100010000000110" => dout <= "100";
when "1100010000000000" => dout <= "000";
when "1100010001000000" => dout <= "011";
when "1100010010000000" => dout <= "100";
when "0000000011000000" => dout <= "000";
when "0000000000000110" => dout <= "100";
when "0000000000000000" => dout <= "000";
when "0000000001000000" => dout <= "011";
when "0000000010000000" => dout <= "100";
when "0000000111000000" => dout <= "000";
when "0000000100000110" => dout <= "100";
when "0000000100000000" => dout <= "000";
when "0000000101000000" => dout <= "011";
when "0000000110000000" => dout <= "100";
when "0000001011000000" => dout <= "000";
when "0000001000000110" => dout <= "100";
when "0000001000000000" => dout <= "000";
when "0000001001000000" => dout <= "011";
when "0000001010000000" => dout <= "100";
when "0000001111000000" => dout <= "000";
when "0000001100000110" => dout <= "100";
when "0000001100000000" => dout <= "000";
when "0000001101000000" => dout <= "011";
when "0000001110000000" => dout <= "100";
when "1000000011000000" => dout <= "000";
when "1000000000000110" => dout <= "100";
when "1000000000000000" => dout <= "000";
when "1000000001000000" => dout <= "011";
when "1000000010000000" => dout <= "100";
when "1000000111000000" => dout <= "000";
when "1000000100000110" => dout <= "100";
when "1000000100000000" => dout <= "000";
when "1000000101000000" => dout <= "011";
when "1000000110000000" => dout <= "100";
when "1000001111000000" => dout <= "000";
when "1000001100000110" => dout <= "100";
when "1000001100000000" => dout <= "000";
when "1000001101000000" => dout <= "011";
when "1000001110000000" => dout <= "100";
when "0000010000000000" => dout <= "000";
when "0000010100000000" => dout <= "000";
when "0001000011000000" => dout <= "000";
when "0001000000000110" => dout <= "100";
when "0001000000000000" => dout <= "000";
when "0001000001000000" => dout <= "011";
when "0001000010000000" => dout <= "100";
when "0001000111000000" => dout <= "000";
when "0001000100000110" => dout <= "100";
when "0001000100000000" => dout <= "000";
when "0001000101000000" => dout <= "011";
when "0001000110000000" => dout <= "100";
when "0001001011000000" => dout <= "000";
when "0001001000000110" => dout <= "100";
when "0001001000000000" => dout <= "000";
when "0001001001000000" => dout <= "011";
when "0001001010000000" => dout <= "100";
when "0001001111000000" => dout <= "000";
when "0001001100000110" => dout <= "100";
when "0001001100000000" => dout <= "000";
when "0001001101000000" => dout <= "011";
when "0001001110000000" => dout <= "100";
when "1000000011010000" => dout <= "000";
when "1000000000010110" => dout <= "100";
when "1000000000010000" => dout <= "000";
when "1000000001010000" => dout <= "011";
when "1000000010010000" => dout <= "100";
when "1000000111010000" => dout <= "000";
when "1000000100010110" => dout <= "100";
when "1000000100010000" => dout <= "000";
when "1000000101010000" => dout <= "011";
when "1000000110010000" => dout <= "100";
when "1000001111010000" => dout <= "000";
when "1000001100010110" => dout <= "100";
when "1000001100010000" => dout <= "000";
when "1000001101010000" => dout <= "011";
when "1000001110010000" => dout <= "100";
when "0001010000000000" => dout <= "000";
when "0001010100000000" => dout <= "000";
when "0010100011000000" => dout <= "000";
when "0010100000000110" => dout <= "100";
when "0010100000000000" => dout <= "000";
when "0010100001000000" => dout <= "011";
when "0010100010000000" => dout <= "100";
when "0010100111000000" => dout <= "000";
when "0010100100000110" => dout <= "100";
when "0010100100000000" => dout <= "000";
when "0010100101000000" => dout <= "011";
when "0010100110000000" => dout <= "100";
when "0010101011000000" => dout <= "000";
when "0010101000000110" => dout <= "100";
when "0010101000000000" => dout <= "000";
when "0010101001000000" => dout <= "011";
when "0010101010000000" => dout <= "100";
when "0010101111000000" => dout <= "000";
when "0010101100000110" => dout <= "100";
when "0010101100000000" => dout <= "000";
when "0010101101000000" => dout <= "011";
when "0010101110000000" => dout <= "100";
when "1000000011101000" => dout <= "000";
when "1000000000101110" => dout <= "100";
when "1000000000101000" => dout <= "000";
when "1000000001101000" => dout <= "011";
when "1000000010101000" => dout <= "100";
when "1000000111101000" => dout <= "000";
when "1000000100101110" => dout <= "100";
when "1000000100101000" => dout <= "000";
when "1000000101101000" => dout <= "011";
when "1000000110101000" => dout <= "100";
when "1000001111101000" => dout <= "000";
when "1000001100101110" => dout <= "100";
when "1000001100101000" => dout <= "000";
when "1000001101101000" => dout <= "011";
when "1000001110101000" => dout <= "100";
when "0010110000000000" => dout <= "000";
when "0010110100000000" => dout <= "000";
when "0001100011000000" => dout <= "000";
when "0001100000000110" => dout <= "100";
when "0001100000000000" => dout <= "000";
when "0001100001000000" => dout <= "011";
when "0001100010000000" => dout <= "100";
when "0001100111000000" => dout <= "000";
when "0001100100000110" => dout <= "100";
when "0001100100000000" => dout <= "000";
when "0001100101000000" => dout <= "011";
when "0001100110000000" => dout <= "100";
when "0001101011000000" => dout <= "000";
when "0001101000000110" => dout <= "100";
when "0001101000000000" => dout <= "000";
when "0001101001000000" => dout <= "011";
when "0001101010000000" => dout <= "100";
when "0001101111000000" => dout <= "000";
when "0001101100000110" => dout <= "100";
when "0001101100000000" => dout <= "000";
when "0001101101000000" => dout <= "011";
when "0001101110000000" => dout <= "100";
when "1000000011011000" => dout <= "000";
when "1000000000011110" => dout <= "100";
when "1000000000011000" => dout <= "000";
when "1000000001011000" => dout <= "011";
when "1000000010011000" => dout <= "100";
when "1000000111011000" => dout <= "000";
when "1000000100011110" => dout <= "100";
when "1000000100011000" => dout <= "000";
when "1000000101011000" => dout <= "011";
when "1000000110011000" => dout <= "100";
when "1000001111011000" => dout <= "000";
when "1000001100011110" => dout <= "100";
when "1000001100011000" => dout <= "000";
when "1000001101011000" => dout <= "011";
when "1000001110011000" => dout <= "100";
when "0001110000000000" => dout <= "000";
when "0001110100000000" => dout <= "000";
when "1111111011000000" => dout <= "000";
when "1111111000000110" => dout <= "100";
when "1111111000000000" => dout <= "000";
when "1111111001000000" => dout <= "011";
when "1111111010000000" => dout <= "100";
when "1111111100000110" => dout <= "100";
when "1111111100000000" => dout <= "000";
when "1111111101000000" => dout <= "011";
when "1111111110000000" => dout <= "100";
when "0100000000000000" => dout <= "000";
when "0100000100000000" => dout <= "000";
when "0100001000000000" => dout <= "000";
when "0100001100000000" => dout <= "000";
when "0100010000000000" => dout <= "000";
when "0100010100000000" => dout <= "000";
when "0100011000000000" => dout <= "000";
when "0100011100000000" => dout <= "000";
when "1111111011001000" => dout <= "000";
when "1111111000001110" => dout <= "100";
when "1111111000001000" => dout <= "000";
when "1111111001001000" => dout <= "011";
when "1111111010001000" => dout <= "100";
when "1111111100001110" => dout <= "100";
when "1111111100001000" => dout <= "000";
when "1111111101001000" => dout <= "011";
when "1111111110001000" => dout <= "100";
when "0100100000000000" => dout <= "000";
when "0100100100000000" => dout <= "000";
when "0100101000000000" => dout <= "000";
when "0100101100000000" => dout <= "000";
when "0100110000000000" => dout <= "000";
when "0100110100000000" => dout <= "000";
when "0100111000000000" => dout <= "000";
when "0100111100000000" => dout <= "000";
when "0011101011000000" => dout <= "000";
when "0011101000000110" => dout <= "100";
when "0011101000000000" => dout <= "000";
when "0011101001000000" => dout <= "011";
when "0011101010000000" => dout <= "100";
when "0011101111000000" => dout <= "000";
when "0011101100000110" => dout <= "100";
when "0011101100000000" => dout <= "000";
when "0011101101000000" => dout <= "011";
when "0011101110000000" => dout <= "100";
when "0011100000000110" => dout <= "100";
when "0011100000000000" => dout <= "000";
when "0011100001000000" => dout <= "011";
when "0011100010000000" => dout <= "100";
when "0011100011000000" => dout <= "000";
when "0011100100000110" => dout <= "100";
when "0011100100000000" => dout <= "000";
when "0011100101000000" => dout <= "011";
when "0011100110000000" => dout <= "100";
when "0011100111000000" => dout <= "000";
when "1000000011111000" => dout <= "000";
when "1000000000111110" => dout <= "100";
when "1000000000111000" => dout <= "000";
when "1000000001111000" => dout <= "011";
when "1000000010111000" => dout <= "100";
when "1000000111111000" => dout <= "000";
when "1000000100111110" => dout <= "100";
when "1000000100111000" => dout <= "000";
when "1000000101111000" => dout <= "011";
when "1000000110111000" => dout <= "100";
when "1000001111111000" => dout <= "000";
when "1000001100111110" => dout <= "100";
when "1000001100111000" => dout <= "000";
when "1000001101111000" => dout <= "011";
when "1000001110111000" => dout <= "100";
when "0011110000000000" => dout <= "000";
when "0011110100000000" => dout <= "000";
when "1111011011011000" => dout <= "000";
when "1111011000011110" => dout <= "100";
when "1111011000011000" => dout <= "000";
when "1111011001011000" => dout <= "011";
when "1111011010011000" => dout <= "100";
when "1111011111011000" => dout <= "000";
when "1111011100011110" => dout <= "100";
when "1111011100011000" => dout <= "000";
when "1111011101011000" => dout <= "011";
when "1111011110011000" => dout <= "100";
when "0011011100000000" => dout <= "001";
when "0010011100000000" => dout <= "001";
when "0011111100000000" => dout <= "001";
when "0010111100000000" => dout <= "001";
when "1111011011100000" => dout <= "000";
when "1111011000100110" => dout <= "100";
when "1111011000100000" => dout <= "000";
when "1111011001100000" => dout <= "011";
when "1111011010100000" => dout <= "100";
when "1111011111100000" => dout <= "000";
when "1111011100100110" => dout <= "100";
when "1111011100100000" => dout <= "000";
when "1111011101100000" => dout <= "011";
when "1111011110100000" => dout <= "100";
when "1111011011101000" => dout <= "000";
when "1111011000101110" => dout <= "100";
when "1111011000101000" => dout <= "000";
when "1111011001101000" => dout <= "011";
when "1111011010101000" => dout <= "100";
when "1111011111101000" => dout <= "000";
when "1111011100101110" => dout <= "100";
when "1111011100101000" => dout <= "000";
when "1111011101101000" => dout <= "011";
when "1111011110101000" => dout <= "100";
when "1111011011110000" => dout <= "000";
when "1111011000110110" => dout <= "100";
when "1111011000110000" => dout <= "000";
when "1111011001110000" => dout <= "011";
when "1111011010110000" => dout <= "100";
when "1111011111110000" => dout <= "000";
when "1111011100110110" => dout <= "100";
when "1111011100110000" => dout <= "000";
when "1111011101110000" => dout <= "011";
when "1111011110110000" => dout <= "100";
when "1111011011111000" => dout <= "000";
when "1111011000111110" => dout <= "100";
when "1111011000111000" => dout <= "000";
when "1111011001111000" => dout <= "011";
when "1111011010111000" => dout <= "100";
when "1111011111111000" => dout <= "000";
when "1111011100111110" => dout <= "100";
when "1111011100111000" => dout <= "000";
when "1111011101111000" => dout <= "011";
when "1111011110111000" => dout <= "100";
when "1101010000000000" => dout <= "000";
when "1101010100000000" => dout <= "000";
when "1001100000000000" => dout <= "000";
when "1001100100000000" => dout <= "000";
when "1101000011000000" => dout <= "000";
when "1101000000000110" => dout <= "100";
when "1101000000000000" => dout <= "000";
when "1101000001000000" => dout <= "011";
when "1101000010000000" => dout <= "100";
when "1101000111000000" => dout <= "000";
when "1101000100000110" => dout <= "100";
when "1101000100000000" => dout <= "000";
when "1101000101000000" => dout <= "011";
when "1101000110000000" => dout <= "100";
when "1101001011000000" => dout <= "000";
when "1101001000000110" => dout <= "100";
when "1101001000000000" => dout <= "000";
when "1101001001000000" => dout <= "011";
when "1101001010000000" => dout <= "100";
when "1101001111000000" => dout <= "000";
when "1101001100000110" => dout <= "100";
when "1101001100000000" => dout <= "000";
when "1101001101000000" => dout <= "011";
when "1101001110000000" => dout <= "100";
when "0010000011000000" => dout <= "000";
when "0010000000000110" => dout <= "100";
when "0010000000000000" => dout <= "000";
when "0010000001000000" => dout <= "011";
when "0010000010000000" => dout <= "100";
when "0010000111000000" => dout <= "000";
when "0010000100000110" => dout <= "100";
when "0010000100000000" => dout <= "000";
when "0010000101000000" => dout <= "011";
when "0010000110000000" => dout <= "100";
when "0010001011000000" => dout <= "000";
when "0010001000000110" => dout <= "100";
when "0010001000000000" => dout <= "000";
when "0010001001000000" => dout <= "011";
when "0010001010000000" => dout <= "100";
when "0010001111000000" => dout <= "000";
when "0010001100000110" => dout <= "100";
when "0010001100000000" => dout <= "000";
when "0010001101000000" => dout <= "011";
when "0010001110000000" => dout <= "100";
when "1000000011100000" => dout <= "000";
when "1000000000100110" => dout <= "100";
when "1000000000100000" => dout <= "000";
when "1000000001100000" => dout <= "011";
when "1000000010100000" => dout <= "100";
when "1000000111100000" => dout <= "000";
when "1000000100100110" => dout <= "100";
when "1000000100100000" => dout <= "000";
when "1000000101100000" => dout <= "011";
when "1000000110100000" => dout <= "100";
when "1000001111100000" => dout <= "000";
when "1000001100100110" => dout <= "100";
when "1000001100100000" => dout <= "000";
when "1000001101100000" => dout <= "011";
when "1000001110100000" => dout <= "100";
when "0010010000000000" => dout <= "000";
when "0010010100000000" => dout <= "000";
when "0000100000000110" => dout <= "100";
when "0000100000000000" => dout <= "000";
when "0000100001000000" => dout <= "011";
when "0000100010000000" => dout <= "100";
when "0000100011000000" => dout <= "000";
when "0000100100000110" => dout <= "100";
when "0000100100000000" => dout <= "000";
when "0000100101000000" => dout <= "011";
when "0000100110000000" => dout <= "100";
when "0000100111000000" => dout <= "000";
when "0000101011000000" => dout <= "000";
when "0000101000000110" => dout <= "100";
when "0000101000000000" => dout <= "000";
when "0000101001000000" => dout <= "011";
when "0000101010000000" => dout <= "100";
when "0000101111000000" => dout <= "000";
when "0000101100000110" => dout <= "100";
when "0000101100000000" => dout <= "000";
when "0000101101000000" => dout <= "011";
when "0000101110000000" => dout <= "100";
when "1000000011001000" => dout <= "000";
when "1000000000001110" => dout <= "100";
when "1000000000001000" => dout <= "000";
when "1000000001001000" => dout <= "011";
when "1000000010001000" => dout <= "100";
when "1000000111001000" => dout <= "000";
when "1000000100001110" => dout <= "100";
when "1000000100001000" => dout <= "000";
when "1000000101001000" => dout <= "011";
when "1000000110001000" => dout <= "100";
when "1000001111001000" => dout <= "000";
when "1000001100001110" => dout <= "100";
when "1000001100001000" => dout <= "000";
when "1000001101001000" => dout <= "011";
when "1000001110001000" => dout <= "100";
when "0000110000000000" => dout <= "000";
when "0000110100000000" => dout <= "000";
when "1000010000000110" => dout <= "100";
when "1000010000000000" => dout <= "000";
when "1000010001000000" => dout <= "011";
when "1000010010000000" => dout <= "100";
when "1000010100000110" => dout <= "100";
when "1000010100000000" => dout <= "000";
when "1000010101000000" => dout <= "011";
when "1000010110000000" => dout <= "100";
when "1000010011000000" => dout <= "000";
when "1000010111000000" => dout <= "000";
when "1111011011000000" => dout <= "000";
when "1111011000000110" => dout <= "100";
when "1111011000000000" => dout <= "000";
when "1111011001000000" => dout <= "011";
when "1111011010000000" => dout <= "100";
when "1111011111000000" => dout <= "000";
when "1111011100000110" => dout <= "100";
when "1111011100000000" => dout <= "000";
when "1111011101000000" => dout <= "011";
when "1111011110000000" => dout <= "100";
when "1010100000000000" => dout <= "000";
when "1010100100000000" => dout <= "000";
when "0011000000000110" => dout <= "100";
when "0011000000000000" => dout <= "000";
when "0011000001000000" => dout <= "011";
when "0011000010000000" => dout <= "100";
when "0011000011000000" => dout <= "000";
when "0011000100000110" => dout <= "100";
when "0011000100000000" => dout <= "000";
when "0011000101000000" => dout <= "011";
when "0011000110000000" => dout <= "100";
when "0011000111000000" => dout <= "000";
when "0011001011000000" => dout <= "000";
when "0011001000000110" => dout <= "100";
when "0011001000000000" => dout <= "000";
when "0011001001000000" => dout <= "011";
when "0011001010000000" => dout <= "100";
when "0011001111000000" => dout <= "000";
when "0011001100000110" => dout <= "100";
when "0011001100000000" => dout <= "000";
when "0011001101000000" => dout <= "011";
when "0011001110000000" => dout <= "100";
when "1000000011110000" => dout <= "000";
when "1000000000110110" => dout <= "100";
when "1000000000110000" => dout <= "000";
when "1000000001110000" => dout <= "011";
when "1000000010110000" => dout <= "100";
when "1000000111110000" => dout <= "000";
when "1000000100110110" => dout <= "100";
when "1000000100110000" => dout <= "000";
when "1000000101110000" => dout <= "011";
when "1000000110110000" => dout <= "100";
when "1000001111110000" => dout <= "000";
when "1000001100110110" => dout <= "100";
when "1000001100110000" => dout <= "000";
when "1000001101110000" => dout <= "011";
when "1000001110110000" => dout <= "100";
when "0011010000000000" => dout <= "000";
when "0011010100000000" => dout <= "000";
when "1111011011010000" => dout <= "000";
when "1111011000010110" => dout <= "100";
when "1111011000010000" => dout <= "000";
when "1111011001010000" => dout <= "011";
when "1111011010010000" => dout <= "100";
when "1111011111010000" => dout <= "000";
when "1111011100010110" => dout <= "100";
when "1111011100010000" => dout <= "000";
when "1111011101010000" => dout <= "011";
when "1111011110010000" => dout <= "100";
when "1010010000000000" => dout <= "000";
when "1010010100000000" => dout <= "000";
when "1010011000000000" => dout <= "000";
when "1010011100000000" => dout <= "000";
when "1010111000000000" => dout <= "000";
when "1010111100000000" => dout <= "000";
when "1010110000000000" => dout <= "000";
when "1010110100000000" => dout <= "000";
when "1010101000000000" => dout <= "000";
when "1010101100000000" => dout <= "000";
when "1111001000000000" => dout <= "000";
when "1111001100000000" => dout <= "000";
when "0110000000000000" => dout <= "000";
when "0110000100000000" => dout <= "000";
when "1100100000000000" => dout <= "000";
when "1100100100000000" => dout <= "000";
when "0110001000000000" => dout <= "000";
when "0110110000000000" => dout <= "000";
when "0110110100000000" => dout <= "000";
when "0110111000000000" => dout <= "000";
when "0110111100000000" => dout <= "000";
when "0000111100000000" => dout <= "000";
when "0110001100000000" => dout <= "000";
when "0110010000000000" => dout <= "000";
when "0110010100000000" => dout <= "000";
when "0110011000000000" => dout <= "000";
when "0110011100000000" => dout <= "000";
when "1000001000000000" => dout <= "000";
when "1101011000000000" => dout <= "000";
when "1111000100000000" => dout <= "000";
when "1100000000000000" => dout <= "000";
when "1100000100000000" => dout <= "000";
when others => dout <= "---";
end case;
end process;
end rtl;

848
common/CPU/cpu86/alu_rtl.vhd Normal file
View File

@@ -0,0 +1,848 @@
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Ver 0.82 Fixed RCR X,CL --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ALU IS
PORT(
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
w : IN std_logic;
wralu : IN std_logic;
wrcc : IN std_logic;
wrtemp : IN std_logic;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END ALU ;
architecture rtl of alu is
component divider is -- Generic Divider
generic(
WIDTH_DIVID : Integer := 32; -- Width Dividend
WIDTH_DIVIS : Integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8); -- Check Overflow against short Byte/Word
port(
clk : in std_logic; -- System Clock, not used in this architecture
reset : in std_logic; -- Active high, not used in this architecture
dividend : in std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : in std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0); -- changed to 16 bits!! (S not D)
remainder : out std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : in std_logic; -- '1' = 2's Complement, '0' = Unsigned
w : in std_logic; -- '0'=byte, '1'=word (cpu processor)
overflow : out std_logic; -- '1' if div by 0 or overflow
start : in std_logic; -- not used in this architecture
done : out std_logic); -- not used in this architecture
end component divider;
component multiplier is -- Generic Multiplier
generic (WIDTH : integer := 16);
port (multiplicant : in std_logic_vector (WIDTH-1 downto 0);
multiplier : in std_logic_vector (WIDTH-1 downto 0);
product : out std_logic_vector (WIDTH+WIDTH-1 downto 0);-- result
twocomp : in std_logic);
end component multiplier;
signal product_s : std_logic_vector(31 downto 0); -- result multiplier
signal dividend_s : std_logic_vector(31 downto 0); -- Input divider
signal remainder_s : std_logic_vector(15 downto 0); -- Divider result
signal quotient_s : std_logic_vector(15 downto 0); -- Divider result
signal divresult_s : std_logic_vector(31 DOWNTO 0); -- Output divider to alubus
signal div_err_s : std_logic; -- Divide by 0
signal twocomp_s : std_logic; -- Sign Extend for IMUL and IDIV
signal wl_s : std_logic; -- Latched w signal, used for muliplier/divider
signal alubus_s : std_logic_vector (15 DOWNTO 0);
signal abus_s : std_logic_vector(15 downto 0);
signal bbus_s : std_logic_vector(15 downto 0);
signal dxbus_s : std_logic_vector(15 downto 0); -- DX register
signal addbbus_s : std_logic_vector(15 downto 0); -- bbus connected to full adder
signal cbus_s : std_logic_vector(16 downto 0); -- Carry Bus
signal outbus_s : std_logic_vector(15 downto 0); -- outbus=abus+bbus
signal sign16a_s : std_logic_vector(15 downto 0); -- sign extended alu_busa(7 downto 0)
signal sign16b_s : std_logic_vector(15 downto 0); -- sign extended alu_busb(7 downto 0)
signal sign32a_s : std_logic_vector(15 downto 0); -- 16 bits alu_busa(15) vector (CWD)
signal aasbus_s : std_logic_vector(15 downto 0); -- used for AAS instruction
signal aas1bus_s : std_logic_vector(15 downto 0);
signal daabus_s : std_logic_vector(7 downto 0); -- used for DAA instruction
signal dasbus_s : std_logic_vector(7 downto 0); -- used for DAS instruction
signal aaabus_s : std_logic_vector(15 downto 0); -- used for AAA instruction
signal aaa1bus_s : std_logic_vector(15 downto 0);
signal aadbus_s : std_logic_vector(15 downto 0); -- used for AAD instruction
signal aad1bus_s : std_logic_vector(10 downto 0);
signal aad2bus_s : std_logic_vector(10 downto 0);
signal setaas_s : std_logic; -- '1' set CF & AF else both 0
signal setaaa_s : std_logic; -- '1' set CF & AF else both 0
signal setdaa_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal setdas_s : std_logic_vector(1 downto 0); -- "11" set CF & AF
signal bit4_s : std_logic; -- used for AF flag
signal cout_s : std_logic;
signal psrreg_s : std_logic_vector(15 downto 0); -- 16 bits flag register
signal zflaglow_s : std_logic; -- low byte zero flag (w=0)
signal zflaghigh_s : std_logic; -- high byte zero flag (w=1)
signal zeroflag_s : std_logic; -- zero flag, asserted when zero
signal c1flag_s : std_logic; -- Asserted when CX=1(w=1) or CL=1(w=0)
signal zflagdx_s : std_logic; -- Result (DX) zero flag, asserted when not zero (used for mul/imul)
signal zflagah_s : std_logic; -- '1' if IMUL(15..8)/=0
signal hflagah_s : std_logic; -- Used for IMUL
signal hflagdx_s : std_logic; -- Used for IMUL
signal overflow_s : std_logic;
signal parityflag_s: std_logic;
signal signflag_s : std_logic;
alias OFLAG : std_logic is psrreg_s(11);
alias DFLAG : std_logic is psrreg_s(10);
alias IFLAG : std_logic is psrreg_s(9);
alias TFLAG : std_logic is psrreg_s(8);
alias SFLAG : std_logic is psrreg_s(7);
alias ZFLAG : std_logic is psrreg_s(6);
alias AFLAG : std_logic is psrreg_s(4);
alias PFLAG : std_logic is psrreg_s(2);
alias CFLAG : std_logic is psrreg_s(0);
signal alureg_s : std_logic_vector(31 downto 0); -- 31 bits temp register for alu_inbusa & alu_inbusb
signal alucout_s : std_logic; -- ALUREG Carry Out signal
signal alu_temp_s : std_logic_vector(15 downto 0); -- Temp/scratchpad register, use ALU_TEMP to select
signal done_s : std_logic; -- Serial divider conversion done
signal startdiv_s : std_logic; -- Serial divider start pulse
begin
ALUU1 : divider
generic map (WIDTH_DIVID => 32, WIDTH_DIVIS => 16, WIDTH_SHORT => 8)
port map (clk => clk,
reset => reset,
dividend => dividend_s, -- DX:AX
divisor => alureg_s(15 downto 0), -- 0&byte/word
--divisor => bbus_s, -- byte/word
quotient => quotient_s, -- 16 bits
remainder => remainder_s, -- 16 bits
twocomp => twocomp_s,
w => wl_s, -- Byte/Word
overflow => div_err_s, -- Divider Overflow. generate int0
start => startdiv_s, -- start conversion, generated by proc
done => done_s); -- conversion done, latch results
ALUU2 : multiplier
generic map (WIDTH => 16) -- Result is 2*WIDTH bits
port map (multiplicant=> alureg_s(31 downto 16),
multiplier => alureg_s(15 downto 0),
product => product_s, -- 32 bits!
twocomp => twocomp_s);
dividend_s <= X"000000"&alureg_s(23 downto 16) when aluopr=ALU_AAM else dxbus_s & alureg_s(31 downto 16);-- DX is sign extended for byte IDIV
-- start serial divider 1 cycle after wralu pulse received. The reason is that the dividend is loaded into the
-- accumulator thus the data must be valid when this happens.
process (clk, reset)
begin
if reset='1' then
startdiv_s <= '0';
elsif rising_edge(clk) then
if (wralu='1' and (aluopr=ALU_DIV or aluopr=ALU_IDIV OR aluopr=ALU_AAM)) then
startdiv_s <= '1';
else
startdiv_s <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Create Full adder
----------------------------------------------------------------------------
fulladd: for bit_nr in 0 to 15 generate
outbus_s(bit_nr) <= abus_s(bit_nr) xor addbbus_s(bit_nr) xor cbus_s(bit_nr);
cbus_s(bit_nr+1) <= (abus_s(bit_nr) and addbbus_s(bit_nr)) or
(abus_s(bit_nr) and cbus_s(bit_nr)) or
(addbbus_s(bit_nr) and cbus_s(bit_nr));
end generate fulladd;
bit4_s <= cbus_s(4);
sign16a_s <= alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7)&alu_inbusa(7)&
alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7) &alu_inbusa(7 downto 0);
sign16b_s <= alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7)&alu_inbusb(7)&
alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7) &alu_inbusb(7 downto 0);
sign32a_s <= alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&alu_inbusa(15)&
alu_inbusa(15);
-- Invert bus for subtract instructions
addbbus_s <= not bbus_s when ((aluopr=ALU_CMP) or (aluopr=ALU_CMP_SE) or (aluopr=ALU_CMPS) or (aluopr=ALU_DEC)
or (aluopr=ALU_SBB) or (aluopr=ALU_SBB_SE) or (aluopr=ALU_PUSH) or (aluopr=ALU_SUB)
or (aluopr=ALU_SUB_SE) or (aluopr=ALU_SCAS)) else bbus_s;
-- sign extend for IDIV and IMUL instructions
twocomp_s <= '1' when ((aluopr=ALU_IDIV) or (aluopr=ALU_IMUL) or
(aluopr=ALU_IDIV2)or (aluopr=ALU_IMUL2)) else '0';
----------------------------------------------------------------------------
-- Sign Extend Logic abus & bbus & dxbus
----------------------------------------------------------------------------
process (w, alu_inbusa, alu_inbusb, sign16a_s, sign16b_s, aluopr, ax_s, alureg_s)
begin
if (w='1') then -- Word, no sign extend, unless signextend is specified
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alureg_s(15 downto 0); -- previous read ES:[DI]
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when ALU_ADD_SE | ALU_ADC_SE | ALU_SBB_SE | ALU_SUB_SE | ALU_CMP_SE |
ALU_OR_SE | ALU_AND_SE | ALU_XOR_SE=>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= sign16b_s; -- Sign extend on 8 bits immediate values (see O80I2RM)
when others =>
abus_s <= alu_inbusa; -- no sign extend
bbus_s <= alu_inbusb;
end case;
else
case aluopr is
when ALU_CMPS =>
abus_s <= alu_inbusa;
bbus_s <= alureg_s(15 downto 0);
when ALU_DIV | ALU_DIV2 =>
abus_s <= ax_s;
bbus_s <= alu_inbusb;
when ALU_IDIV| ALU_IDIV2 =>
abus_s <= ax_s;
bbus_s <= sign16b_s;
when ALU_MUL | ALU_MUL2 | ALU_SCAS =>
abus_s <= alu_inbusa;
bbus_s <= alu_inbusb;
when ALU_NEG | ALU_NOT =>
abus_s <= not(alu_inbusa); -- NEG instruction, not(operand)+1
bbus_s <= alu_inbusb; -- 0001 (0000 for NOT)
when others =>
abus_s <= sign16a_s;
bbus_s <= sign16b_s;
end case;
end if;
end process;
process (wl_s, aluopr, dx_s, alu_inbusa) -- dxbus for DIV/IDIV only
begin
if (wl_s='1') then -- Word, no sign extend
dxbus_s <= dx_s;
else -- Byte
if (((aluopr=ALU_IDIV) or (aluopr=ALU_IDIV2)) and (alu_inbusa(15)='1')) then -- signed DX<-SE(AX)/bbus<-SE(byte)
dxbus_s <= X"FFFF"; -- DX=FFFF (ignored for mul)
else
dxbus_s <= X"0000"; -- DX=0000 (ignored for mul)
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Carry In logic
----------------------------------------------------------------------------
process (aluopr, psrreg_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_NEG | ALU_NOT
=> cbus_s(0) <= '0';
when ALU_SBB | ALU_SBB_SE
=> cbus_s(0) <= not CFLAG;
when ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE
| ALU_CMPS | ALU_SCAS
=> cbus_s(0) <= '1';
when others => cbus_s(0) <= CFLAG; -- ALU_ADC, ALU_SUB, ALU_SBB
end case;
end process;
----------------------------------------------------------------------------
-- Carry Out logic
-- cout is inverted for ALU_SUB and ALU_SBB before written to psrreg_s
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alu_inbusa)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE |
ALU_CMP | ALU_CMP_SE | ALU_CMPS| ALU_SCAS =>
if (w='1') then cout_s <= cbus_s(16);
else cout_s <= cbus_s(8);
end if;
when ALU_NEG => -- CF=0 if operand=0, else 1
if (alu_inbusa=X"0000") then
cout_s <= '1'; -- Note CFLAG=NOT(cout_s)
else
cout_s <= '0'; -- Note CFLAG=NOT(cout_s)
end if;
when others =>
cout_s <= CFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Overflow Logic
----------------------------------------------------------------------------
process (aluopr, w, psrreg_s, cbus_s, alureg_s, alucout_s, zflaghigh_s, zflagdx_s,hflagdx_s,zflagah_s,
hflagah_s, wl_s, product_s, c1flag_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC | ALU_DEC | ALU_SUB | ALU_SUB_SE |
ALU_SBB | ALU_SBB_SE | ALU_CMP | ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
if w='1' then -- 16 bits
overflow_s <= cbus_s(16) xor cbus_s(15);
else
overflow_s <= cbus_s(8) xor cbus_s(7);
end if;
when ALU_ROL1 | ALU_RCL1 | ALU_SHL1 => -- count=1 using constants as in rcl bx,1
if (((w='1') and (alureg_s(15)/=alucout_s)) or
((w='0') and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROL | ALU_RCL | ALU_SHL => -- cl/cx=1
if (( c1flag_s='1' and w='1' and (alureg_s(15)/=alucout_s)) or
( c1flag_s='1' and w='0' and (alureg_s(7) /=alucout_s))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR1 | ALU_RCR1 | ALU_SHR1 | ALU_SAR1 =>
if (((w='1') and (alureg_s(15)/=alureg_s(14))) or
((w='0') and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_ROR | ALU_RCR | ALU_SHR | ALU_SAR => -- if cl/cx=1
if ((c1flag_s='1' and w='1' and (alureg_s(15)/=alureg_s(14))) or
(c1flag_s='1' and w='0' and (alureg_s(7) /=alureg_s(6)))) then
overflow_s <= '1';
else
overflow_s <= '0';
end if;
when ALU_MUL | ALU_MUL2 =>
if (wl_s='0') then
overflow_s <= zflaghigh_s;
else
overflow_s <= zflagdx_s; -- MSW multiply/divide result
end if;
when ALU_IMUL | ALU_IMUL2 => -- if MSbit(1)='1' & AH=FF/DX=FFFF
if ((wl_s='0' and product_s(7)='1' and hflagah_s='1') or
(wl_s='0' and product_s(7)='0' and zflagah_s='0') or
(wl_s='1' and product_s(15)='1' and hflagdx_s='1') or
(wl_s='1' and product_s(15)='0' and zflagdx_s='0')) then
overflow_s <= '0';
else
overflow_s <= '1';
end if;
when others =>
overflow_s <= OFLAG; -- Keep previous value
end case;
end process;
----------------------------------------------------------------------------
-- Zeroflag set if result=0, zflagdx_s=1 when dx/=0, zflagah_s=1 when ah/=0
----------------------------------------------------------------------------
zflaglow_s <= alubus_s(7) or alubus_s(6) or alubus_s(5) or alubus_s(4) or
alubus_s(3) or alubus_s(2) or alubus_s(1) or alubus_s(0);
zflaghigh_s <= alubus_s(15) or alubus_s(14) or alubus_s(13) or alubus_s(12) or
alubus_s(11) or alubus_s(10) or alubus_s(9) or alubus_s(8);
zeroflag_s <= not(zflaghigh_s or zflaglow_s) when w='1' else not(zflaglow_s);
zflagdx_s <= product_s(31) or product_s(30) or product_s(29) or product_s(28) or
product_s(27) or product_s(26) or product_s(25) or product_s(24) or
product_s(23) or product_s(22) or product_s(21) or product_s(20) or
product_s(19) or product_s(18) or product_s(17) or product_s(16);
zflagah_s <= product_s(15) or product_s(14) or product_s(13) or product_s(12) or
product_s(11) or product_s(10) or product_s(09) or product_s(08);
----------------------------------------------------------------------------
-- hflag set if IMUL result AH=FF or DX=FFFF
----------------------------------------------------------------------------
hflagah_s <= product_s(15) and product_s(14) and product_s(13) and product_s(12) and
product_s(11) and product_s(10) and product_s(9) and product_s(8);
hflagdx_s <= product_s(31) and product_s(30) and product_s(29) and product_s(28) and
product_s(27) and product_s(26) and product_s(25) and product_s(24) and
product_s(23) and product_s(22) and product_s(21) and product_s(20) and
product_s(19) and product_s(18) and product_s(17) and product_s(16);
----------------------------------------------------------------------------
-- Parity flag set if even number of bits in LSB
----------------------------------------------------------------------------
parityflag_s <=not(alubus_s(7) xor alubus_s(6) xor alubus_s(5) xor alubus_s(4) xor
alubus_s(3) xor alubus_s(2) xor alubus_s(1) xor alubus_s(0));
----------------------------------------------------------------------------
-- Sign flag
----------------------------------------------------------------------------
signflag_s <= alubus_s(15) when w='1' else alubus_s(7);
----------------------------------------------------------------------------
-- c1flag asserted if CL or CX=1, used to update the OF flags during
-- rotate/shift instructions
----------------------------------------------------------------------------
c1flag_s <= '1' when (cx_s=X"0001" and w='1') OR (cx_s(7 downto 0)=X"01" and w='0') else '0';
----------------------------------------------------------------------------
-- Temp/ScratchPad Register
-- alureg_s can also be used as temp storage
-- temp<=bbus;
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alu_temp_s<= (others => '0');
elsif rising_edge(clk) then
if (wrtemp='1') then
alu_temp_s <= bbus_s;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- ALU Register used for xchg and rotate/shift instruction
-- latch Carry Out alucout_s signal
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
alureg_s <= (others => '0');
alucout_s<= '0';
wl_s <= '0';
elsif rising_edge(clk) then
if (wralu='1') then
alureg_s(31 downto 16) <= abus_s; -- alu_inbusa;
wl_s <= w; -- Latched w version
if w='1' then -- word operation
case aluopr is
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alureg_s(15);
alucout_s<= alureg_s(15);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & alucout_s; -- shift carry in
alucout_s<= alureg_s(15);
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 0) & '0';
alucout_s<= alureg_s(15);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 1);
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb; -- ALU_PASSB
alucout_s<= CFLAG;
end case;
else
case aluopr is -- To aid resource sharing add MSB byte as above
when ALU_ROL | ALU_ROL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alureg_s(7));
alucout_s<= alureg_s(7);
when ALU_ROR | ALU_ROR1 => alureg_s(15 downto 0) <= alureg_s(0) & alureg_s(15 downto 9) & (alureg_s(0) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_RCL | ALU_RCL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & alucout_s); -- shift carry in
alucout_s<= alureg_s(7);
-- when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (psrreg_s(0) & alureg_s(7 downto 1));
when ALU_RCR | ALU_RCR1 => alureg_s(15 downto 0) <= alucout_s & alureg_s(15 downto 9) & (alucout_s & alureg_s(7 downto 1)); -- Ver 0.82
alucout_s<= alureg_s(0);
when ALU_SHL | ALU_SHL1 => alureg_s(15 downto 0) <= alureg_s(14 downto 7) & (alureg_s(6 downto 0) & '0');
alucout_s<= alureg_s(7);
when ALU_SHR | ALU_SHR1 => alureg_s(15 downto 0) <= '0' & alureg_s(15 downto 9) & ('0' & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_SAR | ALU_SAR1 => alureg_s(15 downto 0) <= alureg_s(15) & alureg_s(15 downto 9)& (alureg_s(7) & alureg_s(7 downto 1));
alucout_s<= alureg_s(0);
when ALU_TEMP => alureg_s(15 downto 0) <= bbus_s;
alucout_s<= '-'; -- Don't care!
when ALU_AAM => alureg_s(15 downto 0) <= X"000A";
alucout_s<= '-'; -- Don't care!
when others => alureg_s(15 downto 0) <= bbus_s ;--alu_inbusb -- ALU_PASSB
alucout_s<= CFLAG;
end case;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- AAS Instruction 3F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aas1bus_s)
begin
aas1bus_s<=alu_inbusa-X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aasbus_s <= aas1bus_s(15 downto 8)&X"0"&aas1bus_s(3 downto 0);
setaas_s <= '1'; -- Set CF and AF flag
else
aasbus_s(7 downto 0) <= X"0"&(alu_inbusa(3 downto 0)); -- AL=AL&0Fh
aasbus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- leave AH unchanged
setaas_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- AAA Instruction 37
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,aaa1bus_s)
begin
aaa1bus_s<=alu_inbusa+X"0106";
if ((alu_inbusa(3 downto 0) > "1001") or (psrreg_s(4)='1')) then
aaabus_s <= aaa1bus_s(15 downto 8)&X"0"&aaa1bus_s(3 downto 0);
setaaa_s <= '1'; -- Set CF and AF flag
else
aaabus_s(7 downto 0) <= X"0"&alu_inbusa(3 downto 0); -- AL=AL&0Fh
aaabus_s(15 downto 8)<= alu_inbusa(15 downto 8); -- AH Unchanged
setaaa_s <= '0'; -- Clear CF and AF flag
end if;
end process;
----------------------------------------------------------------------------
-- DAA Instruction 27
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdaa_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdaa_s(0) <= '1'; -- set AF
else
setdaa_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdaa_s(1) <= '1'; -- set CF
else
setdaa_s(1) <= '0'; -- clr CF
end if;
case setdaa_s is
when "00" => daabus_s <= alu_inbusa(7 downto 0);
when "01" => daabus_s <= alu_inbusa(7 downto 0) + X"06";
when "10" => daabus_s <= alu_inbusa(7 downto 0) + X"60";
when others => daabus_s <= alu_inbusa(7 downto 0) + X"66";
end case;
end process;
----------------------------------------------------------------------------
-- DAS Instruction 2F
----------------------------------------------------------------------------
process (alu_inbusa,psrreg_s,setdas_s)
begin
if ((alu_inbusa(3 downto 0) > X"9") or (psrreg_s(4)='1')) then
setdas_s(0) <= '1'; -- set AF
else
setdas_s(0) <= '0'; -- clr AF
end if;
if ((alu_inbusa(7 downto 0) > X"9F") or (psrreg_s(0)='1') or (alu_inbusa(7 downto 0) > X"99")) then
setdas_s(1) <= '1'; -- set CF
else
setdas_s(1) <= '0'; -- clr CF
end if;
case setdas_s is
when "00" => dasbus_s <= alu_inbusa(7 downto 0);
when "01" => dasbus_s <= alu_inbusa(7 downto 0) - X"06";
when "10" => dasbus_s <= alu_inbusa(7 downto 0) - X"60";
when others => dasbus_s <= alu_inbusa(7 downto 0) - X"66";
end case;
end process;
----------------------------------------------------------------------------
-- AAD Instruction 5D 0A
----------------------------------------------------------------------------
process (alu_inbusa,aad1bus_s,aad2bus_s)
begin
aad1bus_s <= ("00" & alu_inbusa(15 downto 8) & '0') + (alu_inbusa(15 downto 8) & "000"); -- AH*2 + AH*8
aad2bus_s <= aad1bus_s + ("000" & alu_inbusa(7 downto 0)); -- + AL
aadbus_s<= "00000000" & aad2bus_s(7 downto 0);
end process;
----------------------------------------------------------------------------
-- ALU Operation
----------------------------------------------------------------------------
process (aluopr,abus_s,bbus_s,outbus_s,psrreg_s,alureg_s,aasbus_s,aaabus_s,daabus_s,sign16a_s,
sign16b_s,sign32a_s,dasbus_s,product_s,divresult_s,alu_temp_s,aadbus_s,quotient_s,remainder_s)
begin
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_INC | ALU_POP | ALU_SUB | ALU_SUB_SE | ALU_DEC | ALU_PUSH | ALU_CMP | ALU_CMP_SE |
ALU_CMPS | ALU_ADC | ALU_ADC_SE | ALU_SBB | ALU_SBB_SE | ALU_SCAS | ALU_NEG | ALU_NOT
=> alubus_s <= outbus_s;
when ALU_OR | ALU_OR_SE
=> alubus_s <= abus_s OR bbus_s;
when ALU_AND | ALU_AND_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2
=> alubus_s <= abus_s AND bbus_s;
when ALU_XOR | ALU_XOR_SE
=> alubus_s <= abus_s XOR bbus_s;
when ALU_LAHF => alubus_s <= psrreg_s(15 downto 2)&'1'&psrreg_s(0);-- flags onto ALUBUS, note reserved bit1=1
when ALU_MUL | ALU_IMUL
=> alubus_s <= product_s(15 downto 0); -- AX of Multiplier
when ALU_MUL2| ALU_IMUL2
=> alubus_s <= product_s(31 downto 16); -- DX of Multiplier
when ALU_DIV | ALU_IDIV
=> alubus_s <= divresult_s(15 downto 0);-- AX of Divider (quotient)
when ALU_DIV2| ALU_IDIV2
=> alubus_s <= divresult_s(31 downto 16);-- DX of Divider (remainder)
when ALU_SEXT => alubus_s <= sign16a_s; -- Used for CBW Instruction
when ALU_SEXTW => alubus_s <= sign32a_s; -- Used for CWD Instruction
when ALU_AAS => alubus_s <= aasbus_s; -- Used for AAS Instruction
when ALU_AAA => alubus_s <= aaabus_s; -- Used for AAA Instruction
when ALU_DAA => alubus_s <= abus_s(15 downto 8) & daabus_s;-- Used for DAA Instruction
when ALU_DAS => alubus_s <= abus_s(15 downto 8) & dasbus_s;-- Used for DAS Instruction
when ALU_AAD => alubus_s <= aadbus_s; -- Used for AAD Instruction
when ALU_AAM => alubus_s <= quotient_s(7 downto 0) & remainder_s(7 downto 0); -- Used for AAM Instruction
when ALU_ROL | ALU_ROL1 | ALU_ROR | ALU_ROR1 | ALU_RCL | ALU_RCL1 | ALU_RCR | ALU_RCR1 |
ALU_SHL | ALU_SHL1 | ALU_SHR | ALU_SHR1 | ALU_SAR | ALU_SAR1 | ALU_REGL
=> alubus_s <= alureg_s(15 downto 0); -- alu_inbusb to output
when ALU_REGH => alubus_s <= alureg_s(31 downto 16); -- alu_inbusa to output
when ALU_PASSA => alubus_s <= abus_s;
--when ALU_PASSB => alubus_s <= bbus_s;
when ALU_TEMP => alubus_s <= alu_temp_s;
when others => alubus_s <= DONTCARE(15 downto 0);
end case;
end process;
alubus <= alubus_s; -- Connect to entity
----------------------------------------------------------------------------
-- Processor Status Register (Flags)
-- bit Flag
-- 15 Reserved
-- 14 Reserved
-- 13 Reserved Set to 1?
-- 12 Reserved Set to 1?
-- 11 Overflow Flag OF
-- 10 Direction Flag DF
-- 9 Interrupt Flag IF
-- 8 Trace Flag TF
-- 7 Sign Flag SF
-- 6 Zero Flag ZF
-- 5 Reserved
-- 4 Auxiliary Carry AF
-- 3 Reserved
-- 2 Parity Flag PF
-- 1 Reserved Set to 1 ????
-- 0 Carry Flag
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
psrreg_s <= "1111000000000010";
elsif rising_edge(clk) then
if (wrcc='1') then
case aluopr is
when ALU_ADD | ALU_ADD_SE | ALU_ADC | ALU_ADC_SE | ALU_INC =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= bit4_s;
PFLAG <= parityflag_s;
CFLAG <= cout_s;
when ALU_DEC => -- Same as for ALU_SUB exclusing the CFLAG :-(
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
when ALU_SUB | ALU_SUB_SE | ALU_SBB | ALU_SBB_SE | ALU_CMP |
ALU_CMP_SE | ALU_CMPS | ALU_SCAS | ALU_NEG =>
OFLAG <= overflow_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= not bit4_s;
PFLAG <= parityflag_s;
CFLAG <= not cout_s;
when ALU_OR | ALU_OR_SE | ALU_AND | ALU_AND_SE | ALU_XOR | ALU_XOR_SE | ALU_TEST0 | ALU_TEST1 | ALU_TEST2 =>
OFLAG <= '0';
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
AFLAG <= '0'; -- None defined, set to 0 to be compatible with debug
PFLAG <= parityflag_s;
CFLAG <= '0';
when ALU_SHL | ALU_SHR | ALU_SAR |
ALU_SHR1 | ALU_SAR1 | ALU_SHL1 =>
OFLAG <= overflow_s;
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
CFLAG <= alucout_s;
when ALU_CLC =>
CFLAG <= '0';
when ALU_CMC =>
CFLAG <= not CFLAG;
when ALU_STC =>
CFLAG <= '1';
when ALU_CLD =>
DFLAG <= '0';
when ALU_STD =>
DFLAG <= '1';
when ALU_CLI =>
IFLAG <= '0';
when ALU_STI =>
IFLAG <= '1';
when ALU_POP => -- Note only POPF executes a WRCC command, thus save for other pops
psrreg_s <= "1111" & alu_inbusa(11 downto 0);
when ALU_SAHF => -- Write all AH bits (not compatible!)
psrreg_s(7 downto 0) <= alu_inbusa(7 downto 6) & '0' & alu_inbusa(4) & '0' &
alu_inbusa(2) & '0' & alu_inbusa(0);-- SAHF only writes bits 7,6,4,2,0
when ALU_AAS =>
AFLAG <= setaas_s; -- set or clear CF/AF flag
CFLAG <= setaas_s;
SFLAG <= '0';
when ALU_AAA =>
AFLAG <= setaaa_s; -- set or clear CF/AF flag
CFLAG <= setaaa_s;
when ALU_DAA =>
AFLAG <= setdaa_s(0); -- set or clear CF/AF flag
CFLAG <= setdaa_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAD =>
SFLAG <= alubus_s(7); --signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= zeroflag_s;
when ALU_AAM =>
SFLAG <= signflag_s;
PFLAG <= parityflag_s;
ZFLAG <= not(zflaglow_s); -- signflag on AL only
when ALU_DAS =>
AFLAG <= setdas_s(0); -- set or clear CF/AF flag
CFLAG <= setdas_s(1);
PFLAG <= parityflag_s;
SFLAG <= signflag_s;
ZFLAG <= zeroflag_s;
-- Shift Rotate Instructions
when ALU_ROL | ALU_ROR | ALU_RCL | ALU_RCR |
ALU_ROL1 | ALU_RCL1 | ALU_ROR1 | ALU_RCR1 =>
CFLAG <= alucout_s;
OFLAG <= overflow_s;
when ALU_MUL | ALU_MUL2 | ALU_IMUL | ALU_IMUL2 => -- Multiply affects CF&OF only
CFLAG <= overflow_s;
OFLAG <= overflow_s;
when ALU_CLRTIF => -- Clear TF and IF flag
IFLAG <= '0';
TFLAG <= '0';
when others =>
psrreg_s <= psrreg_s;
end case;
end if;
end if;
end process;
ccbus <= psrreg_s; -- Connect to entity
-- Latch Divide by 0 error flag & latched divresult.
-- Requires a MCP from all registers to these endpoint registers!
process (clk, reset)
begin
if reset='1' then
div_err <= '0';
divresult_s <= (others => '0');
elsif rising_edge(clk) then
if done_s='1' then -- Latched pulse generated by serial divider
div_err <= div_err_s; -- Divide Overflow
-- pragma synthesis_off
assert div_err_s='0' report "**** Divide Overflow ***" severity note;
-- pragma synthesis_on
if wl_s='1' then -- Latched version required?
divresult_s <= remainder_s & quotient_s;
else
divresult_s <= remainder_s & remainder_s(7 downto 0) & quotient_s(7 downto 0);
end if;
else
div_err <= '0';
end if;
end if;
end process;
end rtl;

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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
ENTITY biu IS
PORT(
clk : IN std_logic;
csbus : IN std_logic_vector (15 DOWNTO 0);
dbus_in : IN std_logic_vector (7 DOWNTO 0);
dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
decode_state : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
intack : IN std_logic;
intr : IN std_logic;
iomem : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
irq_block : IN std_logic;
nmi : IN std_logic;
opc_req : IN std_logic;
read_req : IN std_logic;
reset : IN std_logic;
status : IN status_out_type;
word : IN std_logic;
write_req : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
flush_ack : OUT std_logic;
instr : OUT instruction_type;
inta : OUT std_logic;
inta1 : OUT std_logic;
iom : OUT std_logic;
irq_req : OUT std_logic;
latcho : OUT std_logic;
mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
rdn : OUT std_logic;
rw_ack : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END biu ;
ARCHITECTURE struct OF biu IS
SIGNAL abus_s : std_logic_vector(19 DOWNTO 0);
SIGNAL abusdp_in : std_logic_vector(19 DOWNTO 0);
SIGNAL addrplus4 : std_logic;
SIGNAL biu_status : std_logic_vector(2 DOWNTO 0);
SIGNAL csbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL halt_instr : std_logic;
SIGNAL inta2_s : std_logic; -- Second INTA pulse, used to latch 8 bist vector
SIGNAL ipbusbiu_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ipbusp1_s : std_logic_vector(15 DOWNTO 0);
SIGNAL irq_ack : std_logic;
SIGNAL irq_clr : std_logic;
SIGNAL irq_type : std_logic_vector(1 DOWNTO 0);
SIGNAL latchabus : std_logic;
SIGNAL latchclr : std_logic;
SIGNAL latchm : std_logic;
SIGNAL latchrw : std_logic;
SIGNAL ldposplus1 : std_logic;
SIGNAL lutbus : std_logic_vector(15 DOWNTO 0);
SIGNAL mux_addr : std_logic_vector(2 DOWNTO 0);
SIGNAL mux_data : std_logic_vector(3 DOWNTO 0);
SIGNAL mux_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL muxabus : std_logic_vector(1 DOWNTO 0);
SIGNAL nbreq : std_logic_vector(2 DOWNTO 0);
SIGNAL rdcode_s : std_logic;
SIGNAL rddata_s : std_logic;
SIGNAL reg1freed : std_logic; -- Delayed version (1 clk) of reg1free
SIGNAL reg4free : std_logic;
SIGNAL regnbok : std_logic;
SIGNAL regplus1 : std_logic;
SIGNAL w_biufsm_s : std_logic;
SIGNAL wr_s : std_logic;
SIGNAL flush_ack_internal : std_logic;
SIGNAL inta1_internal : std_logic;
SIGNAL irq_req_internal : std_logic;
SIGNAL latcho_internal : std_logic;
signal nmi_s : std_logic;
signal nmipre_s : std_logic_vector(1 downto 0); -- metastability first FF for nmi
signal outbus_s : std_logic_vector(7 downto 0); -- used in out instr. bus streering
signal latchmd_s : std_logic; -- internal rdl_s signal
signal abusdp_inp1l_s: std_logic_vector(15 downto 0);
signal latchrw_d_s: std_logic; -- latchrw delayed 1 clk cycle
signal latchclr_d_s: std_logic; -- latchclr delayed 1 clk cycle
signal iom_s : std_logic;
signal instr_trace_s : std_logic; -- TF latched by exec_state pulse
signal irq_req_s : std_logic;
-- Component Declarations
COMPONENT biufsm
PORT (
clk : IN std_logic ;
flush_coming : IN std_logic ;
flush_req : IN std_logic ;
irq_req : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic ;
read_req : IN std_logic ;
reg1freed : IN std_logic ;
reg4free : IN std_logic ;
regnbok : IN std_logic ;
reset : IN std_logic ;
w_biufsm_s : IN std_logic ;
write_req : IN std_logic ;
addrplus4 : OUT std_logic ;
biu_error : OUT std_logic ;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic ;
irq_clr : OUT std_logic ;
latchabus : OUT std_logic ;
latchclr : OUT std_logic ;
latchm : OUT std_logic ;
latcho : OUT std_logic ;
latchrw : OUT std_logic ;
ldposplus1 : OUT std_logic ;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic ;
rddata_s : OUT std_logic ;
regplus1 : OUT std_logic ;
rw_ack : OUT std_logic ;
wr_s : OUT std_logic ;
flush_ack : BUFFER std_logic ;
inta1 : BUFFER std_logic
);
END COMPONENT;
COMPONENT formatter
PORT (
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT regshiftmux
PORT (
clk : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
flush_req : IN std_logic ;
latchm : IN std_logic ;
latcho : IN std_logic ;
mux_addr : IN std_logic_vector (2 DOWNTO 0);
mux_data : IN std_logic_vector (3 DOWNTO 0);
mux_reg : IN std_logic_vector (2 DOWNTO 0);
nbreq : IN std_logic_vector (2 DOWNTO 0);
regplus1 : IN std_logic ;
ldposplus1 : IN std_logic ;
reset : IN std_logic ;
irq : IN std_logic ;
inta1 : IN std_logic ; -- Added for ver 0.71
inta2_s : IN std_logic ;
irq_type : IN std_logic_vector (1 DOWNTO 0);
instr : OUT instruction_type ;
halt_instr : OUT std_logic ;
lutbus : OUT std_logic_vector (15 DOWNTO 0);
reg1free : BUFFER std_logic ;
reg1freed : BUFFER std_logic ; -- Delayed version (1 clk) of reg1free
regnbok : OUT std_logic
);
END COMPONENT;
BEGIN
-------------------------------------------------------------------------
-- Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
dbus_out <= DONTCARE(7 downto 0);
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Data from DataPath
dbus_out <= outbus_s;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- OUT instruction bus steering
-- IO/~M & A[1:0]
---------------------------------------------------------------------------
process(dbusdp_in,abus_s)
begin
if abus_s(0)='0' then
outbus_s <= dbusdp_in(7 downto 0); -- D0
else
outbus_s <= dbusdp_in(15 downto 8); -- D1
end if;
end process;
---------------------------------------------------------------------------
-- Latch word for BIU FSM
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
w_biufsm_s<='0';
elsif rising_edge(clk) then
if latchrw='1' then
w_biufsm_s<=word;
end if;
end if;
end process;
-- metastability sync
process(reset,clk) -- ireg
begin
if reset='1' then
nmipre_s <= "00";
elsif rising_edge(clk) then
nmipre_s <= nmipre_s(0) & nmi;
end if;
end process;
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
nmi_s <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
nmi_s <= '0';
else
nmi_s <= nmi_s or ((not nmipre_s(1)) and nmipre_s(0));
end if;
end if;
end process;
-- Instruction trace flag, the trace flag is latched by the decode_state signal. This will
-- result in the instruction after setting the trace flag not being traced (required).
-- The instr_trace_s flag is not set if the current instruction is a HLT
process(reset, clk)
begin
if (reset='1') then
instr_trace_s <= '0';
elsif rising_edge(clk) then
if (decode_state='1' and halt_instr='0') then
instr_trace_s <= status.flag(8);
end if;
end if;
end process;
-- int0_req=Divider/0 error
-- status(8)=TF
-- status(9)=IF
irq_req_s <= '1' when ((status.div_err='1' or instr_trace_s='1' or nmi_s='1' or (status.flag(9)='1' and intr='1')) and irq_block='0') else '0';
-- set/reset FF
process(reset, clk) -- ireg
begin
if (reset='1') then
irq_req_internal <= '0';
elsif rising_edge(clk) then
if (irq_clr='1') then
irq_req_internal <= '0';
elsif irq_req_s='1' then
irq_req_internal <= '1';
end if;
end if;
end process;
--process (nmi_s,status,intr)
process (reset,clk)
begin
if reset='1' then
irq_type <= (others => '0'); -- Don't care value
elsif rising_edge(clk) then
if irq_req_internal='1' then
if nmi_s='1' then
irq_type <= "10"; -- NMI result in INT2
elsif status.flag(8)='1' then
irq_type <= "01"; -- TF result in INT1
else
irq_type <= "00"; -- INTR result in INT <DBUS>
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Delayed signals
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
latchrw_d_s <= '0';
latchclr_d_s <= '0';
elsif rising_edge(clk) then
latchrw_d_s <= latchrw;
latchclr_d_s <= latchclr;
end if;
end process;
---------------------------------------------------------------------------
-- IO/~M strobe latch
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
iom_s <= '0';
elsif rising_edge(clk) then
if latchrw='1' and muxabus/="00" then
iom_s <= iomem;
elsif latchrw='1' then
iom_s <= '0';
end if;
end if;
end process;
iom <= iom_s;
---------------------------------------------------------------------------
-- Shifted WR strobe latch, to add some address and data hold time the WR
-- strobe is negated .5 clock cycles before address and data changes. This
-- is implemented using the falling edge of the clock. Generally using
-- both edges of a clock is not recommended. If this is not desirable
-- use the latchclr signal with the rising edge of clk. This will result
-- in a full clk cycle for the data hold.
---------------------------------------------------------------------------
process(clk,reset) -- note wr should be 1 clk cycle after latchrw
begin
if reset='1' then
wran <= '1';
elsif falling_edge(clk) then -- wran is negated 0.5 cycle before data&address changes
if latchclr_d_s='1' then
wran <= '1';
elsif wr_s='1' then
wran<='0';
end if;
-- elsif rising_edge(clk) then -- wran negated 1 clk cycle before data&address changes
-- if latchclr='1' then
-- wran <= '1';
-- elsif wr_s='1' then
-- wran<='0';
-- end if;
end if;
end process;
---------------------------------------------------------------------------
-- WR strobe latch. This signal can be use to drive the tri-state drivers
-- and will result in a data hold time until the end of the write cycle.
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
wrn <= '1';
elsif rising_edge(clk) then
if latchclr_d_s='1' then -- Change wrn at the same time as addr changes
wrn <= '1';
elsif wr_s='1' then
wrn<='0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- RD strobe latch
-- rd is active low and connected to top entity
-- Use 1 clk delayed latchrw_d_s signal
-- Original signals were rd_data_s and rd_code_s, new signals rddata_s and
-- rdcode_s.
-- Add flushreq_s, prevend rd signal from starting
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
rdn <= '1';
latchmd_s <= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
rdn <= '1';
latchmd_s <= '0';
elsif latchrw_d_s='1' then
latchmd_s <= rddata_s;
-- Bug reported by Rick Kilgore
-- ver 0.69, stops RD from being asserted during second inta
rdn <= not((rdcode_s or rddata_s) AND NOT intack);
-- The next second was added to create a updown pulse on the rd strobe
-- during a flush action. This will result in a dummy read cycle (unavoidable?)
elsif latchrw='1' then
latchmd_s <= rddata_s;
rdn <= not(rdcode_s or rddata_s);
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Second INTA strobe latch
---------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
inta2_s<= '0';
elsif rising_edge(clk) then
if latchclr_d_s='1' then
inta2_s <= '0';
elsif latchrw_d_s='1' then
inta2_s <= intack;
end if;
end if;
end process;
inta <= not (inta2_s OR inta1_internal);
---------------------------------------------------------------------------
-- Databus stearing for the datapath input
-- mdbus_out(31..16) is only used for "int x", the value si used to load
-- ipreg at the same time as loading cs.
-- Note mdbus must be valid (i.e. contain dbus value) before rising edge
-- of wrn/rdn
---------------------------------------------------------------------------
process(clk,reset)
begin
if reset='1' then
mdbus_out <= (others => '0');
elsif rising_edge(clk) then
if latchmd_s='1' then
if word='0' then -- byte read
mdbus_out <= X"00" & dbus_in;
else
if muxabus="00" then -- first cycle of word read
mdbus_out(15 downto 8) <= dbus_in;
else -- Second cycle
mdbus_out(7 downto 0) <= dbus_in;
end if;
end if;
end if;
end if;
end process;
process(reset,clk)
begin
if reset='1' then
ipbusbiu_s <= RESET_IP_C; -- start 0x0000, CS=FFFF
csbusbiu_s <= RESET_CS_C;
elsif rising_edge(clk) then
if latchabus='1' then
if (addrplus4='1') then
ipbusbiu_s <= ipbusbiu_s+'1';
else
ipbusbiu_s <= ipbus; -- get new address after flush
csbusbiu_s <= csbus;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Latch datapath address+4 for mis-aligned R/W
-------------------------------------------------------------------------
ipbusp1_s <= ipbus+'1';
abusdp_inp1l_s <= ipbus when latchrw='0' else ipbusp1_s;
process(abusdp_inp1l_s,muxabus,csbusbiu_s,ipbusbiu_s,csbus,ipbus)
begin
case muxabus is
when "01" => abus_s <= (csbus&"0000") + ("0000"&ipbus); --abusdp_in;
when "10" => abus_s <= (csbus&"0000") + ("0000"&abusdp_inp1l_s); -- Add 1 if odd address and write word
when others => abus_s <= (csbusbiu_s&"0000") + ("0000"&ipbusbiu_s); -- default to BIU word address
end case;
end process;
-------------------------------------------------------------------------
-- Address/Databus Latch
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
abus <= RESET_VECTOR_C;
elsif rising_edge(clk) then
if latchrw='1' then -- Latch Address
abus <= abus_s;
end if;
end if;
end process;
-- Instance port mappings.
fsm : biufsm
PORT MAP (
clk => clk,
flush_coming => flush_coming,
flush_req => flush_req,
irq_req => irq_req_internal,
irq_type => irq_type,
opc_req => opc_req,
read_req => read_req,
reg1freed => reg1freed,
reg4free => reg4free,
regnbok => regnbok,
reset => reset,
w_biufsm_s => w_biufsm_s,
write_req => write_req,
addrplus4 => addrplus4,
biu_error => biu_error,
biu_status => biu_status,
irq_ack => irq_ack,
irq_clr => irq_clr,
latchabus => latchabus,
latchclr => latchclr,
latchm => latchm,
latcho => latcho_internal,
latchrw => latchrw,
ldposplus1 => ldposplus1,
muxabus => muxabus,
rdcode_s => rdcode_s,
rddata_s => rddata_s,
regplus1 => regplus1,
rw_ack => rw_ack,
wr_s => wr_s,
flush_ack => flush_ack_internal,
inta1 => inta1_internal
);
I4 : formatter
PORT MAP (
lutbus => lutbus,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq
);
shift : regshiftmux
PORT MAP (
clk => clk,
dbus_in => dbus_in,
flush_req => flush_req,
latchm => latchm,
latcho => latcho_internal,
mux_addr => mux_addr,
mux_data => mux_data,
mux_reg => mux_reg,
nbreq => nbreq,
regplus1 => regplus1,
ldposplus1 => ldposplus1,
reset => reset,
irq => irq_ack,
inta1 => inta1_internal,
inta2_s => inta2_s,
irq_type => irq_type,
instr => instr,
halt_instr => halt_instr,
lutbus => lutbus,
reg1free => reg4free,
reg1freed => reg1freed,
regnbok => regnbok
);
flush_ack <= flush_ack_internal;
inta1 <= inta1_internal;
irq_req <= irq_req_internal;
latcho <= latcho_internal;
END struct;

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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY biufsm IS
PORT(
clk : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
irq_req : IN std_logic;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic;
read_req : IN std_logic;
reg1freed : IN std_logic; -- Delayed version (1 clk) of reg1free
reg4free : IN std_logic;
regnbok : IN std_logic;
reset : IN std_logic;
w_biufsm_s : IN std_logic;
write_req : IN std_logic;
addrplus4 : OUT std_logic;
biu_error : OUT std_logic;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic;
irq_clr : OUT std_logic;
latchabus : OUT std_logic;
latchclr : OUT std_logic;
latchm : OUT std_logic;
latcho : OUT std_logic;
latchrw : OUT std_logic;
ldposplus1 : OUT std_logic;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic;
rddata_s : OUT std_logic;
regplus1 : OUT std_logic;
rw_ack : OUT std_logic;
wr_s : OUT std_logic;
flush_ack : BUFFER std_logic;
inta1 : BUFFER std_logic
);
END biufsm ;
ARCHITECTURE fsm OF biufsm IS
signal ws_s : std_logic_vector(WS_WIDTH-1 downto 0);
signal oddflag_s : std_logic;
signal rwmem3_s : std_logic; -- Misaligned Read/Write cycle
TYPE STATE_TYPE IS (
Sreset,
Sws,
Smaxws,
Sack,
Srdopc,
Serror,
Swrite,
Swsw,
Smaxwsw,
Sackw,
Swrodd,
Sread,
Srdodd,
Swsr,
Smaxwsr,
Sackr,
Sflush1,
Sfull,
Sint,
Sintws2,
Sflush2,
Sintws1
);
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
SIGNAL biu_error_int : std_logic ;
SIGNAL biu_status_cld : std_logic_vector (2 DOWNTO 0);
BEGIN
clocked_proc : PROCESS (clk,reset)
BEGIN
IF (reset = '1') THEN
current_state <= Sreset;
biu_error <= '0';
biu_status_cld <= "011";
oddflag_s <= '0';
ws_s <= (others=>'0');
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state;
biu_error <= biu_error_int;
ws_s <= (others=>'0');
CASE current_state IS
WHEN Sreset =>
biu_status_cld<="000";
WHEN Sws =>
ws_s <= ws_s + '1';
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Smaxws =>
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Sack =>
oddflag_s<='0';
IF (write_req = '1') THEN
biu_status_cld<="010";
ELSIF (read_req = '1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
ELSIF (regnbok = '0' and
reg4free = '0') THEN
ELSE
biu_status_cld<="011";
END IF;
WHEN Srdopc =>
ws_s <= (others=>'0');
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Swrite =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Swsw =>
ws_s <= ws_s + '1';
WHEN Sackw =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Swrodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Sread =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Srdodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Swsr =>
ws_s <= ws_s + '1';
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req='1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Sfull =>
IF (write_req='1') THEN
biu_status_cld<="010";
ELSIF (read_req='1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
END IF;
WHEN Sintws2 =>
biu_status_cld<="011";
WHEN Sflush2 =>
biu_status_cld<="000";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
current_state,
flush_coming,
flush_req,
irq_req,
irq_type,
opc_req,
read_req,
reg1freed,
reg4free,
regnbok,
rwmem3_s,
write_req,
ws_s
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
addrplus4 <= '0';
biu_error_int <= '0';
irq_ack <= '0';
irq_clr <= '0';
latchabus <= '0';
latchclr <= '0';
latchm <= '0';
latcho <= '0';
latchrw <= '0';
ldposplus1 <= '0';
muxabus <= "00";
rdcode_s <= '0';
rddata_s <= '0';
regplus1 <= '0';
rw_ack <= '0';
wr_s <= '0';
flush_ack <= '0';
inta1 <= '0';
-- Combined Actions
CASE current_state IS
WHEN Sreset =>
latchrw <= '1' ;
next_state <= Srdopc;
WHEN Sws =>
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s=MAX_WS-1) THEN
next_state <= Smaxws;
ELSE
next_state <= Sws;
END IF;
WHEN Smaxws =>
latchabus<='1';
addrplus4<='1';
latchclr <= '1' ;
ldposplus1<='1';
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSE
next_state <= Sack;
END IF;
WHEN Sack =>
latchm<=reg1freed;
regplus1<='1';
IF (write_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Srdopc =>
rdcode_s <= '1';
latcho <= regnbok and opc_req;
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s/=MAX_WS) THEN
next_state <= Sws;
ELSE
next_state <= Smaxws;
END IF;
WHEN Serror =>
biu_error_int <= '1';
next_state <= Serror;
WHEN Swrite =>
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Swsw =>
latcho <= regnbok and opc_req;
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsw;
ELSE
next_state <= Swsw;
END IF;
WHEN Smaxwsw =>
latcho <= regnbok and opc_req;
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackw;
WHEN Sackw =>
latcho <= regnbok and opc_req;
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw<='1';
next_state <= Swrodd;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Swrodd =>
latcho <= regnbok and opc_req;
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Sread =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Srdodd =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Swsr =>
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsr;
ELSE
next_state <= Swsr;
END IF;
WHEN Smaxwsr =>
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackr;
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw <= '1';
next_state <= Srdodd;
ELSIF (flush_req='1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Sflush1 =>
flush_ack<='1';
IF (flush_req='0') THEN
muxabus<="01";
next_state <= Sflush2;
ELSE
next_state <= Sflush1;
END IF;
WHEN Sfull =>
latcho <= regnbok and opc_req;
IF (write_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Sint =>
latcho <= opc_req;
if irq_type="00" then inta1<='1';
end if;
irq_ack<='1';
next_state <= Sintws1;
WHEN Sintws2 =>
if irq_type="00" then
inta1<='1';
end if;
irq_clr <= '1';
next_state <= Sfull;
WHEN Sflush2 =>
latchabus<='1';
addrplus4<='0';
latchrw <= '1' ;
muxabus <="01";
next_state <= Srdopc;
WHEN Sintws1 =>
if irq_type="00" then
inta1<='1';
end if;
next_state <= Sintws2;
WHEN OTHERS =>
next_state <= Sreset;
END CASE;
END PROCESS nextstate_proc;
biu_status <= biu_status_cld;
rwmem3_s <= '1' when (w_biufsm_s='1' and oddflag_s='0') else '0';
END fsm;

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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY cpu86 IS
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END cpu86 ;
ARCHITECTURE struct OF cpu86 IS
SIGNAL biu_error : std_logic;
SIGNAL clrop : std_logic;
SIGNAL dbusdp_out : std_logic_vector(15 DOWNTO 0);
SIGNAL decode_state : std_logic;
SIGNAL eabus : std_logic_vector(15 DOWNTO 0);
SIGNAL flush_ack : std_logic;
SIGNAL flush_coming : std_logic;
SIGNAL flush_req : std_logic;
SIGNAL instr : instruction_type;
SIGNAL inta1 : std_logic;
SIGNAL intack : std_logic;
SIGNAL iomem : std_logic;
SIGNAL irq_blocked : std_logic;
SIGNAL irq_req : std_logic;
SIGNAL latcho : std_logic;
SIGNAL mdbus_out : std_logic_vector(15 DOWNTO 0);
SIGNAL opc_req : std_logic;
SIGNAL path : path_in_type;
SIGNAL proc_error : std_logic;
SIGNAL read_req : std_logic;
SIGNAL reset : std_logic;
SIGNAL rw_ack : std_logic;
SIGNAL segbus : std_logic_vector(15 DOWNTO 0);
SIGNAL status : status_out_type;
SIGNAL word : std_logic;
SIGNAL write_req : std_logic;
SIGNAL wrpath : write_in_type;
-- Component Declarations
COMPONENT biu
PORT (
clk : IN std_logic ;
csbus : IN std_logic_vector (15 DOWNTO 0);
dbus_in : IN std_logic_vector (7 DOWNTO 0);
dbusdp_in : IN std_logic_vector (15 DOWNTO 0);
decode_state : IN std_logic ;
flush_coming : IN std_logic ;
flush_req : IN std_logic ;
intack : IN std_logic ;
intr : IN std_logic ;
iomem : IN std_logic ;
ipbus : IN std_logic_vector (15 DOWNTO 0);
irq_block : IN std_logic ;
nmi : IN std_logic ;
opc_req : IN std_logic ;
read_req : IN std_logic ;
reset : IN std_logic ;
status : IN status_out_type ;
word : IN std_logic ;
write_req : IN std_logic ;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
flush_ack : OUT std_logic ;
instr : OUT instruction_type ;
inta : OUT std_logic ;
inta1 : OUT std_logic ;
iom : OUT std_logic ;
irq_req : OUT std_logic ;
latcho : OUT std_logic ;
mdbus_out : OUT std_logic_vector (15 DOWNTO 0);
rdn : OUT std_logic ;
rw_ack : OUT std_logic ;
wran : OUT std_logic ;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT datapath
PORT (
clk : IN std_logic ;
clrop : IN std_logic ;
instr : IN instruction_type ;
iomem : IN std_logic ;
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
path : IN path_in_type ;
reset : IN std_logic ;
wrpath : IN write_in_type ;
dbusdp_out : OUT std_logic_vector (15 DOWNTO 0);
eabus : OUT std_logic_vector (15 DOWNTO 0);
segbus : OUT std_logic_vector (15 DOWNTO 0);
status : OUT status_out_type
);
END COMPONENT;
COMPONENT proc
PORT (
clk : IN std_logic ;
flush_ack : IN std_logic ;
instr : IN instruction_type ;
inta1 : IN std_logic ;
irq_req : IN std_logic ;
latcho : IN std_logic ;
reset : IN std_logic ;
rw_ack : IN std_logic ;
status : IN status_out_type ;
clrop : OUT std_logic ;
decode_state : OUT std_logic ;
flush_coming : OUT std_logic ;
flush_req : OUT std_logic ;
intack : OUT std_logic ;
iomem : OUT std_logic ;
irq_blocked : OUT std_logic ;
opc_req : OUT std_logic ;
path : OUT path_in_type ;
proc_error : OUT std_logic ;
read_req : OUT std_logic ;
word : OUT std_logic ;
write_req : OUT std_logic ;
wrpath : OUT write_in_type
);
END COMPONENT;
BEGIN
-- synchronous reset
-- Internal use active high, external use active low
-- Async Asserted, sync negated
process (clk, por)
begin
if por='1' then
reset <= '1';
resoutn <= '0';
elsif rising_edge(clk) then
reset <= '0';
resoutn <= '1';
end if;
end process;
cpuerror <= proc_error OR biu_error;
cpubiu : biu
PORT MAP (
clk => clk,
csbus => segbus,
dbus_in => dbus_in,
dbusdp_in => dbusdp_out,
decode_state => decode_state,
flush_coming => flush_coming,
flush_req => flush_req,
intack => intack,
intr => intr,
iomem => iomem,
ipbus => eabus,
irq_block => irq_blocked,
nmi => nmi,
opc_req => opc_req,
read_req => read_req,
reset => reset,
status => status,
word => word,
write_req => write_req,
abus => abus,
biu_error => biu_error,
dbus_out => dbus_out,
flush_ack => flush_ack,
instr => instr,
inta => inta,
inta1 => inta1,
iom => iom,
irq_req => irq_req,
latcho => latcho,
mdbus_out => mdbus_out,
rdn => rdn,
rw_ack => rw_ack,
wran => wran,
wrn => wrn
);
cpudpath : datapath
PORT MAP (
clk => clk,
clrop => clrop,
instr => instr,
iomem => iomem,
mdbus_in => mdbus_out,
path => path,
reset => reset,
wrpath => wrpath,
dbusdp_out => dbusdp_out,
eabus => eabus,
segbus => segbus,
status => status
);
cpuproc : proc
PORT MAP (
clk => clk,
flush_ack => flush_ack,
instr => instr,
inta1 => inta1,
irq_req => irq_req,
latcho => latcho,
reset => reset,
rw_ack => rw_ack,
status => status,
clrop => clrop,
decode_state => decode_state,
flush_coming => flush_coming,
flush_req => flush_req,
intack => intack,
iomem => iomem,
irq_blocked => irq_blocked,
opc_req => opc_req,
path => path,
proc_error => proc_error,
read_req => read_req,
word => word,
write_req => write_req,
wrpath => wrpath
);
END struct;

425
common/CPU/cpu86/cpu86instr.vhd Normal file
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@@ -0,0 +1,425 @@
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE cpu86instr IS
-----------------------------------------------------------------------------
-- INC/DEC Word Register
-----------------------------------------------------------------------------
constant INCREG0 : std_logic_vector(7 downto 0) := X"40"; -- Inc Register
constant INCREG1 : std_logic_vector(7 downto 0) := X"41";
constant INCREG2 : std_logic_vector(7 downto 0) := X"42";
constant INCREG3 : std_logic_vector(7 downto 0) := X"43";
constant INCREG4 : std_logic_vector(7 downto 0) := X"44";
constant INCREG5 : std_logic_vector(7 downto 0) := X"45";
constant INCREG6 : std_logic_vector(7 downto 0) := X"46";
constant INCREG7 : std_logic_vector(7 downto 0) := X"47";
constant DECREG0 : std_logic_vector(7 downto 0) := X"48"; -- DEC Register
constant DECREG1 : std_logic_vector(7 downto 0) := X"49";
constant DECREG2 : std_logic_vector(7 downto 0) := X"4A";
constant DECREG3 : std_logic_vector(7 downto 0) := X"4B";
constant DECREG4 : std_logic_vector(7 downto 0) := X"4C";
constant DECREG5 : std_logic_vector(7 downto 0) := X"4D";
constant DECREG6 : std_logic_vector(7 downto 0) := X"4E";
constant DECREG7 : std_logic_vector(7 downto 0) := X"4F";
-----------------------------------------------------------------------------
-- IN
-----------------------------------------------------------------------------
constant INFIXED0 : std_logic_vector(7 downto 0) := X"E4"; -- Fixed Port Byte
constant INFIXED1 : std_logic_vector(7 downto 0) := X"E5"; -- Fixed Port Word
constant INDX0 : std_logic_vector(7 downto 0) := X"EC"; -- DX Byte
constant INDX1 : std_logic_vector(7 downto 0) := X"ED"; -- DX Word
-----------------------------------------------------------------------------
-- OUT
-----------------------------------------------------------------------------
constant OUTFIXED0 : std_logic_vector(7 downto 0) := X"E6"; -- Fixed Port Byte
constant OUTFIXED1 : std_logic_vector(7 downto 0) := X"E7"; -- Fixed Port Word
constant OUTDX0 : std_logic_vector(7 downto 0) := X"EE"; -- DX Byte
constant OUTDX1 : std_logic_vector(7 downto 0) := X"EF"; -- DX Word
-----------------------------------------------------------------------------
-- Move Immediate to Register
-----------------------------------------------------------------------------
constant MOVI2R0 : std_logic_vector(7 downto 0) := X"B0"; -- Immediate to Register
constant MOVI2R1 : std_logic_vector(7 downto 0) := X"B1"; -- Byte
constant MOVI2R2 : std_logic_vector(7 downto 0) := X"B2";
constant MOVI2R3 : std_logic_vector(7 downto 0) := X"B3";
constant MOVI2R4 : std_logic_vector(7 downto 0) := X"B4";
constant MOVI2R5 : std_logic_vector(7 downto 0) := X"B5";
constant MOVI2R6 : std_logic_vector(7 downto 0) := X"B6";
constant MOVI2R7 : std_logic_vector(7 downto 0) := X"B7";
constant MOVI2R8 : std_logic_vector(7 downto 0) := X"B8"; -- Word
constant MOVI2R9 : std_logic_vector(7 downto 0) := X"B9";
constant MOVI2R10 : std_logic_vector(7 downto 0) := X"BA";
constant MOVI2R11 : std_logic_vector(7 downto 0) := X"BB";
constant MOVI2R12 : std_logic_vector(7 downto 0) := X"BC";
constant MOVI2R13 : std_logic_vector(7 downto 0) := X"BD";
constant MOVI2R14 : std_logic_vector(7 downto 0) := X"BE";
constant MOVI2R15 : std_logic_vector(7 downto 0) := X"BF";
-----------------------------------------------------------------------------
-- Move Immediate to Register/memory
-----------------------------------------------------------------------------
constant MOVI2RM0 : std_logic_vector(7 downto 0) := X"C6";
constant MOVI2RM1 : std_logic_vector(7 downto 0) := X"C7"; -- Word
-----------------------------------------------------------------------------
-- Segment Register to Register or Memory
-----------------------------------------------------------------------------
constant MOVS2RM : std_logic_vector(7 downto 0) := X"8C";
-----------------------------------------------------------------------------
-- Register or Memory to Segment Register
-----------------------------------------------------------------------------
constant MOVRM2S : std_logic_vector(7 downto 0) := X"8E";
-----------------------------------------------------------------------------
-- Memory to Accumulator ADDRL,ADDRH
-----------------------------------------------------------------------------
constant MOVM2A0 : std_logic_vector(7 downto 0) := X"A0";
constant MOVM2A1 : std_logic_vector(7 downto 0) := X"A1";
-----------------------------------------------------------------------------
-- Accumulator to Memory to Accumulator ADDRL,ADDRH
-----------------------------------------------------------------------------
constant MOVA2M0 : std_logic_vector(7 downto 0) := X"A2";
constant MOVA2M1 : std_logic_vector(7 downto 0) := X"A3";
-----------------------------------------------------------------------------
-- Register/Memory to/from Register
-----------------------------------------------------------------------------
constant MOVRM2R0 : std_logic_vector(7 downto 0) := X"88";
constant MOVRM2R1 : std_logic_vector(7 downto 0) := X"89";
constant MOVRM2R2 : std_logic_vector(7 downto 0) := X"8A";
constant MOVRM2R3 : std_logic_vector(7 downto 0) := X"8B";
-----------------------------------------------------------------------------
-- Segment Override Prefix
-----------------------------------------------------------------------------
constant SEGOPES : std_logic_vector(7 downto 0) := X"26";
constant SEGOPCS : std_logic_vector(7 downto 0) := X"2E";
constant SEGOPSS : std_logic_vector(7 downto 0) := X"36";
constant SEGOPDS : std_logic_vector(7 downto 0) := X"3E";
-----------------------------------------------------------------------------
-- ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Register/Memory to Register
-----------------------------------------------------------------------------
constant ADDRM2R0 : std_logic_vector(7 downto 0) := X"00";
constant ADDRM2R1 : std_logic_vector(7 downto 0) := X"01";
constant ADDRM2R2 : std_logic_vector(7 downto 0) := X"02";
constant ADDRM2R3 : std_logic_vector(7 downto 0) := X"03";
constant ADCRM2R0 : std_logic_vector(7 downto 0) := X"10";
constant ADCRM2R1 : std_logic_vector(7 downto 0) := X"11";
constant ADCRM2R2 : std_logic_vector(7 downto 0) := X"12";
constant ADCRM2R3 : std_logic_vector(7 downto 0) := X"13";
constant SUBRM2R0 : std_logic_vector(7 downto 0) := X"28";
constant SUBRM2R1 : std_logic_vector(7 downto 0) := X"29";
constant SUBRM2R2 : std_logic_vector(7 downto 0) := X"2A";
constant SUBRM2R3 : std_logic_vector(7 downto 0) := X"2B";
constant SBBRM2R0 : std_logic_vector(7 downto 0) := X"18";
constant SBBRM2R1 : std_logic_vector(7 downto 0) := X"19";
constant SBBRM2R2 : std_logic_vector(7 downto 0) := X"1A";
constant SBBRM2R3 : std_logic_vector(7 downto 0) := X"1B";
constant CMPRM2R0 : std_logic_vector(7 downto 0) := X"38";
constant CMPRM2R1 : std_logic_vector(7 downto 0) := X"39";
constant CMPRM2R2 : std_logic_vector(7 downto 0) := X"3A";
constant CMPRM2R3 : std_logic_vector(7 downto 0) := X"3B";
constant ANDRM2R0 : std_logic_vector(7 downto 0) := X"20";
constant ANDRM2R1 : std_logic_vector(7 downto 0) := X"21";
constant ANDRM2R2 : std_logic_vector(7 downto 0) := X"22";
constant ANDRM2R3 : std_logic_vector(7 downto 0) := X"23";
constant ORRM2R0 : std_logic_vector(7 downto 0) := X"08";
constant ORRM2R1 : std_logic_vector(7 downto 0) := X"09";
constant ORRM2R2 : std_logic_vector(7 downto 0) := X"0A";
constant ORRM2R3 : std_logic_vector(7 downto 0) := X"0B";
constant XORRM2R0 : std_logic_vector(7 downto 0) := X"30";
constant XORRM2R1 : std_logic_vector(7 downto 0) := X"31";
constant XORRM2R2 : std_logic_vector(7 downto 0) := X"32";
constant XORRM2R3 : std_logic_vector(7 downto 0) := X"33";
-----------------------------------------------------------------------------
-- OPCODE 80,81,83, ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Immediate to Reg/Mem
-- Instruction defined in reg field
-----------------------------------------------------------------------------
constant O80I2RM : std_logic_vector(7 downto 0) := X"80";
constant O81I2RM : std_logic_vector(7 downto 0) := X"81";
constant O83I2RM : std_logic_vector(7 downto 0) := X"83";
-----------------------------------------------------------------------------
-- ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Immediate with ACCU
-----------------------------------------------------------------------------
constant ADDI2AX0 : std_logic_vector(7 downto 0) := X"04";
constant ADDI2AX1 : std_logic_vector(7 downto 0) := X"05";
constant ADCI2AX0 : std_logic_vector(7 downto 0) := X"14";
constant ADCI2AX1 : std_logic_vector(7 downto 0) := X"15";
constant SUBI2AX0 : std_logic_vector(7 downto 0) := X"2C";
constant SUBI2AX1 : std_logic_vector(7 downto 0) := X"2D";
constant SBBI2AX0 : std_logic_vector(7 downto 0) := X"1C";
constant SBBI2AX1 : std_logic_vector(7 downto 0) := X"1D";
constant CMPI2AX0 : std_logic_vector(7 downto 0) := X"3C";
constant CMPI2AX1 : std_logic_vector(7 downto 0) := X"3D";
constant ANDI2AX0 : std_logic_vector(7 downto 0) := X"24";
constant ANDI2AX1 : std_logic_vector(7 downto 0) := X"25";
constant ORI2AX0 : std_logic_vector(7 downto 0) := X"0C";
constant ORI2AX1 : std_logic_vector(7 downto 0) := X"0D";
constant XORI2AX0 : std_logic_vector(7 downto 0) := X"34";
constant XORI2AX1 : std_logic_vector(7 downto 0) := X"35";
-----------------------------------------------------------------------------
-- TEST (Same as AND but without returning any results)
-----------------------------------------------------------------------------
constant TESTRMR0 : std_logic_vector(7 downto 0) := X"84";
constant TESTRMR1 : std_logic_vector(7 downto 0) := X"85";
constant TESTI2AX0 : std_logic_vector(7 downto 0) := X"A8";
constant TESTI2AX1 : std_logic_vector(7 downto 0) := X"A9";
-----------------------------------------------------------------------------
-- NOT/TEST F6/F7 Shared Instructions
-- TEST regfield=000
-- NOT regfield=010
-- MUL regfield=100
-- IMUL regfield=101
-- DIV regfield=110
-- IDIV regfield=111
-----------------------------------------------------------------------------
constant F6INSTR : std_logic_vector(7 downto 0) := X"F6"; -- Byte
constant F7INSTR : std_logic_vector(7 downto 0) := X"F7"; -- Word
-----------------------------------------------------------------------------
-- Carry Flag CLC/CMC/STC
-----------------------------------------------------------------------------
constant CLC : std_logic_vector(7 downto 0) := X"F8";
constant CMC : std_logic_vector(7 downto 0) := X"F5";
constant STC : std_logic_vector(7 downto 0) := X"F9";
constant CLD : std_logic_vector(7 downto 0) := X"FC";
constant STDx : std_logic_vector(7 downto 0) := X"FD";
constant CLI : std_logic_vector(7 downto 0) := X"FA";
constant STI : std_logic_vector(7 downto 0) := X"FB";
-----------------------------------------------------------------------------
-- 8080 Instruction LAHF/SAHF
-----------------------------------------------------------------------------
constant LAHF : std_logic_vector(7 downto 0) := X"9F";
constant SAHF : std_logic_vector(7 downto 0) := X"9E";
-----------------------------------------------------------------------------
-- Conditional Jumps Jxxx
-----------------------------------------------------------------------------
constant JZ : std_logic_vector(7 downto 0) := X"74";
constant JL : std_logic_vector(7 downto 0) := X"7C";
constant JLE : std_logic_vector(7 downto 0) := X"7E";
constant JB : std_logic_vector(7 downto 0) := X"72";
constant JBE : std_logic_vector(7 downto 0) := X"76";
constant JP : std_logic_vector(7 downto 0) := X"7A";
constant JO : std_logic_vector(7 downto 0) := X"70";
constant JS : std_logic_vector(7 downto 0) := X"78";
constant JNE : std_logic_vector(7 downto 0) := X"75";
constant JNL : std_logic_vector(7 downto 0) := X"7D";
constant JNLE : std_logic_vector(7 downto 0) := X"7F";
constant JNB : std_logic_vector(7 downto 0) := X"73";
constant JNBE : std_logic_vector(7 downto 0) := X"77";
constant JNP : std_logic_vector(7 downto 0) := X"7B";
constant JNO : std_logic_vector(7 downto 0) := X"71";
constant JNS : std_logic_vector(7 downto 0) := X"79";
constant JMPS : std_logic_vector(7 downto 0) := X"EB"; -- Short Jump within segment , SignExt DISPL
constant JMP : std_logic_vector(7 downto 0) := X"E9"; -- Long Jump within segment, No SignExt DISPL
constant JMPDIS : std_logic_vector(7 downto 0) := X"EA"; -- Jump Inter Segment (CS:IP given)
-----------------------------------------------------------------------------
-- Push/Pop Flags
-----------------------------------------------------------------------------
constant PUSHF : std_logic_vector(7 downto 0) := X"9C";
constant POPF : std_logic_vector(7 downto 0) := X"9D";
-----------------------------------------------------------------------------
-- PUSH Register
-----------------------------------------------------------------------------
constant PUSHAX : std_logic_vector(7 downto 0) := X"50";
constant PUSHCX : std_logic_vector(7 downto 0) := X"51";
constant PUSHDX : std_logic_vector(7 downto 0) := X"52";
constant PUSHBX : std_logic_vector(7 downto 0) := X"53";
constant PUSHSP : std_logic_vector(7 downto 0) := X"54";
constant PUSHBP : std_logic_vector(7 downto 0) := X"55";
constant PUSHSI : std_logic_vector(7 downto 0) := X"56";
constant PUSHDI : std_logic_vector(7 downto 0) := X"57";
constant PUSHES : std_logic_vector(7 downto 0) := X"06";
constant PUSHCS : std_logic_vector(7 downto 0) := X"0E";
constant PUSHSS : std_logic_vector(7 downto 0) := X"16";
constant PUSHDS : std_logic_vector(7 downto 0) := X"1E";
-----------------------------------------------------------------------------
-- Pop Register
-----------------------------------------------------------------------------
constant POPAX : std_logic_vector(7 downto 0) := X"58";
constant POPCX : std_logic_vector(7 downto 0) := X"59";
constant POPDX : std_logic_vector(7 downto 0) := X"5A";
constant POPBX : std_logic_vector(7 downto 0) := X"5B";
constant POPSP : std_logic_vector(7 downto 0) := X"5C";
constant POPBP : std_logic_vector(7 downto 0) := X"5D";
constant POPSI : std_logic_vector(7 downto 0) := X"5E";
constant POPDI : std_logic_vector(7 downto 0) := X"5F";
constant POPES : std_logic_vector(7 downto 0) := X"07";
constant POPSS : std_logic_vector(7 downto 0) := X"17";
constant POPDS : std_logic_vector(7 downto 0) := X"1F";
constant POPRM : std_logic_vector(7 downto 0) := X"8F";
-----------------------------------------------------------------------------
-- Exchange Register
-----------------------------------------------------------------------------
constant XCHGW : std_logic_vector(7 downto 0) := X"86";
constant XCHGB : std_logic_vector(7 downto 0) := X"87";
constant XCHGAX : std_logic_vector(7 downto 0) := X"90";
constant XCHGCX : std_logic_vector(7 downto 0) := X"91";
constant XCHGDX : std_logic_vector(7 downto 0) := X"92";
constant XCHGBX : std_logic_vector(7 downto 0) := X"93";
constant XCHGSP : std_logic_vector(7 downto 0) := X"94";
constant XCHGBP : std_logic_vector(7 downto 0) := X"95";
constant XCHGSI : std_logic_vector(7 downto 0) := X"96";
constant XCHGDI : std_logic_vector(7 downto 0) := X"97";
-----------------------------------------------------------------------------
-- Load Effective Address
-----------------------------------------------------------------------------
constant LEA : std_logic_vector(7 downto 0) := X"8D";
constant LDS : std_logic_vector(7 downto 0) := X"C5";
constant LES : std_logic_vector(7 downto 0) := X"C4";
-----------------------------------------------------------------------------
-- Convert Instructions
-----------------------------------------------------------------------------
constant CBW : std_logic_vector(7 downto 0) := X"98";
constant CWD : std_logic_vector(7 downto 0) := X"99";
constant AAS : std_logic_vector(7 downto 0) := X"3F";
constant DAS : std_logic_vector(7 downto 0) := X"2F";
constant AAA : std_logic_vector(7 downto 0) := X"37";
constant DAA : std_logic_vector(7 downto 0) := X"27";
constant AAM : std_logic_vector(7 downto 0) := X"D4";
constant AAD : std_logic_vector(7 downto 0) := X"D5";
constant XLAT : std_logic_vector(7 downto 0) := X"D7";
-----------------------------------------------------------------------------
-- Misc Instructions
-----------------------------------------------------------------------------
constant NOP : std_logic_vector(7 downto 0) := X"90"; -- No Operation
constant HLT : std_logic_vector(7 downto 0) := X"F4"; -- Halt Instruction, wait NMI, INTR, Reset
-----------------------------------------------------------------------------
-- Loop Instructions
-----------------------------------------------------------------------------
constant LOOPCX : std_logic_vector(7 downto 0) := X"E2";
constant LOOPZ : std_logic_vector(7 downto 0) := X"E1";
constant LOOPNZ : std_logic_vector(7 downto 0) := X"E0";
constant JCXZ : std_logic_vector(7 downto 0) := X"E3";
-----------------------------------------------------------------------------
-- CALL Instructions
-----------------------------------------------------------------------------
constant CALL : std_logic_vector(7 downto 0) := X"E8"; -- Direct within Segment
constant CALLDIS : std_logic_vector(7 downto 0) := X"9A"; -- Direct Inter Segment
-----------------------------------------------------------------------------
-- RET Instructions
-----------------------------------------------------------------------------
constant RET : std_logic_vector(7 downto 0) := X"C3"; -- Within Segment
constant RETDIS : std_logic_vector(7 downto 0) := X"CB"; -- Direct Inter Segment
constant RETO : std_logic_vector(7 downto 0) := X"C2"; -- Within Segment + Offset
constant RETDISO : std_logic_vector(7 downto 0) := X"CA"; -- Direct Inter Segment +Offset
-----------------------------------------------------------------------------
-- INT Instructions
-----------------------------------------------------------------------------
constant INT : std_logic_vector(7 downto 0) := X"CD"; -- type=second byte
constant INT3 : std_logic_vector(7 downto 0) := X"CC"; -- type=3
constant INTO : std_logic_vector(7 downto 0) := X"CE"; -- type=4
constant IRET : std_logic_vector(7 downto 0) := X"CF"; -- Interrupt Return
-----------------------------------------------------------------------------
-- String/Repeat Instructions
-----------------------------------------------------------------------------
constant MOVSB : std_logic_vector(7 downto 0) := X"A4";
constant MOVSW : std_logic_vector(7 downto 0) := X"A5";
constant CMPSB : std_logic_vector(7 downto 0) := X"A6";
constant CMPSW : std_logic_vector(7 downto 0) := X"A7";
constant SCASB : std_logic_vector(7 downto 0) := X"AE";
constant SCASW : std_logic_vector(7 downto 0) := X"AF";
constant LODSB : std_logic_vector(7 downto 0) := X"AC";
constant LODSW : std_logic_vector(7 downto 0) := X"AD";
constant STOSB : std_logic_vector(7 downto 0) := X"AA";
constant STOSW : std_logic_vector(7 downto 0) := X"AB";
constant REPNE : std_logic_vector(7 downto 0) := X"F2"; -- stop if zf=1
constant REPE : std_logic_vector(7 downto 0) := X"F3"; -- stop if zf/=1
-----------------------------------------------------------------------------
-- Shift/Rotate Instructions
-- Operation define in MODRM REG bits
-- Note REG=110 is undefined
-----------------------------------------------------------------------------
constant SHFTROT0 : std_logic_vector(7 downto 0) := X"D0";
constant SHFTROT1 : std_logic_vector(7 downto 0) := X"D1";
constant SHFTROT2 : std_logic_vector(7 downto 0) := X"D2";
constant SHFTROT3 : std_logic_vector(7 downto 0) := X"D3";
-----------------------------------------------------------------------------
-- FF/FE Instructions. Use regfiled to decode operation
-- INC reg=000 (FF/FE)
-- DEC reg=001 (FF/FE)
-- CALL reg=010 (FF) Indirect within segment
-- CALL reg=011 (FF) Indirect Intersegment
-- JMP reg=100 (FF) Indirect within segment
-- JMP reg=101 (FF) Indirect Intersegment
-- PUSH reg=110 (FF)
-----------------------------------------------------------------------------
constant FEINSTR : std_logic_vector(7 downto 0) := X"FE";
constant FFINSTR : std_logic_vector(7 downto 0) := X"FF";
END cpu86instr;

285
common/CPU/cpu86/cpu86pack.vhd Normal file
View File

@@ -0,0 +1,285 @@
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
PACKAGE cpu86pack IS
constant RESET_CS_C : std_logic_vector(15 downto 0) := (others => '1'); -- FFFF:0000
constant RESET_IP_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_ES_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_SS_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_DS_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_VECTOR_C : std_logic_vector(19 downto 0) := (RESET_CS_C & X"0") + (X"0" & RESET_IP_C);
constant MUL_MCD_C : std_logic_vector(4 downto 0) := "00010"; -- mul MCP
-- Serial Divider delay
-- changed later to done signal
-- You can gain 1 clk cycle, done can be asserted 1 cycle earlier
constant DIV_MCD_C : std_logic_vector(4 downto 0) := "10011"; -- div waitstates 19!
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant ZEROVECTOR_C : std_logic_vector(31 downto 0) := X"00000000";
-- Minimum value for MAX_WS="000", this result in a 2 cycle rd/wr strobe
-- Total Read cycle is 1 cycle for address setup + 2 cycles for rd/wr strobe, thus
-- minimum bus cycle is 3 clk cycles.
constant WS_WIDTH : integer := 3; -- 2^WS_WIDTH=MAX Waitstates
constant MAX_WS : std_logic_vector(WS_WIDTH-1 downto 0) := "000"; -- 3 clk bus cycles
constant DONTCARE : std_logic_vector(31 downto 0):=X"FFFFFFFF";
-- Status record containing some data and flag register
type instruction_type is record
ireg : std_logic_vector(7 downto 0); -- Instruction register
xmod : std_logic_vector(1 downto 0); -- mod is a reserved word
reg : std_logic_vector(2 downto 0); -- between mode and rm
rm : std_logic_vector(2 downto 0);
data : std_logic_vector(15 downto 0);
disp : std_logic_vector(15 downto 0);
nb : std_logic_vector(2 downto 0); -- Number of bytes
end record;
-- Status record containing some data and flag register
type status_out_type is record
ax : std_logic_vector(15 downto 0);
cx_one : std_logic; -- '1' if CX=0001
cx_zero : std_logic; -- '1' if CX=0000
cl : std_logic_vector(7 downto 0); -- 5 bits shift/rotate counter
flag : std_logic_vector(15 downto 0);
div_err : std_logic; -- Divider overflow
end record;
--------------------------------------------------------------------------------------
-- Data Path Records
--------------------------------------------------------------------------------------
type path_in_type is record
datareg_input : std_logic_vector(6 downto 0); -- dimux(3) & w & seldreg(3)
alu_operation : std_logic_vector(14 downto 0);-- selalua(4) & selalub(4) & aluopr(7)
dbus_output : std_logic_vector(1 downto 0); -- (Odd/Even) domux setting
segreg_input : std_logic_vector(3 downto 0); -- simux & selsreg
ea_output : std_logic_vector(9 downto 0); -- dispmux(3) & eamux(4) & [flag]&segop(2)
end record;
-- Write Strobe Record for Data Path
type write_in_type is record
wrd : std_logic; -- Write datareg
wralu : std_logic; -- Write ALU result
wrcc : std_logic; -- Write Flag register
wrs : std_logic; -- Write Segment register
wrip : std_logic; -- Write Instruction Pointer
wrop : std_logic; -- Write Segment Prefix register, Set Prefix Flag
wrtemp: std_logic; -- Write to ALU_TEMP register
end record;
constant SET_OPFLAG : std_logic:='1'; -- Override Prefix Flag
-- DIMUX
constant DATAIN_IN : std_logic_vector(2 downto 0) := "000";
constant EABUS_IN : std_logic_vector(2 downto 0) := "001";
constant ALUBUS_IN : std_logic_vector(2 downto 0) := "010";
constant MDBUS_IN : std_logic_vector(2 downto 0) := "011";
constant ES_IN : std_logic_vector(2 downto 0) := "100";
constant CS_IN : std_logic_vector(2 downto 0) := "101";
constant SS_IN : std_logic_vector(2 downto 0) := "110";
constant DS_IN : std_logic_vector(2 downto 0) := "111";
-- SIMUX Segment Register input Mux
constant SDATAIN_IN : std_logic_vector(1 downto 0) := "00";
constant SEABUS_IN : std_logic_vector(1 downto 0) := "01"; -- Effective Address
constant SALUBUS_IN : std_logic_vector(1 downto 0) := "10";
constant SMDBUS_IN : std_logic_vector(1 downto 0) := "11";
-- DOMUX (Note bit 2=odd/even)
constant ALUBUS_OUT : std_logic_vector(1 downto 0) := "00";
constant CCBUS_OUT : std_logic_vector(1 downto 0) := "01";
constant DIBUS_OUT : std_logic_vector(1 downto 0) := "10";
constant IPBUS_OUT : std_logic_vector(1 downto 0) := "11";
-- dispmux(3) & eamux(4) & poflag & segop[1:0]
-- note some bits may be dontcare!
constant NB_ES_IP : std_logic_vector(9 downto 0) := "0000000000"; -- IPREG+NB ADDR=ES:IP
constant NB_CS_IP : std_logic_vector(9 downto 0) := "0000000001";
constant NB_SS_IP : std_logic_vector(9 downto 0) := "0000000010";
constant NB_DS_IP : std_logic_vector(9 downto 0) := "0000000011";
constant NB_ES_EA : std_logic_vector(9 downto 0) := "0000001000"; -- IPREG+NB ADDR=EA
constant NB_CS_EA : std_logic_vector(9 downto 0) := "0000001001";
constant NB_SS_EA : std_logic_vector(9 downto 0) := "0000001010";
constant NB_DS_EA : std_logic_vector(9 downto 0) := "0000001011";
constant DISP_ES_EA : std_logic_vector(9 downto 0) := "0010001000"; -- IPREG+DISP ADDR=EA
constant DISP_CS_EA : std_logic_vector(9 downto 0) := "0010001001";
constant DISP_SS_EA : std_logic_vector(9 downto 0) := "0010001010";
constant DISP_DS_EA : std_logic_vector(9 downto 0) := "0010001011";
constant DISP_CS_IP : std_logic_vector(9 downto 0) := "0010000001"; -- Used for Jx instructions
constant PORT_00_DX : std_logic_vector(6 downto 0) := "0000010"; -- EAMUX IN/OUT instruction
constant PORT_00_EA : std_logic_vector(6 downto 0) := "0000001"; -- EAMUX Segm=00 00:IP or 00:DISP
constant NB_SS_SP : std_logic_vector(6 downto 0) := "0000100"; -- IP=IP+NBREQ, EAMUX=SS:SP , 100, 101, 110 unused
constant LD_SS_SP : std_logic_vector(6 downto 0) := "0100100"; -- Load new IP from MDBUS & out=SS:SP
constant LD_MD_IP : std_logic_vector(9 downto 0) := "0100000001"; -- Load new IP from MDBUS (e.g. RET instruction)
constant LD_CS_IP : std_logic_vector(9 downto 0) := "0110000001"; -- Load new IP (e.g. RET instruction)
constant EA_CS_IP : std_logic_vector(9 downto 0) := "1000001001"; -- Load new IP (e.g. RET instruction)
constant IPB_CS_IP : std_logic_vector(9 downto 0) := "1110000001"; -- Select IPBUS=IPREG
constant MD_EA2_DS : std_logic_vector(9 downto 0) := "0100011011"; -- IP<-MD, addr=DS:EA2
-- SELALUA/B or SELDREG(2 downto 0)
constant REG_AX : std_logic_vector(3 downto 0) := "0000"; -- W=1 Into ALUBUS A or B
constant REG_CX : std_logic_vector(3 downto 0) := "0001";
constant REG_DX : std_logic_vector(3 downto 0) := "0010";
constant REG_BX : std_logic_vector(3 downto 0) := "0011";
constant REG_SP : std_logic_vector(3 downto 0) := "0100";
constant REG_BP : std_logic_vector(3 downto 0) := "0101";
constant REG_SI : std_logic_vector(3 downto 0) := "0110";
constant REG_DI : std_logic_vector(3 downto 0) := "0111";
constant REG_DATAIN : std_logic_vector(3 downto 0) := "1000"; -- Pass data_in to ALU
constant REG_MDBUS : std_logic_vector(3 downto 0) := "1111"; -- Pass memory bus (mdbus) to ALU
-- Only for SELALUB
constant REG_CONST1 : std_logic_vector(3 downto 0) := "1001"; -- Used for INC/DEC function, W=0/1
constant REG_CONST2 : std_logic_vector(3 downto 0) := "1010"; -- Used for POP/PUSH function W=1
-- W+SELDREG
constant REG_AH : std_logic_vector(3 downto 0) := "0100"; -- W=1 SELDREG=AH
---------------------------------------------------------------
-- ALU Operations
-- Use ireg(5 downto 3) / modrm(5 downto 3) / ireg(3 downto 0)
-- Constants for
---------------------------------------------------------------
constant ALU_ADD : std_logic_vector(6 downto 0) := "0000000";
constant ALU_OR : std_logic_vector(6 downto 0) := "0000001";
constant ALU_ADC : std_logic_vector(6 downto 0) := "0000010";
constant ALU_SBB : std_logic_vector(6 downto 0) := "0000011";
constant ALU_AND : std_logic_vector(6 downto 0) := "0000100";
constant ALU_SUB : std_logic_vector(6 downto 0) := "0000101";
constant ALU_XOR : std_logic_vector(6 downto 0) := "0000110";
constant ALU_CMP : std_logic_vector(6 downto 0) := "0000111"; -- See also ALU_CMPS
constant ALU_TEST0 : std_logic_vector(6 downto 0) := "0001000";
constant ALU_TEST1 : std_logic_vector(6 downto 0) := "0001101";
-- Random assignment, these can be changed.
constant ALU_PUSH : std_logic_vector(6 downto 0) := "0001001"; -- Used for PUSH (SUB)
constant ALU_POP : std_logic_vector(6 downto 0) := "0001010"; -- Used for POP (ADD)
constant ALU_REGL : std_logic_vector(6 downto 0) := "0001011"; -- alureg(15..0) (latched alu_busb)
constant ALU_REGH : std_logic_vector(6 downto 0) := "0111011"; -- alureg(31..16) (latched alu_busa)
constant ALU_PASSA : std_logic_vector(6 downto 0) := "0001100"; -- abus_s only
constant ALU_TEMP : std_logic_vector(6 downto 0) := "1111001"; -- Used to select temp/scratchpad register (80186 only)
-- CONST & instr.irg(3 downto 0)
constant ALU_SAHF : std_logic_vector(6 downto 0) := "0001110"; -- AH -> Flags
-- CONST & instr.irg(3 downto 0)
constant ALU_LAHF : std_logic_vector(6 downto 0) := "0001111"; -- Flags->ALUBUS (->AH)
-- CONSTANT & instr.ireg(1) & modrm.reg(5 downto 3)
-- CONSTANT=001
constant ALU_ROL1 : std_logic_vector(6 downto 0) := "0010000"; -- count=1
constant ALU_ROR1 : std_logic_vector(6 downto 0) := "0010001";
constant ALU_RCL1 : std_logic_vector(6 downto 0) := "0010010";
constant ALU_RCR1 : std_logic_vector(6 downto 0) := "0010011";
constant ALU_SHL1 : std_logic_vector(6 downto 0) := "0010100";
constant ALU_SHR1 : std_logic_vector(6 downto 0) := "0010101";
constant ALU_SAR1 : std_logic_vector(6 downto 0) := "0010111";
constant ALU_ROL : std_logic_vector(6 downto 0) := "0011000"; -- Count in CL
constant ALU_ROR : std_logic_vector(6 downto 0) := "0011001";
constant ALU_RCL : std_logic_vector(6 downto 0) := "0011010";
constant ALU_RCR : std_logic_vector(6 downto 0) := "0011011";
constant ALU_SHL : std_logic_vector(6 downto 0) := "0011100";
constant ALU_SHR : std_logic_vector(6 downto 0) := "0011101";
constant ALU_SAR : std_logic_vector(6 downto 0) := "0011111";
-- CONST & modrm.reg(5 downto 3)/instr.ireg(5 downto 3)
constant ALU_INC : std_logic_vector(6 downto 0) := "0100000"; -- Increment
constant ALU_DEC : std_logic_vector(6 downto 0) := "0100001"; -- Decrement also used for LOOP/JCXZ
constant ALU_CLRTIF : std_logic_vector(6 downto 0) := "0100010"; -- Clear TF/IF flag, used for INT
constant ALU_CMPS : std_logic_vector(6 downto 0) := "0100111"; -- Compare String ALUREG-MDBUS
constant ALU_SCAS : std_logic_vector(6 downto 0) := "0101111"; -- AX/AL-MDBUS, no SEXT
-- CONST & instr.irg(3 downto 0)
constant ALU_CMC : std_logic_vector(6 downto 0) := "0100101"; -- Complement Carry
constant ALU_CLC : std_logic_vector(6 downto 0) := "0101000"; -- Clear Carry
constant ALU_STC : std_logic_vector(6 downto 0) := "0101001"; -- Set Carry
constant ALU_CLI : std_logic_vector(6 downto 0) := "0101010"; -- Clear interrupt
constant ALU_STI : std_logic_vector(6 downto 0) := "0101011"; -- Set Interrupt
constant ALU_CLD : std_logic_vector(6 downto 0) := "0101100"; -- Clear Direction
constant ALU_STD : std_logic_vector(6 downto 0) := "0101101"; -- Set Direction
-- CONST & modrm.reg(5 downto 3)
constant ALU_TEST2 : std_logic_vector(6 downto 0) := "0110000"; -- F6/F7
constant ALU_NOT : std_logic_vector(6 downto 0) := "0110010"; -- F6/F7
constant ALU_NEG : std_logic_vector(6 downto 0) := "0110011"; -- F6/F7
constant ALU_MUL : std_logic_vector(6 downto 0) := "0110100"; -- F6/F7
constant ALU_IMUL : std_logic_vector(6 downto 0) := "0110101"; -- F6/F7
constant ALU_DIV : std_logic_vector(6 downto 0) := "0110110"; -- F6/F7
constant ALU_IDIV : std_logic_vector(6 downto 0) := "0110111"; -- F6/F7
-- Second cycle write DX
constant ALU_MUL2 : std_logic_vector(6 downto 0) := "0111100"; -- F6/F7
constant ALU_IMUL2 : std_logic_vector(6 downto 0) := "0111101"; -- F6/F7
constant ALU_DIV2 : std_logic_vector(6 downto 0) := "0111110"; -- F6/F7
constant ALU_IDIV2 : std_logic_vector(6 downto 0) := "0111111"; -- F6/F7
-- CONST & instr.ireg(3 downto 0)
constant ALU_SEXT : std_logic_vector(6 downto 0) := "0111000"; -- Used for CBW
constant ALU_SEXTW : std_logic_vector(6 downto 0) := "0111001"; -- Used for CWD
-- CONSTANT & & instr.ireg(1) & instr.ireg(5 downto 3)
constant ALU_AAM : std_logic_vector(6 downto 0) := "1000010";
constant ALU_AAD : std_logic_vector(6 downto 0) := "1001010";
constant ALU_DAA : std_logic_vector(6 downto 0) := "1001100";
constant ALU_DAS : std_logic_vector(6 downto 0) := "1001101";
constant ALU_AAA : std_logic_vector(6 downto 0) := "1001110";
constant ALU_AAS : std_logic_vector(6 downto 0) := "1001111";
constant ALU_ADD_SE : std_logic_vector(6 downto 0) := "1100000";
constant ALU_OR_SE : std_logic_vector(6 downto 0) := "1100001";
constant ALU_ADC_SE : std_logic_vector(6 downto 0) := "1100010";
constant ALU_SBB_SE : std_logic_vector(6 downto 0) := "1100011";
constant ALU_AND_SE : std_logic_vector(6 downto 0) := "1100100";
constant ALU_SUB_SE : std_logic_vector(6 downto 0) := "1100101";
constant ALU_XOR_SE : std_logic_vector(6 downto 0) := "1100110";
constant ALU_CMP_SE : std_logic_vector(6 downto 0) := "1100111";
END cpu86pack;

720
common/CPU/cpu86/d_table.vhd Normal file
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@@ -0,0 +1,720 @@
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity d_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(3 downto 0));
end d_table;
architecture rtl of d_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "0000";
when "1110100100000000" => dout <= "0000";
when "1111111111100000" => dout <= "0000";
when "1111111100100110" => dout <= "0000";
when "1111111100100000" => dout <= "0000";
when "1111111101100000" => dout <= "0000";
when "1111111110100000" => dout <= "0000";
when "1110101000000000" => dout <= "0110";
when "1111111100101110" => dout <= "0000";
when "1111111100101000" => dout <= "0000";
when "1111111101101000" => dout <= "0000";
when "1111111110101000" => dout <= "0000";
when "1110100000000000" => dout <= "0000";
when "1111111111010000" => dout <= "0000";
when "1111111100010110" => dout <= "0000";
when "1111111100010000" => dout <= "0000";
when "1111111101010000" => dout <= "0000";
when "1111111110010000" => dout <= "0000";
when "1001101000000000" => dout <= "0110";
when "1111111100011110" => dout <= "0000";
when "1111111100011000" => dout <= "0000";
when "1111111101011000" => dout <= "0000";
when "1111111110011000" => dout <= "0000";
when "1100001100000000" => dout <= "0000";
when "1100001000000000" => dout <= "0010";
when "1100101100000000" => dout <= "0000";
when "1100101000000000" => dout <= "0010";
when "0111010000000000" => dout <= "0000";
when "0111110000000000" => dout <= "0000";
when "0111111000000000" => dout <= "0000";
when "0111001000000000" => dout <= "0000";
when "0111011000000000" => dout <= "0000";
when "0111101000000000" => dout <= "0000";
when "0111000000000000" => dout <= "0000";
when "0111100000000000" => dout <= "0000";
when "0111010100000000" => dout <= "0000";
when "0111110100000000" => dout <= "0000";
when "0111111100000000" => dout <= "0000";
when "0111001100000000" => dout <= "0000";
when "0111011100000000" => dout <= "0000";
when "0111101100000000" => dout <= "0000";
when "0111000100000000" => dout <= "0000";
when "0111100100000000" => dout <= "0000";
when "1110001100000000" => dout <= "0000";
when "1110001000000000" => dout <= "0000";
when "1110000100000000" => dout <= "0000";
when "1110000000000000" => dout <= "0000";
when "1100110100000000" => dout <= "0000";
when "1100110000000000" => dout <= "0000";
when "1100111000000000" => dout <= "0000";
when "1100111100000000" => dout <= "0000";
when "1111100000000000" => dout <= "0000";
when "1111010100000000" => dout <= "0000";
when "1111100100000000" => dout <= "0000";
when "1111110000000000" => dout <= "0000";
when "1111110100000000" => dout <= "0000";
when "1111101000000000" => dout <= "0000";
when "1111101100000000" => dout <= "0000";
when "1111010000000000" => dout <= "0000";
when "1001101100000000" => dout <= "0000";
when "1111000000000000" => dout <= "0000";
when "1001000000000000" => dout <= "0000";
when "0010011000000000" => dout <= "0000";
when "0010111000000000" => dout <= "0000";
when "0011011000000000" => dout <= "0000";
when "0011111000000000" => dout <= "0000";
when "1000100011000000" => dout <= "0000";
when "1000100000000000" => dout <= "0000";
when "1000100001000000" => dout <= "0000";
when "1000100010000000" => dout <= "0000";
when "1000100000000110" => dout <= "0000";
when "1000100111000000" => dout <= "0000";
when "1000100100000000" => dout <= "0000";
when "1000100101000000" => dout <= "0000";
when "1000100110000000" => dout <= "0000";
when "1000100100000110" => dout <= "0000";
when "1000101011000000" => dout <= "0000";
when "1000101000000000" => dout <= "0000";
when "1000101001000000" => dout <= "0000";
when "1000101010000000" => dout <= "0000";
when "1000101000000110" => dout <= "0000";
when "1000101111000000" => dout <= "0000";
when "1000101100000000" => dout <= "0000";
when "1000101101000000" => dout <= "0000";
when "1000101110000000" => dout <= "0000";
when "1000101100000110" => dout <= "0000";
when "1100011000000000" => dout <= "0011";
when "1100011001000000" => dout <= "0101";
when "1100011010000000" => dout <= "0111";
when "1100011000000110" => dout <= "0111";
when "1100011100000000" => dout <= "0100";
when "1100011101000000" => dout <= "0110";
when "1100011110000000" => dout <= "1000";
when "1100011100000110" => dout <= "1000";
when "1011000000000000" => dout <= "0001";
when "1011000100000000" => dout <= "0001";
when "1011001000000000" => dout <= "0001";
when "1011001100000000" => dout <= "0001";
when "1011010000000000" => dout <= "0001";
when "1011010100000000" => dout <= "0001";
when "1011011000000000" => dout <= "0001";
when "1011011100000000" => dout <= "0001";
when "1011100000000000" => dout <= "0010";
when "1011100100000000" => dout <= "0010";
when "1011101000000000" => dout <= "0010";
when "1011101100000000" => dout <= "0010";
when "1011110000000000" => dout <= "0010";
when "1011110100000000" => dout <= "0010";
when "1011111000000000" => dout <= "0010";
when "1011111100000000" => dout <= "0010";
when "1010000000000000" => dout <= "0000";
when "1010000100000000" => dout <= "0000";
when "1010001000000000" => dout <= "0000";
when "1010001100000000" => dout <= "0000";
when "1000111011000000" => dout <= "0000";
when "1000111000000000" => dout <= "0000";
when "1000111001000000" => dout <= "0000";
when "1000111010000000" => dout <= "0000";
when "1000111000000110" => dout <= "0000";
when "1000110011000000" => dout <= "0000";
when "1000110000000000" => dout <= "0000";
when "1000110001000000" => dout <= "0000";
when "1000110010000000" => dout <= "0000";
when "1000110000000110" => dout <= "0000";
when "1111111100110000" => dout <= "0000";
when "1111111101110000" => dout <= "0000";
when "1111111110110000" => dout <= "0000";
when "1111111100110110" => dout <= "0000";
when "0101000000000000" => dout <= "0000";
when "0101000100000000" => dout <= "0000";
when "0101001000000000" => dout <= "0000";
when "0101001100000000" => dout <= "0000";
when "0101010000000000" => dout <= "0000";
when "0101010100000000" => dout <= "0000";
when "0101011000000000" => dout <= "0000";
when "0101011100000000" => dout <= "0000";
when "0000011000000000" => dout <= "0000";
when "0000111000000000" => dout <= "0000";
when "0001011000000000" => dout <= "0000";
when "0001111000000000" => dout <= "0000";
when "1000111100000000" => dout <= "0000";
when "1000111101000000" => dout <= "0000";
when "1000111110000000" => dout <= "0000";
when "1000111100000110" => dout <= "0000";
when "1000111111000000" => dout <= "0000";
when "0101100000000000" => dout <= "0000";
when "0101100100000000" => dout <= "0000";
when "0101101000000000" => dout <= "0000";
when "0101101100000000" => dout <= "0000";
when "0101110000000000" => dout <= "0000";
when "0101110100000000" => dout <= "0000";
when "0101111000000000" => dout <= "0000";
when "0101111100000000" => dout <= "0000";
when "0000011100000000" => dout <= "0000";
when "0001011100000000" => dout <= "0000";
when "0001111100000000" => dout <= "0000";
when "1000011011000000" => dout <= "0000";
when "1000011000000000" => dout <= "0000";
when "1000011001000000" => dout <= "0000";
when "1000011010000000" => dout <= "0000";
when "1000011000000110" => dout <= "0000";
when "1000011111000000" => dout <= "0000";
when "1000011100000000" => dout <= "0000";
when "1000011101000000" => dout <= "0000";
when "1000011110000000" => dout <= "0000";
when "1000011100000110" => dout <= "0000";
when "1001000100000000" => dout <= "0000";
when "1001001000000000" => dout <= "0000";
when "1001001100000000" => dout <= "0000";
when "1001010000000000" => dout <= "0000";
when "1001010100000000" => dout <= "0000";
when "1001011000000000" => dout <= "0000";
when "1001011100000000" => dout <= "0000";
when "1110010000000000" => dout <= "0000";
when "1110010100000000" => dout <= "0000";
when "1110110000000000" => dout <= "0000";
when "1110110100000000" => dout <= "0000";
when "1110011000000000" => dout <= "0000";
when "1110011100000000" => dout <= "0000";
when "1110111100000000" => dout <= "0000";
when "1110111000000000" => dout <= "0000";
when "1101011100000000" => dout <= "0000";
when "1001111100000000" => dout <= "0000";
when "1001111000000000" => dout <= "0000";
when "1001110000000000" => dout <= "0000";
when "1001110100000000" => dout <= "0000";
when "1000110100000110" => dout <= "0000";
when "1000110111000000" => dout <= "0000";
when "1000110100000000" => dout <= "0000";
when "1000110101000000" => dout <= "0000";
when "1000110110000000" => dout <= "0000";
when "1100010100000110" => dout <= "0000";
when "1100010100000000" => dout <= "0000";
when "1100010101000000" => dout <= "0000";
when "1100010110000000" => dout <= "0000";
when "1100010000000110" => dout <= "0000";
when "1100010000000000" => dout <= "0000";
when "1100010001000000" => dout <= "0000";
when "1100010010000000" => dout <= "0000";
when "0000000011000000" => dout <= "0000";
when "0000000000000110" => dout <= "0000";
when "0000000000000000" => dout <= "0000";
when "0000000001000000" => dout <= "0000";
when "0000000010000000" => dout <= "0000";
when "0000000111000000" => dout <= "0000";
when "0000000100000110" => dout <= "0000";
when "0000000100000000" => dout <= "0000";
when "0000000101000000" => dout <= "0000";
when "0000000110000000" => dout <= "0000";
when "0000001011000000" => dout <= "0000";
when "0000001000000110" => dout <= "0000";
when "0000001000000000" => dout <= "0000";
when "0000001001000000" => dout <= "0000";
when "0000001010000000" => dout <= "0000";
when "0000001111000000" => dout <= "0000";
when "0000001100000110" => dout <= "0000";
when "0000001100000000" => dout <= "0000";
when "0000001101000000" => dout <= "0000";
when "0000001110000000" => dout <= "0000";
when "1000000011000000" => dout <= "0011";
when "1000000000000110" => dout <= "0111";
when "1000000000000000" => dout <= "0011";
when "1000000001000000" => dout <= "0101";
when "1000000010000000" => dout <= "0111";
when "1000000111000000" => dout <= "0100";
when "1000000100000110" => dout <= "1000";
when "1000000100000000" => dout <= "0100";
when "1000000101000000" => dout <= "0110";
when "1000000110000000" => dout <= "1000";
when "1000001111000000" => dout <= "0011";
when "1000001100000110" => dout <= "0111";
when "1000001100000000" => dout <= "0011";
when "1000001101000000" => dout <= "0101";
when "1000001110000000" => dout <= "0111";
when "0000010000000000" => dout <= "0001";
when "0000010100000000" => dout <= "0010";
when "0001000011000000" => dout <= "0000";
when "0001000000000110" => dout <= "0000";
when "0001000000000000" => dout <= "0000";
when "0001000001000000" => dout <= "0000";
when "0001000010000000" => dout <= "0000";
when "0001000111000000" => dout <= "0000";
when "0001000100000110" => dout <= "0000";
when "0001000100000000" => dout <= "0000";
when "0001000101000000" => dout <= "0000";
when "0001000110000000" => dout <= "0000";
when "0001001011000000" => dout <= "0000";
when "0001001000000110" => dout <= "0000";
when "0001001000000000" => dout <= "0000";
when "0001001001000000" => dout <= "0000";
when "0001001010000000" => dout <= "0000";
when "0001001111000000" => dout <= "0000";
when "0001001100000110" => dout <= "0000";
when "0001001100000000" => dout <= "0000";
when "0001001101000000" => dout <= "0000";
when "0001001110000000" => dout <= "0000";
when "1000000011010000" => dout <= "0011";
when "1000000000010110" => dout <= "0111";
when "1000000000010000" => dout <= "0011";
when "1000000001010000" => dout <= "0101";
when "1000000010010000" => dout <= "0111";
when "1000000111010000" => dout <= "0100";
when "1000000100010110" => dout <= "1000";
when "1000000100010000" => dout <= "0100";
when "1000000101010000" => dout <= "0110";
when "1000000110010000" => dout <= "1000";
when "1000001111010000" => dout <= "0011";
when "1000001100010110" => dout <= "0111";
when "1000001100010000" => dout <= "0011";
when "1000001101010000" => dout <= "0101";
when "1000001110010000" => dout <= "0111";
when "0001010000000000" => dout <= "0001";
when "0001010100000000" => dout <= "0010";
when "0010100011000000" => dout <= "0000";
when "0010100000000110" => dout <= "0000";
when "0010100000000000" => dout <= "0000";
when "0010100001000000" => dout <= "0000";
when "0010100010000000" => dout <= "0000";
when "0010100111000000" => dout <= "0000";
when "0010100100000110" => dout <= "0000";
when "0010100100000000" => dout <= "0000";
when "0010100101000000" => dout <= "0000";
when "0010100110000000" => dout <= "0000";
when "0010101011000000" => dout <= "0000";
when "0010101000000110" => dout <= "0000";
when "0010101000000000" => dout <= "0000";
when "0010101001000000" => dout <= "0000";
when "0010101010000000" => dout <= "0000";
when "0010101111000000" => dout <= "0000";
when "0010101100000110" => dout <= "0000";
when "0010101100000000" => dout <= "0000";
when "0010101101000000" => dout <= "0000";
when "0010101110000000" => dout <= "0000";
when "1000000011101000" => dout <= "0011";
when "1000000000101110" => dout <= "0111";
when "1000000000101000" => dout <= "0011";
when "1000000001101000" => dout <= "0101";
when "1000000010101000" => dout <= "0111";
when "1000000111101000" => dout <= "0100";
when "1000000100101110" => dout <= "1000";
when "1000000100101000" => dout <= "0100";
when "1000000101101000" => dout <= "0110";
when "1000000110101000" => dout <= "1000";
when "1000001111101000" => dout <= "0011";
when "1000001100101110" => dout <= "0111";
when "1000001100101000" => dout <= "0011";
when "1000001101101000" => dout <= "0101";
when "1000001110101000" => dout <= "0111";
when "0010110000000000" => dout <= "0001";
when "0010110100000000" => dout <= "0010";
when "0001100011000000" => dout <= "0000";
when "0001100000000110" => dout <= "0000";
when "0001100000000000" => dout <= "0000";
when "0001100001000000" => dout <= "0000";
when "0001100010000000" => dout <= "0000";
when "0001100111000000" => dout <= "0000";
when "0001100100000110" => dout <= "0000";
when "0001100100000000" => dout <= "0000";
when "0001100101000000" => dout <= "0000";
when "0001100110000000" => dout <= "0000";
when "0001101011000000" => dout <= "0000";
when "0001101000000110" => dout <= "0000";
when "0001101000000000" => dout <= "0000";
when "0001101001000000" => dout <= "0000";
when "0001101010000000" => dout <= "0000";
when "0001101111000000" => dout <= "0000";
when "0001101100000110" => dout <= "0000";
when "0001101100000000" => dout <= "0000";
when "0001101101000000" => dout <= "0000";
when "0001101110000000" => dout <= "0000";
when "1000000011011000" => dout <= "0011";
when "1000000000011110" => dout <= "0111";
when "1000000000011000" => dout <= "0011";
when "1000000001011000" => dout <= "0101";
when "1000000010011000" => dout <= "0111";
when "1000000111011000" => dout <= "0100";
when "1000000100011110" => dout <= "1000";
when "1000000100011000" => dout <= "0100";
when "1000000101011000" => dout <= "0110";
when "1000000110011000" => dout <= "1000";
when "1000001111011000" => dout <= "0011";
when "1000001100011110" => dout <= "0111";
when "1000001100011000" => dout <= "0011";
when "1000001101011000" => dout <= "0101";
when "1000001110011000" => dout <= "0111";
when "0001110000000000" => dout <= "0001";
when "0001110100000000" => dout <= "0010";
when "1111111011000000" => dout <= "0000";
when "1111111000000110" => dout <= "0000";
when "1111111000000000" => dout <= "0000";
when "1111111001000000" => dout <= "0000";
when "1111111010000000" => dout <= "0000";
when "1111111100000110" => dout <= "0000";
when "1111111100000000" => dout <= "0000";
when "1111111101000000" => dout <= "0000";
when "1111111110000000" => dout <= "0000";
when "0100000000000000" => dout <= "0000";
when "0100000100000000" => dout <= "0000";
when "0100001000000000" => dout <= "0000";
when "0100001100000000" => dout <= "0000";
when "0100010000000000" => dout <= "0000";
when "0100010100000000" => dout <= "0000";
when "0100011000000000" => dout <= "0000";
when "0100011100000000" => dout <= "0000";
when "1111111011001000" => dout <= "0000";
when "1111111000001110" => dout <= "0000";
when "1111111000001000" => dout <= "0000";
when "1111111001001000" => dout <= "0000";
when "1111111010001000" => dout <= "0000";
when "1111111100001110" => dout <= "0000";
when "1111111100001000" => dout <= "0000";
when "1111111101001000" => dout <= "0000";
when "1111111110001000" => dout <= "0000";
when "0100100000000000" => dout <= "0000";
when "0100100100000000" => dout <= "0000";
when "0100101000000000" => dout <= "0000";
when "0100101100000000" => dout <= "0000";
when "0100110000000000" => dout <= "0000";
when "0100110100000000" => dout <= "0000";
when "0100111000000000" => dout <= "0000";
when "0100111100000000" => dout <= "0000";
when "0011101011000000" => dout <= "0000";
when "0011101000000110" => dout <= "0000";
when "0011101000000000" => dout <= "0000";
when "0011101001000000" => dout <= "0000";
when "0011101010000000" => dout <= "0000";
when "0011101111000000" => dout <= "0000";
when "0011101100000110" => dout <= "0000";
when "0011101100000000" => dout <= "0000";
when "0011101101000000" => dout <= "0000";
when "0011101110000000" => dout <= "0000";
when "0011100000000110" => dout <= "0000";
when "0011100000000000" => dout <= "0000";
when "0011100001000000" => dout <= "0000";
when "0011100010000000" => dout <= "0000";
when "0011100011000000" => dout <= "0000";
when "0011100100000110" => dout <= "0000";
when "0011100100000000" => dout <= "0000";
when "0011100101000000" => dout <= "0000";
when "0011100110000000" => dout <= "0000";
when "0011100111000000" => dout <= "0000";
when "1000000011111000" => dout <= "0011";
when "1000000000111110" => dout <= "0111";
when "1000000000111000" => dout <= "0011";
when "1000000001111000" => dout <= "0101";
when "1000000010111000" => dout <= "0111";
when "1000000111111000" => dout <= "0100";
when "1000000100111110" => dout <= "1000";
when "1000000100111000" => dout <= "0100";
when "1000000101111000" => dout <= "0110";
when "1000000110111000" => dout <= "1000";
when "1000001111111000" => dout <= "0011";
when "1000001100111110" => dout <= "0111";
when "1000001100111000" => dout <= "0011";
when "1000001101111000" => dout <= "0101";
when "1000001110111000" => dout <= "0111";
when "0011110000000000" => dout <= "0001";
when "0011110100000000" => dout <= "0010";
when "1111011011011000" => dout <= "0000";
when "1111011000011110" => dout <= "0000";
when "1111011000011000" => dout <= "0000";
when "1111011001011000" => dout <= "0000";
when "1111011010011000" => dout <= "0000";
when "1111011111011000" => dout <= "0000";
when "1111011100011110" => dout <= "0000";
when "1111011100011000" => dout <= "0000";
when "1111011101011000" => dout <= "0000";
when "1111011110011000" => dout <= "0000";
when "0011011100000000" => dout <= "0000";
when "0010011100000000" => dout <= "0000";
when "0011111100000000" => dout <= "0000";
when "0010111100000000" => dout <= "0000";
when "1111011011100000" => dout <= "0000";
when "1111011000100110" => dout <= "0000";
when "1111011000100000" => dout <= "0000";
when "1111011001100000" => dout <= "0000";
when "1111011010100000" => dout <= "0000";
when "1111011111100000" => dout <= "0000";
when "1111011100100110" => dout <= "0000";
when "1111011100100000" => dout <= "0000";
when "1111011101100000" => dout <= "0000";
when "1111011110100000" => dout <= "0000";
when "1111011011101000" => dout <= "0000";
when "1111011000101110" => dout <= "0000";
when "1111011000101000" => dout <= "0000";
when "1111011001101000" => dout <= "0000";
when "1111011010101000" => dout <= "0000";
when "1111011111101000" => dout <= "0000";
when "1111011100101110" => dout <= "0000";
when "1111011100101000" => dout <= "0000";
when "1111011101101000" => dout <= "0000";
when "1111011110101000" => dout <= "0000";
when "1111011011110000" => dout <= "0000";
when "1111011000110110" => dout <= "0000";
when "1111011000110000" => dout <= "0000";
when "1111011001110000" => dout <= "0000";
when "1111011010110000" => dout <= "0000";
when "1111011111110000" => dout <= "0000";
when "1111011100110110" => dout <= "0000";
when "1111011100110000" => dout <= "0000";
when "1111011101110000" => dout <= "0000";
when "1111011110110000" => dout <= "0000";
when "1111011011111000" => dout <= "0000";
when "1111011000111110" => dout <= "0000";
when "1111011000111000" => dout <= "0000";
when "1111011001111000" => dout <= "0000";
when "1111011010111000" => dout <= "0000";
when "1111011111111000" => dout <= "0000";
when "1111011100111110" => dout <= "0000";
when "1111011100111000" => dout <= "0000";
when "1111011101111000" => dout <= "0000";
when "1111011110111000" => dout <= "0000";
when "1101010000000000" => dout <= "0000";
when "1101010100000000" => dout <= "0000";
when "1001100000000000" => dout <= "0000";
when "1001100100000000" => dout <= "0000";
when "1101000011000000" => dout <= "0000";
when "1101000000000110" => dout <= "0000";
when "1101000000000000" => dout <= "0000";
when "1101000001000000" => dout <= "0000";
when "1101000010000000" => dout <= "0000";
when "1101000111000000" => dout <= "0000";
when "1101000100000110" => dout <= "0000";
when "1101000100000000" => dout <= "0000";
when "1101000101000000" => dout <= "0000";
when "1101000110000000" => dout <= "0000";
when "1101001011000000" => dout <= "0000";
when "1101001000000110" => dout <= "0000";
when "1101001000000000" => dout <= "0000";
when "1101001001000000" => dout <= "0000";
when "1101001010000000" => dout <= "0000";
when "1101001111000000" => dout <= "0000";
when "1101001100000110" => dout <= "0000";
when "1101001100000000" => dout <= "0000";
when "1101001101000000" => dout <= "0000";
when "1101001110000000" => dout <= "0000";
when "0010000011000000" => dout <= "0000";
when "0010000000000110" => dout <= "0000";
when "0010000000000000" => dout <= "0000";
when "0010000001000000" => dout <= "0000";
when "0010000010000000" => dout <= "0000";
when "0010000111000000" => dout <= "0000";
when "0010000100000110" => dout <= "0000";
when "0010000100000000" => dout <= "0000";
when "0010000101000000" => dout <= "0000";
when "0010000110000000" => dout <= "0000";
when "0010001011000000" => dout <= "0000";
when "0010001000000110" => dout <= "0000";
when "0010001000000000" => dout <= "0000";
when "0010001001000000" => dout <= "0000";
when "0010001010000000" => dout <= "0000";
when "0010001111000000" => dout <= "0000";
when "0010001100000110" => dout <= "0000";
when "0010001100000000" => dout <= "0000";
when "0010001101000000" => dout <= "0000";
when "0010001110000000" => dout <= "0000";
when "1000000011100000" => dout <= "0011";
when "1000000000100110" => dout <= "0111";
when "1000000000100000" => dout <= "0011";
when "1000000001100000" => dout <= "0101";
when "1000000010100000" => dout <= "0111";
when "1000000111100000" => dout <= "0100";
when "1000000100100110" => dout <= "1000";
when "1000000100100000" => dout <= "0100";
when "1000000101100000" => dout <= "0110";
when "1000000110100000" => dout <= "1000";
when "1000001111100000" => dout <= "0011";
when "1000001100100110" => dout <= "0111";
when "1000001100100000" => dout <= "0011";
when "1000001101100000" => dout <= "0101";
when "1000001110100000" => dout <= "0111";
when "0010010000000000" => dout <= "0001";
when "0010010100000000" => dout <= "0010";
when "0000100000000110" => dout <= "0000";
when "0000100000000000" => dout <= "0000";
when "0000100001000000" => dout <= "0000";
when "0000100010000000" => dout <= "0000";
when "0000100011000000" => dout <= "0000";
when "0000100100000110" => dout <= "0000";
when "0000100100000000" => dout <= "0000";
when "0000100101000000" => dout <= "0000";
when "0000100110000000" => dout <= "0000";
when "0000100111000000" => dout <= "0000";
when "0000101011000000" => dout <= "0000";
when "0000101000000110" => dout <= "0000";
when "0000101000000000" => dout <= "0000";
when "0000101001000000" => dout <= "0000";
when "0000101010000000" => dout <= "0000";
when "0000101111000000" => dout <= "0000";
when "0000101100000110" => dout <= "0000";
when "0000101100000000" => dout <= "0000";
when "0000101101000000" => dout <= "0000";
when "0000101110000000" => dout <= "0000";
when "1000000011001000" => dout <= "0011";
when "1000000000001110" => dout <= "0111";
when "1000000000001000" => dout <= "0011";
when "1000000001001000" => dout <= "0101";
when "1000000010001000" => dout <= "0111";
when "1000000111001000" => dout <= "0100";
when "1000000100001110" => dout <= "1000";
when "1000000100001000" => dout <= "0100";
when "1000000101001000" => dout <= "0110";
when "1000000110001000" => dout <= "1000";
when "1000001111001000" => dout <= "0011";
when "1000001100001110" => dout <= "0111";
when "1000001100001000" => dout <= "0011";
when "1000001101001000" => dout <= "0101";
when "1000001110001000" => dout <= "0111";
when "0000110000000000" => dout <= "0001";
when "0000110100000000" => dout <= "0010";
when "1000010000000110" => dout <= "0000";
when "1000010000000000" => dout <= "0000";
when "1000010001000000" => dout <= "0000";
when "1000010010000000" => dout <= "0000";
when "1000010100000110" => dout <= "0000";
when "1000010100000000" => dout <= "0000";
when "1000010101000000" => dout <= "0000";
when "1000010110000000" => dout <= "0000";
when "1000010011000000" => dout <= "0000";
when "1000010111000000" => dout <= "0000";
when "1111011011000000" => dout <= "0011";
when "1111011000000110" => dout <= "0111";
when "1111011000000000" => dout <= "0011";
when "1111011001000000" => dout <= "0101";
when "1111011010000000" => dout <= "0111";
when "1111011111000000" => dout <= "0100";
when "1111011100000110" => dout <= "1000";
when "1111011100000000" => dout <= "0100";
when "1111011101000000" => dout <= "0110";
when "1111011110000000" => dout <= "1000";
when "1010100000000000" => dout <= "0001";
when "1010100100000000" => dout <= "0010";
when "0011000000000110" => dout <= "0000";
when "0011000000000000" => dout <= "0000";
when "0011000001000000" => dout <= "0000";
when "0011000010000000" => dout <= "0000";
when "0011000011000000" => dout <= "0000";
when "0011000100000110" => dout <= "0000";
when "0011000100000000" => dout <= "0000";
when "0011000101000000" => dout <= "0000";
when "0011000110000000" => dout <= "0000";
when "0011000111000000" => dout <= "0000";
when "0011001011000000" => dout <= "0000";
when "0011001000000110" => dout <= "0000";
when "0011001000000000" => dout <= "0000";
when "0011001001000000" => dout <= "0000";
when "0011001010000000" => dout <= "0000";
when "0011001111000000" => dout <= "0000";
when "0011001100000110" => dout <= "0000";
when "0011001100000000" => dout <= "0000";
when "0011001101000000" => dout <= "0000";
when "0011001110000000" => dout <= "0000";
when "1000000011110000" => dout <= "0011";
when "1000000000110110" => dout <= "0111";
when "1000000000110000" => dout <= "0011";
when "1000000001110000" => dout <= "0101";
when "1000000010110000" => dout <= "0111";
when "1000000111110000" => dout <= "0100";
when "1000000100110110" => dout <= "1000";
when "1000000100110000" => dout <= "0100";
when "1000000101110000" => dout <= "0110";
when "1000000110110000" => dout <= "1000";
when "1000001111110000" => dout <= "0011";
when "1000001100110110" => dout <= "0111";
when "1000001100110000" => dout <= "0011";
when "1000001101110000" => dout <= "0101";
when "1000001110110000" => dout <= "0111";
when "0011010000000000" => dout <= "0001";
when "0011010100000000" => dout <= "0010";
when "1111011011010000" => dout <= "0000";
when "1111011000010110" => dout <= "0000";
when "1111011000010000" => dout <= "0000";
when "1111011001010000" => dout <= "0000";
when "1111011010010000" => dout <= "0000";
when "1111011111010000" => dout <= "0000";
when "1111011100010110" => dout <= "0000";
when "1111011100010000" => dout <= "0000";
when "1111011101010000" => dout <= "0000";
when "1111011110010000" => dout <= "0000";
when "1010010000000000" => dout <= "0000";
when "1010010100000000" => dout <= "0000";
when "1010011000000000" => dout <= "0000";
when "1010011100000000" => dout <= "0000";
when "1010111000000000" => dout <= "0000";
when "1010111100000000" => dout <= "0000";
when "1010110000000000" => dout <= "0000";
when "1010110100000000" => dout <= "0000";
when "1010101000000000" => dout <= "0000";
when "1010101100000000" => dout <= "0000";
when "1111001000000000" => dout <= "0000";
when "1111001100000000" => dout <= "0000";
when "0110000000000000" => dout <= "0000";
when "0110000100000000" => dout <= "0000";
when "1100100000000000" => dout <= "0000";
when "1100100100000000" => dout <= "0000";
when "0110001000000000" => dout <= "0000";
when "0110110000000000" => dout <= "0000";
when "0110110100000000" => dout <= "0000";
when "0110111000000000" => dout <= "0000";
when "0110111100000000" => dout <= "0000";
when "0000111100000000" => dout <= "0000";
when "0110001100000000" => dout <= "0000";
when "0110010000000000" => dout <= "0000";
when "0110010100000000" => dout <= "0000";
when "0110011000000000" => dout <= "0000";
when "0110011100000000" => dout <= "0000";
when "1000001000000000" => dout <= "0000";
when "1101011000000000" => dout <= "0000";
when "1111000100000000" => dout <= "0000";
when "1100000000000000" => dout <= "0000";
when "1100000100000000" => dout <= "0000";
when others => dout <= "----";
end case;
end process;
end rtl;

476
common/CPU/cpu86/datapath_struct.vhd Normal file
View File

@@ -0,0 +1,476 @@
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
ENTITY datapath IS
PORT(
clk : IN std_logic;
clrop : IN std_logic;
instr : IN instruction_type;
iomem : IN std_logic;
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
path : IN path_in_type;
reset : IN std_logic;
wrpath : IN write_in_type;
dbusdp_out : OUT std_logic_vector (15 DOWNTO 0);
eabus : OUT std_logic_vector (15 DOWNTO 0);
segbus : OUT std_logic_vector (15 DOWNTO 0);
status : OUT status_out_type
);
END datapath ;
ARCHITECTURE struct OF datapath IS
-- Internal signal declarations
SIGNAL alu_inbusa : std_logic_vector(15 DOWNTO 0);
SIGNAL alu_inbusb : std_logic_vector(15 DOWNTO 0);
SIGNAL alubus : std_logic_vector(15 DOWNTO 0);
SIGNAL aluopr : std_logic_vector(6 DOWNTO 0);
SIGNAL ax_s : std_logic_vector(15 DOWNTO 0);
SIGNAL bp_s : std_logic_vector(15 DOWNTO 0);
SIGNAL bx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ccbus : std_logic_vector(15 DOWNTO 0);
SIGNAL cs_s : std_logic_vector(15 DOWNTO 0);
SIGNAL cx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL data_in : std_logic_vector(15 DOWNTO 0);
SIGNAL di_s : std_logic_vector(15 DOWNTO 0);
SIGNAL dibus : std_logic_vector(15 DOWNTO 0);
SIGNAL dimux : std_logic_vector(2 DOWNTO 0);
SIGNAL disp : std_logic_vector(15 DOWNTO 0);
SIGNAL dispmux : std_logic_vector(2 DOWNTO 0);
SIGNAL div_err : std_logic;
SIGNAL domux : std_logic_vector(1 DOWNTO 0);
SIGNAL ds_s : std_logic_vector(15 DOWNTO 0);
SIGNAL dx_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ea : std_logic_vector(15 DOWNTO 0);
SIGNAL eamux : std_logic_vector(3 DOWNTO 0);
SIGNAL es_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ipbus : std_logic_vector(15 DOWNTO 0);
SIGNAL ipreg : std_logic_vector(15 DOWNTO 0);
SIGNAL nbreq : std_logic_vector(2 DOWNTO 0);
SIGNAL opmux : std_logic_vector(1 DOWNTO 0);
SIGNAL rm : std_logic_vector(2 DOWNTO 0);
SIGNAL sdbus : std_logic_vector(15 DOWNTO 0);
SIGNAL segop : std_logic_vector(2 DOWNTO 0);
SIGNAL selalua : std_logic_vector(3 DOWNTO 0);
SIGNAL selalub : std_logic_vector(3 DOWNTO 0);
SIGNAL seldreg : std_logic_vector(2 DOWNTO 0);
SIGNAL selds : std_logic;
SIGNAL selsreg : std_logic_vector(1 DOWNTO 0);
SIGNAL si_s : std_logic_vector(15 DOWNTO 0);
SIGNAL sibus : std_logic_vector(15 DOWNTO 0);
SIGNAL simux : std_logic_vector(1 DOWNTO 0);
SIGNAL sp_s : std_logic_vector(15 DOWNTO 0);
SIGNAL ss_s : std_logic_vector(15 DOWNTO 0);
SIGNAL w : std_logic;
SIGNAL wralu : std_logic;
SIGNAL wrcc : std_logic;
SIGNAL wrd : std_logic;
SIGNAL wrip : std_logic;
SIGNAL wrop : std_logic;
SIGNAL wrs : std_logic;
SIGNAL wrtemp : std_logic;
SIGNAL xmod : std_logic_vector(1 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL eabus_internal : std_logic_vector (15 DOWNTO 0);
signal domux_s : std_logic_vector(2 downto 0);
signal opreg_s : std_logic_vector(1 downto 0); -- Override Segment Register
signal opflag_s : std_logic; -- set if segment override in progress
signal eam_s : std_logic_vector(15 downto 0);
signal segsel_s : std_logic_vector(5 downto 0); -- segbus select
signal int0cs_s : std_logic;
-- Component Declarations
COMPONENT ALU
PORT (
alu_inbusa : IN std_logic_vector (15 DOWNTO 0);
alu_inbusb : IN std_logic_vector (15 DOWNTO 0);
aluopr : IN std_logic_vector (6 DOWNTO 0);
ax_s : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic ;
cx_s : IN std_logic_vector (15 DOWNTO 0);
dx_s : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
w : IN std_logic ;
wralu : IN std_logic ;
wrcc : IN std_logic ;
wrtemp : IN std_logic ;
alubus : OUT std_logic_vector (15 DOWNTO 0);
ccbus : OUT std_logic_vector (15 DOWNTO 0);
div_err : OUT std_logic
);
END COMPONENT;
COMPONENT dataregfile
PORT (
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic ;
wrd : IN std_logic ;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
clk : IN std_logic ;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT ipregister
PORT (
clk : IN std_logic ;
ipbus : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic ;
wrip : IN std_logic ;
ipreg : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT segregfile
PORT (
selsreg : IN std_logic_vector (1 DOWNTO 0);
sibus : IN std_logic_vector (15 DOWNTO 0);
wrs : IN std_logic ;
reset : IN std_logic ;
clk : IN std_logic ;
sdbus : OUT std_logic_vector (15 DOWNTO 0);
dimux : IN std_logic_vector (2 DOWNTO 0);
es_s : OUT std_logic_vector (15 DOWNTO 0);
cs_s : OUT std_logic_vector (15 DOWNTO 0);
ss_s : OUT std_logic_vector (15 DOWNTO 0);
ds_s : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
dimux <= path.datareg_input(6 downto 4); -- Data Register Input Path
w <= path.datareg_input(3);
seldreg <= path.datareg_input(2 downto 0);
selalua <= path.alu_operation(14 downto 11); -- ALU Path
selalub <= path.alu_operation(10 downto 7);
aluopr <= path.alu_operation(6 downto 0);
domux <= path.dbus_output; -- Data Output Path
simux <= path.segreg_input(3 downto 2); -- Segment Register Input Path
selsreg <= path.segreg_input(1 downto 0);
dispmux <= path.ea_output(9 downto 7); -- select ipreg addition
eamux <= path.ea_output(6 downto 3); -- 4 bits
segop <= path.ea_output(2 downto 0); -- segop(2)=override flag
wrd <= wrpath.wrd;
wralu <= wrpath.wralu;
wrcc <= wrpath.wrcc;
wrs <= wrpath.wrs;
wrip <= wrpath.wrip;
wrop <= wrpath.wrop;
wrtemp<= wrpath.wrtemp;
status.ax <= ax_s;
status.cx_one <= '1' when (cx_s=X"0001") else '0';
status.cx_zero <= '1' when (cx_s=X"0000") else '0';
status.cl <= cx_s(7 downto 0); -- used for shift/rotate
status.flag <= ccbus;
status.div_err <= div_err; -- Divider overflow
disp <= instr.disp;
data_in <= instr.data;
nbreq <= instr.nb;
rm <= instr.rm;
xmod <= instr.xmod;
----------------------------------------------------------------------------
-- Determine effective address
----------------------------------------------------------------------------
process (rm, ax_s,bx_s,cx_s,dx_s,bp_s,sp_s,si_s,di_s,disp,xmod)
begin
case rm is
when "000" => if xmod="11" then eam_s <= ax_s;
else eam_s <= bx_s + si_s + disp;
end if;
selds<='1';
when "001" => if xmod="11" then eam_s <= cx_s;
else eam_s <= bx_s + di_s + disp;
end if;
selds<='1';
when "010" => if xmod="11" then eam_s <= dx_s;
else eam_s <= bp_s + si_s + disp;
end if;
selds<='0';
when "011" => if xmod="11" then eam_s <= bx_s;
else eam_s <= bp_s + di_s + disp;
end if;
selds<='0';
when "100" => if xmod="11" then eam_s <= sp_s;
else eam_s <= si_s + disp;
end if;
selds<='1';
when "101" => if xmod="11" then eam_s <= bp_s;
else eam_s <= di_s + disp;
end if;
selds<='1';
when "110" => if xmod="00" then
eam_s <= disp;
selds <='1';
elsif xmod="11" then
eam_s <= si_s;
selds <='1';
else
eam_s <= bp_s + disp;
selds <='0'; -- Use SS
end if;
when others=> if xmod="11" then eam_s <= di_s;
else eam_s <= bx_s + disp;
end if;
selds<='1';
end case;
end process;
ea<=eam_s;
process(data_in,eabus_internal,alubus,mdbus_in,simux)
begin
case simux is
when "00" => sibus <= data_in;
when "01" => sibus <= eabus_internal;
when "10" => sibus <= alubus;
when others => sibus <= mdbus_in;
end case;
end process;
process(dispmux,nbreq,disp,mdbus_in,ipreg,eabus_internal)
begin
case dispmux is
when "000" => ipbus <= ("0000000000000"&nbreq) + ipreg;
when "001" => ipbus <= (("0000000000000"&nbreq)+disp) + ipreg;
when "011" => ipbus <= disp; -- disp contains new IP value
when "100" => ipbus <= eabus_internal; -- ipbus=effective address
when "101" => ipbus <= ipreg; -- bodge to get ipreg onto ipbus
when others => ipbus <= mdbus_in;
end case;
end process;
domux_s <= eabus_internal(0) & domux;
process(domux_s, alubus,ccbus, dibus, ipbus)
begin
case domux_s is
when "000" => dbusdp_out <= alubus; -- Even
when "001" => dbusdp_out <= ccbus;
when "010" => dbusdp_out <= dibus;
when "011" => dbusdp_out <= ipbus; -- CALL Instruction
when "100" => dbusdp_out <= alubus(7 downto 0)& alubus(15 downto 8); -- Odd
when "101" => dbusdp_out <= ccbus(7 downto 0) & ccbus(15 downto 8);
when "110" => dbusdp_out <= dibus(7 downto 0) & dibus(15 downto 8);
when others => dbusdp_out <= ipbus(7 downto 0) & ipbus(15 downto 8);
end case;
end process;
-- Write Prefix Register
process(clk,reset)
begin
if (reset = '1') then
opreg_s <= "01"; -- Default CS Register
opflag_s<= '0'; -- Clear Override Prefix Flag
elsif rising_edge(clk) then
if wrop='1' then
opreg_s <= segop(1 downto 0); -- Set override register
opflag_s<= '1'; -- segop(2); -- Set flag
elsif clrop='1' then
opreg_s <= "11"; -- Default Data Segment Register
opflag_s<= '0';
end if;
end if;
end process;
process (opflag_s,opreg_s,selds,eamux,segop)
begin
if opflag_s='1' and segop(2)='0' then -- Prefix register set and disable override not set?
opmux <= opreg_s(1 downto 0); -- Set mux to override prefix reg
elsif eamux(3)='1' then
opmux <= eamux(1 downto 0);
elsif eamux(0)='0' then
opmux <= "01"; -- Select CS for IP
else
opmux <= '1'&selds; -- DS if selds=1 else SS
end if;
end process;
process(dimux, data_in,alubus,mdbus_in,sdbus,eabus_internal)
begin
case dimux is
when "000" => dibus <= data_in; -- Operand
when "001" => dibus <= eabus_internal;-- Offset
when "010" => dibus <= alubus; -- Output ALU
when "011" => dibus <= mdbus_in; -- Memory Bus
when others => dibus <= sdbus; -- Segment registers
end case;
end process;
int0cs_s <= '1' when eamux(3 downto 1)="011" else '0';
segsel_s <= iomem & int0cs_s & eamux(2 downto 1) & opmux; -- 5 bits
process(segsel_s,es_s,cs_s,ss_s,ds_s) -- Segment Output Mux
begin
case segsel_s is
when "000000" => segbus <= es_s; -- 00**, opmux select register
when "000001" => segbus <= cs_s;
when "000010" => segbus <= ss_s;
when "000011" => segbus <= ds_s;
when "000100" => segbus <= es_s; -- 01**, opmux select register
when "000101" => segbus <= cs_s;
when "000110" => segbus <= ss_s;
when "000111" => segbus <= ds_s;
when "001000" => segbus <= ss_s; -- 10**=SS, used for PUSH& POP
when "001001" => segbus <= ss_s;
when "001010" => segbus <= ss_s;
when "001011" => segbus <= ss_s;
when "001100" => segbus <= es_s; -- 01**, opmux select register
when "001101" => segbus <= cs_s;
when "001110" => segbus <= ss_s;
when "001111" => segbus <= ds_s;
when others => segbus <= ZEROVECTOR_C(15 downto 0);-- IN/OUT instruction 0x0000:PORT/DX
end case;
end process;
-- Offset Mux
-- Note ea*4 required if non-32 bits memory access is used(?)
-- Currently CS &IP are read in one go (fits 32 bits)
process(ipreg,ea,sp_s,dx_s,eamux,si_s,di_s,bx_s,ax_s)
begin
case eamux is
when "0000" => eabus_internal <= ipreg;--ipbus;--ipreg;
when "0001" => eabus_internal <= ea;
when "0010" => eabus_internal <= dx_s;
when "0011" => eabus_internal <= ea + "10"; -- for call mem32/int
when "0100" => eabus_internal <= sp_s; -- 10* select SP_S
when "0101" => eabus_internal <= sp_s;
when "0110" => eabus_internal <= ea(13 downto 0)&"00";
when "0111" => eabus_internal <=(ea(13 downto 0)&"00") + "10"; -- for int
when "1000" => eabus_internal <= di_s; -- Select ES:DI
when "1011" => eabus_internal <= si_s; -- Select DS:SI
when "1001" => eabus_internal <= ea; -- added for JMP SI instruction
when "1111" => eabus_internal <= bx_s + (X"00"&ax_s(7 downto 0)); -- XLAT instruction
when others => eabus_internal <= DONTCARE(15 downto 0);
end case;
end process;
-- Instance port mappings.
I6 : ALU
PORT MAP (
alu_inbusa => alu_inbusa,
alu_inbusb => alu_inbusb,
aluopr => aluopr,
ax_s => ax_s,
clk => clk,
cx_s => cx_s,
dx_s => dx_s,
reset => reset,
w => w,
wralu => wralu,
wrcc => wrcc,
wrtemp => wrtemp,
alubus => alubus,
ccbus => ccbus,
div_err => div_err
);
I0 : dataregfile
PORT MAP (
dibus => dibus,
selalua => selalua,
selalub => selalub,
seldreg => seldreg,
w => w,
wrd => wrd,
alu_inbusa => alu_inbusa,
alu_inbusb => alu_inbusb,
bp_s => bp_s,
bx_s => bx_s,
di_s => di_s,
si_s => si_s,
reset => reset,
clk => clk,
data_in => data_in,
mdbus_in => mdbus_in,
sp_s => sp_s,
ax_s => ax_s,
cx_s => cx_s,
dx_s => dx_s
);
I9 : ipregister
PORT MAP (
clk => clk,
ipbus => ipbus,
reset => reset,
wrip => wrip,
ipreg => ipreg
);
I15 : segregfile
PORT MAP (
selsreg => selsreg,
sibus => sibus,
wrs => wrs,
reset => reset,
clk => clk,
sdbus => sdbus,
dimux => dimux,
es_s => es_s,
cs_s => cs_s,
ss_s => ss_s,
ds_s => ds_s
);
eabus <= eabus_internal;
END struct;

198
common/CPU/cpu86/dataregfile_rtl.vhd Normal file
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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY dataregfile IS
PORT(
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic;
wrd : IN std_logic;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
clk : IN std_logic;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END dataregfile ;
architecture rtl of dataregfile is
signal axreg_s : std_logic_vector(15 downto 0);
signal cxreg_s : std_logic_vector(15 downto 0);
signal dxreg_s : std_logic_vector(15 downto 0);
signal bxreg_s : std_logic_vector(15 downto 0);
signal spreg_s : std_logic_vector(15 downto 0);
signal bpreg_s : std_logic_vector(15 downto 0);
signal sireg_s : std_logic_vector(15 downto 0);
signal direg_s : std_logic_vector(15 downto 0);
signal seldreg_s : std_logic_vector(3 downto 0); -- w & seldreg
signal selalua_s : std_logic_vector(4 downto 0); -- w & dibus & selalua
signal selalub_s : std_logic_vector(4 downto 0); -- w & dibus & selalub
signal alu_inbusb_s: std_logic_vector (15 downto 0);
begin
----------------------------------------------------------------------------
-- 8 registers of 16 bits each
----------------------------------------------------------------------------
seldreg_s <= w & seldreg;
process (clk,reset)
begin
if reset='1' then
axreg_s <= (others => '0');
cxreg_s <= (others => '0');
dxreg_s <= (others => '0');
bxreg_s <= (others => '0');
spreg_s <= (others => '0');
bpreg_s <= (others => '0');
sireg_s <= (others => '0');
direg_s <= (others => '0');
elsif rising_edge(clk) then
if (wrd='1') then
case seldreg_s is
when "0000" => axreg_s(7 downto 0) <= dibus(7 downto 0); -- w=0 8 bits write
when "0001" => cxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0010" => dxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0011" => bxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0100" => axreg_s(15 downto 8) <= dibus(7 downto 0);
when "0101" => cxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0110" => dxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0111" => bxreg_s(15 downto 8) <= dibus(7 downto 0);
when "1000" => axreg_s <= dibus; -- w=1 16 bits write
when "1001" => cxreg_s <= dibus;
when "1010" => dxreg_s <= dibus;
when "1011" => bxreg_s <= dibus;
when "1100" => spreg_s <= dibus;
when "1101" => bpreg_s <= dibus;
when "1110" => sireg_s <= dibus;
when others => direg_s <= dibus;
end case;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Output Port A
----------------------------------------------------------------------------
selalua_s <= w & selalua;
process (selalua_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in)
begin
case selalua_s is
when "00000" => alu_inbusa <= X"00" & axreg_s(7 downto 0); -- Select 8 bits MSB=0
when "00001" => alu_inbusa <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusa <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusa <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusa <= X"00" & axreg_s(15 downto 8); -- AH
when "00101" => alu_inbusa <= X"00" & cxreg_s(15 downto 8); -- CH
when "00110" => alu_inbusa <= X"00" & dxreg_s(15 downto 8); -- DH
when "00111" => alu_inbusa <= X"00" & bxreg_s(15 downto 8); -- BH
when "10000" => alu_inbusa <= axreg_s;
when "10001" => alu_inbusa <= cxreg_s;
when "10010" => alu_inbusa <= dxreg_s;
when "10011" => alu_inbusa <= bxreg_s;
when "10100" => alu_inbusa <= spreg_s;
when "10101" => alu_inbusa <= bpreg_s;
when "10110" => alu_inbusa <= sireg_s;
when "10111" => alu_inbusa <= direg_s;
when others => alu_inbusa <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
----------------------------------------------------------------------------
-- Output Port B
----------------------------------------------------------------------------
selalub_s <= w & selalub;
process (selalub_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in,data_in)
begin
case selalub_s is
when "00000" => alu_inbusb_s <= X"00" & axreg_s(7 downto 0);
when "00001" => alu_inbusb_s <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusb_s <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusb_s <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusb_s <= X"00" & axreg_s(15 downto 8);
when "00101" => alu_inbusb_s <= X"00" & cxreg_s(15 downto 8);
when "00110" => alu_inbusb_s <= X"00" & dxreg_s(15 downto 8);
when "00111" => alu_inbusb_s <= X"00" & bxreg_s(15 downto 8);
when "10000" => alu_inbusb_s <= axreg_s;
when "10001" => alu_inbusb_s <= cxreg_s;
when "10010" => alu_inbusb_s <= dxreg_s;
when "10011" => alu_inbusb_s <= bxreg_s;
when "10100" => alu_inbusb_s <= spreg_s;
when "10101" => alu_inbusb_s <= bpreg_s;
when "10110" => alu_inbusb_s <= sireg_s;
when "10111" => alu_inbusb_s <= direg_s;
when "01000" => alu_inbusb_s <= X"00"& data_in(7 downto 0); -- Pass data_in to ALU (port B only)
when "11000" => alu_inbusb_s <= data_in; -- Pass data_in to ALU (port B only)
when "01001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC byte function
when "11001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC word function
when "11010" => alu_inbusb_s <= X"0002"; -- Used for POP/PUSH function
when others => alu_inbusb_s <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
alu_inbusb <= alu_inbusb_s; -- connect to entity
bx_s <= bxreg_s; -- Used for EA calculation
bp_s <= bpreg_s;
si_s <= sireg_s;
di_s <= direg_s;
sp_s <= spreg_s; -- Used for eamux, PUSH and POP instructions
ax_s <= axreg_s; -- Used for datapath FSM
cx_s <= cxreg_s;
dx_s <= dxreg_s; -- Used for IN/OUT instructions & Divider
end rtl;

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common/CPU/cpu86/divider_rtl_ser.vhd Normal file
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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY divider IS
GENERIC(
WIDTH_DIVID : integer := 32; -- Width Dividend
WIDTH_DIVIS : integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8 -- Check Overflow against short Byte/Word
);
PORT(
clk : IN std_logic; -- System Clock
reset : IN std_logic; -- Active high
dividend : IN std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : IN std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : OUT std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
remainder : OUT std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : IN std_logic;
w : IN std_logic; -- UNUSED!
overflow : OUT std_logic;
start : IN std_logic;
done : OUT std_logic
);
END divider ;
ARCHITECTURE rtl_ser OF divider IS
signal dividend_s : std_logic_vector(WIDTH_DIVID downto 0);
signal divisor_s : std_logic_vector(WIDTH_DIVIS downto 0);
signal divis_rect_s : std_logic_vector(WIDTH_DIVIS-1 downto 0);
signal signquot_s : std_logic;
signal signremain_s : std_logic;
signal accumulator_s : std_logic_vector(WIDTH_DIVID downto 0);
signal aluout_s : std_logic_vector(WIDTH_DIVIS downto 0);
signal newaccu_s : std_logic_vector(WIDTH_DIVID downto 0);
signal quot_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal remain_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
constant null_s : std_logic_vector(31 downto 0) := X"00000000";
signal count_s : std_logic_vector (3 downto 0); -- Number of iterations
signal overflow_s : std_logic; --_vector (WIDTH_DIVIS downto 0);
signal sremainder_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal squotient_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal signfailure_s : std_logic;
signal zeroq_s : std_logic;
signal zeror_s : std_logic;
signal zerod_s : std_logic;
signal pos_s : std_logic;
signal neg_s : std_logic;
type states is (s0,s1,s2);
signal state,nextstate: states;
function rectifyd (r : in std_logic_vector (WIDTH_DIVID downto 0); -- Rectifier for dividend + 1 bit
twoc: in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH_DIVID downto 0);
begin
if ((r(WIDTH_DIVID) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH_DIVID) and twoc));
end;
function rectifys (r : in std_logic_vector (WIDTH_DIVIS-1 downto 0); -- Rectifier for divisor
twoc: in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH_DIVIS-1 downto 0);
begin
if ((r(WIDTH_DIVIS-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH_DIVIS-1) and twoc));
end;
begin
-- Sign Quotient
signquot_s <= (dividend(WIDTH_DIVID-1) xor divisor(WIDTH_DIVIS-1)) and twocomp;
-- Sign Remainder
signremain_s <= dividend(WIDTH_DIVID-1) and twocomp;
dividend_s <= '0'&dividend when twocomp='0' else rectifyd(dividend(WIDTH_DIVID-1)&dividend, twocomp);
divisor_s <= ('1'&divisor) when (divisor(WIDTH_DIVIS-1) and twocomp)='1' else not('0'&divisor) + '1';
-- Subtractor (Adder, WIDTH_DIVIS+1)
aluout_s <= accumulator_s(WIDTH_DIVID downto WIDTH_DIVID-WIDTH_DIVIS) + divisor_s;
-- Append Quotient section to aluout_s
newaccu_s <= aluout_s & accumulator_s(WIDTH_DIVID-WIDTH_DIVIS-1 downto 0);
process (clk,reset)
begin
if (reset='1') then
accumulator_s <= (others => '0');
elsif (rising_edge(clk)) then
if start='1' then
accumulator_s <= dividend_s(WIDTH_DIVID-1 downto 0) & '0'; -- Load Dividend in remainder +shl
elsif pos_s='1' then -- Positive, remain=shl(remain,1)
accumulator_s <= newaccu_s(WIDTH_DIVID-1 downto 0) & '1'; -- Use sub result
elsif neg_s='1' then -- Negative, shl(remainder,0)
accumulator_s <= accumulator_s(WIDTH_DIVID-1 downto 0) & '0';-- Use original remainder
end if;
end if;
end process;
-- 2 Process Control FSM
process (clk,reset)
begin
if (reset = '1') then
state <= s0;
count_s <= (others => '0');
elsif (rising_edge(clk)) then
state <= nextstate;
if (state=s1) then
count_s <= count_s - '1';
elsif (state=s0) then
count_s <= CONV_STD_LOGIC_VECTOR(WIDTH_DIVIS-1, 4); -- extra step CAN REDUCE BY 1 since DONE is latched!!
end if;
end if;
end process;
process(state,start,aluout_s,count_s)
begin
case state is
when s0 =>
pos_s <= '0';
neg_s <= '0';
if start='1' then
nextstate <= s1;
else
nextstate <= s0;
end if;
when s1 =>
neg_s <= aluout_s(WIDTH_DIVIS);
pos_s <= not(aluout_s(WIDTH_DIVIS));
if (count_s=null_s(3 downto 0)) then nextstate <= s2; -- Done
else nextstate <= s1; -- Next sub&shift
end if;
when s2=>
pos_s <= '0';
neg_s <= '0';
nextstate <= s0;
when others =>
pos_s <= '0';
neg_s <= '0';
nextstate <= s0;
end case;
end process;
-- Correct remainder (SHR,1)
remain_s <= accumulator_s(WIDTH_DIVID downto WIDTH_DIVID-WIDTH_DIVIS+1);
-- Overflow if remainder>divisor or divide by 0 or sign error. Change all to positive.
divis_rect_s <= rectifys(divisor, twocomp);
overflow_s <= '1' when ((remain_s>=divis_rect_s) or (zerod_s='1')) else '0';
-- bottom part of remainder is quotient
quot_s <= accumulator_s(WIDTH_DIVIS-1 downto 0);
-- Remainder Result
sremainder_s <= ((not(remain_s)) + '1') when signremain_s='1' else remain_s;
remainder <= sremainder_s;
-- Qotient Result
squotient_s <= ((not(quot_s)) + '1') when signquot_s='1' else quot_s;
quotient <= squotient_s;
-- Detect zero vector
zeror_s <= '1' when (twocomp='1' and sremainder_s=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
zeroq_s <= '1' when (twocomp='1' and squotient_s=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
zerod_s <= '1' when (divisor=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
-- Detect Sign failure
signfailure_s <= '1' when (signquot_s='1' and squotient_s(WIDTH_DIVIS-1)='0' and zeroq_s='0') or
(signremain_s='1' and sremainder_s(WIDTH_DIVIS-1)='0' and zeror_s='0') else '0';
done <= '1' when state=s2 else '0';
overflow <= '1' when (overflow_s='1' or signfailure_s='1') else '0';
end architecture rtl_ser;

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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY formatter IS
PORT(
lutbus : IN std_logic_vector (15 DOWNTO 0);
mux_addr : OUT std_logic_vector (2 DOWNTO 0);
mux_data : OUT std_logic_vector (3 DOWNTO 0);
mux_reg : OUT std_logic_vector (2 DOWNTO 0);
nbreq : OUT std_logic_vector (2 DOWNTO 0)
);
END formatter ;
ARCHITECTURE struct OF formatter IS
-- Architecture declarations
SIGNAL dout : std_logic_vector(15 DOWNTO 0);
SIGNAL dout4 : std_logic_vector(7 DOWNTO 0);
SIGNAL dout5 : std_logic_vector(7 DOWNTO 0);
SIGNAL muxout : std_logic_vector(7 DOWNTO 0);
SIGNAL mw_I1temp_din : std_logic_vector(15 DOWNTO 0);
-- Component Declarations
COMPONENT a_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT d_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (3 DOWNTO 0)
);
END COMPONENT;
COMPONENT m_table
PORT (
ireg : IN std_logic_vector (7 DOWNTO 0);
modrrm : IN std_logic_vector (7 DOWNTO 0);
muxout : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT n_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
COMPONENT r_table
PORT (
addr : IN std_logic_vector (15 DOWNTO 0);
dout : OUT std_logic_vector (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
dout <= dout4 & muxout;
mw_I1temp_din <= lutbus;
i1combo_proc: PROCESS (mw_I1temp_din)
VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
BEGIN
temp_din := mw_I1temp_din(15 DOWNTO 0);
dout5 <= temp_din(7 DOWNTO 0);
dout4 <= temp_din(15 DOWNTO 8);
END PROCESS i1combo_proc;
-- Instance port mappings.
I2 : a_table
PORT MAP (
addr => dout,
dout => mux_addr
);
I3 : d_table
PORT MAP (
addr => dout,
dout => mux_data
);
I6 : m_table
PORT MAP (
ireg => dout4,
modrrm => dout5,
muxout => muxout
);
I4 : n_table
PORT MAP (
addr => dout,
dout => nbreq
);
I5 : r_table
PORT MAP (
addr => dout,
dout => mux_reg
);
END struct;

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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY ipregister IS
PORT(
clk : IN std_logic;
ipbus : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
wrip : IN std_logic;
ipreg : OUT std_logic_vector (15 DOWNTO 0)
);
END ipregister ;
architecture rtl of ipregister is
signal ipreg_s : std_logic_vector(15 downto 0);
begin
----------------------------------------------------------------------------
-- Instructon Pointer Register
----------------------------------------------------------------------------
process (clk, reset)
begin
if reset='1' then
ipreg_s <= RESET_IP_C; -- See cpu86pack
elsif rising_edge(clk) then
if (wrip='1') then
ipreg_s<= ipbus;
end if;
end if;
end process;
ipreg <= ipreg_s;
end rtl;

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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity m_table is
port ( ireg : in std_logic_vector(7 downto 0);
modrrm: in std_logic_vector(7 downto 0);
muxout: out std_logic_vector(7 downto 0));
end m_table;
architecture rtl of m_table is
signal lutout_s: std_logic_vector(1 downto 0);
signal ea_s : std_logic; -- Asserted if mod=00 and rm=110
signal m11_s : std_logic; -- Asserted if mod=11
signal mux_s : std_logic_vector(3 downto 0);
begin
ea_s <= '1' when (modrrm(7 downto 6)="00" and modrrm(2 downto 0)="110") else '0';
m11_s<= '1' when modrrm(7 downto 6)="11" else '0';
mux_s <= lutout_s & m11_s & ea_s;
process (mux_s,modrrm)
begin
case mux_s is
when "1000" => muxout <= modrrm(7 downto 6)&"000000";
when "1010" => muxout <= modrrm(7 downto 6)&"000000";
when "1001" => muxout <= "00000110";
when "1011" => muxout <= "00000110";
when "1100" => muxout <= modrrm(7 downto 3)&"000";
when "1101" => muxout <= "00"&modrrm(5 downto 3)&"110";
when "1110" => muxout <= "11"&modrrm(5 downto 3)&"000";
when others => muxout <= (others => '0');
end case;
end process;
process(ireg)
begin
case ireg is
when "11111111" => lutout_s <= "11";
when "10001000" => lutout_s <= "10";
when "10001001" => lutout_s <= "10";
when "10001010" => lutout_s <= "10";
when "10001011" => lutout_s <= "10";
when "11000110" => lutout_s <= "11";
when "11000111" => lutout_s <= "11";
when "10001110" => lutout_s <= "10";
when "10001100" => lutout_s <= "10";
when "10001111" => lutout_s <= "11";
when "10000110" => lutout_s <= "10";
when "10000111" => lutout_s <= "10";
when "10001101" => lutout_s <= "10";
when "11000101" => lutout_s <= "10";
when "11000100" => lutout_s <= "10";
when "00000000" => lutout_s <= "10";
when "00000001" => lutout_s <= "10";
when "00000010" => lutout_s <= "10";
when "00000011" => lutout_s <= "10";
when "10000000" => lutout_s <= "11";
when "10000001" => lutout_s <= "11";
when "10000011" => lutout_s <= "11";
when "00010000" => lutout_s <= "10";
when "00010001" => lutout_s <= "10";
when "00010010" => lutout_s <= "10";
when "00010011" => lutout_s <= "10";
when "00101000" => lutout_s <= "10";
when "00101001" => lutout_s <= "10";
when "00101010" => lutout_s <= "10";
when "00101011" => lutout_s <= "10";
when "00011000" => lutout_s <= "10";
when "00011001" => lutout_s <= "10";
when "00011010" => lutout_s <= "10";
when "00011011" => lutout_s <= "10";
when "11111110" => lutout_s <= "11";
when "00111010" => lutout_s <= "10";
when "00111011" => lutout_s <= "10";
when "00111000" => lutout_s <= "10";
when "00111001" => lutout_s <= "10";
when "11110110" => lutout_s <= "11";
when "11110111" => lutout_s <= "11";
when "11010000" => lutout_s <= "10";
when "11010001" => lutout_s <= "10";
when "11010010" => lutout_s <= "10";
when "11010011" => lutout_s <= "10";
when "00100000" => lutout_s <= "10";
when "00100001" => lutout_s <= "10";
when "00100010" => lutout_s <= "10";
when "00100011" => lutout_s <= "10";
when "00001000" => lutout_s <= "10";
when "00001001" => lutout_s <= "10";
when "00001010" => lutout_s <= "10";
when "00001011" => lutout_s <= "10";
when "10000100" => lutout_s <= "10";
when "10000101" => lutout_s <= "10";
when "00110000" => lutout_s <= "10";
when "00110001" => lutout_s <= "10";
when "00110010" => lutout_s <= "10";
when "00110011" => lutout_s <= "10";
when "10000010" => lutout_s <= "01";
when others => lutout_s <= "00";
end case;
end process;
end rtl;

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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY multiplier IS
GENERIC(
WIDTH : integer := 16
);
PORT(
multiplicant : IN std_logic_vector (WIDTH-1 DOWNTO 0);
multiplier : IN std_logic_vector (WIDTH-1 DOWNTO 0);
product : OUT std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0); -- result
twocomp : IN std_logic
);
END multiplier ;
architecture rtl of multiplier is
function rectify (r : in std_logic_vector (WIDTH-1 downto 0); -- Rectifier for signed multiplication
twoc : in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH-1 downto 0);
begin
if ((r(WIDTH-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH-1) and twoc));
end;
signal multiplicant_s : std_logic_vector (WIDTH-1 downto 0);
signal multiplier_s : std_logic_vector (WIDTH-1 downto 0);
signal product_s : std_logic_vector (WIDTH+WIDTH-1 downto 0); -- Result
signal sign_s : std_logic;
begin
multiplicant_s <= rectify(multiplicant,twocomp);
multiplier_s <= rectify(multiplier,twocomp);
sign_s <= multiplicant(WIDTH-1) xor multiplier(WIDTH-1); -- sign product
product_s <= multiplicant_s * multiplier_s;
product <= ((not(product_s)) + '1') when (sign_s and twocomp)='1' else product_s;
end rtl;

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-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity n_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end n_table;
architecture rtl of n_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "010";
when "1110100100000000" => dout <= "011";
when "1111111111100000" => dout <= "010";
when "1111111100100110" => dout <= "100";
when "1111111100100000" => dout <= "010";
when "1111111101100000" => dout <= "011";
when "1111111110100000" => dout <= "100";
when "1110101000000000" => dout <= "101";
when "1111111100101110" => dout <= "100";
when "1111111100101000" => dout <= "010";
when "1111111101101000" => dout <= "011";
when "1111111110101000" => dout <= "100";
when "1110100000000000" => dout <= "011";
when "1111111111010000" => dout <= "010";
when "1111111100010110" => dout <= "100";
when "1111111100010000" => dout <= "010";
when "1111111101010000" => dout <= "011";
when "1111111110010000" => dout <= "100";
when "1001101000000000" => dout <= "101";
when "1111111100011110" => dout <= "100";
when "1111111100011000" => dout <= "010";
when "1111111101011000" => dout <= "011";
when "1111111110011000" => dout <= "100";
when "1100001100000000" => dout <= "001";
when "1100001000000000" => dout <= "011";
when "1100101100000000" => dout <= "001";
when "1100101000000000" => dout <= "011";
when "0111010000000000" => dout <= "010";
when "0111110000000000" => dout <= "010";
when "0111111000000000" => dout <= "010";
when "0111001000000000" => dout <= "010";
when "0111011000000000" => dout <= "010";
when "0111101000000000" => dout <= "010";
when "0111000000000000" => dout <= "010";
when "0111100000000000" => dout <= "010";
when "0111010100000000" => dout <= "010";
when "0111110100000000" => dout <= "010";
when "0111111100000000" => dout <= "010";
when "0111001100000000" => dout <= "010";
when "0111011100000000" => dout <= "010";
when "0111101100000000" => dout <= "010";
when "0111000100000000" => dout <= "010";
when "0111100100000000" => dout <= "010";
when "1110001100000000" => dout <= "010";
when "1110001000000000" => dout <= "010";
when "1110000100000000" => dout <= "010";
when "1110000000000000" => dout <= "010";
when "1100110100000000" => dout <= "010";
when "1100110000000000" => dout <= "001";
when "1100111000000000" => dout <= "001";
when "1100111100000000" => dout <= "001";
when "1111100000000000" => dout <= "001";
when "1111010100000000" => dout <= "001";
when "1111100100000000" => dout <= "001";
when "1111110000000000" => dout <= "001";
when "1111110100000000" => dout <= "001";
when "1111101000000000" => dout <= "001";
when "1111101100000000" => dout <= "001";
when "1111010000000000" => dout <= "001";
when "1001101100000000" => dout <= "001";
when "1111000000000000" => dout <= "001";
when "1001000000000000" => dout <= "001";
when "0010011000000000" => dout <= "001";
when "0010111000000000" => dout <= "001";
when "0011011000000000" => dout <= "001";
when "0011111000000000" => dout <= "001";
when "1000100011000000" => dout <= "010";
when "1000100000000000" => dout <= "010";
when "1000100001000000" => dout <= "011";
when "1000100010000000" => dout <= "100";
when "1000100000000110" => dout <= "100";
when "1000100111000000" => dout <= "010";
when "1000100100000000" => dout <= "010";
when "1000100101000000" => dout <= "011";
when "1000100110000000" => dout <= "100";
when "1000100100000110" => dout <= "100";
when "1000101011000000" => dout <= "010";
when "1000101000000000" => dout <= "010";
when "1000101001000000" => dout <= "011";
when "1000101010000000" => dout <= "100";
when "1000101000000110" => dout <= "100";
when "1000101111000000" => dout <= "010";
when "1000101100000000" => dout <= "010";
when "1000101101000000" => dout <= "011";
when "1000101110000000" => dout <= "100";
when "1000101100000110" => dout <= "100";
when "1100011000000000" => dout <= "011";
when "1100011001000000" => dout <= "100";
when "1100011010000000" => dout <= "101";
when "1100011000000110" => dout <= "101";
when "1100011100000000" => dout <= "100";
when "1100011101000000" => dout <= "101";
when "1100011110000000" => dout <= "110";
when "1100011100000110" => dout <= "110";
when "1011000000000000" => dout <= "010";
when "1011000100000000" => dout <= "010";
when "1011001000000000" => dout <= "010";
when "1011001100000000" => dout <= "010";
when "1011010000000000" => dout <= "010";
when "1011010100000000" => dout <= "010";
when "1011011000000000" => dout <= "010";
when "1011011100000000" => dout <= "010";
when "1011100000000000" => dout <= "011";
when "1011100100000000" => dout <= "011";
when "1011101000000000" => dout <= "011";
when "1011101100000000" => dout <= "011";
when "1011110000000000" => dout <= "011";
when "1011110100000000" => dout <= "011";
when "1011111000000000" => dout <= "011";
when "1011111100000000" => dout <= "011";
when "1010000000000000" => dout <= "011";
when "1010000100000000" => dout <= "011";
when "1010001000000000" => dout <= "011";
when "1010001100000000" => dout <= "011";
when "1000111011000000" => dout <= "010";
when "1000111000000000" => dout <= "010";
when "1000111001000000" => dout <= "011";
when "1000111010000000" => dout <= "100";
when "1000111000000110" => dout <= "100";
when "1000110011000000" => dout <= "010";
when "1000110000000000" => dout <= "010";
when "1000110001000000" => dout <= "011";
when "1000110010000000" => dout <= "100";
when "1000110000000110" => dout <= "100";
when "1111111100110000" => dout <= "010";
when "1111111101110000" => dout <= "011";
when "1111111110110000" => dout <= "100";
when "1111111100110110" => dout <= "100";
when "0101000000000000" => dout <= "001";
when "0101000100000000" => dout <= "001";
when "0101001000000000" => dout <= "001";
when "0101001100000000" => dout <= "001";
when "0101010000000000" => dout <= "001";
when "0101010100000000" => dout <= "001";
when "0101011000000000" => dout <= "001";
when "0101011100000000" => dout <= "001";
when "0000011000000000" => dout <= "001";
when "0000111000000000" => dout <= "001";
when "0001011000000000" => dout <= "001";
when "0001111000000000" => dout <= "001";
when "1000111100000000" => dout <= "010";
when "1000111101000000" => dout <= "011";
when "1000111110000000" => dout <= "100";
when "1000111100000110" => dout <= "100";
when "1000111111000000" => dout <= "010";
when "0101100000000000" => dout <= "001";
when "0101100100000000" => dout <= "001";
when "0101101000000000" => dout <= "001";
when "0101101100000000" => dout <= "001";
when "0101110000000000" => dout <= "001";
when "0101110100000000" => dout <= "001";
when "0101111000000000" => dout <= "001";
when "0101111100000000" => dout <= "001";
when "0000011100000000" => dout <= "001";
when "0001011100000000" => dout <= "001";
when "0001111100000000" => dout <= "001";
when "1000011011000000" => dout <= "010";
when "1000011000000000" => dout <= "010";
when "1000011001000000" => dout <= "011";
when "1000011010000000" => dout <= "100";
when "1000011000000110" => dout <= "100";
when "1000011111000000" => dout <= "010";
when "1000011100000000" => dout <= "010";
when "1000011101000000" => dout <= "011";
when "1000011110000000" => dout <= "100";
when "1000011100000110" => dout <= "100";
when "1001000100000000" => dout <= "001";
when "1001001000000000" => dout <= "001";
when "1001001100000000" => dout <= "001";
when "1001010000000000" => dout <= "001";
when "1001010100000000" => dout <= "001";
when "1001011000000000" => dout <= "001";
when "1001011100000000" => dout <= "001";
when "1110010000000000" => dout <= "010";
when "1110010100000000" => dout <= "010";
when "1110110000000000" => dout <= "001";
when "1110110100000000" => dout <= "001";
when "1110011000000000" => dout <= "010";
when "1110011100000000" => dout <= "010";
when "1110111100000000" => dout <= "001";
when "1110111000000000" => dout <= "001";
when "1101011100000000" => dout <= "001";
when "1001111100000000" => dout <= "001";
when "1001111000000000" => dout <= "001";
when "1001110000000000" => dout <= "001";
when "1001110100000000" => dout <= "001";
when "1000110100000110" => dout <= "100";
when "1000110111000000" => dout <= "010";
when "1000110100000000" => dout <= "010";
when "1000110101000000" => dout <= "011";
when "1000110110000000" => dout <= "100";
when "1100010100000110" => dout <= "100";
when "1100010100000000" => dout <= "010";
when "1100010101000000" => dout <= "011";
when "1100010110000000" => dout <= "100";
when "1100010000000110" => dout <= "100";
when "1100010000000000" => dout <= "010";
when "1100010001000000" => dout <= "011";
when "1100010010000000" => dout <= "100";
when "0000000011000000" => dout <= "010";
when "0000000000000110" => dout <= "100";
when "0000000000000000" => dout <= "010";
when "0000000001000000" => dout <= "011";
when "0000000010000000" => dout <= "100";
when "0000000111000000" => dout <= "010";
when "0000000100000110" => dout <= "100";
when "0000000100000000" => dout <= "010";
when "0000000101000000" => dout <= "011";
when "0000000110000000" => dout <= "100";
when "0000001011000000" => dout <= "010";
when "0000001000000110" => dout <= "100";
when "0000001000000000" => dout <= "010";
when "0000001001000000" => dout <= "011";
when "0000001010000000" => dout <= "100";
when "0000001111000000" => dout <= "010";
when "0000001100000110" => dout <= "100";
when "0000001100000000" => dout <= "010";
when "0000001101000000" => dout <= "011";
when "0000001110000000" => dout <= "100";
when "1000000011000000" => dout <= "011";
when "1000000000000110" => dout <= "101";
when "1000000000000000" => dout <= "011";
when "1000000001000000" => dout <= "100";
when "1000000010000000" => dout <= "101";
when "1000000111000000" => dout <= "100";
when "1000000100000110" => dout <= "110";
when "1000000100000000" => dout <= "100";
when "1000000101000000" => dout <= "101";
when "1000000110000000" => dout <= "110";
when "1000001111000000" => dout <= "011";
when "1000001100000110" => dout <= "101";
when "1000001100000000" => dout <= "011";
when "1000001101000000" => dout <= "100";
when "1000001110000000" => dout <= "101";
when "0000010000000000" => dout <= "010";
when "0000010100000000" => dout <= "011";
when "0001000011000000" => dout <= "010";
when "0001000000000110" => dout <= "100";
when "0001000000000000" => dout <= "010";
when "0001000001000000" => dout <= "011";
when "0001000010000000" => dout <= "100";
when "0001000111000000" => dout <= "010";
when "0001000100000110" => dout <= "100";
when "0001000100000000" => dout <= "010";
when "0001000101000000" => dout <= "011";
when "0001000110000000" => dout <= "100";
when "0001001011000000" => dout <= "010";
when "0001001000000110" => dout <= "100";
when "0001001000000000" => dout <= "010";
when "0001001001000000" => dout <= "011";
when "0001001010000000" => dout <= "100";
when "0001001111000000" => dout <= "010";
when "0001001100000110" => dout <= "100";
when "0001001100000000" => dout <= "010";
when "0001001101000000" => dout <= "011";
when "0001001110000000" => dout <= "100";
when "1000000011010000" => dout <= "011";
when "1000000000010110" => dout <= "101";
when "1000000000010000" => dout <= "011";
when "1000000001010000" => dout <= "100";
when "1000000010010000" => dout <= "101";
when "1000000111010000" => dout <= "100";
when "1000000100010110" => dout <= "110";
when "1000000100010000" => dout <= "100";
when "1000000101010000" => dout <= "101";
when "1000000110010000" => dout <= "110";
when "1000001111010000" => dout <= "011";
when "1000001100010110" => dout <= "101";
when "1000001100010000" => dout <= "011";
when "1000001101010000" => dout <= "100";
when "1000001110010000" => dout <= "101";
when "0001010000000000" => dout <= "010";
when "0001010100000000" => dout <= "011";
when "0010100011000000" => dout <= "010";
when "0010100000000110" => dout <= "100";
when "0010100000000000" => dout <= "010";
when "0010100001000000" => dout <= "011";
when "0010100010000000" => dout <= "100";
when "0010100111000000" => dout <= "010";
when "0010100100000110" => dout <= "100";
when "0010100100000000" => dout <= "010";
when "0010100101000000" => dout <= "011";
when "0010100110000000" => dout <= "100";
when "0010101011000000" => dout <= "010";
when "0010101000000110" => dout <= "100";
when "0010101000000000" => dout <= "010";
when "0010101001000000" => dout <= "011";
when "0010101010000000" => dout <= "100";
when "0010101111000000" => dout <= "010";
when "0010101100000110" => dout <= "100";
when "0010101100000000" => dout <= "010";
when "0010101101000000" => dout <= "011";
when "0010101110000000" => dout <= "100";
when "1000000011101000" => dout <= "011";
when "1000000000101110" => dout <= "101";
when "1000000000101000" => dout <= "011";
when "1000000001101000" => dout <= "100";
when "1000000010101000" => dout <= "101";
when "1000000111101000" => dout <= "100";
when "1000000100101110" => dout <= "110";
when "1000000100101000" => dout <= "100";
when "1000000101101000" => dout <= "101";
when "1000000110101000" => dout <= "110";
when "1000001111101000" => dout <= "011";
when "1000001100101110" => dout <= "101";
when "1000001100101000" => dout <= "011";
when "1000001101101000" => dout <= "100";
when "1000001110101000" => dout <= "101";
when "0010110000000000" => dout <= "010";
when "0010110100000000" => dout <= "011";
when "0001100011000000" => dout <= "010";
when "0001100000000110" => dout <= "100";
when "0001100000000000" => dout <= "010";
when "0001100001000000" => dout <= "011";
when "0001100010000000" => dout <= "100";
when "0001100111000000" => dout <= "010";
when "0001100100000110" => dout <= "100";
when "0001100100000000" => dout <= "010";
when "0001100101000000" => dout <= "011";
when "0001100110000000" => dout <= "100";
when "0001101011000000" => dout <= "010";
when "0001101000000110" => dout <= "100";
when "0001101000000000" => dout <= "010";
when "0001101001000000" => dout <= "011";
when "0001101010000000" => dout <= "100";
when "0001101111000000" => dout <= "010";
when "0001101100000110" => dout <= "100";
when "0001101100000000" => dout <= "010";
when "0001101101000000" => dout <= "011";
when "0001101110000000" => dout <= "100";
when "1000000011011000" => dout <= "011";
when "1000000000011110" => dout <= "101";
when "1000000000011000" => dout <= "011";
when "1000000001011000" => dout <= "100";
when "1000000010011000" => dout <= "101";
when "1000000111011000" => dout <= "100";
when "1000000100011110" => dout <= "110";
when "1000000100011000" => dout <= "100";
when "1000000101011000" => dout <= "101";
when "1000000110011000" => dout <= "110";
when "1000001111011000" => dout <= "011";
when "1000001100011110" => dout <= "101";
when "1000001100011000" => dout <= "011";
when "1000001101011000" => dout <= "100";
when "1000001110011000" => dout <= "101";
when "0001110000000000" => dout <= "010";
when "0001110100000000" => dout <= "011";
when "1111111011000000" => dout <= "010";
when "1111111000000110" => dout <= "100";
when "1111111000000000" => dout <= "010";
when "1111111001000000" => dout <= "011";
when "1111111010000000" => dout <= "100";
when "1111111100000110" => dout <= "100";
when "1111111100000000" => dout <= "010";
when "1111111101000000" => dout <= "011";
when "1111111110000000" => dout <= "100";
when "0100000000000000" => dout <= "001";
when "0100000100000000" => dout <= "001";
when "0100001000000000" => dout <= "001";
when "0100001100000000" => dout <= "001";
when "0100010000000000" => dout <= "001";
when "0100010100000000" => dout <= "001";
when "0100011000000000" => dout <= "001";
when "0100011100000000" => dout <= "001";
when "1111111011001000" => dout <= "010";
when "1111111000001110" => dout <= "100";
when "1111111000001000" => dout <= "010";
when "1111111001001000" => dout <= "011";
when "1111111010001000" => dout <= "100";
when "1111111100001110" => dout <= "100";
when "1111111100001000" => dout <= "010";
when "1111111101001000" => dout <= "011";
when "1111111110001000" => dout <= "100";
when "0100100000000000" => dout <= "001";
when "0100100100000000" => dout <= "001";
when "0100101000000000" => dout <= "001";
when "0100101100000000" => dout <= "001";
when "0100110000000000" => dout <= "001";
when "0100110100000000" => dout <= "001";
when "0100111000000000" => dout <= "001";
when "0100111100000000" => dout <= "001";
when "0011101011000000" => dout <= "010";
when "0011101000000110" => dout <= "100";
when "0011101000000000" => dout <= "010";
when "0011101001000000" => dout <= "011";
when "0011101010000000" => dout <= "100";
when "0011101111000000" => dout <= "010";
when "0011101100000110" => dout <= "100";
when "0011101100000000" => dout <= "010";
when "0011101101000000" => dout <= "011";
when "0011101110000000" => dout <= "100";
when "0011100000000110" => dout <= "100";
when "0011100000000000" => dout <= "010";
when "0011100001000000" => dout <= "011";
when "0011100010000000" => dout <= "100";
when "0011100011000000" => dout <= "010";
when "0011100100000110" => dout <= "100";
when "0011100100000000" => dout <= "010";
when "0011100101000000" => dout <= "011";
when "0011100110000000" => dout <= "100";
when "0011100111000000" => dout <= "010";
when "1000000011111000" => dout <= "011";
when "1000000000111110" => dout <= "101";
when "1000000000111000" => dout <= "011";
when "1000000001111000" => dout <= "100";
when "1000000010111000" => dout <= "101";
when "1000000111111000" => dout <= "100";
when "1000000100111110" => dout <= "110";
when "1000000100111000" => dout <= "100";
when "1000000101111000" => dout <= "101";
when "1000000110111000" => dout <= "110";
when "1000001111111000" => dout <= "011";
when "1000001100111110" => dout <= "101";
when "1000001100111000" => dout <= "011";
when "1000001101111000" => dout <= "100";
when "1000001110111000" => dout <= "101";
when "0011110000000000" => dout <= "010";
when "0011110100000000" => dout <= "011";
when "1111011011011000" => dout <= "010";
when "1111011000011110" => dout <= "100";
when "1111011000011000" => dout <= "010";
when "1111011001011000" => dout <= "011";
when "1111011010011000" => dout <= "100";
when "1111011111011000" => dout <= "010";
when "1111011100011110" => dout <= "100";
when "1111011100011000" => dout <= "010";
when "1111011101011000" => dout <= "011";
when "1111011110011000" => dout <= "100";
when "0011011100000000" => dout <= "001";
when "0010011100000000" => dout <= "001";
when "0011111100000000" => dout <= "001";
when "0010111100000000" => dout <= "001";
when "1111011011100000" => dout <= "010";
when "1111011000100110" => dout <= "100";
when "1111011000100000" => dout <= "010";
when "1111011001100000" => dout <= "011";
when "1111011010100000" => dout <= "100";
when "1111011111100000" => dout <= "010";
when "1111011100100110" => dout <= "100";
when "1111011100100000" => dout <= "010";
when "1111011101100000" => dout <= "011";
when "1111011110100000" => dout <= "100";
when "1111011011101000" => dout <= "010";
when "1111011000101110" => dout <= "100";
when "1111011000101000" => dout <= "010";
when "1111011001101000" => dout <= "011";
when "1111011010101000" => dout <= "100";
when "1111011111101000" => dout <= "010";
when "1111011100101110" => dout <= "100";
when "1111011100101000" => dout <= "010";
when "1111011101101000" => dout <= "011";
when "1111011110101000" => dout <= "100";
when "1111011011110000" => dout <= "010";
when "1111011000110110" => dout <= "100";
when "1111011000110000" => dout <= "010";
when "1111011001110000" => dout <= "011";
when "1111011010110000" => dout <= "100";
when "1111011111110000" => dout <= "010";
when "1111011100110110" => dout <= "100";
when "1111011100110000" => dout <= "010";
when "1111011101110000" => dout <= "011";
when "1111011110110000" => dout <= "100";
when "1111011011111000" => dout <= "010";
when "1111011000111110" => dout <= "100";
when "1111011000111000" => dout <= "010";
when "1111011001111000" => dout <= "011";
when "1111011010111000" => dout <= "100";
when "1111011111111000" => dout <= "010";
when "1111011100111110" => dout <= "100";
when "1111011100111000" => dout <= "010";
when "1111011101111000" => dout <= "011";
when "1111011110111000" => dout <= "100";
when "1101010000000000" => dout <= "010";
when "1101010100000000" => dout <= "010";
when "1001100000000000" => dout <= "001";
when "1001100100000000" => dout <= "001";
when "1101000011000000" => dout <= "010";
when "1101000000000110" => dout <= "100";
when "1101000000000000" => dout <= "010";
when "1101000001000000" => dout <= "011";
when "1101000010000000" => dout <= "100";
when "1101000111000000" => dout <= "010";
when "1101000100000110" => dout <= "100";
when "1101000100000000" => dout <= "010";
when "1101000101000000" => dout <= "011";
when "1101000110000000" => dout <= "100";
when "1101001011000000" => dout <= "010";
when "1101001000000110" => dout <= "100";
when "1101001000000000" => dout <= "010";
when "1101001001000000" => dout <= "011";
when "1101001010000000" => dout <= "100";
when "1101001111000000" => dout <= "010";
when "1101001100000110" => dout <= "100";
when "1101001100000000" => dout <= "010";
when "1101001101000000" => dout <= "011";
when "1101001110000000" => dout <= "100";
when "0010000011000000" => dout <= "010";
when "0010000000000110" => dout <= "100";
when "0010000000000000" => dout <= "010";
when "0010000001000000" => dout <= "011";
when "0010000010000000" => dout <= "100";
when "0010000111000000" => dout <= "010";
when "0010000100000110" => dout <= "100";
when "0010000100000000" => dout <= "010";
when "0010000101000000" => dout <= "011";
when "0010000110000000" => dout <= "100";
when "0010001011000000" => dout <= "010";
when "0010001000000110" => dout <= "100";
when "0010001000000000" => dout <= "010";
when "0010001001000000" => dout <= "011";
when "0010001010000000" => dout <= "100";
when "0010001111000000" => dout <= "010";
when "0010001100000110" => dout <= "100";
when "0010001100000000" => dout <= "010";
when "0010001101000000" => dout <= "011";
when "0010001110000000" => dout <= "100";
when "1000000011100000" => dout <= "011";
when "1000000000100110" => dout <= "101";
when "1000000000100000" => dout <= "011";
when "1000000001100000" => dout <= "100";
when "1000000010100000" => dout <= "101";
when "1000000111100000" => dout <= "100";
when "1000000100100110" => dout <= "110";
when "1000000100100000" => dout <= "100";
when "1000000101100000" => dout <= "101";
when "1000000110100000" => dout <= "110";
when "1000001111100000" => dout <= "011";
when "1000001100100110" => dout <= "101";
when "1000001100100000" => dout <= "011";
when "1000001101100000" => dout <= "100";
when "1000001110100000" => dout <= "101";
when "0010010000000000" => dout <= "010";
when "0010010100000000" => dout <= "011";
when "0000100000000110" => dout <= "100";
when "0000100000000000" => dout <= "010";
when "0000100001000000" => dout <= "011";
when "0000100010000000" => dout <= "100";
when "0000100011000000" => dout <= "010";
when "0000100100000110" => dout <= "100";
when "0000100100000000" => dout <= "010";
when "0000100101000000" => dout <= "011";
when "0000100110000000" => dout <= "100";
when "0000100111000000" => dout <= "010";
when "0000101011000000" => dout <= "010";
when "0000101000000110" => dout <= "100";
when "0000101000000000" => dout <= "010";
when "0000101001000000" => dout <= "011";
when "0000101010000000" => dout <= "100";
when "0000101111000000" => dout <= "010";
when "0000101100000110" => dout <= "100";
when "0000101100000000" => dout <= "010";
when "0000101101000000" => dout <= "011";
when "0000101110000000" => dout <= "100";
when "1000000011001000" => dout <= "011";
when "1000000000001110" => dout <= "101";
when "1000000000001000" => dout <= "011";
when "1000000001001000" => dout <= "100";
when "1000000010001000" => dout <= "101";
when "1000000111001000" => dout <= "100";
when "1000000100001110" => dout <= "110";
when "1000000100001000" => dout <= "100";
when "1000000101001000" => dout <= "101";
when "1000000110001000" => dout <= "110";
when "1000001111001000" => dout <= "011";
when "1000001100001110" => dout <= "101";
when "1000001100001000" => dout <= "011";
when "1000001101001000" => dout <= "100";
when "1000001110001000" => dout <= "101";
when "0000110000000000" => dout <= "010";
when "0000110100000000" => dout <= "011";
when "1000010000000110" => dout <= "100";
when "1000010000000000" => dout <= "010";
when "1000010001000000" => dout <= "011";
when "1000010010000000" => dout <= "100";
when "1000010100000110" => dout <= "100";
when "1000010100000000" => dout <= "010";
when "1000010101000000" => dout <= "011";
when "1000010110000000" => dout <= "100";
when "1000010011000000" => dout <= "010";
when "1000010111000000" => dout <= "010";
when "1111011011000000" => dout <= "011";
when "1111011000000110" => dout <= "101";
when "1111011000000000" => dout <= "011";
when "1111011001000000" => dout <= "100";
when "1111011010000000" => dout <= "101";
when "1111011111000000" => dout <= "100";
when "1111011100000110" => dout <= "110";
when "1111011100000000" => dout <= "100";
when "1111011101000000" => dout <= "101";
when "1111011110000000" => dout <= "110";
when "1010100000000000" => dout <= "010";
when "1010100100000000" => dout <= "011";
when "0011000000000110" => dout <= "100";
when "0011000000000000" => dout <= "010";
when "0011000001000000" => dout <= "011";
when "0011000010000000" => dout <= "100";
when "0011000011000000" => dout <= "010";
when "0011000100000110" => dout <= "100";
when "0011000100000000" => dout <= "010";
when "0011000101000000" => dout <= "011";
when "0011000110000000" => dout <= "100";
when "0011000111000000" => dout <= "010";
when "0011001011000000" => dout <= "010";
when "0011001000000110" => dout <= "100";
when "0011001000000000" => dout <= "010";
when "0011001001000000" => dout <= "011";
when "0011001010000000" => dout <= "100";
when "0011001111000000" => dout <= "010";
when "0011001100000110" => dout <= "100";
when "0011001100000000" => dout <= "010";
when "0011001101000000" => dout <= "011";
when "0011001110000000" => dout <= "100";
when "1000000011110000" => dout <= "011";
when "1000000000110110" => dout <= "101";
when "1000000000110000" => dout <= "011";
when "1000000001110000" => dout <= "100";
when "1000000010110000" => dout <= "101";
when "1000000111110000" => dout <= "100";
when "1000000100110110" => dout <= "110";
when "1000000100110000" => dout <= "100";
when "1000000101110000" => dout <= "101";
when "1000000110110000" => dout <= "110";
when "1000001111110000" => dout <= "011";
when "1000001100110110" => dout <= "101";
when "1000001100110000" => dout <= "011";
when "1000001101110000" => dout <= "100";
when "1000001110110000" => dout <= "101";
when "0011010000000000" => dout <= "010";
when "0011010100000000" => dout <= "011";
when "1111011011010000" => dout <= "010";
when "1111011000010110" => dout <= "100";
when "1111011000010000" => dout <= "010";
when "1111011001010000" => dout <= "011";
when "1111011010010000" => dout <= "100";
when "1111011111010000" => dout <= "010";
when "1111011100010110" => dout <= "100";
when "1111011100010000" => dout <= "010";
when "1111011101010000" => dout <= "011";
when "1111011110010000" => dout <= "100";
when "1010010000000000" => dout <= "001";
when "1010010100000000" => dout <= "001";
when "1010011000000000" => dout <= "001";
when "1010011100000000" => dout <= "001";
when "1010111000000000" => dout <= "001";
when "1010111100000000" => dout <= "001";
when "1010110000000000" => dout <= "001";
when "1010110100000000" => dout <= "001";
when "1010101000000000" => dout <= "001";
when "1010101100000000" => dout <= "001";
when "1111001000000000" => dout <= "001";
when "1111001100000000" => dout <= "001";
when "0110000000000000" => dout <= "001";
when "0110000100000000" => dout <= "001";
when "1100100000000000" => dout <= "001";
when "1100100100000000" => dout <= "001";
when "0110001000000000" => dout <= "001";
when "0110110000000000" => dout <= "010";
when "0110110100000000" => dout <= "001";
when "0110111000000000" => dout <= "001";
when "0110111100000000" => dout <= "001";
when "0000111100000000" => dout <= "001";
when "0110001100000000" => dout <= "001";
when "0110010000000000" => dout <= "001";
when "0110010100000000" => dout <= "001";
when "0110011000000000" => dout <= "001";
when "0110011100000000" => dout <= "001";
when "1000001000000000" => dout <= "001";
when "1101011000000000" => dout <= "001";
when "1111000100000000" => dout <= "001";
when "1100000000000000" => dout <= "001";
when "1100000100000000" => dout <= "001";
when others => dout <= "111";
end case;
end process;
end rtl;

2758
common/CPU/cpu86/proc_rtl.vhd Normal file
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721
common/CPU/cpu86/r_table.vhd Normal file
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@@ -0,0 +1,721 @@
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity r_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end r_table;
architecture rtl of r_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "000";
when "1110100100000000" => dout <= "000";
when "1111111111100000" => dout <= "001";
when "1111111100100110" => dout <= "001";
when "1111111100100000" => dout <= "001";
when "1111111101100000" => dout <= "001";
when "1111111110100000" => dout <= "001";
when "1110101000000000" => dout <= "000";
when "1111111100101110" => dout <= "001";
when "1111111100101000" => dout <= "001";
when "1111111101101000" => dout <= "001";
when "1111111110101000" => dout <= "001";
when "1110100000000000" => dout <= "000";
when "1111111111010000" => dout <= "001";
when "1111111100010110" => dout <= "001";
when "1111111100010000" => dout <= "001";
when "1111111101010000" => dout <= "001";
when "1111111110010000" => dout <= "001";
when "1001101000000000" => dout <= "000";
when "1111111100011110" => dout <= "001";
when "1111111100011000" => dout <= "001";
when "1111111101011000" => dout <= "001";
when "1111111110011000" => dout <= "001";
when "1100001100000000" => dout <= "000";
when "1100001000000000" => dout <= "000";
when "1100101100000000" => dout <= "000";
when "1100101000000000" => dout <= "000";
when "0111010000000000" => dout <= "000";
when "0111110000000000" => dout <= "000";
when "0111111000000000" => dout <= "000";
when "0111001000000000" => dout <= "000";
when "0111011000000000" => dout <= "000";
when "0111101000000000" => dout <= "000";
when "0111000000000000" => dout <= "000";
when "0111100000000000" => dout <= "000";
when "0111010100000000" => dout <= "000";
when "0111110100000000" => dout <= "000";
when "0111111100000000" => dout <= "000";
when "0111001100000000" => dout <= "000";
when "0111011100000000" => dout <= "000";
when "0111101100000000" => dout <= "000";
when "0111000100000000" => dout <= "000";
when "0111100100000000" => dout <= "000";
when "1110001100000000" => dout <= "000";
when "1110001000000000" => dout <= "000";
when "1110000100000000" => dout <= "000";
when "1110000000000000" => dout <= "000";
when "1100110100000000" => dout <= "000";
when "1100110000000000" => dout <= "000";
when "1100111000000000" => dout <= "000";
when "1100111100000000" => dout <= "000";
when "1111100000000000" => dout <= "000";
when "1111010100000000" => dout <= "000";
when "1111100100000000" => dout <= "000";
when "1111110000000000" => dout <= "000";
when "1111110100000000" => dout <= "000";
when "1111101000000000" => dout <= "000";
when "1111101100000000" => dout <= "000";
when "1111010000000000" => dout <= "000";
when "1001101100000000" => dout <= "000";
when "1111000000000000" => dout <= "000";
when "1001000000000000" => dout <= "000";
when "0010011000000000" => dout <= "000";
when "0010111000000000" => dout <= "000";
when "0011011000000000" => dout <= "000";
when "0011111000000000" => dout <= "000";
when "1000100011000000" => dout <= "001";
when "1000100000000000" => dout <= "001";
when "1000100001000000" => dout <= "001";
when "1000100010000000" => dout <= "001";
when "1000100000000110" => dout <= "001";
when "1000100111000000" => dout <= "001";
when "1000100100000000" => dout <= "001";
when "1000100101000000" => dout <= "001";
when "1000100110000000" => dout <= "001";
when "1000100100000110" => dout <= "001";
when "1000101011000000" => dout <= "001";
when "1000101000000000" => dout <= "001";
when "1000101001000000" => dout <= "001";
when "1000101010000000" => dout <= "001";
when "1000101000000110" => dout <= "001";
when "1000101111000000" => dout <= "001";
when "1000101100000000" => dout <= "001";
when "1000101101000000" => dout <= "001";
when "1000101110000000" => dout <= "001";
when "1000101100000110" => dout <= "001";
when "1100011000000000" => dout <= "001";
when "1100011001000000" => dout <= "001";
when "1100011010000000" => dout <= "001";
when "1100011000000110" => dout <= "001";
when "1100011100000000" => dout <= "001";
when "1100011101000000" => dout <= "001";
when "1100011110000000" => dout <= "001";
when "1100011100000110" => dout <= "001";
when "1011000000000000" => dout <= "010";
when "1011000100000000" => dout <= "010";
when "1011001000000000" => dout <= "010";
when "1011001100000000" => dout <= "010";
when "1011010000000000" => dout <= "010";
when "1011010100000000" => dout <= "010";
when "1011011000000000" => dout <= "010";
when "1011011100000000" => dout <= "010";
when "1011100000000000" => dout <= "010";
when "1011100100000000" => dout <= "010";
when "1011101000000000" => dout <= "010";
when "1011101100000000" => dout <= "010";
when "1011110000000000" => dout <= "010";
when "1011110100000000" => dout <= "010";
when "1011111000000000" => dout <= "010";
when "1011111100000000" => dout <= "010";
when "1010000000000000" => dout <= "011";
when "1010000100000000" => dout <= "011";
when "1010001000000000" => dout <= "011";
when "1010001100000000" => dout <= "011";
when "1000111011000000" => dout <= "001";
when "1000111000000000" => dout <= "001";
when "1000111001000000" => dout <= "001";
when "1000111010000000" => dout <= "001";
when "1000111000000110" => dout <= "001";
when "1000110011000000" => dout <= "001";
when "1000110000000000" => dout <= "001";
when "1000110001000000" => dout <= "001";
when "1000110010000000" => dout <= "001";
when "1000110000000110" => dout <= "001";
when "1111111100110000" => dout <= "001";
when "1111111101110000" => dout <= "001";
when "1111111110110000" => dout <= "001";
when "1111111100110110" => dout <= "001";
when "0101000000000000" => dout <= "010";
when "0101000100000000" => dout <= "010";
when "0101001000000000" => dout <= "010";
when "0101001100000000" => dout <= "010";
when "0101010000000000" => dout <= "010";
when "0101010100000000" => dout <= "010";
when "0101011000000000" => dout <= "010";
when "0101011100000000" => dout <= "010";
when "0000011000000000" => dout <= "011";
when "0000111000000000" => dout <= "011";
when "0001011000000000" => dout <= "011";
when "0001111000000000" => dout <= "011";
when "1000111100000000" => dout <= "001";
when "1000111101000000" => dout <= "001";
when "1000111110000000" => dout <= "001";
when "1000111100000110" => dout <= "001";
when "1000111111000000" => dout <= "001";
when "0101100000000000" => dout <= "010";
when "0101100100000000" => dout <= "010";
when "0101101000000000" => dout <= "010";
when "0101101100000000" => dout <= "010";
when "0101110000000000" => dout <= "010";
when "0101110100000000" => dout <= "010";
when "0101111000000000" => dout <= "010";
when "0101111100000000" => dout <= "010";
when "0000011100000000" => dout <= "011";
when "0001011100000000" => dout <= "011";
when "0001111100000000" => dout <= "011";
when "1000011011000000" => dout <= "001";
when "1000011000000000" => dout <= "001";
when "1000011001000000" => dout <= "001";
when "1000011010000000" => dout <= "001";
when "1000011000000110" => dout <= "001";
when "1000011111000000" => dout <= "001";
when "1000011100000000" => dout <= "001";
when "1000011101000000" => dout <= "001";
when "1000011110000000" => dout <= "001";
when "1000011100000110" => dout <= "001";
when "1001000100000000" => dout <= "010";
when "1001001000000000" => dout <= "010";
when "1001001100000000" => dout <= "010";
when "1001010000000000" => dout <= "010";
when "1001010100000000" => dout <= "010";
when "1001011000000000" => dout <= "010";
when "1001011100000000" => dout <= "010";
when "1110010000000000" => dout <= "000";
when "1110010100000000" => dout <= "000";
when "1110110000000000" => dout <= "000";
when "1110110100000000" => dout <= "000";
when "1110011000000000" => dout <= "000";
when "1110011100000000" => dout <= "000";
when "1110111100000000" => dout <= "000";
when "1110111000000000" => dout <= "000";
when "1101011100000000" => dout <= "000";
when "1001111100000000" => dout <= "000";
when "1001111000000000" => dout <= "000";
when "1001110000000000" => dout <= "000";
when "1001110100000000" => dout <= "000";
when "1000110100000110" => dout <= "001";
when "1000110111000000" => dout <= "001";
when "1000110100000000" => dout <= "001";
when "1000110101000000" => dout <= "001";
when "1000110110000000" => dout <= "001";
when "1100010100000110" => dout <= "001";
when "1100010100000000" => dout <= "001";
when "1100010101000000" => dout <= "001";
when "1100010110000000" => dout <= "001";
when "1100010000000110" => dout <= "001";
when "1100010000000000" => dout <= "001";
when "1100010001000000" => dout <= "001";
when "1100010010000000" => dout <= "001";
when "0000000011000000" => dout <= "001";
when "0000000000000110" => dout <= "001";
when "0000000000000000" => dout <= "001";
when "0000000001000000" => dout <= "001";
when "0000000010000000" => dout <= "001";
when "0000000111000000" => dout <= "001";
when "0000000100000110" => dout <= "001";
when "0000000100000000" => dout <= "001";
when "0000000101000000" => dout <= "001";
when "0000000110000000" => dout <= "001";
when "0000001011000000" => dout <= "001";
when "0000001000000110" => dout <= "001";
when "0000001000000000" => dout <= "001";
when "0000001001000000" => dout <= "001";
when "0000001010000000" => dout <= "001";
when "0000001111000000" => dout <= "001";
when "0000001100000110" => dout <= "001";
when "0000001100000000" => dout <= "001";
when "0000001101000000" => dout <= "001";
when "0000001110000000" => dout <= "001";
when "1000000011000000" => dout <= "001";
when "1000000000000110" => dout <= "001";
when "1000000000000000" => dout <= "001";
when "1000000001000000" => dout <= "001";
when "1000000010000000" => dout <= "001";
when "1000000111000000" => dout <= "001";
when "1000000100000110" => dout <= "001";
when "1000000100000000" => dout <= "001";
when "1000000101000000" => dout <= "001";
when "1000000110000000" => dout <= "001";
when "1000001111000000" => dout <= "001";
when "1000001100000110" => dout <= "001";
when "1000001100000000" => dout <= "001";
when "1000001101000000" => dout <= "001";
when "1000001110000000" => dout <= "001";
when "0000010000000000" => dout <= "000";
when "0000010100000000" => dout <= "000";
when "0001000011000000" => dout <= "001";
when "0001000000000110" => dout <= "001";
when "0001000000000000" => dout <= "001";
when "0001000001000000" => dout <= "001";
when "0001000010000000" => dout <= "001";
when "0001000111000000" => dout <= "001";
when "0001000100000110" => dout <= "001";
when "0001000100000000" => dout <= "001";
when "0001000101000000" => dout <= "001";
when "0001000110000000" => dout <= "001";
when "0001001011000000" => dout <= "001";
when "0001001000000110" => dout <= "001";
when "0001001000000000" => dout <= "001";
when "0001001001000000" => dout <= "001";
when "0001001010000000" => dout <= "001";
when "0001001111000000" => dout <= "001";
when "0001001100000110" => dout <= "001";
when "0001001100000000" => dout <= "001";
when "0001001101000000" => dout <= "001";
when "0001001110000000" => dout <= "001";
when "1000000011010000" => dout <= "001";
when "1000000000010110" => dout <= "001";
when "1000000000010000" => dout <= "001";
when "1000000001010000" => dout <= "001";
when "1000000010010000" => dout <= "001";
when "1000000111010000" => dout <= "001";
when "1000000100010110" => dout <= "001";
when "1000000100010000" => dout <= "001";
when "1000000101010000" => dout <= "001";
when "1000000110010000" => dout <= "001";
when "1000001111010000" => dout <= "001";
when "1000001100010110" => dout <= "001";
when "1000001100010000" => dout <= "001";
when "1000001101010000" => dout <= "001";
when "1000001110010000" => dout <= "001";
when "0001010000000000" => dout <= "000";
when "0001010100000000" => dout <= "000";
when "0010100011000000" => dout <= "001";
when "0010100000000110" => dout <= "001";
when "0010100000000000" => dout <= "001";
when "0010100001000000" => dout <= "001";
when "0010100010000000" => dout <= "001";
when "0010100111000000" => dout <= "001";
when "0010100100000110" => dout <= "001";
when "0010100100000000" => dout <= "001";
when "0010100101000000" => dout <= "001";
when "0010100110000000" => dout <= "001";
when "0010101011000000" => dout <= "001";
when "0010101000000110" => dout <= "001";
when "0010101000000000" => dout <= "001";
when "0010101001000000" => dout <= "001";
when "0010101010000000" => dout <= "001";
when "0010101111000000" => dout <= "001";
when "0010101100000110" => dout <= "001";
when "0010101100000000" => dout <= "001";
when "0010101101000000" => dout <= "001";
when "0010101110000000" => dout <= "001";
when "1000000011101000" => dout <= "001";
when "1000000000101110" => dout <= "001";
when "1000000000101000" => dout <= "001";
when "1000000001101000" => dout <= "001";
when "1000000010101000" => dout <= "001";
when "1000000111101000" => dout <= "001";
when "1000000100101110" => dout <= "001";
when "1000000100101000" => dout <= "001";
when "1000000101101000" => dout <= "001";
when "1000000110101000" => dout <= "001";
when "1000001111101000" => dout <= "001";
when "1000001100101110" => dout <= "001";
when "1000001100101000" => dout <= "001";
when "1000001101101000" => dout <= "001";
when "1000001110101000" => dout <= "001";
when "0010110000000000" => dout <= "000";
when "0010110100000000" => dout <= "000";
when "0001100011000000" => dout <= "001";
when "0001100000000110" => dout <= "001";
when "0001100000000000" => dout <= "001";
when "0001100001000000" => dout <= "001";
when "0001100010000000" => dout <= "001";
when "0001100111000000" => dout <= "001";
when "0001100100000110" => dout <= "001";
when "0001100100000000" => dout <= "001";
when "0001100101000000" => dout <= "001";
when "0001100110000000" => dout <= "001";
when "0001101011000000" => dout <= "001";
when "0001101000000110" => dout <= "001";
when "0001101000000000" => dout <= "001";
when "0001101001000000" => dout <= "001";
when "0001101010000000" => dout <= "001";
when "0001101111000000" => dout <= "001";
when "0001101100000110" => dout <= "001";
when "0001101100000000" => dout <= "001";
when "0001101101000000" => dout <= "001";
when "0001101110000000" => dout <= "001";
when "1000000011011000" => dout <= "001";
when "1000000000011110" => dout <= "001";
when "1000000000011000" => dout <= "001";
when "1000000001011000" => dout <= "001";
when "1000000010011000" => dout <= "001";
when "1000000111011000" => dout <= "001";
when "1000000100011110" => dout <= "001";
when "1000000100011000" => dout <= "001";
when "1000000101011000" => dout <= "001";
when "1000000110011000" => dout <= "001";
when "1000001111011000" => dout <= "001";
when "1000001100011110" => dout <= "001";
when "1000001100011000" => dout <= "001";
when "1000001101011000" => dout <= "001";
when "1000001110011000" => dout <= "001";
when "0001110000000000" => dout <= "000";
when "0001110100000000" => dout <= "000";
when "1111111011000000" => dout <= "001";
when "1111111000000110" => dout <= "001";
when "1111111000000000" => dout <= "001";
when "1111111001000000" => dout <= "001";
when "1111111010000000" => dout <= "001";
when "1111111100000110" => dout <= "001";
when "1111111100000000" => dout <= "001";
when "1111111101000000" => dout <= "001";
when "1111111110000000" => dout <= "001";
when "0100000000000000" => dout <= "010";
when "0100000100000000" => dout <= "010";
when "0100001000000000" => dout <= "010";
when "0100001100000000" => dout <= "010";
when "0100010000000000" => dout <= "010";
when "0100010100000000" => dout <= "010";
when "0100011000000000" => dout <= "010";
when "0100011100000000" => dout <= "010";
when "1111111011001000" => dout <= "001";
when "1111111000001110" => dout <= "001";
when "1111111000001000" => dout <= "001";
when "1111111001001000" => dout <= "001";
when "1111111010001000" => dout <= "001";
when "1111111100001110" => dout <= "001";
when "1111111100001000" => dout <= "001";
when "1111111101001000" => dout <= "001";
when "1111111110001000" => dout <= "001";
when "0100100000000000" => dout <= "010";
when "0100100100000000" => dout <= "010";
when "0100101000000000" => dout <= "010";
when "0100101100000000" => dout <= "010";
when "0100110000000000" => dout <= "010";
when "0100110100000000" => dout <= "010";
when "0100111000000000" => dout <= "010";
when "0100111100000000" => dout <= "010";
when "0011101011000000" => dout <= "001";
when "0011101000000110" => dout <= "001";
when "0011101000000000" => dout <= "001";
when "0011101001000000" => dout <= "001";
when "0011101010000000" => dout <= "001";
when "0011101111000000" => dout <= "001";
when "0011101100000110" => dout <= "001";
when "0011101100000000" => dout <= "001";
when "0011101101000000" => dout <= "001";
when "0011101110000000" => dout <= "001";
when "0011100000000110" => dout <= "001";
when "0011100000000000" => dout <= "001";
when "0011100001000000" => dout <= "001";
when "0011100010000000" => dout <= "001";
when "0011100011000000" => dout <= "001";
when "0011100100000110" => dout <= "001";
when "0011100100000000" => dout <= "001";
when "0011100101000000" => dout <= "001";
when "0011100110000000" => dout <= "001";
when "0011100111000000" => dout <= "001";
when "1000000011111000" => dout <= "001";
when "1000000000111110" => dout <= "001";
when "1000000000111000" => dout <= "001";
when "1000000001111000" => dout <= "001";
when "1000000010111000" => dout <= "001";
when "1000000111111000" => dout <= "001";
when "1000000100111110" => dout <= "001";
when "1000000100111000" => dout <= "001";
when "1000000101111000" => dout <= "001";
when "1000000110111000" => dout <= "001";
when "1000001111111000" => dout <= "001";
when "1000001100111110" => dout <= "001";
when "1000001100111000" => dout <= "001";
when "1000001101111000" => dout <= "001";
when "1000001110111000" => dout <= "001";
when "0011110000000000" => dout <= "000";
when "0011110100000000" => dout <= "000";
when "1111011011011000" => dout <= "001";
when "1111011000011110" => dout <= "001";
when "1111011000011000" => dout <= "001";
when "1111011001011000" => dout <= "001";
when "1111011010011000" => dout <= "001";
when "1111011111011000" => dout <= "001";
when "1111011100011110" => dout <= "001";
when "1111011100011000" => dout <= "001";
when "1111011101011000" => dout <= "001";
when "1111011110011000" => dout <= "001";
when "0011011100000000" => dout <= "000";
when "0010011100000000" => dout <= "000";
when "0011111100000000" => dout <= "000";
when "0010111100000000" => dout <= "000";
when "1111011011100000" => dout <= "001";
when "1111011000100110" => dout <= "001";
when "1111011000100000" => dout <= "001";
when "1111011001100000" => dout <= "001";
when "1111011010100000" => dout <= "001";
when "1111011111100000" => dout <= "001";
when "1111011100100110" => dout <= "001";
when "1111011100100000" => dout <= "001";
when "1111011101100000" => dout <= "001";
when "1111011110100000" => dout <= "001";
when "1111011011101000" => dout <= "001";
when "1111011000101110" => dout <= "001";
when "1111011000101000" => dout <= "001";
when "1111011001101000" => dout <= "001";
when "1111011010101000" => dout <= "001";
when "1111011111101000" => dout <= "001";
when "1111011100101110" => dout <= "001";
when "1111011100101000" => dout <= "001";
when "1111011101101000" => dout <= "001";
when "1111011110101000" => dout <= "001";
when "1111011011110000" => dout <= "001";
when "1111011000110110" => dout <= "001";
when "1111011000110000" => dout <= "001";
when "1111011001110000" => dout <= "001";
when "1111011010110000" => dout <= "001";
when "1111011111110000" => dout <= "001";
when "1111011100110110" => dout <= "001";
when "1111011100110000" => dout <= "001";
when "1111011101110000" => dout <= "001";
when "1111011110110000" => dout <= "001";
when "1111011011111000" => dout <= "001";
when "1111011000111110" => dout <= "001";
when "1111011000111000" => dout <= "001";
when "1111011001111000" => dout <= "001";
when "1111011010111000" => dout <= "001";
when "1111011111111000" => dout <= "001";
when "1111011100111110" => dout <= "001";
when "1111011100111000" => dout <= "001";
when "1111011101111000" => dout <= "001";
when "1111011110111000" => dout <= "001";
when "1101010000000000" => dout <= "000";
when "1101010100000000" => dout <= "000";
when "1001100000000000" => dout <= "000";
when "1001100100000000" => dout <= "000";
when "1101000011000000" => dout <= "001";
when "1101000000000110" => dout <= "001";
when "1101000000000000" => dout <= "001";
when "1101000001000000" => dout <= "001";
when "1101000010000000" => dout <= "001";
when "1101000111000000" => dout <= "001";
when "1101000100000110" => dout <= "001";
when "1101000100000000" => dout <= "001";
when "1101000101000000" => dout <= "001";
when "1101000110000000" => dout <= "001";
when "1101001011000000" => dout <= "001";
when "1101001000000110" => dout <= "001";
when "1101001000000000" => dout <= "001";
when "1101001001000000" => dout <= "001";
when "1101001010000000" => dout <= "001";
when "1101001111000000" => dout <= "001";
when "1101001100000110" => dout <= "001";
when "1101001100000000" => dout <= "001";
when "1101001101000000" => dout <= "001";
when "1101001110000000" => dout <= "001";
when "0010000011000000" => dout <= "001";
when "0010000000000110" => dout <= "001";
when "0010000000000000" => dout <= "001";
when "0010000001000000" => dout <= "001";
when "0010000010000000" => dout <= "001";
when "0010000111000000" => dout <= "001";
when "0010000100000110" => dout <= "001";
when "0010000100000000" => dout <= "001";
when "0010000101000000" => dout <= "001";
when "0010000110000000" => dout <= "001";
when "0010001011000000" => dout <= "001";
when "0010001000000110" => dout <= "001";
when "0010001000000000" => dout <= "001";
when "0010001001000000" => dout <= "001";
when "0010001010000000" => dout <= "001";
when "0010001111000000" => dout <= "001";
when "0010001100000110" => dout <= "001";
when "0010001100000000" => dout <= "001";
when "0010001101000000" => dout <= "001";
when "0010001110000000" => dout <= "001";
when "1000000011100000" => dout <= "001";
when "1000000000100110" => dout <= "001";
when "1000000000100000" => dout <= "001";
when "1000000001100000" => dout <= "001";
when "1000000010100000" => dout <= "001";
when "1000000111100000" => dout <= "001";
when "1000000100100110" => dout <= "001";
when "1000000100100000" => dout <= "001";
when "1000000101100000" => dout <= "001";
when "1000000110100000" => dout <= "001";
when "1000001111100000" => dout <= "001";
when "1000001100100110" => dout <= "001";
when "1000001100100000" => dout <= "001";
when "1000001101100000" => dout <= "001";
when "1000001110100000" => dout <= "001";
when "0010010000000000" => dout <= "000";
when "0010010100000000" => dout <= "000";
when "0000100000000110" => dout <= "001";
when "0000100000000000" => dout <= "001";
when "0000100001000000" => dout <= "001";
when "0000100010000000" => dout <= "001";
when "0000100011000000" => dout <= "001";
when "0000100100000110" => dout <= "001";
when "0000100100000000" => dout <= "001";
when "0000100101000000" => dout <= "001";
when "0000100110000000" => dout <= "001";
when "0000100111000000" => dout <= "001";
when "0000101011000000" => dout <= "001";
when "0000101000000110" => dout <= "001";
when "0000101000000000" => dout <= "001";
when "0000101001000000" => dout <= "001";
when "0000101010000000" => dout <= "001";
when "0000101111000000" => dout <= "001";
when "0000101100000110" => dout <= "001";
when "0000101100000000" => dout <= "001";
when "0000101101000000" => dout <= "001";
when "0000101110000000" => dout <= "001";
when "1000000011001000" => dout <= "001";
when "1000000000001110" => dout <= "001";
when "1000000000001000" => dout <= "001";
when "1000000001001000" => dout <= "001";
when "1000000010001000" => dout <= "001";
when "1000000111001000" => dout <= "001";
when "1000000100001110" => dout <= "001";
when "1000000100001000" => dout <= "001";
when "1000000101001000" => dout <= "001";
when "1000000110001000" => dout <= "001";
when "1000001111001000" => dout <= "001";
when "1000001100001110" => dout <= "001";
when "1000001100001000" => dout <= "001";
when "1000001101001000" => dout <= "001";
when "1000001110001000" => dout <= "001";
when "0000110000000000" => dout <= "000";
when "0000110100000000" => dout <= "000";
when "1000010000000110" => dout <= "001";
when "1000010000000000" => dout <= "001";
when "1000010001000000" => dout <= "001";
when "1000010010000000" => dout <= "001";
when "1000010100000110" => dout <= "001";
when "1000010100000000" => dout <= "001";
when "1000010101000000" => dout <= "001";
when "1000010110000000" => dout <= "001";
when "1000010011000000" => dout <= "001";
when "1000010111000000" => dout <= "001";
when "1111011011000000" => dout <= "000";
when "1111011000000110" => dout <= "000";
when "1111011000000000" => dout <= "000";
when "1111011001000000" => dout <= "000";
when "1111011010000000" => dout <= "000";
when "1111011111000000" => dout <= "000";
when "1111011100000110" => dout <= "000";
when "1111011100000000" => dout <= "000";
when "1111011101000000" => dout <= "000";
when "1111011110000000" => dout <= "000";
when "1010100000000000" => dout <= "000";
when "1010100100000000" => dout <= "000";
when "0011000000000110" => dout <= "001";
when "0011000000000000" => dout <= "001";
when "0011000001000000" => dout <= "001";
when "0011000010000000" => dout <= "001";
when "0011000011000000" => dout <= "001";
when "0011000100000110" => dout <= "001";
when "0011000100000000" => dout <= "001";
when "0011000101000000" => dout <= "001";
when "0011000110000000" => dout <= "001";
when "0011000111000000" => dout <= "001";
when "0011001011000000" => dout <= "001";
when "0011001000000110" => dout <= "001";
when "0011001000000000" => dout <= "001";
when "0011001001000000" => dout <= "001";
when "0011001010000000" => dout <= "001";
when "0011001111000000" => dout <= "001";
when "0011001100000110" => dout <= "001";
when "0011001100000000" => dout <= "001";
when "0011001101000000" => dout <= "001";
when "0011001110000000" => dout <= "001";
when "1000000011110000" => dout <= "001";
when "1000000000110110" => dout <= "001";
when "1000000000110000" => dout <= "001";
when "1000000001110000" => dout <= "001";
when "1000000010110000" => dout <= "001";
when "1000000111110000" => dout <= "001";
when "1000000100110110" => dout <= "001";
when "1000000100110000" => dout <= "001";
when "1000000101110000" => dout <= "001";
when "1000000110110000" => dout <= "001";
when "1000001111110000" => dout <= "001";
when "1000001100110110" => dout <= "001";
when "1000001100110000" => dout <= "001";
when "1000001101110000" => dout <= "001";
when "1000001110110000" => dout <= "001";
when "0011010000000000" => dout <= "000";
when "0011010100000000" => dout <= "000";
when "1111011011010000" => dout <= "001";
when "1111011000010110" => dout <= "001";
when "1111011000010000" => dout <= "001";
when "1111011001010000" => dout <= "001";
when "1111011010010000" => dout <= "001";
when "1111011111010000" => dout <= "001";
when "1111011100010110" => dout <= "001";
when "1111011100010000" => dout <= "001";
when "1111011101010000" => dout <= "001";
when "1111011110010000" => dout <= "001";
when "1010010000000000" => dout <= "000";
when "1010010100000000" => dout <= "000";
when "1010011000000000" => dout <= "000";
when "1010011100000000" => dout <= "000";
when "1010111000000000" => dout <= "000";
when "1010111100000000" => dout <= "000";
when "1010110000000000" => dout <= "000";
when "1010110100000000" => dout <= "000";
when "1010101000000000" => dout <= "000";
when "1010101100000000" => dout <= "000";
when "1111001000000000" => dout <= "000";
when "1111001100000000" => dout <= "000";
when "0110000000000000" => dout <= "000";
when "0110000100000000" => dout <= "000";
when "1100100000000000" => dout <= "000";
when "1100100100000000" => dout <= "000";
when "0110001000000000" => dout <= "000";
when "0110110000000000" => dout <= "000";
when "0110110100000000" => dout <= "000";
when "0110111000000000" => dout <= "000";
when "0110111100000000" => dout <= "000";
when "0000111100000000" => dout <= "000";
when "0110001100000000" => dout <= "000";
when "0110010000000000" => dout <= "000";
when "0110010100000000" => dout <= "000";
when "0110011000000000" => dout <= "000";
when "0110011100000000" => dout <= "000";
when "1000001000000000" => dout <= "000";
when "1101011000000000" => dout <= "000";
when "1111000100000000" => dout <= "000";
when "1100000000000000" => dout <= "000";
when "1100000100000000" => dout <= "000";
when others => dout <= "---";
end case;
end process;
end rtl;

25
common/CPU/cpu86/readme.txt Normal file
View File

@@ -0,0 +1,25 @@
This directory contains the synthesizable CPU86 (8088) processor VHDL source files.
File dependency order:
cpu86pack.vhd
cpu86instr.vhd
biufsm_fsm.vhd
a_table.vhd
d_table.vhd
n_table.vhd
r_table.vhd
m_table.vhd
formatter_struct.vhd
regshiftmux_regshift.vhd
biu_struct.vhd
dataregfile_rtl.vhd
segregfile_rtl.vhd
divider_rtl_ser.vhd
multiplier_rtl.vhd
alu_rtl.vhd
ipregister_rtl.vhd
datapath_struct.vhd
proc_rtl.vhd
cpu86_struct.vhd

305
common/CPU/cpu86/regshiftmux_regshift.vhd Normal file
View File

@@ -0,0 +1,305 @@
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY regshiftmux IS
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
flush_req : IN std_logic;
latchm : IN std_logic;
latcho : IN std_logic;
mux_addr : IN std_logic_vector (2 DOWNTO 0);
mux_data : IN std_logic_vector (3 DOWNTO 0);
mux_reg : IN std_logic_vector (2 DOWNTO 0);
nbreq : IN std_logic_vector (2 DOWNTO 0);
regplus1 : IN std_logic;
ldposplus1 : IN std_logic;
reset : IN std_logic;
irq : IN std_logic;
inta1 : IN std_logic; -- Added for ver 0.71
inta2_s : IN std_logic;
irq_type : IN std_logic_vector (1 DOWNTO 0);
instr : OUT instruction_type;
halt_instr : OUT std_logic;
lutbus : OUT std_logic_vector (15 DOWNTO 0);
reg1free : BUFFER std_logic;
reg1freed : BUFFER std_logic; -- Delayed version (1 clk) of reg1free
regnbok : OUT std_logic
);
END regshiftmux ;
architecture regshift of regshiftmux is
signal reg72_s : std_logic_vector(71 downto 0);
signal regcnt_s : std_logic_vector(3 downto 0); -- Note need possible 9 byte positions
signal ldpos_s : std_logic_vector(3 downto 0); -- redundant signal (=regcnt_s)
signal ireg_s : std_logic_vector(7 downto 0);
signal mod_s : std_logic_vector(1 downto 0);
signal rm_s : std_logic_vector(2 downto 0);
signal opcreg_s : std_logic_vector(2 downto 0);
signal opcdata_s: std_logic_vector(15 downto 0);
signal opcaddr_s: std_logic_vector(15 downto 0);
signal nbreq_s : std_logic_vector(2 downto 0); -- latched nbreq only for instr
signal flush_req1_s : std_logic; -- Delayed version of flush_req
signal flush_req2_s : std_logic; -- Delayed version of flush_req (address setup requires 2 clk cycle)
begin
instr.ireg <= ireg_s;
instr.xmod <= mod_s;
instr.rm <= rm_s;
instr.reg <= opcreg_s;
instr.data <= opcdata_s(7 downto 0)&opcdata_s(15 downto 8);
instr.disp <= opcaddr_s(7 downto 0)&opcaddr_s(15 downto 8);
instr.nb <= nbreq_s; -- use latched version
halt_instr <= '1' when ireg_s=HLT else '0';
-------------------------------------------------------------------------
-- reg counter (how many bytes available in pre-fetch queue)
-- ldpos (load position in queue, if MSB=1 then ignore parts of word)
-- Don't forget resource sharing during synthesis :-)
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
regcnt_s <= (others => '0'); -- wrap around after first pulse!
ldpos_s <= (others => '1');
flush_req1_s <= '0';
flush_req2_s <= '0';
elsif rising_edge(clk) then
flush_req1_s <= flush_req; -- delay 1 cycle
flush_req2_s <= flush_req1_s; -- delay 2 cycles
if flush_req2_s='1' then
regcnt_s <= (others => '0'); -- Update during Smaxws state
elsif latcho='1' then
regcnt_s <= regcnt_s - ('0'&nbreq);
elsif regplus1='1' and reg1freed='1' then
regcnt_s <= regcnt_s + '1';
end if;
if flush_req2_s='1' then
ldpos_s <= (others => '1'); -- Result in part of dbus loaded into queue
elsif latcho='1' then
ldpos_s <= ldpos_s - ('0'&nbreq);
elsif ldposplus1='1' and reg1freed='1' then
ldpos_s <= ldpos_s + '1';
end if;
end if;
end process;
reg1free <= '1' when ldpos_s/="1000" else '0'; -- Note maxcnt=9!!
process(reset,clk)
begin
if reset='1' then
reg1freed <= '1';
elsif rising_edge(clk) then
reg1freed <= reg1free;
end if;
end process;
regnbok <= '1' when (regcnt_s>='0'&nbreq) else '0'; -- regcnt must be >= nb required
lutbus <= reg72_s(71 downto 56); -- Only for opcode LUT decoder
-------------------------------------------------------------------------
-- Load 8 bits instruction into 72 bits prefetch queue (9 bytes)
-- Latched by latchm signal (from biufsm)
-- ldpos=0 means loading at 71 downto 64 etc
-- Shiftn is connected to nbreq
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
reg72_s <= NOP & X"0000000000000000"; --(others => '0');
elsif rising_edge(clk) then
if latchm='1' then
case ldpos_s is -- Load new data, shift in lsb byte first
when "0000" => reg72_s(71 downto 64) <= dbus_in;
when "0001" => reg72_s(63 downto 56) <= dbus_in;
when "0010" => reg72_s(55 downto 48) <= dbus_in;
when "0011" => reg72_s(47 downto 40) <= dbus_in;
when "0100" => reg72_s(39 downto 32) <= dbus_in;
when "0101" => reg72_s(31 downto 24) <= dbus_in;
when "0110" => reg72_s(23 downto 16) <= dbus_in;
when "0111" => reg72_s(15 downto 8) <= dbus_in;
when "1000" => reg72_s(7 downto 0) <= dbus_in;
when others => reg72_s <= reg72_s;
end case;
end if;
if latcho='1' then
case nbreq is -- remove nb byte(s) when latcho is active
when "001" => reg72_s <= reg72_s(63 downto 0) & "--------"; -- smaller synth results than "00000000"
when "010" => reg72_s <= reg72_s(55 downto 0) & "----------------";
when "011" => reg72_s <= reg72_s(47 downto 0) & "------------------------";
when "100" => reg72_s <= reg72_s(39 downto 0) & "--------------------------------";
when "101" => reg72_s <= reg72_s(31 downto 0) & "----------------------------------------";
when "110" => reg72_s <= reg72_s(23 downto 0) & "------------------------------------------------";
when others => reg72_s <= reg72_s;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Opcode Data
-- Note format LSB-MSB
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
opcdata_s <= (others => '0');
elsif rising_edge(clk) then
if latcho='1' then
case mux_data is
when "0000" => opcdata_s <= (others => '0'); -- Correct???
when "0001" => opcdata_s <= reg72_s(63 downto 56) & X"00";
when "0010" => opcdata_s <= reg72_s(63 downto 48);
when "0011" => opcdata_s <= reg72_s(55 downto 48) & X"00";
when "0100" => opcdata_s <= reg72_s(55 downto 40);
when "0101" => opcdata_s <= reg72_s(47 downto 40) & X"00";
when "0110" => opcdata_s <= reg72_s(47 downto 32);
when "0111" => opcdata_s <= reg72_s(39 downto 32) & X"00";
when "1000" => opcdata_s <= reg72_s(39 downto 24);
when others => opcdata_s <= "----------------"; -- generate Error?
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Opcode Address/Offset/Displacement
-- Format LSB, MSB!
-- Single Displacement byte sign extended
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
opcaddr_s <= (others => '0');
elsif rising_edge(clk) then
if inta2_s='1' then
opcaddr_s <= dbus_in & X"00"; -- Read 8 bits vector
elsif latcho='1' then
--if irq='1' then
if irq='1' or inta1='1' then -- added for ver 0.71
opcaddr_s <= "000000" & irq_type & X"00";
else
case mux_addr is
when "000" => opcaddr_s <= (others => '0'); -- Correct ????
when "001" => opcaddr_s <= reg72_s(63 downto 56) & reg72_s(63)& reg72_s(63)& reg72_s(63)& reg72_s(63)&
reg72_s(63)& reg72_s(63)& reg72_s(63)& reg72_s(63); -- MSB Sign extended
when "010" => opcaddr_s <= reg72_s(63 downto 48);
when "011" => opcaddr_s <= reg72_s(55 downto 48) & reg72_s(55)& reg72_s(55)& reg72_s(55)& reg72_s(55)&
reg72_s(55)& reg72_s(55)& reg72_s(55)& reg72_s(55); -- MSB Sign Extended
when "100" => opcaddr_s <= reg72_s(55 downto 40);
when "101" => opcaddr_s <= reg72_s(63 downto 56) & X"00"; -- No sign extend, MSB=0
when "110" => opcaddr_s <= X"0300"; -- INT3 type=3
when others => opcaddr_s <= X"0400"; -- INTO type=4
end case;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Opcode Register
-- Note : "11" is push segment reg[2]=0 reg[1..0]=reg
-- : Note reg[2]=0 if mux_reg=011
-------------------------------------------------------------------------
process(reset,clk)
begin
if reset='1' then
opcreg_s <= (others => '0');
elsif rising_edge(clk) then
if latcho='1' then
case mux_reg is
when "000" => opcreg_s <= (others => '0'); -- Correct ??
when "001" => opcreg_s <= reg72_s(61 downto 59);
when "010" => opcreg_s <= reg72_s(66 downto 64);
when "011" => opcreg_s <= '0' & reg72_s(68 downto 67); -- bit2 forced to 0
when "100" => opcreg_s <= reg72_s(58 downto 56);
when others => opcreg_s <= "---";
--assert FALSE report "**** Incorrect mux_reg in Opcode Regs Register" severity error;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- Opcode, Mod R/M Register, and latched nbreq!
-- Create fake xmod and rm if offset (addr_mux) is 1,2,5,6,7. In this case
-- there is no second opcode byte. The fake xmod and rm result in an
-- EA=Displacement.
-------------------------------------------------------------------------
process(reset,clk) -- ireg
begin
if reset='1' then
ireg_s <= NOP; -- default instr
mod_s <= (others => '0'); -- default mod
rm_s <= (others => '0'); -- default rm
nbreq_s <= "001"; -- single NOP
elsif rising_edge(clk) then
if latcho='1' then
if irq='1' or inta1='1' then -- force INT instruction, added for ver 0.71
ireg_s <= INT;
nbreq_s<= "000"; -- used in datapath to add to IP address
mod_s <= "00"; -- Fake mod (select displacement for int type
rm_s <= "110"; -- Fake rm
else
ireg_s <= reg72_s(71 downto 64);
nbreq_s<= nbreq;
if (mux_addr= "001" or mux_addr= "010" or mux_addr= "101"
or mux_addr= "110" or mux_addr= "111") then
mod_s <= "00"; -- Fake mod
rm_s <= "110"; -- Fake rm
else
mod_s <= reg72_s(63 downto 62);
rm_s <= reg72_s(58 downto 56);
end if;
end if;
end if;
end if;
end process;
end regshift;

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