mirror of
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SonSon: update to common sound chip
This commit is contained in:
Gyorgy Szombathelyi
parent
58e23d2405
commit
4dd702f4ef
@ -40,7 +40,7 @@
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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@ -245,13 +245,14 @@ set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
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set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
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set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
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set_global_assignment -name VHDL_FILE rtl/sonson_soundboard.vhd
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd
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set_global_assignment -name VHDL_FILE rtl/dpram.vhd
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set_global_assignment -name VHDL_FILE rtl/sprom.vhd
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set_global_assignment -name VHDL_FILE rtl/spram.vhd
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set_global_assignment -name VHDL_FILE ../../common/Sound/ym2149/YM2149.vhd
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set_global_assignment -name VHDL_FILE ../../common/Sound/ym2149/vol_table_array.vhd
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set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809i.v
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set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -1,329 +0,0 @@
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//
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// Copyright (c) MikeJ - Jan 2005
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// Copyright (c) 2016-2018 Sorgelig
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//
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// All rights reserved
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//
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// Redistribution and use in source and synthezised forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// Redistributions in synthesized form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// Neither the name of the author nor the names of other contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// BDIR BC MODE
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// 0 0 inactive
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// 0 1 read value
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// 1 0 write value
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// 1 1 set address
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//
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module YM2149
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(
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input CLK, // Global clock
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input CE, // PSG Clock enable
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input RESET, // Chip RESET (set all Registers to '0', active hi)
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input BDIR, // Bus Direction (0 - read , 1 - write)
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input BC, // Bus control
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input A8,
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input A9_L,
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input [7:0] DI, // Data In
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output [7:0] DO, // Data Out
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output [7:0] CHANNEL_A, // PSG Output channel A
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output [7:0] CHANNEL_B, // PSG Output channel B
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output [7:0] CHANNEL_C, // PSG Output channel C
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input SEL,
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input MODE,
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output [5:0] ACTIVE,
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input [7:0] IOA_in,
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output [7:0] IOA_out,
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input [7:0] IOB_in,
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output [7:0] IOB_out
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);
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assign ACTIVE = ~ymreg[7][5:0];
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assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff;
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assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff;
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reg [7:0] addr;
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reg [7:0] ymreg[16];
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wire cs = !A9_L & A8;
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// Write to PSG
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reg env_reset;
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always @(posedge CLK) begin
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if(RESET) begin
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ymreg <= '{default:0};
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ymreg[7] <= '1;
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addr <= '0;
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env_reset <= 0;
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end else begin
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env_reset <= 0;
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if(cs & BDIR) begin
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if(BC) addr <= DI;
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else if(!addr[7:4]) begin
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ymreg[addr[3:0]] <= DI;
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env_reset <= (addr == 13);
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end
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end
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end
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end
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// Read from PSG
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assign DO = dout;
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reg [7:0] dout;
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always_comb begin
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dout = 8'hFF;
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if(cs & ~BDIR & BC & !addr[7:4]) begin
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case(addr[3:0])
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0: dout = ymreg[0];
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1: dout = ymreg[1][3:0];
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2: dout = ymreg[2];
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3: dout = ymreg[3][3:0];
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4: dout = ymreg[4];
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5: dout = ymreg[5][3:0];
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6: dout = ymreg[6][4:0];
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7: dout = ymreg[7];
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8: dout = ymreg[8][4:0];
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9: dout = ymreg[9][4:0];
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10: dout = ymreg[10][4:0];
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11: dout = ymreg[11];
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12: dout = ymreg[12];
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13: dout = ymreg[13][3:0];
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14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
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15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
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endcase
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end
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end
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reg ena_div;
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reg ena_div_noise;
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// p_divider
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always @(posedge CLK) begin
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reg [3:0] cnt_div;
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reg noise_div;
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if(CE) begin
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ena_div <= 0;
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ena_div_noise <= 0;
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if(!cnt_div) begin
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cnt_div <= {SEL, 3'b111};
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ena_div <= 1;
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noise_div <= (~noise_div);
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if (noise_div) ena_div_noise <= 1;
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end else begin
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cnt_div <= cnt_div - 1'b1;
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end
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end
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end
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reg [2:0] noise_gen_op;
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// p_noise_gen
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always @(posedge CLK) begin
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reg [16:0] poly17;
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reg [4:0] noise_gen_cnt;
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if(CE) begin
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if (ena_div_noise) begin
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if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
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noise_gen_cnt <= 0;
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poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
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end else begin
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noise_gen_cnt <= noise_gen_cnt + 1'd1;
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end
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noise_gen_op <= {3{poly17[0]}};
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end
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end
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end
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wire [11:0] tone_gen_freq[1:3];
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assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
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assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
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assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
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reg [3:1] tone_gen_op;
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//p_tone_gens
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always @(posedge CLK) begin
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integer i;
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reg [11:0] tone_gen_cnt[1:3];
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if(CE) begin
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// looks like real chips count up - we need to get the Exact behaviour ..
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for (i = 1; i <= 3; i = i + 1) begin
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if(ena_div) begin
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if (tone_gen_freq[i]) begin
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if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
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tone_gen_cnt[i] <= 0;
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tone_gen_op[i] <= ~tone_gen_op[i];
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end else begin
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tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
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end
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end else begin
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tone_gen_op[i] <= ymreg[7][i];
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tone_gen_cnt[i] <= 0;
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end
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end
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end
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end
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end
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reg env_ena;
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wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
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//p_envelope_freq
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always @(posedge CLK) begin
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reg [15:0] env_gen_cnt;
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if(CE) begin
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env_ena <= 0;
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if(ena_div) begin
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if (env_gen_cnt >= env_gen_comp) begin
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env_gen_cnt <= 0;
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env_ena <= 1;
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end else begin
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env_gen_cnt <= (env_gen_cnt + 1'd1);
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end
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end
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end
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end
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reg [4:0] env_vol;
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wire is_bot = (env_vol == 5'b00000);
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wire is_bot_p1 = (env_vol == 5'b00001);
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wire is_top_m1 = (env_vol == 5'b11110);
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wire is_top = (env_vol == 5'b11111);
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always @(posedge CLK) begin
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reg env_hold;
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reg env_inc;
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// envelope shapes
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// C AtAlH
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// 0 0 x x \___
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//
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// 0 1 x x /___
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//
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// 1 0 0 0 \\\\
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//
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// 1 0 0 1 \___
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//
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// 1 0 1 0 \/\/
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// ___
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// 1 0 1 1 \
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//
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// 1 1 0 0 ////
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// ___
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// 1 1 0 1 /
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//
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// 1 1 1 0 /\/\
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//
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// 1 1 1 1 /___
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if(env_reset | RESET) begin
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// load initial state
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if(!ymreg[13][2]) begin // attack
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env_vol <= 5'b11111;
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env_inc <= 0; // -1
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end else begin
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env_vol <= 5'b00000;
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env_inc <= 1; // +1
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end
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env_hold <= 0;
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end
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else if(CE) begin
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if (env_ena) begin
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if (!env_hold) begin
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if (env_inc) env_vol <= (env_vol + 5'b00001);
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else env_vol <= (env_vol + 5'b11111);
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end
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// envelope shape control.
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if(!ymreg[13][3]) begin
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if(!env_inc) begin // down
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if(is_bot_p1) env_hold <= 1;
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end else if (is_top) env_hold <= 1;
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end else if(ymreg[13][0]) begin // hold = 1
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if(!env_inc) begin // down
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if(ymreg[13][1]) begin // alt
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if(is_bot) env_hold <= 1;
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end else if(is_bot_p1) env_hold <= 1;
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end else if(ymreg[13][1]) begin // alt
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if(is_top) env_hold <= 1;
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end else if(is_top_m1) env_hold <= 1;
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end else if(ymreg[13][1]) begin // alternate
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if(env_inc == 1'b0) begin // down
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if(is_bot_p1) env_hold <= 1;
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if(is_bot) begin
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env_hold <= 0;
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env_inc <= 1;
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end
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end else begin
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if(is_top_m1) env_hold <= 1;
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if(is_top) begin
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env_hold <= 0;
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env_inc <= 0;
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end
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end
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end
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end
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end
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end
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reg [5:0] A,B,C;
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always @(posedge CLK) begin
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A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}};
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B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}};
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C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
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end
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wire [7:0] volTable[64] = '{
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//YM2149
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8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04,
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8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13,
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8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47,
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8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
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//AY8910
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8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06,
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8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22,
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8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72,
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8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff
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};
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assign CHANNEL_A = volTable[A];
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assign CHANNEL_B = volTable[B];
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assign CHANNEL_C = volTable[C];
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endmodule
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@ -23,34 +23,6 @@ end sonson_soundboard;
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architecture SYN of sonson_soundboard is
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component YM2149
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port (
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CLK : in std_logic;
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CE : in std_logic;
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RESET : in std_logic;
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A8 : in std_logic := '1';
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A9_L : in std_logic := '0';
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BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write)
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BC : in std_logic; -- Bus control
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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CHANNEL_A : out std_logic_vector(7 downto 0);
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CHANNEL_B : out std_logic_vector(7 downto 0);
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CHANNEL_C : out std_logic_vector(7 downto 0);
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SEL : in std_logic;
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MODE : in std_logic;
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ACTIVE : out std_logic_vector(5 downto 0);
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IOA_in : in std_logic_vector(7 downto 0);
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IOA_out : out std_logic_vector(7 downto 0);
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IOB_in : in std_logic_vector(7 downto 0);
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IOB_out : out std_logic_vector(7 downto 0)
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);
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end component;
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COMPONENT mc6809i
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GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" );
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PORT
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@ -201,62 +173,42 @@ begin
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q => wram_do
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);
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ay83910_inst1: YM2149
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ay83910_inst1: work.YM2149
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port map (
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CLK => clk,
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CE => clk_en_snd,
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RESET => reset,
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A8 => '1',
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A9_L => not ay1_cs,
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BDIR => not cpu_rw,
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BC => not cpu_addr(0) or cpu_rw,
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DI => cpu_do,
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DO => ay1_do,
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CHANNEL_A => ay1_chan_a,
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CHANNEL_B => ay1_chan_b,
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CHANNEL_C => ay1_chan_c,
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ENA => clk_en_snd,
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RESET_L => not reset,
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I_A8 => '1',
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I_A9_L => not ay1_cs,
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I_BDIR => not cpu_rw,
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I_BC1 => not cpu_addr(0) or cpu_rw,
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I_DA => cpu_do,
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O_DA => ay1_do,
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SEL => '0',
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MODE => '1',
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O_AUDIO_L => audio_out_l,
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ACTIVE => open,
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I_IOA => (others => '0'),
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IOA_in => (others => '0'),
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IOA_out => open,
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IOB_in => (others => '0'),
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IOB_out => open
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I_IOB => (others => '0')
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);
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audio_out_l <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c;
|
||||
|
||||
ay83910_inst2: YM2149
|
||||
ay83910_inst2: work.YM2149
|
||||
port map (
|
||||
CLK => clk,
|
||||
CE => clk_en_snd,
|
||||
RESET => reset,
|
||||
A8 => '1',
|
||||
A9_L => not ay2_cs,
|
||||
BDIR => not cpu_rw,
|
||||
BC => not cpu_addr(0) or cpu_rw,
|
||||
DI => cpu_do,
|
||||
DO => ay2_do,
|
||||
CHANNEL_A => ay2_chan_a,
|
||||
CHANNEL_B => ay2_chan_b,
|
||||
CHANNEL_C => ay2_chan_c,
|
||||
ENA => clk_en_snd,
|
||||
RESET_L => not reset,
|
||||
I_A8 => '1',
|
||||
I_A9_L => not ay2_cs,
|
||||
I_BDIR => not cpu_rw,
|
||||
I_BC1 => not cpu_addr(0) or cpu_rw,
|
||||
I_DA => cpu_do,
|
||||
O_DA => ay2_do,
|
||||
|
||||
SEL => '0',
|
||||
MODE => '1',
|
||||
O_AUDIO_L => audio_out_r,
|
||||
|
||||
ACTIVE => open,
|
||||
I_IOA => (others => '0'),
|
||||
|
||||
IOA_in => (others => '0'),
|
||||
IOA_out => open,
|
||||
|
||||
IOB_in => (others => '0'),
|
||||
IOB_out => open
|
||||
I_IOB => (others => '0')
|
||||
);
|
||||
|
||||
audio_out_r <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c;
|
||||
|
||||
end SYN;
|
||||
Loading…
x
Reference in New Issue
Block a user