github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-19 17:27:59 +00:00
Code Issues Releases Wiki Activity

try other CPU (not needed)

Browse Source
This commit is contained in:
Gehstock 2018-12-25 00:07:31 +01:00
parent cde4060e1e
commit 4e2cce7647
9 changed files with 2191 additions and 138 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf
View File

@ -46,23 +46,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Centipede.sv
set_global_assignment -name VERILOG_FILE rtl/centipede.v
set_global_assignment -name VERILOG_FILE rtl/pf_ram.v
set_global_assignment -name VERILOG_FILE rtl/p6502.v
set_global_assignment -name VERILOG_FILE rtl/bc6502.v
set_global_assignment -name VERILOG_FILE rtl/addsub.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
# Pin & Location Assignments
# ==========================
@ -162,6 +145,27 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# end ENTITY(Centipede)
# ---------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Centipede.sv
set_global_assignment -name VERILOG_FILE rtl/centipede.v
set_global_assignment -name VERILOG_FILE rtl/pf_ram.v
set_global_assignment -name VERILOG_FILE rtl/p6502.v
set_global_assignment -name VERILOG_FILE rtl/bc6502.v
set_global_assignment -name VHDL_FILE rtl/t65/T65_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/t65/T65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/t65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/t65/T65.vhd
set_global_assignment -name VERILOG_FILE rtl/addsub.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pokey/POKEY.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pokey/matoro.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

21
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede.sv
View File

@ -46,7 +46,7 @@ localparam CONF_STR = {
"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"O5,Joystick Control,Normal,Upright;",
"T7,Reset;",
"V,v1.00.",`BUILD_DATE
"V,v1.20.",`BUILD_DATE
};
wire [31:0] status;
@ -55,7 +55,6 @@ wire [1:0] switches;
wire [9:0] kbjoy;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
//wire [7:0] joystick;
wire scandoubler_disable;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
@ -82,43 +81,41 @@ wire m_right = ~status[5] ? ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2] : ~kbjo
wire m_start1 = ~kbjoy[1];
wire m_start2 = ~kbjoy[2];
wire m_coin = ~kbjoy[3];
wire m_fire1 = ~kbjoy[0] & ~joystick_0[4] & ~joystick_1[4];// & ~joystick_0[4] & ~joystick_1[4];
wire m_fire2 = ~kbjoy[0] & ~joystick_0[5] & ~joystick_1[5];// & ~joystick_0[4] & ~joystick_1[4];
//wire l_coin = ~kbjoy[3];
wire l_coin, c_coin, r_coin = 1'b1;
wire c_coin = ~kbjoy[3];
wire l_coin, r_coin = 1'b1;
wire m_test = ~status[1];
wire m_slam = 1'b1;//generate Noise
wire m_cocktail = 1'b1;
wire [9:0] playerinput_i = { r_coin, c_coin, l_coin, m_test, m_cocktail, m_slam, m_start2, m_start1, m_fire1, m_fire2 };
//wire [9:0] playerinput_i = { m_coin, coin_c, coin_l, m_test, m_cocktail, m_slam, m_start, start2, fire2, m_fire };
centipede centipede(
.clk_100mhz(clk_100mhz),
.clk_12mhz(clk_12),
.reset(status[0] | status[7] | buttons[1]),
.playerinput_i(playerinput_i),
.playerinput_i({ r_coin, c_coin, l_coin, m_test, m_cocktail, m_slam, m_start2, m_start1, m_fire1, m_fire2 }),
.trakball_i(),
.joystick_i({m_right , m_left, m_down, m_up, m_right , m_left, m_down, m_up}),
.sw1_i(8'h54),
.sw2_i(8'b0),
.rgb_o({b,g,r}),
.rgb_o({ b,g,r}),
.hsync_o(hs),
.vsync_o(vs),
.hblank_o(hblank),
.vblank_o(vblank),
.audio_o(audio)
.audio_o(audio),
.audio2_o(audio2)
);
wire [3:0] audio;
wire [3:0] audio2;
dac #(
.msbi_g(15))
dac (
.clk_i(clk_24),
.res_n_i(1),
.dac_i({4{audio}}),
.dac_i({2{audio,audio2}}),
.dac_o(AUDIO_L)
);

4
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/build_id.v
View File

@ -1,2 +1,2 @@
`define BUILD_DATE "181220"
`define BUILD_TIME "180518"
`define BUILD_DATE "181224"
`define BUILD_TIME "230222"

269
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v
View File

@ -15,9 +15,9 @@
// do some debugging of the pokey code I was using.
//
//`define async_lr
`define orig_phi0
`define T65
`define no_colormap
`define MILL
module centipede(
input clk_100mhz,
input clk_12mhz,
@ -34,7 +34,8 @@ module centipede(
output vsync_o,
output hblank_o,
output vblank_o,
output [3:0] audio_o
output [7:0] audio_o,
output [7:0] audio2_o
);
//
@ -48,7 +49,7 @@ module centipede(
wire rom_n;
wire ram0_n;
wire steerclr_n, watchdog_n, out0_n, irqres_n;
wire pokey_n, swrd_n, pf_n;
wire pokey_n, pokey2_n, swrd_n, pf_n;
wire coloram_n, ea_read_n, ea_ctrl_n, ea_addr_n;
wire in0_n, in1_n;
@ -66,7 +67,7 @@ module centipede(
reg irq;
wire rw_n;
wire [15:0] ab;
wire [23:0] ab;
wire [7:0] db_in;
wire [7:0] db_out;
@ -128,11 +129,7 @@ module centipede(
reg [1:0] gry;
wire [1:0] y;
`ifdef async_lr
wire [1:0] mr;
`else
reg [1:0] mr;
`endif
wire [7:0] line_ram_addr;
reg [1:0] line_ram[0:255];
@ -179,7 +176,7 @@ module centipede(
wire [3:0] rama;
wire [7:0] audio;
wire [7:0] audio2;
//
wire mob_n;
wire blank_clk;
@ -265,52 +262,48 @@ vprom(
.q(vprom_out)
);
always @(posedge s_256h_n or posedge reset)
if (reset)
vprom_reg <= 0;
else
vprom_reg <= vprom_out;
assign vsync = vprom_reg[0];
assign vreset = vprom_reg[2];
assign hs_set = reset | ~s_256h_n;
always @(posedge s_256h_n or posedge reset)
if (reset)
vprom_reg <= 0;
else
vprom_reg <= vprom_out;
assign vsync = vprom_reg[0];
assign vreset = vprom_reg[2];
assign hs_set = reset | ~s_256h_n;
always @(posedge s_32h or posedge hs_set)
if (hs_set)
hs <= 1;
else
hs <= s_64h;
always @(posedge s_32h or posedge hs_set)
if (hs_set)
hs <= 1;
else
hs <= s_64h;
assign hsync_reset = reset | hs;
assign hsync_reset = reset | hs;
always @(posedge s_8h or posedge hsync_reset)
if (hsync_reset)
hsync <= 0;
else
hsync <= s_32h;
always @(posedge s_8h or posedge hsync_reset)
if (hsync_reset)
hsync <= 0;
else
hsync <= s_32h;
//
always @(posedge s_6mhz)
if (reset)
coloren <= 0;
else
coloren <= s_256hd;
always @(posedge s_6mhz)
if (reset)
coloren <= 0;
else
coloren <= s_256hd;
assign s_6_12 = ~(s_6mhz & s_12mhz);
reg xxx1;
assign s_6_12 = ~(s_6mhz & s_12mhz);
reg xxx1;
always @(posedge s_6_12)
if (reset)
xxx1 <= 0;
else
xxx1 <= coloren;
always @(posedge s_6_12)
if (reset)
xxx1 <= 0;
else
xxx1 <= coloren;
assign vblank = vprom_reg[3];
assign hblank = (~xxx1 & ~coloren);
assign vblank = vprom_reg[3];
assign hblank = (~xxx1 & ~coloren);
sprom #(
.init_file("./roms/136001-prog.hex"),
.widthad_a(13),
@ -344,22 +337,7 @@ ram(
// assign irq_n = ~irq;
assign irq_n = irq;
`ifdef orig_phi0
always @(posedge s_1h)
if (reset)
phi0a <= 1'b0;
else
case ({(pf_n | s_4h), s_2h})
2'b00: phi0a <= phi0a;
2'b01: phi0a <= 1'b0;
2'b10: phi0a <= 1'b1;
2'b11: phi0a <= ~phi0a;
endcase
assign phi0 = ~phi0a;
assign pac_n = ~phi0a;
`else
always @(posedge s_1h or posedge reset)
if (reset)
phi0a <= 1'b0;
@ -368,7 +346,7 @@ ram(
assign phi0 = ~phi0a;
assign pac_n = ~phi0a;
`endif
// watchdog?
always @(posedge s_12mhz)
@ -388,21 +366,43 @@ ram(
assign mpu_clk = s_6mhz;
assign mpu_reset_n = ~mpu_reset;
`ifdef T65
assign phi2 = ~phi0;
T65 T65(
.Mode("00"),
.Res_n(mpu_reset_n),
.Enable(1'b1),
.Clk(phi0),
.Rdy(1'b1),
.Abort_n(1'b1),
.IRQ_n(irq_n),
.NMI_n(1'b1),
.SO_n(1'b1),
.R_W_n(rw_n),
.A(ab),
.DI(db_in[7:0]),
.DO(db_out[7:0])
);
`else
p6502 p6502(
.clk(mpu_clk),
.reset_n(mpu_reset_n),
.nmi(1'b1),
.irq(irq_n),
.so(1'b0),
.rdy(1'b1),
.phi0(phi0),
.phi2(phi2),
.rw_n(rw_n),
.a(ab),
.din(db_in[7:0]),
.dout(db_out[7:0])
);
p6502 p6502(
.clk(mpu_clk),
.reset_n(mpu_reset_n),
.nmi(1'b1),
.irq(irq_n),
.so(1'b0),
.rdy(1'b1),
.phi0(phi0),
.phi2(phi2),
.rw_n(rw_n),
.a(ab[15:0]),
.din(db_in[7:0]),
.dout(db_out[7:0])
);
`endif
// Address Decoder
assign write_n = ~(phi2 & ~rw_n);
@ -440,6 +440,7 @@ ram(
assign coloram_n = (adecode[5] | ab[9])/* | pac_n*/;
assign pokey_n = adecode[4];
assign pokey2_n = adecode[3];
assign in0_n = adecode[3] | ab[1];
assign in1_n = adecode[3] | ~ab[1];
@ -622,15 +623,13 @@ ram(
always @(posedge s_6mhz)
line_ram[line_ram_addr] <= y;
`ifdef async_lr
assign mr = line_ram[line_ram_addr];
`else
always @(posedge s_12mhz)
if (reset)
mr <= 0;
else
mr <= line_ram[line_ram_addr];
`endif
always @(posedge s_6mhz_n)
if (reset)
@ -731,7 +730,7 @@ sprom #(
assign db_in =
~rom_n ? rom_out :
~ram0_n ? ram_out :
~coloram_n ? { 4'b0, coloram_out } :
~coloram_n ? { 4'b0, coloram_rgbi } :
~pframrd_n ? pf_out[7:0] :
~ea_read_n ? hs_out :
~in0_n ? playerin_out :
@ -974,7 +973,21 @@ POKEY POKEY(
.audio(audio),
.clk(clk_100mhz)
);
`ifdef MILL
POKEY POKEY2(
.Din(db_out[7:0]),
.Dout(),
.A(ab[3:0]),
.P(8'b0),
.phi2(phi2),
.readHighWriteLow(rw_n),
.cs0Bar(pokey2_n),
.audio(audio2),
.clk(clk_100mhz)
);
`endif
// Video output circuitry
// The video output circuit receives motion object, playfield, address and data inputs
@ -997,16 +1010,16 @@ POKEY POKEY(
assign rama_sel = { coloram_n, gry0_or_1 };
assign rama =
(rama_sel == 2'b00) ? { ab[3:0] } :
(rama_sel == 2'b01) ? { ab[3:0] } :
(rama_sel == 2'b10) ? { {gry0_or_1, 1'b1}, area[1:0] } :
(rama_sel == 2'b11) ? { {gry0_or_1, 1'b1}, gry[1:0] } :
4'b0;
// assign rama =
// (rama_sel == 2'b00) ? { ab[3:0] } :
// (rama_sel == 2'b01) ? { ab[3:0] } :
// (rama_sel == 2'b10) ? { {gry0_or_1, 1'b1}, area[1:0] } :
// (rama_sel == 2'b11) ? { {gry0_or_1, 1'b1}, gry[1:0] } :
// 4'b0;
// assign rama = gry0_or_1 ?
// { {gry0_or_1, 1'b1}, gry[1:0] } :
// { {gry0_or_1, 1'b1}, area[1:0] };
assign rama = gry0_or_1 ?
{ {gry0_or_1, 1'b1}, gry[1:0] } :
{ {gry0_or_1, 1'b1}, area[1:0] };
dpram #(
@ -1023,21 +1036,63 @@ color_ram(
.data_b_o(coloram_rgbi)
);
assign rgb_o = gry == 2'b00 & area[1:0] == 2'b00 ? 9'b000_000_000 :
gry == 2'b00 & area[1:0] == 2'b01 ? 9'b000_000_111 :
gry == 2'b00 & area[1:0] == 2'b10 ? 9'b000_111_000 :
gry == 2'b00 & area[1:0] == 2'b11 ? 9'b111_000_000 :
gry == 2'b01 ? 9'b000_000_111 :
gry == 2'b10 ? 9'b000_111_000 :
gry == 2'b11 ? 9'b111_000_000 : 0;
// output to the top level
`ifdef no_colormap
// bbb_ggg_rrr
assign rgb_o =
//hack
//`define pf_only
//`define mo_only
`define pf_and_mo
`ifdef pf_only
area[1:0] == 2'b00 ? 9'b000_000_000 :
area[1:0] == 2'b01 ? 9'b000_000_111 :
area[1:0] == 2'b10 ? 9'b000_111_000 :
area[1:0] == 2'b11 ? 9'b111_000_000 :
`endif
`ifdef mo_only
gry == 2'b00 ? 9'b000_000_111 :
gry == 2'b01 ? 9'b000_111_000 :
gry == 2'b10 ? 9'b111_000_000 :
gry == 2'b11 ? 9'b111_111_111 :
`endif
`ifdef pf_and_mo
gry == 2'b00 & area[1:0] == 2'b00 ? 9'b000_000_000 :
gry == 2'b00 & area[1:0] == 2'b01 ? 9'b000_000_111 :
gry == 2'b00 & area[1:0] == 2'b10 ? 9'b000_111_000 :
gry == 2'b00 & area[1:0] == 2'b11 ? 9'b111_000_000 :
gry == 2'b01 ? 9'b000_000_111 :
gry == 2'b10 ? 9'b000_111_000 :
gry == 2'b11 ? 9'b111_000_000 :
`endif
0;
`else
assign rgb_o =
rgbi == 4'b0000 ? 9'b000_000_000 ://Player
rgbi == 4'b0001 ? 9'b000_000_100 :
rgbi == 4'b0010 ? 9'b000_100_000 :
rgbi == 4'b0011 ? 9'b000_100_100 :
rgbi == 4'b0100 ? 9'b100_000_000 :
rgbi == 4'b0101 ? 9'b100_000_100 :
rgbi == 4'b0110 ? 9'b100_100_000 :
rgbi == 4'b0111 ? 9'b100_100_100 :
rgbi == 4'b1000 ? 9'b000_000_000 :
rgbi == 4'b1001 ? 9'b000_000_111 :
rgbi == 4'b1010 ? 9'b000_111_000 :
rgbi == 4'b1011 ? 9'b000_111_111 :
rgbi == 4'b1100 ? 9'b111_000_000 :
rgbi == 4'b1101 ? 9'b111_000_111 :
rgbi == 4'b1110 ? 9'b111_111_000 :
rgbi == 4'b1111 ? 9'b111_111_111 :
0;
`endif
assign sync_o = comp_sync;
assign hsync_o = hsync;
assign vsync_o = vsync;
assign audio_o = audio ;
`ifdef MILL
assign audio2_o = audio2 ;
`endif
assign hblank_o = hblank;
assign vblank_o = vblank;

564
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65.vhd Normal file
View File

@ -0,0 +1,564 @@
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
--if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
-- P(Flag_B) <= '1';
--end if;
--if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
-- P(Flag_I) <= '1';
-- P(Flag_B) <= B_o;
--end if;
-- B=1 always on the 6502
P(Flag_B) <= '1';
if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
if MCycle = "011" then
-- B=0 in *copy* of P pushed onto the stack
P(Flag_B) <= '0';
elsif MCycle = "100" then
P(Flag_I) <= '1';
end if;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;

260
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_ALU.vhd Normal file
View File

@ -0,0 +1,260 @@
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
begin
C := P_In(Flag_C) or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op(3 downto 0) is
when "0000" =>
-- ORA
Q_t := BusA or BusB;
when "0001" =>
-- AND
Q_t := BusA and BusB;
when "0010" =>
-- EOR
Q_t := BusA xor BusB;
when "0011" =>
-- ADC
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when "0101" | "1101" =>
-- LDA
when "0110" =>
-- CMP
P_Out(Flag_C) <= SBC_C;
when "0111" =>
-- SBC
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when "1000" =>
-- ASL
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when "1001" =>
-- ROL
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when "1010" =>
-- LSR
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1011" =>
-- ROR
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1100" =>
-- BIT
P_Out(Flag_V) <= BusB(6);
when "1110" =>
-- DEC
Q_t := std_logic_vector(unsigned(BusA) - 1);
when "1111" =>
-- INC
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
end case;
case Op(3 downto 0) is
when "0011" =>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when "0110" | "0111" =>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when "0100" =>
when "1100" =>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;

1052
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_MCode.vhd Normal file
View File

File diff suppressed because it is too large Load Diff

117
Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/t65/T65_Pack.vhd Normal file
View File

@ -0,0 +1,117 @@
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;

4
Arcade_MiST/Konami Classic/ReadMe.txt Normal file
View File

@ -0,0 +1,4 @@
Games that should work on this Hardware
Rally X
Tutankhm
RocnRope