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Change Joystick Controls
This commit is contained in:
Gehstock
parent
a42e87b2c2
commit
cde4060e1e
@ -1,54 +0,0 @@
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{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Clock multiplexers are found and protected" { } { } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "*" { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
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Binary file not shown.
@ -44,7 +44,7 @@ localparam CONF_STR = {
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"Centipede;;",
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"O1,Test,off,on;",
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"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
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"O5,Joystick Control,Upright,Normal;",
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"O5,Joystick Control,Normal,Upright;",
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"T7,Reset;",
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"V,v1.00.",`BUILD_DATE
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};
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@ -75,15 +75,16 @@ pll pll
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.c4(clk_100mhz)
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);
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wire m_up = status[5] ? ~kbjoy[6] & ~joystick_0[1] & ~joystick_1[1] : ~kbjoy[4] & ~joystick_0[3] & ~joystick_1[3];
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wire m_down = status[5] ? ~kbjoy[7] & ~joystick_0[0] & ~joystick_1[0] : ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2];
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wire m_left = status[5] ? ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2] : ~kbjoy[6] & ~joystick_0[1] & ~joystick_1[1];
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wire m_right = status[5] ? ~kbjoy[4] & ~joystick_0[3] & ~joystick_1[3] : ~kbjoy[7] & ~joystick_0[0] & ~joystick_1[0];
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wire m_up = ~status[5] ? ~kbjoy[7] & ~joystick_0[0] & ~joystick_1[0] : ~kbjoy[4] & ~joystick_0[3] & ~joystick_1[3];
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wire m_down = ~status[5] ? ~kbjoy[6] & ~joystick_0[1] & ~joystick_1[1] : ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2];
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wire m_left = ~status[5] ? ~kbjoy[4] & ~joystick_0[3] & ~joystick_1[3] : ~kbjoy[6] & ~joystick_0[1] & ~joystick_1[1];
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wire m_right = ~status[5] ? ~kbjoy[5] & ~joystick_0[2] & ~joystick_1[2] : ~kbjoy[7] & ~joystick_0[0] & ~joystick_1[0];
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wire m_start1 = ~kbjoy[1];
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wire m_start2 = ~kbjoy[2];
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wire m_coin = ~kbjoy[3];
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wire m_fire1 = ~kbjoy[0] & ~joystick_0[4] & ~joystick_1[4];// & ~joystick_0[4] & ~joystick_1[4];
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wire m_fire2 = ~kbjoy[0] & ~joystick_0[5] & ~joystick_1[5];// & ~joystick_0[4] & ~joystick_1[4];
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wire m_start2 = 1'b1;
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wire m_start1 = ~kbjoy[3];//ESC
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//wire l_coin = ~kbjoy[3];
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wire l_coin, c_coin, r_coin = 1'b1;
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wire m_test = ~status[1];
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@ -1,2 +1,2 @@
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`define BUILD_DATE "181218"
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`define BUILD_TIME "200200"
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`define BUILD_DATE "181220"
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`define BUILD_TIME "180518"
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Binary file not shown.
@ -49,14 +49,12 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/ZigZag_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/ZigZag.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_sprite.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_clut.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
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set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
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set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
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@ -42,7 +42,7 @@ module ZigZag_MiST
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localparam CONF_STR = {
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"ZigZag;;",
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"O2,Joystick Control,Upright,Normal;",
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"O2,Joystick Control,Normal,Upright;",
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"O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
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"T6,Reset;",
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"V,v1.10.",`BUILD_DATE
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@ -73,15 +73,18 @@ pll pll
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.c3(clk_6)
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);
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wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
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wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2];
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wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1];
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wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0];
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wire m_up = ~status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
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wire m_down = ~status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2];
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wire m_left = ~status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1];
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wire m_right = ~status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0];
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wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4];
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wire m_start1 = kbjoy[1];
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wire m_start2 = kbjoy[2];
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wire m_coin = kbjoy[3];
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wire m_skip = kbjoy[9];
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ZigZag ZigZag
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(
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@ -1,2 +1,2 @@
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`define BUILD_DATE "181220"
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`define BUILD_TIME "145810"
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`define BUILD_TIME "173859"
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@ -1,24 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all,ieee.numeric_std.all;
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entity mc_clut is
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port (
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clk : in std_logic;
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addr : in std_logic_vector(4 downto 0);
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data : out std_logic_vector(7 downto 0)
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);
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end entity;
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architecture prom of mc_clut is
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type rom is array(0 to 31) of std_logic_vector(7 downto 0);
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signal rom_data: rom := (
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X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38",X"00",X"F0",X"15",X"1F",X"00",X"F6",X"06",X"07",
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X"00",X"91",X"07",X"F6",X"00",X"F0",X"FE",X"07",X"00",X"38",X"07",X"FE",X"00",X"07",X"3F",X"FE");
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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data <= rom_data(to_integer(unsigned(addr)));
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end if;
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end process;
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end architecture;
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@ -34,11 +34,16 @@ architecture RTL of MC_COL_PAL is
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signal W_COL_ROM_DO : std_logic_vector(7 downto 0);
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begin
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clut : entity work.mc_clut
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clut : entity work.sprom
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generic map (
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init_file => "./Rom/col.hex",
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widthad_a => 5,
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width_a => 8)
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port map (
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CLK => I_CLK_6M,
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ADDR => I_COL(2 downto 0) & I_VID(1 downto 0),
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DATA => W_COL_ROM_DO
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address => I_COL(2 downto 0) & I_VID(1 downto 0),
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clock => I_CLK_6M,
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q => W_COL_ROM_DO
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);
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--- VID OUT --------------------------------------------------------
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@ -1,90 +0,0 @@
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------------------------------------------------------------------------------
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-- FPGA MOONCRESTA STARS
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--
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-- Version : 2.00
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--
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-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
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--
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-- Important !
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--
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-- This program is freeware for non-commercial use.
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-- The author does not guarantee this program.
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-- You can use this at your own risk.
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity MC_STARS is
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port (
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I_CLK_18M : in std_logic;
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I_CLK_6M : in std_logic;
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I_H_FLIP : in std_logic;
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I_V_SYNC : in std_logic;
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I_8HF : in std_logic;
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I_256HnX : in std_logic;
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I_1VF : in std_logic;
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I_2V : in std_logic;
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I_STARS_ON : in std_logic;
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I_STARS_OFFn : in std_logic;
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O_R : out std_logic_vector(1 downto 0);
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O_G : out std_logic_vector(1 downto 0);
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O_B : out std_logic_vector(1 downto 0);
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O_NOISE : out std_logic
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);
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end;
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architecture RTL of MC_STARS is
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signal CLK_1C : std_logic := '0';
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signal W_2D_Qn : std_logic := '0';
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signal W_3B : std_logic := '0';
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signal noise : std_logic := '0';
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signal W_2A : std_logic := '0';
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signal W_4P : std_logic := '0';
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signal CLK_1AB : std_logic := '0';
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signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0');
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signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0');
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begin
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O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
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O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
|
||||
O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
|
||||
|
||||
CLK_1C <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
|
||||
CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
|
||||
W_3B <= W_2D_Qn xor W_1AB_Q(4);
|
||||
|
||||
W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
|
||||
W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
|
||||
|
||||
O_NOISE <= noise ;
|
||||
|
||||
process(I_2V)
|
||||
begin
|
||||
if rising_edge(I_2V) then
|
||||
noise <= W_2D_Qn;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK_1C, I_V_SYNC)
|
||||
begin
|
||||
if(I_V_SYNC = '1') then
|
||||
W_1C_Q <= (others => '0');
|
||||
elsif rising_edge(CLK_1C) then
|
||||
W_1C_Q <= W_1C_Q(0) & '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(CLK_1AB, I_STARS_ON)
|
||||
begin
|
||||
if(I_STARS_ON = '0') then
|
||||
W_1AB_Q <= (others => '0');
|
||||
W_2D_Qn <= '1';
|
||||
elsif rising_edge(CLK_1AB) then
|
||||
W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
|
||||
W_2D_Qn <= not W_1AB_Q(15);
|
||||
end if;
|
||||
end process;
|
||||
end RTL;
|
||||
Loading…
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Reference in New Issue
Block a user