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Code Issues Releases Wiki Activity

Midway8080: move to common MiST components, add 15kHz and YPbPr support

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This commit is contained in:
Gyorgy Szombathelyi 2019-06-03 19:57:31 +02:00
parent 6402124f90
commit 59dba0f893
18 changed files with 330 additions and 1287 deletions
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8
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/Midway8080.qsf
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@ -115,11 +115,13 @@ set_global_assignment -name SEARCH_PATH src/platform/midway8080/ -tag from_archi
set_global_assignment -name SEARCH_PATH src/platform/midway8080/invaders/ -tag from_archive
set_global_assignment -name SEARCH_PATH src/platform/midway8080/invaders/roms/ -tag from_archive
set_global_assignment -name SEARCH_PATH src/target/mist/ -tag from_archive
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/output_files/vid.stp
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name VHDL_FILE src/mist/pll27.vhd
set_global_assignment -name VERILOG_FILE src/mist/ps2_intf.v
set_global_assignment -name VERILOG_FILE src/mist/osd.v
set_global_assignment -name VERILOG_FILE src/mist/keyboard.v
set_global_assignment -name VHDL_FILE src/Z80.vhd
set_global_assignment -name VERILOG_FILE src/mist/user_io.v
set_global_assignment -name VHDL_FILE src/mist/target_top.vhd
set_global_assignment -name VHDL_FILE src/mist/target_pkg.vhd
set_global_assignment -name VHDL_FILE src/mist/sigma_delta_dac.vhd
@ -135,7 +137,6 @@ set_global_assignment -name VHDL_FILE src/sprite_pkg.vhd
set_global_assignment -name VHDL_FILE src/spram.vhd
set_global_assignment -name VHDL_FILE src/Sound.vhd
set_global_assignment -name VHDL_FILE src/project_pkg.vhd
set_global_assignment -name QIP_FILE src/pllclk_ez.qip
set_global_assignment -name VHDL_FILE src/platform_variant_pkg.vhd
set_global_assignment -name VHDL_FILE src/platform_pkg.vhd
set_global_assignment -name VHDL_FILE src/platform.vhd
@ -160,5 +161,4 @@ set_global_assignment -name VHDL_FILE src/T80.vhd
set_global_assignment -name VHDL_FILE src/T80_ALU.vhd
set_global_assignment -name VHDL_FILE src/T80_Reg.vhd
set_global_assignment -name VHDL_FILE src/T80_MCode.vhd
set_global_assignment -name QIP_FILE src/mist/pll27.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

126
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/Midway8080.sdc Normal file
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@ -0,0 +1,126 @@
## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {VGA_*}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

8
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/readme.txt
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@ -2,8 +2,14 @@ Midway 8080 Arcade Platform for Mist FPGA
- with OSD
- Keyboard/Joystick Support
- only VGA Supported
- 15kHz RGB/VGA/YPbPr Supported
Controls:
-- ESC or Button C : Coin
-- 1, 2 or Button Start : Start
-- SPACE or Button A : Fire
-- LEFT, RIGHT : Move
Following Games currently working:

6
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/InputMapper.VHDL
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@ -56,11 +56,11 @@ begin
jamma_v(0).d(1) := jamma.p(2).start;
jamma_v(0).d(2) := jamma.p(1).start;
jamma_v(0).d(4) := jamma.p(1).button(1);
jamma_v(1).d(4) := jamma.p(1).button(1);
jamma_v(1).d(4) := jamma.p(2).button(1);
jamma_v(0).d(5) := jamma.p(1).left;
jamma_v(1).d(5) := jamma.p(1).left;
jamma_v(1).d(5) := jamma.p(2).left;
jamma_v(0).d(6) := jamma.p(1).right;
jamma_v(1).d(6) := jamma.p(1).right;
jamma_v(1).d(6) := jamma.p(2).right;
-- map the dipswitches
keybd_v(1).d(3 downto 0) := dips(3 downto 0);

31
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/Sound.vhd
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@ -39,8 +39,8 @@ architecture SYN of Sound is
-- Signal Declarations
-- audio module clock
signal clk_10M : std_logic;
signal clk_5M : std_logic;
signal clk_10M : std_logic;
-- port latches
signal s1_r : std_logic_vector(5 downto 0);
@ -73,38 +73,13 @@ begin
end if;
end process;
-- apparently the audio module wants a 10MHz clock
process (sysClk, reset)
subtype count_t is integer range 0 to CLK_MHz/5;
variable count : count_t := 0;
begin
if reset = '1' then
count := 0;
clk_10M <= '0';
clk_5M <= '0';
elsif rising_edge(sysClk) then
clk_10M <= '0';
clk_5M <= '0';
if count = count_t'high/2 then
clk_10M <= '1';
count := count + 1;
elsif count = count_t'high then
clk_10M <= '1';
clk_5M <= '1';
count := 0;
else
count := count + 1;
end if;
end if;
end process;
-- can use anything suitable
snd_clk <= clk_5M;
snd_clk <= sysClk;
audio_inst : invaders_audio
port map
(
Clk => clk_10M,
Clk => sysClk,
S1 => s1_r,
S2 => s2_r,
Aud => snd_data_s

2
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/invaders_audio.vhd
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@ -130,7 +130,7 @@ begin
begin
wait until rising_edge(Clk);
Clk7680_ena <= '0';
if ClkDiv = 1277 then
if ClkDiv = 781 then
Clk7680_ena <= '1';
ClkDiv <= (others => '0');
else

191
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/mist/osd.v
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@ -1,191 +0,0 @@
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input pclk,
// SPI interface
input sck,
input ss,
input sdi,
// VGA signals coming from core
input [5:0] red_in,
input [5:0] green_in,
input [5:0] blue_in,
input hs_in,
input vs_in,
// enable scanlines
input scanline_ena_h,
// VGA signals going to video connector
output [5:0] red_out,
output [5:0] green_out,
output [5:0] blue_out,
output hs_out,
output vs_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd1;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg [7:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [10:0] bcnt;
reg osd_enable;
reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge sck, posedge ss) begin
if(ss == 1'b1) begin
cnt <= 5'd0;
bcnt <= 11'd0;
end else begin
sbuf <= { sbuf[6:0], sdi};
// 0:7 is command, rest payload
if(cnt < 15)
cnt <= cnt + 4'd1;
else
cnt <= 4'd8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], sdi};
// lower three command bits are line address
bcnt <= { sbuf[1:0], sdi, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100)
osd_enable <= sdi;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], sdi};
bcnt <= bcnt + 11'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg hsD, hsD2;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
reg scanline = 0;
always @(posedge pclk) begin
// bring hsync into local clock domain
hsD <= hs_in;
hsD2 <= hsD;
// falling edge of hs_in
if(!hsD && hsD2) begin
h_cnt <= 10'd0;
hs_high <= h_cnt;
scanline <= ~scanline;
end
// rising edge of hs_in
else if(hsD && !hsD2) begin
h_cnt <= 10'd0;
hs_low <= h_cnt;
end
else
h_cnt <= h_cnt + 10'd1;
end
// vertical counter
reg [9:0] v_cnt;
reg vsD, vsD2;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
always @(posedge hs_in) begin
// bring vsync into local clock domain
vsD <= vs_in;
vsD2 <= vsD;
// falling edge of vs_in
if(!vsD && vsD2) begin
v_cnt <= 10'd0;
vs_high <= v_cnt;
end
// rising edge of vs_in
else if(vsD && !vsD2) begin
v_cnt <= 10'd0;
vs_low <= v_cnt;
end
else
v_cnt <= v_cnt + 10'd1;
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
reg h_osd_active, v_osd_active;
always @(posedge pclk) begin
if(hs_in != hs_pol) begin
if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
if(h_cnt == h_osd_end) h_osd_active <= 1'b0;
end
if(vs_in != vs_pol) begin
if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
if(v_cnt == v_osd_end) v_osd_active <= 1'b0;
end
end
wire osd_de = osd_enable && h_osd_active && v_osd_active;
wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register
wire [6:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_pixel = osd_byte[osd_vcnt[3:1]];
reg [7:0] osd_byte;
always @(posedge pclk)
osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
wire [2:0] osd_color = OSD_COLOR;
wire [5:0] red_t = (scanline && scanline_ena_h)?{1'b0, red_in[5:1]}: red_in;
wire [5:0] green_t = (scanline && scanline_ena_h)?{1'b0, green_in[5:1]}: green_in;
wire [5:0] blue_t = (scanline && scanline_ena_h)?{1'b0, blue_in[5:1]}: blue_in;
assign red_out = !osd_de?red_t: {osd_pixel, osd_pixel, osd_color[2], red_t[5:3] };
assign green_out = !osd_de?green_t:{osd_pixel, osd_pixel, osd_color[1], green_t[5:3]};
assign blue_out = !osd_de?blue_t: {osd_pixel, osd_pixel, osd_color[0], blue_t[5:3] };
assign hs_out = hs_in;
assign vs_out = vs_in;
endmodule

4
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27.qip
View File

@ -1,6 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll27.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll27_inst.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll27.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll27.ppf"]

100
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27.vhd
View File

@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Web Edition
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@ -44,8 +44,7 @@ ENTITY pll27 IS
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC
c1 : OUT STD_LOGIC
);
END pll27;
@ -56,10 +55,9 @@ ARCHITECTURE SYN OF pll27 IS
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
@ -74,10 +72,6 @@ ARCHITECTURE SYN OF pll27 IS
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
@ -135,32 +129,26 @@ ARCHITECTURE SYN OF pll27 IS
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c0 <= sub_wire2;
c2 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 13500,
clk0_divide_by => 9,
clk0_duty_cycle => 50,
clk0_multiply_by => 7,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_divide_by => 9,
clk1_duty_cycle => 50,
clk1_multiply_by => 20,
clk1_multiply_by => 8,
clk1_phase_shift => "0",
clk2_divide_by => 27,
clk2_duty_cycle => 50,
clk2_multiply_by => 40,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
@ -195,7 +183,7 @@ BEGIN
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
@ -212,7 +200,7 @@ BEGIN
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
inclk => sub_wire4,
clk => sub_wire0
);
@ -239,15 +227,12 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "13500"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.014000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "6.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@ -269,33 +254,25 @@ END SYN;
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "16"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.01400000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "6.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@ -319,32 +296,25 @@ END SYN;
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "13500"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "40"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@ -378,7 +348,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
@ -397,18 +367,16 @@ END SYN;
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll27_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

6
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/mist/pll27_inst.vhd
View File

@ -1,6 +0,0 @@
pll27_inst : pll27 PORT MAP (
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
c2 => c2_sig
);

276
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/mist/target_top.vhd
View File

@ -9,6 +9,7 @@ use work.video_controller_pkg.all;
use work.project_pkg.all;
use work.platform_pkg.all;
use work.target_pkg.all;
use work.mist.all;
entity target_top is
port
@ -38,7 +39,6 @@ end target_top;
architecture SYN of target_top is
signal init : std_logic := '1';
signal clock_50 : std_logic;
signal clkrst_i : from_CLKRST_t;
signal buttons_i : from_BUTTONS_t;
signal switches_i : from_SWITCHES_t;
@ -55,32 +55,51 @@ architecture SYN of target_top is
signal target_i : from_TARGET_IO_t;
signal target_o : to_TARGET_IO_t;
signal clk_kb : std_logic;
signal joystick1 : std_logic_vector(7 downto 0);
signal joystick2 : std_logic_vector(7 downto 0);
signal switches : std_logic_vector(1 downto 0);
signal buttons : std_logic_vector(1 downto 0);
signal joystick1 : std_logic_vector(7 downto 0);
signal joystick2 : std_logic_vector(7 downto 0);
signal mist_joy1 : std_logic_vector(31 downto 0);
signal mist_joy2 : std_logic_vector(31 downto 0);
signal switches : std_logic_vector(1 downto 0);
signal buttons : std_logic_vector(1 downto 0);
signal ps2Clk : std_logic;
signal ps2Data : std_logic;
signal kbd_joy0 : std_logic_vector(7 downto 0);
signal osd_pclk : std_logic;
signal clk8m : std_logic;
signal clk16m : std_logic;
signal ps2Data : std_logic;
signal kbd_joy0 :std_logic_vector(7 downto 0);
signal clk6m : std_logic;
signal clk24m : std_logic;
signal scandoubler_disable : std_logic;
signal hsync_out : std_logic;
signal vsync_out : std_logic;
signal csync_out : std_logic;
signal VGA_R_O : std_logic_vector(5 downto 0);
signal VGA_G_O : std_logic_vector(5 downto 0);
signal VGA_B_O : std_logic_vector(5 downto 0);
signal VGA_HS_O : std_logic;
signal VGA_VS_O : std_logic;
signal status : std_logic_vector(7 downto 0);
signal reset : std_logic;
signal ypbpr : std_logic;
signal status : std_logic_vector(31 downto 0);
signal VGA_R_O : std_logic_vector(5 downto 0);
signal VGA_G_O : std_logic_vector(5 downto 0);
signal VGA_B_O : std_logic_vector(5 downto 0);
signal VGA_HS_O : std_logic;
signal VGA_VS_O : std_logic;
signal sd_r : std_logic_vector(5 downto 0);
signal sd_g : std_logic_vector(5 downto 0);
signal sd_b : std_logic_vector(5 downto 0);
signal sd_hs : std_logic;
signal sd_vs : std_logic;
signal osd_red_i : std_logic_vector(5 downto 0);
signal osd_green_i : std_logic_vector(5 downto 0);
signal osd_blue_i : std_logic_vector(5 downto 0);
signal osd_vs_i : std_logic;
signal osd_hs_i : std_logic;
signal osd_red_o : std_logic_vector(5 downto 0);
signal osd_green_o : std_logic_vector(5 downto 0);
signal osd_blue_o : std_logic_vector(5 downto 0);
signal vga_y_o : std_logic_vector(5 downto 0);
signal vga_pb_o : std_logic_vector(5 downto 0);
signal vga_pr_o : std_logic_vector(5 downto 0);
constant CONF_STR : string :=
"Midw.8080;;"&
"O12,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;"&
"O3,Joystick swap,Off,On;"&
"T0,Reset;"&
"V,v1.0 by Gehstock;";
constant CONF_STR : string := "Midw.8080;;O4,Scanlines,OFF,ON;T5,Reset;V,v1.0 by Gehstock;";
function to_slv(s: string) return std_logic_vector is
constant ss: string(1 to s'length) := s;
variable rval: std_logic_vector(1 to 8 * s'length);
@ -96,34 +115,7 @@ architecture SYN of target_top is
return rval;
end function;
component user_io
generic ( STRLEN : integer := 0 );
port (
SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
SPI_MISO : out std_logic;
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
switches : out std_logic_vector(1 downto 0);
buttons : out std_logic_vector(1 downto 0);
scandoubler_disable : out std_logic;
joystick_0 : out std_logic_vector(7 downto 0);
joystick_1 : out std_logic_vector(7 downto 0);
status : out std_logic_vector(7 downto 0);
ps2_clk : in std_logic;
ps2_kbd_clk : out std_logic;
ps2_kbd_data : out std_logic
);
end component user_io;
component osd
port (
pclk, sck, ss, sdi, hs_in, vs_in, scanline_ena_h : in std_logic;
red_in, blue_in, green_in : in std_logic_vector(5 downto 0);
red_out, blue_out, green_out : out std_logic_vector(5 downto 0);
hs_out, vs_out : out std_logic
);
end component osd;
component keyboard
PORT(
clk : in std_logic;
@ -133,55 +125,15 @@ architecture SYN of target_top is
joystick : out std_logic_vector (7 downto 0)
);
end component;
component pll27
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC
);
end component;
begin
LED <= '1';
-- OSD
osd_pclk <= clk16m when scandoubler_disable='0' else clk8m;
-- a minimig vga->scart cable expects a composite sync signal on the VGA_HS output
-- and VCC on VGA_VS (to switch into rgb mode)
csync_out <= '1' when (hsync_out = vsync_out) else '0';
VGA_HS <= hsync_out when scandoubler_disable='0' else csync_out;
VGA_VS <= vsync_out when scandoubler_disable='0' else '1';
osd_inst : osd
port map (
pclk => osd_pclk,
sdi => SPI_DI,
sck => SPI_SCK,
ss => SPI_SS3,
red_in => VGA_R_O,
green_in => VGA_G_O,
blue_in => VGA_B_O,
hs_in => VGA_HS_O,
vs_in => VGA_VS_O,
scanline_ena_h => status(4),
red_out => VGA_R,
green_out => VGA_G,
blue_out => VGA_B,
hs_out => hsync_out,
vs_out => vsync_out
);
user_io_inst : user_io
user_io_inst : work.mist.user_io
generic map (STRLEN => CONF_STR'length)
port map (
port map (
clk_sys => clk6m,
SPI_CLK => SPI_SCK,
SPI_SS_IO => CONF_DATA0,
SPI_MOSI => SPI_DI,
@ -190,50 +142,40 @@ LED <= '1';
switches => switches,
buttons => buttons,
scandoubler_disable => scandoubler_disable,
joystick_1 => joystick2,
joystick_0 => joystick1,
ypbpr => ypbpr,
joystick_0 => mist_joy1,
joystick_1 => mist_joy2,
status => status,
ps2_clk => clk_kb,
ps2_kbd_clk => ps2Clk,
ps2_kbd_data => ps2Data
);
);
u_keyboard : keyboard
u_keyboard : keyboard
port map(
clk => clock_50,
reset => reset,
ps2_kbd_clk => ps2Clk,
ps2_kbd_data => ps2Data,
joystick => kbd_joy0
);
clk => clk6m,
reset => clkrst_i.arst,
ps2_kbd_clk => ps2Clk,
ps2_kbd_data => ps2Data,
joystick => kbd_joy0
);
kbclk : pll27
port map
(
Clock_inst : entity work.pll27
port map (
inclk0 => CLOCK_27,
c0 => clk_kb,
c1 => clk8m,
c2 => clk16m
c0 => clk6m,
c1 => clk24m
);
clkrst_i.clk_ref <= CLOCK_27;
pll_27_inst : entity work.pllclk_ez
port map
(
inclk0 => CLOCK_27,
c0 => clock_50, -- master clock
c1 => clkrst_i.clk(1) -- video clock
);
clkrst_i.clk(0)<=clock_50;
clkrst_i.clk(0) <= clk6m;
clkrst_i.clk(1) <= clk6m;
-- FPGA STARTUP
-- should extend power-on reset if registers init to '0'
process (clock_50)
process (clk6m)
variable count : std_logic_vector (11 downto 0) := (others => '0');
begin
if rising_edge(clock_50) then
if rising_edge(clk6m) then
if count = X"FFF" then
init <= '0';
else
@ -243,7 +185,7 @@ kbclk : pll27
end if;
end process;
clkrst_i.arst <= init or status(5) or buttons(1);
clkrst_i.arst <= init or status(0) or buttons(1);
clkrst_i.arst_n <= not clkrst_i.arst;
GEN_RESETS : for i in 0 to 3 generate
@ -261,40 +203,42 @@ kbclk : pll27
end generate GEN_RESETS;
inputs_i.jamma_n.coin(1) <= not (kbd_joy0(3)) or status(2);--ESC
inputs_i.jamma_n.p(1).start <= not (kbd_joy0(3)) or status(2);--ESC
inputs_i.jamma_n.p(1).up <= not (joystick1(3) or joystick2(3) or kbd_joy0(4));
inputs_i.jamma_n.p(1).down <= not (joystick1(2) or joystick2(2) or kbd_joy0(5));
inputs_i.jamma_n.p(1).left <= not (joystick1(1) or joystick2(1) or kbd_joy0(6));
inputs_i.jamma_n.p(1).right <= not (joystick1(0) or joystick2(0) or kbd_joy0(7));
inputs_i.jamma_n.p(1).button(1) <= not (joystick1(4) or joystick2(4) or kbd_joy0(0));
inputs_i.jamma_n.p(1).button(2) <= '1';
inputs_i.jamma_n.p(1).button(3) <= '1';
inputs_i.jamma_n.p(1).button(4) <= '1';
inputs_i.jamma_n.p(1).button(5) <= '1';
inputs_i.jamma_n.p(2).up <= not (joystick1(3) or joystick2(3) or kbd_joy0(4));
inputs_i.jamma_n.p(2).down <= not (joystick1(2) or joystick2(2) or kbd_joy0(5));
inputs_i.jamma_n.p(2).left <= not (joystick1(1) or joystick2(1) or kbd_joy0(6));
inputs_i.jamma_n.p(2).right <= not (joystick1(0) or joystick2(0) or kbd_joy0(7));
inputs_i.jamma_n.p(2).button(1) <= not (joystick1(4) or joystick2(4) or kbd_joy0(0));
inputs_i.jamma_n.p(2).button(2) <= '1';
inputs_i.jamma_n.p(2).button(3) <= '1';
inputs_i.jamma_n.p(2).button(4) <= '1';
inputs_i.jamma_n.p(2).button(5) <= '1';
joystick1 <= mist_joy1(7 downto 0) when status(3) = '0' else mist_joy2(7 downto 0);
joystick2 <= mist_joy2(7 downto 0) when status(3) = '0' else mist_joy1(7 downto 0);
inputs_i.jamma_n.coin(1) <= not (kbd_joy0(3) or joystick1(6) or joystick2(6));--ESC
inputs_i.jamma_n.p(1).start <= not (kbd_joy0(1) or joystick1(7));--1
inputs_i.jamma_n.p(1).up <= not (joystick1(3) or kbd_joy0(4));
inputs_i.jamma_n.p(1).down <= not (joystick1(2) or kbd_joy0(5));
inputs_i.jamma_n.p(1).left <= not (joystick1(1) or kbd_joy0(6));
inputs_i.jamma_n.p(1).right <= not (joystick1(0) or kbd_joy0(7));
inputs_i.jamma_n.p(1).button(1) <= not (joystick1(4) or kbd_joy0(0));
inputs_i.jamma_n.p(1).button(2) <= not (joystick1(5));
inputs_i.jamma_n.p(1).button(3) <= '1';
inputs_i.jamma_n.p(1).button(4) <= '1';
inputs_i.jamma_n.p(1).button(5) <= '1';
inputs_i.jamma_n.p(2).start <= not (kbd_joy0(2) or joystick2(7));--2
inputs_i.jamma_n.p(2).up <= not (joystick2(3) or kbd_joy0(4));
inputs_i.jamma_n.p(2).down <= not (joystick2(2) or kbd_joy0(5));
inputs_i.jamma_n.p(2).left <= not (joystick2(1) or kbd_joy0(6));
inputs_i.jamma_n.p(2).right <= not (joystick2(0) or kbd_joy0(7));
inputs_i.jamma_n.p(2).button(1) <= not (joystick2(4) or kbd_joy0(0));
inputs_i.jamma_n.p(2).button(2) <= not (joystick2(5));
inputs_i.jamma_n.p(2).button(3) <= '1';
inputs_i.jamma_n.p(2).button(4) <= '1';
inputs_i.jamma_n.p(2).button(5) <= '1';
-- not currently wired to any inputs
inputs_i.jamma_n.coin_cnt <= (others => '1');
inputs_i.jamma_n.coin(2) <= '1';
inputs_i.jamma_n.service <= '1';
inputs_i.jamma_n.tilt <= '1';
inputs_i.jamma_n.test <= '1';
BLK_VIDEO : block
begin
@ -315,14 +259,14 @@ kbclk : pll27
dacl : entity work.sigma_delta_dac
port map (
clk => CLOCK_27,
clk => clk6m,
din => audio_o.ldata(15 downto 8),
dout => AUDIO_L
);
dacr : entity work.sigma_delta_dac
port map (
clk => CLOCK_27,
clk => clk6m,
din => audio_o.rdata(15 downto 8),
dout => AUDIO_R
);
@ -359,4 +303,30 @@ kbclk : pll27
target_i => target_i,
target_o => target_o
);
mist_video : work.mist.mist_video
port map (
clk_sys => clk24m,
scanlines => status(2 downto 1),
scandoubler_disable => scandoubler_disable,
ypbpr => ypbpr,
rotate => "00",
SPI_SCK => SPI_SCK,
SPI_SS3 => SPI_SS3,
SPI_DI => SPI_DI,
R => VGA_R_O,
G => VGA_G_O,
B => VGA_B_O,
HSync => VGA_HS_O,
VSync => VGA_VS_O,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS
);
end SYN;

411
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/mist/user_io.v
View File

@ -1,411 +0,0 @@
//
// user_io.v
//
// user_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// parameter STRLEN and the actual length of conf_str have to match
module user_io #(parameter STRLEN=0) (
input [(8*STRLEN)-1:0] conf_str,
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output reg [7:0] status,
// connection to sd card emulation
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
input sd_conf,
input sd_sdhc,
output reg [7:0] sd_dout,
output reg sd_dout_strobe,
input [7:0] sd_din,
output reg sd_din_strobe,
// ps2 keyboard emulation
input ps2_clk, // 12-16khz provided by core
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// serial com port
input [7:0] serial_data,
input serial_strobe
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [7:0] byte_cnt; // counts bytes
reg [7:0] joystick0;
reg [7:0] joystick1;
reg [4:0] but_sw;
reg [2:0] stick_idx;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
// filter spi clock. the 8 bit gate delay is ~2.5ns in total
wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
// drive MISO only when transmitting core id
always@(negedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
SPI_MISO <= core_type[~bit_cnt];
end else begin
// reading serial fifo
if(cmd == 8'h1b) begin
// send alternating flag byte and data
if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt];
else SPI_MISO <= serial_out_byte[~bit_cnt];
end
// reading config string
else if(cmd == 8'h14) begin
// returning a byte from string
if(byte_cnt < STRLEN + 1)
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
// reading sd card status
else if(cmd == 8'h16) begin
if(byte_cnt == 1)
SPI_MISO <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6))
SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
// reading sd card write data
else if(cmd == 8'h18)
SPI_MISO <= sd_din[~bit_cnt];
else
SPI_MISO <= 1'b0;
end
end
end
// ---------------- PS2 ---------------------
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
// keyboard
reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge ps2_clk) begin
ps2_kbd_r_inc <= 1'b0;
if(ps2_kbd_r_inc)
ps2_kbd_rptr <= ps2_kbd_rptr + 1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1'b1;
// reset parity
ps2_kbd_parity <= 1'b1;
// start transmitter
ps2_kbd_tx_state <= 4'd1;
// put start bit on data line
ps2_kbd_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9)
ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10)
ps2_kbd_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11)
ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
else
ps2_kbd_tx_state <= 4'd0;
end
end
// mouse
reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge ps2_clk) begin
ps2_mouse_r_inc <= 1'b0;
if(ps2_mouse_r_inc)
ps2_mouse_rptr <= ps2_mouse_rptr + 1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1'b1;
// reset parity
ps2_mouse_parity <= 1'b1;
// start transmitter
ps2_mouse_tx_state <= 4'd1;
// put start bit on data line
ps2_mouse_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9)
ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10)
ps2_mouse_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11)
ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
else
ps2_mouse_tx_state <= 4'd0;
end
end
// fifo to receive serial data from core to be forwarded to io controller
// 16 byte fifo to store serial bytes
localparam SERIAL_OUT_FIFO_BITS = 6;
reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
// status[0] is reset signal from io controller and is thus used to flush
// the fifo
always @(posedge serial_strobe or posedge status[0]) begin
if(status[0] == 1) begin
serial_out_wptr <= 0;
end else begin
serial_out_fifo[serial_out_wptr] <= serial_data;
serial_out_wptr <= serial_out_wptr + 1;
end
end
always@(negedge spi_sck or posedge status[0]) begin
if(status[0] == 1) begin
serial_out_rptr <= 0;
end else begin
if((byte_cnt != 0) && (cmd == 8'h1b)) begin
// read last bit -> advance read pointer
if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
serial_out_rptr <= serial_out_rptr + 1;
end
end
end
// SPI receiver
always@(posedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
bit_cnt <= 3'd0;
byte_cnt <= 8'd0;
sd_ack <= 1'b0;
sd_dout_strobe <= 1'b0;
sd_din_strobe <= 1'b0;
end else begin
sd_dout_strobe <= 1'b0;
sd_din_strobe <= 1'b0;
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
bit_cnt <= bit_cnt + 3'd1;
if((bit_cnt == 7)&&(byte_cnt != 8'd255))
byte_cnt <= byte_cnt + 8'd1;
// finished reading command byte
if(bit_cnt == 7) begin
if(byte_cnt == 0) begin
cmd <= { sbuf, SPI_MOSI};
// fetch first byte when sectore FPGA->IO command has been seen
if({ sbuf, SPI_MOSI} == 8'h18)
sd_din_strobe <= 1'b1;
if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
sd_ack <= 1'b1;
end else begin
// buttons and switches
if(cmd == 8'h01)
but_sw <= { sbuf[3:0], SPI_MOSI };
if(cmd == 8'h02)
joystick_0 <= { sbuf, SPI_MOSI };
if(cmd == 8'h03)
joystick_1 <= { sbuf, SPI_MOSI };
if(cmd == 8'h04) begin
// store incoming ps2 mouse bytes
ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI };
ps2_mouse_wptr <= ps2_mouse_wptr + 1;
end
if(cmd == 8'h05) begin
// store incoming ps2 keyboard bytes
ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI };
ps2_kbd_wptr <= ps2_kbd_wptr + 1;
end
if(cmd == 8'h15)
status <= { sbuf[6:0], SPI_MOSI };
// send sector IO -> FPGA
if(cmd == 8'h17) begin
// flag that download begins
sd_dout <= { sbuf, SPI_MOSI};
sd_dout_strobe <= 1'b1;
end
// send sector FPGA -> IO
if(cmd == 8'h18)
sd_din_strobe <= 1'b1;
// send SD config IO -> FPGA
if(cmd == 8'h19) begin
// flag that download begins
sd_dout <= { sbuf, SPI_MOSI};
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
sd_dout_strobe <= 1'b1;
end
// joystick analog
if(cmd == 8'h1a) begin
// first byte is joystick indes
if(byte_cnt == 1)
stick_idx <= { sbuf[1:0], SPI_MOSI };
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0)
joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
else if(stick_idx == 1)
joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0)
joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
else if(stick_idx == 1)
joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
end
end
end
end
end
end
endmodule

8
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/platform_pkg.vhd
View File

@ -23,10 +23,10 @@ package platform_pkg is
-- Platform-specific constants (optional)
--
constant CLK0_FREQ_MHz : natural := 20;
constant CPU_FREQ_MHz : natural := 2;
constant INVADERS_CPU_CLK_ENA_DIVIDE_BY : natural := 20 / 2;
constant CLK0_FREQ_MHz : natural := 6;
constant CPU_FREQ_MHz : natural := 2;
constant INVADERS_CPU_CLK_ENA_DIVIDE_BY : natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
type from_PLATFORM_IO_t is record
not_used : std_logic;

5
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/pllclk_ez.qip
View File

@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pllclk_ez.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.ppf"]

399
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/pllclk_ez.vhd
View File

@ -1,399 +0,0 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pllclk_ez.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pllclk_ez IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pllclk_ez;
ARCHITECTURE SYN OF pllclk_ez IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 20,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 40,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pllclk_ez",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllclk_ez.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

16
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/project_pkg.vhd
View File

@ -13,15 +13,15 @@ package project_pkg is
--
constant PACE_HAS_PLL : boolean := true;
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz;
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_PAL_320x288_50Hz;
constant PACE_CLK0_DIVIDE_BY : natural := 27;
constant PACE_CLK0_MULTIPLY_BY : natural := 20; -- 50*2/5 = 20MHz
constant PACE_CLK0_MULTIPLY_BY : natural := 6; -- 6MHz
constant PACE_CLK1_DIVIDE_BY : natural := 27;
constant PACE_CLK1_MULTIPLY_BY : natural := 40; -- 50*4/5 = 40MHz
constant PACE_VIDEO_H_SCALE : integer := 2;
constant PACE_VIDEO_V_SCALE : integer := 2;
constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '1'; -- Not currently used?
constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '1';
constant PACE_CLK1_MULTIPLY_BY : natural := 6; -- 6MHz
constant PACE_VIDEO_H_SCALE : integer := 1;
constant PACE_VIDEO_V_SCALE : integer := 1;
constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '0';
constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '0';
constant PACE_VIDEO_BORDER_RGB : RGB_t := RGB_BLACK;
constant PACE_HAS_OSD : boolean := false;
@ -32,7 +32,7 @@ package project_pkg is
-- rotate native video (for VGA monitor)
-- - need to change H,V size in platform_pkg.vhd
-- constant INVADERS_ROTATE_VIDEO : boolean := true;
constant INVADERS_ROTATE_VIDEO : boolean := true;
constant INVADERS_ROM_IN_FLASH : boolean := false;
constant PACE_HAS_FLASH : boolean := false;

17
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/video_controller.vhd
View File

@ -258,9 +258,20 @@ begin
v_back_porch_r <= 13;
v_border_r <= (240-VIDEO_V_SIZE)/2;
when others =>
null;
end case;
when PACE_VIDEO_PAL_320x288_50Hz =>
-- 6MHz
h_front_porch_r <= 6;
h_sync_r <= 28;
h_back_porch_r <= 30;
h_border_r <= (320-VIDEO_H_SIZE)/2;
v_front_porch_r <= 8;
v_sync_r <= 3;
v_back_porch_r <= 13;
v_border_r <= (288-VIDEO_V_SIZE)/2;
when others =>
null;
end case;
h_video_r <= VIDEO_H_SIZE;
v_video_r <= VIDEO_V_SIZE;

3
Arcade_MiST/Midway8080 Hardware/Midway8080_MiST/src/video_controller_pkg.vhd
View File

@ -21,7 +21,8 @@ package video_controller_pkg is
PACE_VIDEO_ARCADE_STD_336x240_60Hz, -- arcade std resolution (7.16MHz)
PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64, -- arcade std resolution (28.64MHz)
PACE_VIDEO_CVBS_720x288p_50Hz, -- generic composite
PACE_VIDEO_LCM_320x240_60Hz -- DE2 LCD
PACE_VIDEO_LCM_320x240_60Hz, -- DE2 LCD
PACE_VIDEO_PAL_320x288_50Hz
);
type PACEVideoDisplay_t is