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https://github.com/Gehstock/Mist_FPGA.git
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Text layer dispayed. Colours wrong
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Jose Tejada
parent
1e7af193c5
commit
5d4e16e165
@ -1,34 +1,37 @@
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/***********************************
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FPGA Druaga ( Video Part )
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FPGA Druaga ( Video Part )
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Copyright (c) 2007 MiSTer-X
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Copyright (c) 2007 MiSTer-X
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************************************/
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module DRUAGA_VIDEO
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(
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input VCLKx8,
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input VCLK,
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input VCLK_EN,
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input VCLKx8,
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input VCLK,
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input VCLK_EN,
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input [8:0] PH,
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input [8:0] PV,
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output PCLK,
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output PCLK_EN,
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output [7:0] POUT,
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output VB,
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input [8:0] PH,
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input [8:0] PV,
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output PCLK,
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output PCLK_EN,
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output [7:0] POUT,
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output VB,
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output [10:0] VRAM_A,
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input [15:0] VRAM_D,
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output [10:0] VRAM_A,
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input [15:0] VRAM_D,
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output [6:0] SPRA_A,
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input [23:0] SPRA_D,
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output [6:0] SPRA_A,
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input [23:0] SPRA_D,
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input [8:0] SCROLL,
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input [8:0] SCROLL,
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input [16:0] ROMAD,
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input [7:0] ROMDT,
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input ROMEN
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input [16:0] ROMAD,
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input [ 7:0] ROMDT,
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input ROMEN,
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input [ 2:0] MODEL
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);
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parameter [2:0] SUPERPAC=3'd5;
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wire [8:0] HPOS = PH-8'd16;
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wire [8:0] VPOS = PV;
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@ -37,14 +40,14 @@ wire oHB = (PH>=290) & (PH<492);
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assign VB = (PV==224);
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reg [4:0] PALT_A;
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wire [7:0] PALT_D;
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reg [4:0] PALT_A;
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wire [7:0] PALT_D;
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wire [7:0] CLT0_A;
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wire [3:0] CLT0_D;
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wire [7:0] CLT0_A;
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wire [3:0] CLT0_D;
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wire [11:0] BGCH_A;
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wire [7:0] BGCH_D;
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wire [11:0] BGCH_A;
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wire [7:0] BGCH_D;
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//
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@ -58,53 +61,53 @@ always @(posedge VCLKx8) if (PH == 290) BGVSCR <= SCROLL;
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//----------------------------------------
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// BG scanline generator
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//----------------------------------------
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reg [7:0] BGPN;
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reg BGH;
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reg [7:0] BGPN;
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reg BGH;
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wire [5:0] COL = HPOS[8:3];
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wire [5:0] ROW = VPOS[8:3];
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wire [5:0] ROW2 = ROW + 6'h02;
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wire [5:0] COL = HPOS[8:3];
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wire [5:0] ROW = VPOS[8:3];
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wire [5:0] ROW2 = ROW + 6'h02;
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wire [7:0] CHRC = VRAM_D[7:0];
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wire [5:0] BGPL = VRAM_D[13:8];
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wire [7:0] CHRC = VRAM_D[7:0];
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wire [5:0] BGPL = VRAM_D[13:8];
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wire [8:0] HP = HPOS;
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wire [8:0] VP = COL[5] ? VPOS : BGVPOS;
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wire [11:0] CHRA = { CHRC, ~HP[2], VP[2:0] };
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wire [7:0] CHRO = BGCH_D;
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wire [8:0] HP = HPOS;
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wire [8:0] VP = COL[5] ? VPOS : BGVPOS;
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wire [11:0] CHRA = { CHRC, ~HP[2], VP[2:0] };
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wire [7:0] CHRO = BGCH_D;
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always @ ( posedge VCLKx8 ) begin
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if (VCLK_EN)
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case ( HP[1:0] )
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2'b00: begin BGPN <= { BGPL, CHRO[7], CHRO[3] }; BGH <= VRAM_D[14]; end
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2'b01: begin BGPN <= { BGPL, CHRO[6], CHRO[2] }; BGH <= VRAM_D[14]; end
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2'b10: begin BGPN <= { BGPL, CHRO[5], CHRO[1] }; BGH <= VRAM_D[14]; end
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2'b11: begin BGPN <= { BGPL, CHRO[4], CHRO[0] }; BGH <= VRAM_D[14]; end
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endcase
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if (VCLK_EN)
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case ( HP[1:0] )
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2'b00: begin BGPN <= { BGPL, CHRO[7], CHRO[3] }; BGH <= VRAM_D[14]; end
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2'b01: begin BGPN <= { BGPL, CHRO[6], CHRO[2] }; BGH <= VRAM_D[14]; end
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2'b10: begin BGPN <= { BGPL, CHRO[5], CHRO[1] }; BGH <= VRAM_D[14]; end
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2'b11: begin BGPN <= { BGPL, CHRO[4], CHRO[0] }; BGH <= VRAM_D[14]; end
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endcase
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end
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wire [10:0] VRAMADRS = COL[5] ? { 4'b1111, COL[1:0], ROW[4], ROW2[3:0] } : { VP[8:3], HP[7:3] };
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wire [10:0] VRAMADRS = COL[5] ? { 4'b1111, COL[1:0], ROW[4], ROW2[3:0] } : { VP[8:3], HP[7:3] };
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assign CLT0_A = BGPN;
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assign BGCH_A = CHRA;
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assign VRAM_A = VRAMADRS;
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assign VRAM_A = VRAMADRS & ( MODEL==SUPERPAC ? 11'h3FF : 11'h7FF );
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wire BGHI = BGH & (CLT0_D!=4'd15);
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wire [4:0] BGCOL = { 1'b1, CLT0_D };
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wire BGHI = BGH & (CLT0_D!=4'd15);
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wire [4:0] BGCOL = { 1'b1, CLT0_D };
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//----------------------------------------
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// Sprite scanline generator
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//----------------------------------------
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wire [4:0] SPCOL;
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wire [4:0] SPCOL;
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DRUAGA_SPRITE spr
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(
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VCLKx8, VCLK_EN,
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HPOS, VPOS, oHB,
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SPRA_A, SPRA_D,
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SPCOL,
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ROMAD,ROMDT,ROMEN
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VCLKx8, VCLK_EN,
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HPOS, VPOS, oHB,
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SPRA_A, SPRA_D,
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SPCOL,
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ROMAD,ROMDT,ROMEN
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);
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//----------------------------------------
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@ -118,8 +121,12 @@ assign PCLK_EN = VCLK_EN;
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//----------------------------------------
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// ROMs
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//----------------------------------------
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wire [7:0] chr_data = MODEL==SUPERPAC ? ~ROMDT : ROMDT;
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dpram #(8,12) bgchr(.clk_a(VCLKx8), .addr_a(BGCH_A), .q_a(BGCH_D),
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.clk_b(VCLKx8), .addr_b(ROMAD[11:0]), .we_b(ROMEN & (ROMAD[16:12]=={1'b1,4'h2})), .d_b(ROMDT));
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.clk_b(VCLKx8), .addr_b(ROMAD[11:0]),
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.we_b(ROMEN & (ROMAD[16:12]=={1'b1,4'h2})),
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.d_b(chr_data)
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);
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dpram #(4,8) clut0(.clk_a(VCLKx8), .addr_a(CLT0_A^8'h03), .q_a(CLT0_D),
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.clk_b(VCLKx8), .addr_b(ROMAD[7:0]), .we_b(ROMEN & (ROMAD[16:8]=={1'b1,8'h34})), .d_b(ROMDT[3:0]));
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dpram #(8,5) pelet(.clk_a(VCLKx8), .addr_a(PALT_A), .q_a(PALT_D),
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@ -96,7 +96,8 @@ wire MCPU_IRQ, MCPU_IRQEN;
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wire SCPU_IRQ, SCPU_IRQEN;
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wire SCPU_RESET, IO_RESET;
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wire PSG_ENABLE;
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REGS regs
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REGS #(.SUPERPAC(SUPERPAC)) regs
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(
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CLKCPUx2, RESET, oVB,
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MCPU_ADRS, MCPU_VMA, MCPU_WE,
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@ -105,7 +106,8 @@ REGS regs
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MCPU_IRQ, MCPU_IRQEN,
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SCPU_IRQ, SCPU_IRQEN,
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SCPU_RESET, IO_RESET,
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PSG_ENABLE
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PSG_ENABLE,
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MODEL
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);
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@ -133,7 +135,8 @@ DRUAGA_VIDEO video
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.VRAM_A(vram_a), .VRAM_D(vram_d),
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.SPRA_A(spra_a), .SPRA_D(spra_d),
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.SCROLL({1'b0,SCROLL}),
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.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN)
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.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN),
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.MODEL(MODEL)
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);
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assign POUT = (IsMOTOS & (PV==0)) ? 8'h0 : oPOUT;
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@ -246,16 +249,21 @@ reg mram_cs0, mram_cs1,
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mram_cs2, mram_cs3,
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mram_cs4, mram_cs5;
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reg [10:0] cram_ad;
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wire [10:0] mram_ad = MCPU_ADRS[10:0];
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assign IO_CS = ( MCPU_ADRS[15:11] == 5'b01001 ) & MCPU_VMA; // $4800-$4FFF
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wire mrom_cs = ( MCPU_ADRS[15] ) & MCPU_VMA; // $8000-$FFFF
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always @(*) begin
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cram_ad = mram_ad;
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if( MODEL == SUPERPAC ) begin
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mram_cs0 = ( MCPU_ADRS[15:10] == 6'b000000 ) && MCPU_VMA; // $0000-$03FF
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mram_cs1 = ( MCPU_ADRS[15:10] == 6'b000001 ) && MCPU_VMA; // $0400-$07FF
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mram_cs2 = ( MCPU_ADRS[15:11] == 5'b00001 ) && MCPU_VMA; // $1000-$17FF
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mram_cs3 = ( MCPU_ADRS[15:11] == 5'b00010 ) && MCPU_VMA; // $1800-$1FFF
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mram_cs4 = ( MCPU_ADRS[15:11] == 5'b00011 ) && MCPU_VMA; // $2000-$27FF
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if( mram_cs0 | mram_cs1 ) cram_ad[10]=0;
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end else begin
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mram_cs0 = ( MCPU_ADRS[15:11] == 5'b00000 ) && MCPU_VMA; // $0000-$07FF
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mram_cs1 = ( MCPU_ADRS[15:11] == 5'b00001 ) && MCPU_VMA; // $0800-$0FFF
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@ -285,10 +293,8 @@ assign MCPU_DI = mram_cs0 ? mram_o0 :
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IO_CS ? IO_O :
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8'h0;
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wire [10:0] mram_ad = MCPU_ADRS[10:0];
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dpram #(8,11) main_ram0( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o0), .we_a(mram_w0), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[ 7:0]));
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dpram #(8,11) main_ram1( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o1), .we_a(mram_w1), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[15:8]));
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dpram #(8,11) main_ram0( .clk_a(CPUCLKx2), .addr_a(cram_ad), .d_a(MCPU_DO), .q_a(mram_o0), .we_a(mram_w0), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[ 7:0]));
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dpram #(8,11) main_ram1( .clk_a(CPUCLKx2), .addr_a(cram_ad), .d_a(MCPU_DO), .q_a(mram_o1), .we_a(mram_w1), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[15:8]));
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dpram #(8,11) main_ram2( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o2), .we_a(mram_w2), .clk_b(MCLK), .addr_b({ 4'b1111, spra_a }), .q_b(spra_d[ 7: 0]));
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dpram #(8,11) main_ram3( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o3), .we_a(mram_w3), .clk_b(MCLK), .addr_b({ 4'b1111, spra_a }), .q_b(spra_d[15: 8]));
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@ -314,17 +320,17 @@ endmodule
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module REGS
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(
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input MCPU_CLK,
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input RESET,
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input VBLANK,
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input MCPU_CLK,
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input RESET,
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input VBLANK,
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input [15:0] MCPU_ADRS,
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input MCPU_VMA,
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input MCPU_WE,
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input MCPU_VMA,
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input MCPU_WE,
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input [15:0] SCPU_ADRS,
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input SCPU_VMA,
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input SCPU_WE,
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input SCPU_VMA,
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input SCPU_WE,
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output reg [7:0] SCROLL,
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output MCPU_IRQ,
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@ -333,14 +339,23 @@ module REGS
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output reg SCPU_IRQEN,
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output SCPU_RESET,
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output IO_RESET,
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output reg PSG_ENABLE
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output reg PSG_ENABLE,
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input [2:0] MODEL
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);
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parameter [2:0] SUPERPAC=3'd5;
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// BG Scroll Register
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wire MCPU_SCRWE = ( ( MCPU_ADRS[15:11] == 5'b00111 ) & MCPU_VMA & MCPU_WE );
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always @ ( negedge MCPU_CLK or posedge RESET ) begin
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if ( RESET ) SCROLL <= 8'h0;
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else if ( MCPU_SCRWE ) SCROLL <= MCPU_ADRS[10:3];
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else begin
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if( MODEL==SUPERPAC )
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SCROLL <= 8'd0;
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else if ( MCPU_SCRWE )
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SCROLL <= MCPU_ADRS[10:3];
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end
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end
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// MainCPU IRQ Generator
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