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Gehstock
2019-12-25 15:56:02 +01:00
parent 9aa907a359
commit 63e9d957d3
116 changed files with 5611 additions and 8236 deletions
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6
Arcade_MiST/Atari Vector/LunarLander_MiST/LunarLander.qpf Normal file
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DATE = "19:48:06 May 24, 2017"
QUARTUS_VERSION = "16.0.2"
# Revisions
PROJECT_REVISION = "LunarLander"

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Arcade_MiST/Atari Vector/LunarLander_MiST/LunarLander.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 16:03:28 October 01, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DigDugII_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY LunarLander_MiST
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ---------------------------
# start ENTITY(DigDugII_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(DigDugII_mist)
# -------------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE rtl/LunarLander_MiST.sv
set_global_assignment -name VHDL_FILE rtl/llander_top.vhd
set_global_assignment -name VHDL_FILE rtl/llander.vhd
set_global_assignment -name VHDL_FILE rtl/llander_vg.vhd
set_global_assignment -name VHDL_FILE rtl/llander_ram.vhd
set_global_assignment -name VHDL_FILE rtl/llander_dw.vhd
set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_VEC_ROM_2.vhd
set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_VEC_ROM_1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_VEC_ROM_0.vhd
set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_PROG_ROM_3.vhd
set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_PROG_ROM_2.vhd
set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_PROG_ROM_1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_PROG_ROM_0.vhd
set_global_assignment -name VHDL_FILE rtl/rom/LLANDER_DVG_ROM.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/ovo.vhd
set_global_assignment -name VHDL_FILE rtl/base_pack.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/p2ram.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Atari Vector/LunarLander_MiST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
del /s PLLJ_PLLSPE_INFO.txt
pause

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Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/LunarLander_MiST.sv Normal file
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module LunarLander_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27/*,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
*/
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"LunarLander;;",
"O12,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;",
"O3,Test,Off,On;",
"O45,Language,English,Spanish,French,German;",
"O68,Fuel,450,600,750,900,1100,1300,1550,1800;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clk_50, clk_25, clk_6, locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clk_50),
.c1(clk_25),
.c2(clk_6),
.locked(locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire hs, vs, hso, vso;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [3:0] r, g, b;
wire [7:0] ro, go, bo;
wire vgade;
wire [7:0] audio;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
//this must go to sdram
wire [18:0] vram_write_addr;
wire [3:0] vram_write_data;
wire [18:0] vram_read_addr;
wire [3:0] vram_read_data;
wire vram_wren;
/*
sdram sdram (
.SDRAM_DQ(SDRAM_DQ),
.SDRAM_A(SDRAM_A),
.SDRAM_DQML(SDRAM_DQML),
.SDRAM_DQMH(SDRAM_DQMH),
.SDRAM_BA(SDRAM_BA),
.SDRAM_nCS(SDRAM_nCS),
.SDRAM_nWE(SDRAM_nWE),
.SDRAM_nRAS(SDRAM_nRAS),
.SDRAM_nCAS(SDRAM_nCAS),
.SDRAM_CKE(SDRAM_CKE),
.init(~locked), // init signal after FPGA config to initialize RAM
.clk(clk_50), // sdram is accessed at up to 128MHz
.clkref(clk_25), // reference clock to sync to
.din(vram_write_data), // data input from chipset/cpu
.dout(vram_read_data), // data output to chipset/cpu
.raddr(vram_read_addr), // 25 bit byte address
.waddr(vram_write_addr), // 25 bit byte address
.rd(~vram_wren), // cpu/chipset requests read
.we(vram_wren)
);*/
//reduced ram size
p2ram p2ram (
.clock(clk_25),
.data(vram_write_data),
.rdaddress(vram_read_addr[15:0]),
.wraddress(vram_write_addr[15:0]),
.wren(vram_wren),
.q(vram_read_data)
);
LLANDER_TOP LLANDER_TOP (
.ROT_LEFT_L(~m_left),
.ROT_RIGHT_L(~m_right),
.ABORT_L(~m_fire2),
.GAME_SEL_L(~m_fire1),
.START_L(~btn_one_player),
.COIN1_L(~btn_coin),
.COIN2_L(1'b1),
.THRUST(thrust),
.DIAG_STEP_L(1'b1),
.SLAM_L(1'b1),
.SELF_TEST_L(~status[3]),
.START_SEL_L(1'b1),
.AUDIO_OUT(audio),
.VIDEO_R_OUT(r),
.VIDEO_G_OUT(g),
.VIDEO_B_OUT(b),
.LAMP2(lamp2),
.LAMP3(lamp3),
.LAMP4(lamp4),
.LAMP5(lamp5),
.HSYNC_OUT(hs),
.VSYNC_OUT(vs),
.VID_HBLANK(hb),
.VID_VBLANK(vb),
.VGA_DE(vgade),
.DIP({1'b0,1'b0,status[4],status[5],~status[6],1'b1,status[7],status[8]}),//todo dip full
.RESET_L(~(status[0] | buttons[1])),
.clk_6(clk_6),
.clk_25(clk_25),
.vram_write_addr(vram_write_addr),
.vram_write_data(vram_write_data),
.vram_read_addr(vram_read_addr),
.vram_read_data(vram_read_data),
.vram_wren(vram_wren)
);
ovo #(
.COLS(1),
.LINES(1),
.RGB(24'hFF00FF))
diff (
.i_r({r,r}),
.i_g({g,g}),
.i_b({b,b}),
.i_hs(~hs),
.i_vs(~vs),
.i_de(vgade),
.i_en(1),
.i_clk(clk_25),
.o_r(ro),
.o_g(go),
.o_b(bo),
.o_hs(hso),
.o_vs(vso),
.o_de(),
.ena(diff_count > 0),
.in0(difficulty),
.in1()
);
reg [7:0] thrust = 0;
// 1 second = 50,000,000 cycles (duh)
// If we want to go from zero to full throttle in 1 second we tick every
// 196,850 cycles.
always @(posedge clk_50) begin :thrust_count
int thrust_count;
thrust_count <= thrust_count + 1'd1;
if (thrust_count == 'd196_850) begin
thrust_count <= 0;
if (m_down && thrust > 0)
thrust <= thrust - 1'd1;
if (m_up && thrust < 'd254)
thrust <= thrust + 1'd1;
end
end
int diff_count = 0;
always @(posedge clk_50) begin
if (diff_count > 0)
diff_count <= diff_count - 1;
if (~m_fire2)
diff_count <= 'd500_000_000; // 10 seconds
end
wire lamp2, lamp3, lamp4, lamp5;
wire [1:0] difficulty;
always_comb begin
if(lamp5)
difficulty = 2'd3;
else if(lamp4)
difficulty = 2'd2;
else if(lamp3)
difficulty = 2'd1;
else
difficulty = 2'd0;
end
mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_25 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? ro[7:2] : 0 ),
.G ( blankn ? go[7:2] : 0 ),
.B ( blankn ? bo[7:2] : 0 ),
.HSync ( hso ),
.VSync ( vso ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.scandoubler_disable(1),//scandoublerD ),
.scanlines ( status[2:1] ),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clk_25 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(8))
dac(
.clk_i(clk_25),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
wire m_up = btn_up | joystick_0[3] | joystick_1[3];
wire m_down = btn_down | joystick_0[2] | joystick_1[2];
wire m_left = btn_left | joystick_0[1] | joystick_1[1];
wire m_right = btn_right | joystick_0[0] | joystick_1[0];
wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_fire2 = btn_fire2 | joystick_0[5] | joystick_1[5];
//wire m_fire3 = btn_fire3 | joystick_0[6] | joystick_1[6];
reg btn_one_player = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
//reg btn_fire3 = 0;
reg btn_coin = 0;
always @(posedge clk_25) begin
reg old_state;
old_state <= key_strobe;
if(old_state != key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
// 'h14: btn_fire3 <= key_pressed; // ctrl
'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
endmodule

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Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/base_pack.vhd Normal file
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--------------------------------------------------------------------------------
-- BASE
-- Definitions
--------------------------------------------------------------------------------
-- DO 3/2009
--------------------------------------------------------------------------------
-- Base
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE base_pack IS
--------------------------------------
SUBTYPE uv IS unsigned;
SUBTYPE sv IS signed;
SUBTYPE uv1_0 IS unsigned(1 DOWNTO 0);
SUBTYPE uv0_1 IS unsigned(0 TO 1);
SUBTYPE uv3_0 IS unsigned(3 DOWNTO 0);
SUBTYPE uv0_3 IS unsigned(0 TO 3);
SUBTYPE uv7_0 IS unsigned(7 DOWNTO 0);
SUBTYPE uv0_7 IS unsigned(0 TO 7);
SUBTYPE uv2 IS unsigned(1 DOWNTO 0);
SUBTYPE uv3 IS unsigned(2 DOWNTO 0);
SUBTYPE uv4 IS unsigned(3 DOWNTO 0);
SUBTYPE uv5 IS unsigned(4 DOWNTO 0);
SUBTYPE uv6 IS unsigned(5 DOWNTO 0);
SUBTYPE uv7 IS unsigned(6 DOWNTO 0);
SUBTYPE uv8 IS unsigned(7 DOWNTO 0);
SUBTYPE uv9 IS unsigned(8 DOWNTO 0);
SUBTYPE uv10 IS unsigned(9 DOWNTO 0);
SUBTYPE uv11 IS unsigned(10 DOWNTO 0);
SUBTYPE uv12 IS unsigned(11 DOWNTO 0);
SUBTYPE uv13 IS unsigned(12 DOWNTO 0);
SUBTYPE uv14 IS unsigned(13 DOWNTO 0);
SUBTYPE uv15 IS unsigned(14 DOWNTO 0);
SUBTYPE uv16 IS unsigned(15 DOWNTO 0);
SUBTYPE uv24 IS unsigned(23 DOWNTO 0);
SUBTYPE uv32 IS unsigned(31 DOWNTO 0);
SUBTYPE uv64 IS unsigned(63 DOWNTO 0);
SUBTYPE uv128 IS unsigned(127 DOWNTO 0);
SUBTYPE sv2 IS signed(1 DOWNTO 0);
SUBTYPE sv4 IS signed(3 DOWNTO 0);
SUBTYPE sv8 IS signed(7 DOWNTO 0);
SUBTYPE sv16 IS signed(15 DOWNTO 0);
SUBTYPE sv32 IS signed(31 DOWNTO 0);
SUBTYPE sv64 IS signed(63 DOWNTO 0);
SUBTYPE sv128 IS signed(127 DOWNTO 0);
TYPE arr_uv0_3 IS ARRAY(natural RANGE <>) OF uv0_3;
TYPE arr_uv0_7 IS ARRAY(natural RANGE <>) OF uv0_7;
TYPE arr_uv4 IS ARRAY(natural RANGE <>) OF uv4;
TYPE arr_uv8 IS ARRAY(natural RANGE <>) OF uv8;
TYPE arr_uv16 IS ARRAY(natural RANGE <>) OF uv16;
TYPE arr_uv32 IS ARRAY(natural RANGE <>) OF uv32;
TYPE arr_uv64 IS ARRAY(natural RANGE <>) OF uv64;
SUBTYPE uint1 IS natural RANGE 0 TO 1;
SUBTYPE uint2 IS natural RANGE 0 TO 3;
SUBTYPE uint3 IS natural RANGE 0 TO 7;
SUBTYPE uint4 IS natural RANGE 0 TO 15;
SUBTYPE uint5 IS natural RANGE 0 TO 31;
SUBTYPE uint6 IS natural RANGE 0 TO 63;
SUBTYPE uint7 IS natural RANGE 0 TO 127;
SUBTYPE uint8 IS natural RANGE 0 TO 255;
SUBTYPE uint12 IS natural RANGE 0 TO 4095;
SUBTYPE uint16 IS natural RANGE 0 TO 65535;
SUBTYPE uint24 IS natural RANGE 0 TO 16777215;
-------------------------------------------------------------
FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic;
FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic;
FUNCTION vv (CONSTANT s : std_logic;
CONSTANT N : natural) RETURN unsigned;
--------------------------------------
FUNCTION to_std_logic (a : boolean) RETURN std_logic;
--------------------------------------
FUNCTION mux (
s : std_logic;
a : unsigned;
b : unsigned) RETURN unsigned;
--------------------------------------
FUNCTION mux (
s : boolean;
a : unsigned;
b : unsigned) RETURN unsigned;
--------------------------------------
FUNCTION mux (
s : std_logic;
a : std_logic;
b : std_logic) RETURN std_logic;
--------------------------------------
FUNCTION mux (
s : boolean;
a : std_logic;
b : std_logic) RETURN std_logic;
--------------------------------------
FUNCTION mux (
s : boolean;
a : boolean;
b : boolean) RETURN boolean;
--------------------------------------
FUNCTION mux (
s : boolean;
a : natural;
b : natural) RETURN natural;
--------------------------------------
FUNCTION mux (
s : std_logic;
a : character;
b : character) RETURN character;
--------------------------------------
FUNCTION mux (
s : boolean;
a : character;
b : character) RETURN character;
--------------------------------------
FUNCTION sext (
e : unsigned;
l : natural) RETURN unsigned;
--------------------------------------
FUNCTION sext (
e : std_logic;
l : natural) RETURN unsigned;
--------------------------------------
FUNCTION uext (
e : unsigned;
l : natural) RETURN unsigned;
--------------------------------------
FUNCTION uext (
e : std_logic;
l : natural) RETURN unsigned;
--------------------------------------
PROCEDURE wure (
SIGNAL clk : IN std_logic;
CONSTANT n : IN natural:=1);
--------------------------------------
PROCEDURE wufe (
SIGNAL clk : IN std_logic;
CONSTANT n : IN natural:=1);
--------------------------------------
FUNCTION To_HString (v : unsigned) RETURN string;
FUNCTION To_String (v : unsigned) RETURN string;
--------------------------------------
FUNCTION To_Upper (c : character) RETURN character;
FUNCTION To_Upper (s : string) RETURN string;
FUNCTION To_String (i : natural; b : integer) RETURN string;
FUNCTION To_Natural (s : string; b : integer) RETURN natural;
FUNCTION ilog2 (CONSTANT v : natural) RETURN natural;
END PACKAGE base_pack;
--------------------------------------------------------------------------------
PACKAGE BODY base_pack IS
-------------------------------------------------------------
FUNCTION vv (CONSTANT s : std_logic;
CONSTANT N : natural) RETURN unsigned IS
VARIABLE v : unsigned(N-1 DOWNTO 0);
BEGIN
v:=(OTHERS => s);
RETURN v;
END FUNCTION vv;
-------------------------------------------------------------
-- Vector OR (reduce)
FUNCTION v_or (CONSTANT v : unsigned) RETURN std_logic IS
VARIABLE r : std_logic := '0';
VARIABLE Z : unsigned(v'range) := (OTHERS =>'0');
BEGIN
--pragma synthesis_off
IF 1=1 THEN
FOR I IN v'range LOOP
r:=r OR v(I);
END LOOP;
RETURN r;
ELSE
--pragma synthesis_on
IF v/=Z THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
--pragma synthesis_off
END IF;
--pragma synthesis_on
END FUNCTION v_or;
-------------------------------------------------------------
-- Vector AND (reduce)
FUNCTION v_and (CONSTANT v : unsigned) RETURN std_logic IS
VARIABLE r : std_logic := '1';
VARIABLE U : unsigned(v'range) := (OTHERS =>'1');
BEGIN
--pragma synthesis_off
IF 1=1 THEN
FOR I IN v'range LOOP
r:=r AND v(I);
END LOOP;
RETURN r;
ELSE
--pragma synthesis_on
IF v/=U THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
--pragma synthesis_off
END IF;
--pragma synthesis_on
END FUNCTION v_and;
--------------------------------------
FUNCTION to_std_logic (a : boolean) RETURN std_logic IS
BEGIN
IF a THEN RETURN '1';
ELSE RETURN '0';
END IF;
END FUNCTION to_std_logic;
--------------------------------------
-- Sélection/Multiplexage s=1:a, s=0:b
FUNCTION mux (
s : std_logic;
a : unsigned;
b : unsigned) RETURN unsigned IS
VARIABLE x : unsigned(a'range) :=(OTHERS => 'X');
BEGIN
ASSERT a'length=b'length
REPORT "mux(): Different lengths" SEVERITY failure;
IF s='1' THEN
RETURN a;
ELSIF s='0' THEN
RETURN b;
ELSE
RETURN x;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : boolean;
a : unsigned;
b : unsigned) RETURN unsigned IS
BEGIN
ASSERT a'length=b'length
REPORT "mux(): Different lengths" SEVERITY failure;
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=1:a, s=0:b
FUNCTION mux (
s : std_logic;
a : std_logic;
b : std_logic)
RETURN std_logic IS
BEGIN
RETURN (S AND A) OR (NOT S AND B);
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : boolean;
a : std_logic;
b : std_logic)
RETURN std_logic IS
BEGIN
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : boolean;
a : boolean;
b : boolean)
RETURN boolean IS
BEGIN
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=1:a, s=0:b
FUNCTION mux (
s : boolean;
a : natural;
b : natural)
RETURN natural IS
BEGIN
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : std_logic;
a : character;
b : character)
RETURN character IS
BEGIN
IF s='1' THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Sélection/Multiplexage s=true:a, s=false:b
FUNCTION mux (
s : boolean;
a : character;
b : character)
RETURN character IS
BEGIN
IF s THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION mux;
--------------------------------------
-- Étend un vecteur avec extension de signe
FUNCTION sext (
e : unsigned;
l : natural) RETURN unsigned IS
VARIABLE t : unsigned(l-1 DOWNTO 0);
BEGIN
-- <AFAIRE> Vérifier numeric_std.resize ...
t:=(OTHERS => e(e'left));
t(e'length-1 DOWNTO 0):=e;
RETURN t;
END FUNCTION sext;
--------------------------------------
-- Étend un vecteur avec extension de signe
FUNCTION sext (
e : std_logic;
l : natural) RETURN unsigned IS
VARIABLE t : unsigned(l-1 DOWNTO 0);
BEGIN
-- <AFAIRE> Vérifier numeric_std.resize ...
t:=(OTHERS => e);
RETURN t;
END FUNCTION sext;
--------------------------------------
-- Étend un vecteur sans extension de signe
FUNCTION uext (
e : unsigned;
l : natural) RETURN unsigned IS
VARIABLE t : unsigned(l-1 DOWNTO 0);
BEGIN
-- <AFAIRE> Vérifier numeric_std.resize ...
t:=(OTHERS => '0');
t(e'length-1 DOWNTO 0):=e;
RETURN t;
END FUNCTION uext;
--------------------------------------
-- Étend un vecteur sans extension de signe
FUNCTION uext (
e : std_logic;
l : natural) RETURN unsigned IS
VARIABLE t : unsigned(l-1 DOWNTO 0);
BEGIN
-- <AFAIRE> Vérifier numeric_std.resize ...
t:=(OTHERS => '0');
t(0):=e;
RETURN t;
END FUNCTION uext;
--------------------------------------
-- Wait Until Rising Edge
PROCEDURE wure(
SIGNAL clk : IN std_logic;
CONSTANT n : IN natural:=1) IS
BEGIN
FOR i IN 1 TO n LOOP
WAIT UNTIL rising_edge(clk);
END LOOP;
END PROCEDURE wure;
--------------------------------------
-- Wait Until Rising Edge
PROCEDURE wufe(
SIGNAL clk : IN std_logic;
CONSTANT n : IN natural:=1) IS
BEGIN
FOR i IN 1 TO n LOOP
WAIT UNTIL falling_edge(clk);
END LOOP;
END PROCEDURE wufe;
--------------------------------------
CONSTANT HexString : string(1 TO 16):="0123456789ABCDEF";
-- Conversion unsigned -> Chaîne hexadécimale
FUNCTION To_HString(v : unsigned) RETURN string IS
VARIABLE r : string(1 TO ((v'length)+3)/4);
VARIABLE x : unsigned(1 TO v'length);
VARIABLE i,j : integer;
BEGIN
x:=v;
i:=1;
j:=1;
r:=(OTHERS =>' ');
WHILE i<v'length LOOP
IF x(i)='X' OR x(i+1)='X' OR x(i+2)='X' OR x(i+3)='X' THEN
r(j):='X';
ELSIF x(i)='U' OR x(i+1)='U' OR x(i+2)='U' OR x(i+3)='U' THEN
r(j):='U';
ELSIF x(i)='Z' OR x(i+1)='Z' OR x(i+2)='Z' OR x(i+3)='Z' THEN
r(j):='Z';
ELSIF x(i)='H' OR x(i+1)='H' OR x(i+2)='H' OR x(i+3)='H' THEN
r(j):='H';
ELSIF x(i)='L' OR x(i+1)='L' OR x(i+2)='L' OR x(i+3)='L' THEN
r(j):='L';
ELSIF x(i)='W' OR x(i+1)='W' OR x(i+2)='W' OR x(i+3)='W' THEN
r(j):='W';
ELSE
r(j):=HexString(to_integer(unsigned(x(i TO i+3)))+1);
END IF;
i:=i+4;
j:=j+1;
END LOOP;
RETURN r;
END FUNCTION To_HString;
-- Conversion unsigned -> Chaîne binaire
FUNCTION To_String(v : unsigned) RETURN string IS
VARIABLE r : string(1 TO v'length);
VARIABLE x : unsigned(1 TO v'length);
BEGIN
x:=v;
FOR i IN 1 TO v'length LOOP
CASE x(i) IS
WHEN '0' => r(i):='0';
WHEN '1' => r(i):='1';
WHEN 'X' => r(i):='X';
WHEN 'Z' => r(i):='Z';
WHEN 'U' => r(i):='U';
WHEN 'H' => r(i):='H';
WHEN 'L' => r(i):='L';
WHEN '-' => r(i):='-';
WHEN 'W' => r(i):='W';
END CASE;
-- r(i):=std_logic'image(x(i))(1);
END LOOP;
RETURN r;
END FUNCTION To_String;
--------------------------------------
-- Conversion majuscules caractère
FUNCTION To_Upper(c : character) RETURN character IS
VARIABLE r : character;
BEGIN
CASE c IS
WHEN 'a' => r := 'A';
WHEN 'b' => r := 'B';
WHEN 'c' => r := 'C';
WHEN 'd' => r := 'D';
WHEN 'e' => r := 'E';
WHEN 'f' => r := 'F';
WHEN 'g' => r := 'G';
WHEN 'h' => r := 'H';
WHEN 'i' => r := 'I';
WHEN 'j' => r := 'J';
WHEN 'k' => r := 'K';
WHEN 'l' => r := 'L';
WHEN 'm' => r := 'M';
WHEN 'n' => r := 'N';
WHEN 'o' => r := 'O';
WHEN 'p' => r := 'P';
WHEN 'q' => r := 'Q';
WHEN 'r' => r := 'R';
WHEN 's' => r := 'S';
WHEN 't' => r := 'T';
WHEN 'u' => r := 'U';
WHEN 'v' => r := 'V';
WHEN 'w' => r := 'W';
WHEN 'x' => r := 'X';
WHEN 'y' => r := 'Y';
WHEN 'z' => r := 'Z';
WHEN OTHERS => r := c;
END CASE;
RETURN r;
END To_Upper;
--------------------------------------
-- Conversion majuscules chaîne
FUNCTION To_Upper(s: string) RETURN string IS
VARIABLE r: string (s'range);
BEGIN
FOR i IN s'range LOOP
r(i):= to_upper(s(i));
END LOOP;
RETURN r;
END To_Upper;
--------------------------------------
-- Conversion entier -> chaîne
FUNCTION To_String(i: natural; b: integer) RETURN string IS
VARIABLE r : string(1 TO 10);
VARIABLE j,k : natural;
VARIABLE t : character;
BEGIN
j:=i;
k:=10;
WHILE j>=b LOOP
r(k):=HexString(j MOD b);
j:=j/b;
k:=k-1;
END LOOP;
RETURN r(k TO 10);
END FUNCTION To_String;
--------------------------------------
-- Conversion chaîne -> entier
FUNCTION To_Natural (s : string; b : integer) RETURN natural IS
VARIABLE v,r : natural;
BEGIN
r:=0;
FOR i IN s'range LOOP
CASE s(i) IS
WHEN '0' => v:=0;
WHEN '1' => v:=1;
WHEN '2' => v:=2;
WHEN '3' => v:=3;
WHEN '4' => v:=4;
WHEN '5' => v:=5;
WHEN '6' => v:=6;
WHEN '7' => v:=7;
WHEN '8' => v:=8;
WHEN '9' => v:=9;
WHEN 'a' | 'A' => v:=10;
WHEN 'b' | 'B' => v:=11;
WHEN 'c' | 'C' => v:=12;
WHEN 'd' | 'D' => v:=13;
WHEN 'e' | 'E' => v:=14;
WHEN 'f' | 'F' => v:=15;
WHEN OTHERS =>
v:=1000;
END CASE;
ASSERT v<b REPORT "To_Natural : Chaîne invalide :" & s SEVERITY error;
r:=r*b+v;
END LOOP;
RETURN r;
END FUNCTION To_Natural;
--------------------------------------
-- Renvoie le log entier en base 2, à peu près
FUNCTION ilog2 (CONSTANT v : natural) RETURN natural IS
VARIABLE r : natural := 1;
VARIABLE n : natural := 0;
BEGIN
WHILE v>r LOOP
n:=n+1;
r:=r*2;
END LOOP;
RETURN n;
END FUNCTION ilog2;
END PACKAGE BODY base_pack;

0
Arcade_MiST/NinjaKun_MiST/rtl/build_id.tcl → Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/build_id.tcl
View File

75
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/dpram.vhd Normal file
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@@ -0,0 +1,75 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
entity dpram is
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0');
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
numwords_b => 2**addr_width_g,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
widthad_b => addr_width_g,
width_a => data_width_g,
width_b => data_width_g,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
address_a => address_a,
address_b => address_b,
clock0 => clock_a,
clock1 => clock_b,
clocken0 => enable_a,
clocken1 => enable_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => q_a,
q_b => q_b
);
END SYN;

0
Arcade_MiST/Sega Zaxxon Hardware/rtl/gen_ram.vhd → Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/gen_ram.vhd
View File

648
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander.vhd Normal file
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@@ -0,0 +1,648 @@
--
-- A simulation model of Lunar Lander hardware
-- James Sweet 2019
-- This is not endorsed by fpgaarcade, please do not bother MikeJ with support requests
--
-- Built upon model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LLander is
port (
CLK_6 : in std_logic;
CLK_25 : in std_logic;
RESET_6_L : in std_logic;
--
DIP : in std_logic_vector(7 downto 0);
--
ROT_LEFT_L : in std_logic;
ROT_RIGHT_L : in std_logic;
ABORT_L : in std_logic;
GAME_SEL_L : in std_logic;
START_L : in std_logic;
COIN1_L : in std_logic;
COIN2_L : in std_logic;
--
THRUST : in std_logic_vector(7 downto 0);
--
DIAG_STEP_L : in std_logic;
SLAM_L : in std_logic;
SELF_TEST_L : in std_logic;
--
START_SEL_L : out std_logic;
LAMP2 : out std_logic;
LAMP3 : out std_logic;
LAMP4 : out std_logic;
LAMP5 : out std_logic;
COIN_CTR : out std_logic;
--
AUDIO_OUT : out std_logic_vector(7 downto 0);
--
X_VECTOR : out std_logic_vector(9 downto 0);
Y_VECTOR : out std_logic_vector(9 downto 0);
Z_VECTOR : out std_logic_vector(3 downto 0);
BEAM_ON : out std_logic;
BEAM_ENA : out std_logic
);
end;
architecture RTL of LLander is
signal ena_count : std_logic_vector(10 downto 0) := (others => '0');
signal ena_3M : std_ulogic;
signal ena_1_5M : std_ulogic;
signal ena_1_5M_e : std_ulogic;
signal ena_3K : std_ulogic;
signal ena_12k : std_ulogic;
signal clk_3k : std_ulogic;
signal clk_6K : std_ulogic;
signal clk_12K : std_ulogic;
-- cpu
signal c_addr : std_logic_vector(23 downto 0);
signal c_din : std_logic_vector(7 downto 0);
signal c_dout : std_logic_vector(7 downto 0);
signal c_rw_l : std_logic;
signal c_irq_l : std_logic;
signal c_nmi_l : std_logic;
signal reset_l : std_logic;
signal wd_cnt : std_logic_vector(7 downto 0);
--
signal nmi_count : std_logic_vector(3 downto 0);
-- addr decode
signal zpage_l : std_logic;
signal io_l : std_logic;
signal vmem_l : std_logic;
signal pmem_l : std_logic;
--
signal sinp0_l : std_logic;
signal sinp1_l : std_logic;
signal opts_l : std_logic;
signal pot_l : std_logic;
--
signal dma_go_l : std_logic;
signal outck_l : std_logic;
signal wdclr_l : std_logic;
signal explode_l : std_logic;
signal dma_reset_l : std_logic;
signal audio_l : std_logic;
signal noiserst_l : std_logic;
--
signal shipthrusten : std_logic;
--
signal test_l : std_logic;
signal halt : std_logic;
-- memory
signal rom0_dout : std_logic_vector(7 downto 0);
signal rom1_dout : std_logic_vector(7 downto 0);
signal rom2_dout : std_logic_vector(7 downto 0);
signal rom3_dout : std_logic_vector(7 downto 0);
signal rom_dout : std_logic_vector(7 downto 0);
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_dout : std_logic_vector(7 downto 0);
signal vg_dout : std_logic_vector(7 downto 0);
signal ram_we : std_logic;
-- io
signal dips_p6_l : std_logic_vector(7 downto 0);
signal dips_ip_sel : std_logic_vector(1 downto 0);
signal control_ip0_l : std_logic_vector(7 downto 0);
signal control_ip0_sel : std_logic;
signal control_ip1_l : std_logic_vector(7 downto 0);
signal control_ip1_sel : std_logic;
-- sound
signal aud : std_logic_vector(5 downto 0);
signal tone3khz : std_logic_vector(3 downto 0);
signal tone6khz : std_logic_vector(3 downto 0);
signal t_e_vol : std_logic_vector(2 downto 0);
signal noise_shift : std_logic_vector(15 downto 0);
signal noise : std_logic;
signal shpsnd : std_logic_vector(3 downto 0);
signal lifesnd : std_logic_vector(3 downto 0);
signal lifeen : std_logic;
signal shpsnd_prefilter : std_logic;
signal shpsnd_filter_t1 : std_logic_vector(3 downto 0);
signal shpsnd_filter_t2 : std_logic_vector(3 downto 0);
signal shpsnd_filter_t3 : std_logic_vector(3 downto 0);
signal shpsnd_filtered : std_logic_vector(5 downto 0);
signal expaud : std_logic_vector(2 downto 0);
signal expitch : std_logic_vector(1 downto 0);
signal noise_cnt : std_logic_vector(3 downto 0);
signal expld_snd : std_logic_vector(3 downto 0);
signal clkdiv2 : std_logic_vector(3 downto 0);
signal audio_out2 : std_logic_vector(7 downto 0);
begin
p_ena : process -- clock divider
begin
wait until rising_edge(CLK_6);
ena_count <= ena_count + "1";
ena_3M <= not ena_count(0); -- 3 Mhz;
ena_1_5M <= '0';
ena_1_5M_e <= '0';
if (ena_count(1 downto 0) = "00") then
ena_1_5M <= '1'; -- 1.5 Mhz
end if;
if (ena_count(1 downto 0) = "10") then
ena_1_5M_e <= '1'; -- 1.5 Mhz (early)
end if;
ena_12k <= '0';
if (ena_count(8 downto 0) = "000000000") then
ena_12k <= '1';
end if;
ena_3k <= '0';
if (ena_count(10 downto 0) = "00000000000") then
ena_3k <= '1';
end if;
clk_3k <= ena_count(10);
end process;
cpu : entity work.T65 -- main cpu
port map (
Mode => "00",
Res_n => reset_l,
Enable => ena_1_5M,
Clk => CLK_6,
Rdy => '1',
Abort_n => '1',
IRQ_n => '1',
NMI_n => c_nmi_l,
SO_n => '1',
R_W_n => c_rw_l,
Sync => open,
EF => open,
MF => open,
XF => open,
ML_n => open,
VP_n => open,
VDA => open,
VPA => open,
A => c_addr,
DI => c_din,
DO => c_dout
);
p_nmi : process(reset_l, CLK_6)
variable carry : boolean;
begin
if (reset_l = '0') then
c_nmi_l <= '1';
nmi_count <= "0000";
elsif rising_edge(CLK_6) then
-- divide 3k signal by 12
carry := (nmi_count = "1111");
c_nmi_l <= '1';
if (test_l = '1') and carry then
c_nmi_l <= '0';
end if;
if (ena_3K = '1') then
if carry then
nmi_count <= "0100";
else
nmi_count <= nmi_count + "1";
end if;
end if;
end if;
end process;
p_wd_reset : process(RESET_6_L, CLK_6)
begin
if (RESET_6_L = '0') then
wd_cnt <= "00000000";
reset_l <= '0';
elsif rising_edge(CLK_6) then
if (wdclr_l = '0') then
wd_cnt <= "00000000";
elsif (ena_3K = '1') then
wd_cnt <= wd_cnt + "1";
end if;
if (ena_3k = '1') and (wd_cnt = "01111111") then
reset_l <= not reset_l;
end if;
-- simulation
-- reset_l <= reset_6_l;
end if;
end process;
p_addr_decode1 : process(c_addr, c_rw_l, ena_1_5M, reset_l)
variable deca : std_logic_vector(3 downto 0);
variable decb : std_logic_vector(3 downto 0);
variable decc : std_logic_vector(7 downto 0);
variable input_read : std_logic;
variable control_write : std_logic;
begin
-- cpu address bit 15 is tied to ground
-- as far as the rest of the system is concerned
deca := "1111";
case c_addr(14 downto 13) is
when "00" => deca := "1110";
when "01" => deca := "1101";
when "10" => deca := "1011";
when "11" => deca := "0111";
when others => null;
end case;
zpage_l <= deca(0);
io_l <= deca(1);
vmem_l <= deca(2);
pmem_l <= deca(3);
input_read := (not deca(1)) and (not c_addr(12)) and c_rw_l;
decb := "1111";
if (input_read = '1') then
case c_addr(11 downto 10) is
when "00" => decb := "1110";
when "01" => decb := "1101";
when "10" => decb := "1011";
when "11" => decb := "0111";
when others => null;
end case;
end if;
sinp0_l <= decb(0);
sinp1_l <= decb(1);
opts_l <= decb(2);
pot_l <= decb(3);
control_write := (not deca(1)) and c_addr(12) and (not c_rw_l);-- and ena_1_5M;
decc := "11111111";
if (control_write = '1') then
case c_addr(11 downto 9) is
when "000" => decc := "11111110";
when "001" => decc := "11111101";
when "010" => decc := "11111011";
when "011" => decc := "11110111";
when "100" => decc := "11101111";
when "101" => decc := "11011111";
when "110" => decc := "10111111";
when "111" => decc := "01111111";
when others => null;
end case;
end if;
dma_go_l <= decc(0);
outck_l <= decc(1);
wdclr_l <= decc(2);
dma_reset_l <= decc(4);
audio_l <= decc(6);
noiserst_l <= decc(7);
end process;
lamp_reg : process(reset_l, clk_6)
begin
if (reset_l = '0') then
lamp5 <= '0';
lamp4 <= '0';
lamp3 <= '0';
lamp2 <= '0';
start_sel_l <= '0';
coin_ctr <= '0';
elsif rising_edge(CLK_6) then
if (ena_1_5M = '1') then
if (outck_l = '0') then
lamp5 <= c_dout(0);
lamp4 <= c_dout(1);
lamp3 <= c_dout(2);
lamP2 <= c_dout(3);
start_sel_l <= c_dout(4);
coin_ctr <= c_dout(5);
end if;
end if;
end if;
end process;
p_input_registers : process
begin
wait until rising_edge(CLK_6);
dips_p6_l <= DIP;
-- diag step, self test, slam, halt
control_ip0_l(7) <= DIAG_STEP_L;
control_ip0_l(6) <= clk_3k;
control_ip0_l(5) <= '1';
control_ip0_l(4) <= '1';
control_ip0_l(3) <= '1';
control_ip0_l(2) <= SLAM_L;
control_ip0_l(1) <= test_l;
control_ip0_l(0) <= halt;
test_l <= SELF_TEST_L;
-- left, right, abort, game select, coin11, coin2, start
control_ip1_l(7) <= ROT_LEFT_L;
control_ip1_l(6) <= ROT_RIGHT_L;
control_ip1_l(5) <= ABORT_L;
control_ip1_l(4) <= GAME_SEL_L;
control_ip1_l(3) <= not COIN1_L;
control_ip1_l(2) <= '1';
control_ip1_l(1) <= not COIN2_L;
control_ip1_l(0) <= START_L;
end process;
p_input_sel : process(c_addr, dips_p6_l, control_ip0_l, control_ip1_l, clk_3k, halt)
begin
control_ip1_sel <= '0';
case c_addr(2 downto 0) is
when "000" => control_ip1_sel <= not control_ip1_l(0);
when "001" => control_ip1_sel <= not control_ip1_l(1);
when "010" => control_ip1_sel <= not control_ip1_l(2);
when "011" => control_ip1_sel <= not control_ip1_l(3);
when "100" => control_ip1_sel <= not control_ip1_l(4);
when "101" => control_ip1_sel <= not control_ip1_l(5);
when "110" => control_ip1_sel <= not control_ip1_l(6);
when "111" => control_ip1_sel <= not control_ip1_l(7);
when others => null;
end case;
dips_ip_sel <= "00";
case c_addr(1 downto 0) is
when "00" => dips_ip_sel <= dips_p6_l(1) & dips_p6_l(0);
when "01" => dips_ip_sel <= dips_p6_l(3) & dips_p6_l(2);
when "10" => dips_ip_sel <= dips_p6_l(5) & dips_p6_l(4);
when "11" => dips_ip_sel <= dips_p6_l(7) & dips_p6_l(6);
when others => null;
end case;
end process;
rom0 : entity work.LLANDER_PROG_ROM_0
port map (
addr => c_addr(10 downto 0),
data => rom0_dout,
clk => CLK_6
);
rom1 : entity work.LLANDER_PROG_ROM_1
port map (
addr => c_addr(10 downto 0),
data => rom1_dout,
clk => CLK_6
);
rom2 : entity work.LLANDER_PROG_ROM_2
port map (
addr => c_addr(10 downto 0),
data => rom2_dout,
clk => CLK_6
);
rom3 : entity work.LLANDER_PROG_ROM_3
port map (
addr => c_addr(10 downto 0),
data => rom3_dout,
clk => CLK_6
);
p_rom_mux : process(c_addr, rom0_dout, rom1_dout, rom2_dout, rom3_dout)
begin
rom_dout <= (others => '0');
case c_addr(12 downto 11) is
when "00" => rom_dout <= rom0_dout;
when "01" => rom_dout <= rom1_dout;
when "10" => rom_dout <= rom2_dout;
when "11" => rom_dout <= rom3_dout;
when others => null;
end case;
end process;
-- Zero-page RAM
--RAM: Entity work.RAM256
--port map(
-- clock => clk_6,
-- address => c_addr(7 downto 0),
-- data => c_dout,
-- wren => ram_we,
-- q => ram_dout
-- );
RAM: Entity work.gen_ram
generic map(
dWidth => 8,
aWidth => 8)
port map(
clk => clk_6,
we => ram_we,
addr => c_addr(7 downto 0),
d => c_dout,
q => ram_dout
);
ram_we <= (not zpage_l) and (not c_rw_l) and ena_1_5M;
-- CPU Data in mux controlled by address decoder
p_cpu_data_mux : process(c_addr, ram_dout, rom_dout, vg_dout, zpage_l, pmem_l, vmem_l,
sinp0_l, control_ip0_l, sinp1_l, control_ip1_sel,
opts_l, dips_ip_sel, pot_l, thrust)
begin
c_din <= (others => '0');
if (sinp0_l = '0') then
c_din <= control_ip0_l;
elsif (sinp1_l = '0') then
c_din <= control_ip1_sel & "1111111";
elsif (opts_l = '0') then
c_din <= "111111" & dips_ip_sel;
elsif (pot_l = '0') then
c_din <= thrust ;
elsif (zpage_l = '0') then
c_din <= ram_dout;
elsif (pmem_l = '0') then
c_din <= rom_dout;
elsif (vmem_l = '0') then
c_din <= vg_dout;
end if;
end process;
--
-- audio
--
-- Thrust Aud0 through Aud 2 - volume
-- Explosion - Aud 3, volume by Aud 0 through Aud 2
-- 3k - Aud 4
-- 6k - Aud 5
-- Output register for audio control
p_aud_reg : process(RESET_L, CLK_6)
begin
if (reset_l = '0') then
aud <= "000000";
elsif rising_edge(CLK_6) then
if (ena_1_5M = '1') then
if (audio_l = '0') then
aud <= c_dout(5 downto 0);
end if;
end if;
end if;
end process;
tone3khz <= "1111" when clk_3k = '1' and aud(4) = '1' else "0000";
tone6khz <= "1111" when clk_6k = '1' and aud(5) = '1' else "0000";
t_e_vol <= aud(2 downto 0);
shipthrusten <= aud(0) or aud(1) or aud(2);
-- LFSR to generate noise used in the ship thrust and explosion sounds
p_noise_gen : process(RESET_L, CLK_6)
variable shift_in : std_logic;
begin
if (reset_l = '0') then
noise_shift <= (others => '0');
noise <= '0';
elsif rising_edge(CLK_6) then
if (ena_12k = '1') then
shift_in := not(noise_shift(6) xor noise_shift(14));
noise_shift <= noise_shift(14 downto 0) & shift_in;
noise <= shift_in; -- one clock late
end if;
end if;
end process;
-- Ship thrust sound, passes noise through a low pass filter
p_ship_snd : process
begin
wait until rising_edge(CLK_6);
shpsnd_prefilter <= noise and shipthrusten;
-- simple low pass filter
if (ena_3k = '1') then
if (shpsnd_prefilter = '1') then
shpsnd_filter_t1 <= t_e_vol & '0';
else
shpsnd_filter_t1 <= "0000";
end if;
shpsnd_filter_t2 <= shpsnd_filter_t1;
shpsnd_filter_t3 <= shpsnd_filter_t2;
end if;
shpsnd_filtered <= ("00" & shpsnd_filter_t1 ) +
('0' & shpsnd_filter_t2 & '0') +
("00" & shpsnd_filter_t3 );
end process;
p_expld_gen : process(reset_l, clk_6, aud)
begin
if reset_l = '0' then
expaud <= "000";
elsif (aud(3) = '1') and (noise = '1') then
expaud <= aud(2 downto 0);
else
expaud <= "000";
end if;
end process;
p_audio_output_reg : process
variable sum : std_logic_vector(8 downto 0);
begin
wait until rising_edge(clk_6);
sum := ('0' & tone6khz)+ ('0' & tone3khz)+ ("00" & expaud & "000") + ('0' & shpsnd_filtered & "00");
if (sum(8) = '0') then
AUDIO_OUT <= sum(7 downto 0);
else -- clip
AUDIO_OUT <= "11111111";
end if;
end process;
--
-- vector generator
--
vg : entity work.LLANDER_VG
port map (
C_ADDR => c_addr(15 downto 0),
C_DIN => c_dout,
C_DOUT => vg_dout,
C_RW_L => c_rw_l,
VMEM_L => vmem_l,
DMA_GO_L => dma_go_l,
DMA_RESET_L => dma_reset_l,
HALT_OP => halt,
X_VECTOR => X_VECTOR,
Y_VECTOR => Y_VECTOR,
Z_VECTOR => Z_VECTOR,
BEAM_ON => BEAM_ON,
--
ENA_1_5M => ena_1_5m,
ENA_1_5M_E => ena_1_5m_e,
RESET_L => reset_l,
CLK_6 => CLK_6,
CLK_25 => CLK_25
);
BEAM_ENA <= ena_1_5m;
end RTL;

450
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/llander_dw.vhd Normal file
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@@ -0,0 +1,450 @@
--
-- A simulation model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
-- This code is not part of the original game.
-- Dave Wood (oldgit) Feb 2019
-- My smaller version (512 x 512 screen). This module takes the Vectors and beam intensisty and
-- produces a double buffered raster graphics screen. The intensity was used to give a 'blue hue' as per the original game
-- to the rocks and text but produces white for the ships.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use work.pkg_asteroids.all;
entity LLANDER_DW is
port (
RESET : in std_logic;
clk_25 : in std_logic;
clk_6 : in std_logic;
X_VECTOR : in std_logic_vector(9 downto 0);
Y_VECTOR : in std_logic_vector(9 downto 0);
Z_VECTOR : in std_logic_vector(3 downto 0);
BEAM_ON : in std_logic;
BEAM_ENA : in std_logic;
VIDEO_R_OUT : out std_logic_vector(3 downto 0);
VIDEO_G_OUT : out std_logic_vector(3 downto 0);
VIDEO_B_OUT : out std_logic_vector(3 downto 0);
HSYNC_OUT : out std_logic;
VSYNC_OUT : out std_logic;
VID_DE : out std_logic;
VID_HBLANK : out std_logic;
VID_VBLANK : out std_logic;
vram_write_addr : out std_logic_vector(18 downto 0);
vram_write_data : out std_logic_vector(3 downto 0);
vram_read_addr : out std_logic_vector(18 downto 0);
vram_read_data : in std_logic_vector(3 downto 0);
vram_wren : out std_logic
);
end;
architecture RTL of LLANDER_DW is
-- types & constants
subtype Bus12 is std_logic_vector (11 downto 0);
constant V_FRONT_PORCH_START : Bus12 := x"1e0"; -- line 480
constant V_SYNC_START : Bus12 := x"1ea"; -- line 490
constant V_BACK_PORCH_START : Bus12 := x"1ec"; -- line 492
constant LINE_PER_FRAME : Bus12 := x"20d"; -- 525 lines
constant H_FRONT_PORCH_START : Bus12 := x"280"; -- pixel 640
constant H_SYNC_START : Bus12 := x"290"; -- pixel 656
constant H_BACK_PORCH_START : Bus12 := x"2f0"; -- pixel 752
constant PIXEL_PER_LINE : Bus12 := x"320"; -- 800 pixels
signal lcount : std_logic_vector(9 downto 0);
signal pcount : std_logic_vector(10 downto 0);
signal hterm : boolean;
signal vterm : boolean;
signal v_sync : std_logic;
signal h_sync : std_logic;
signal v_blank : std_logic;
signal h_blank : std_logic;
signal raster_active : std_logic;
--
signal beam_ena_t : std_logic_vector(2 downto 0);
signal beam_load : std_logic;
signal video_r : std_logic_vector(3 downto 0);
signal video_g : std_logic_vector(3 downto 0);
signal video_b : std_logic_vector(3 downto 0);
signal dw_addr : std_logic_vector(18 downto 0);
signal up_addr : std_logic_vector(17 downto 0);
signal vid_out : std_logic_vector(3 downto 0);
signal Y_Vid : std_logic_vector(8 downto 0);
signal X_Vid : std_logic_vector(8 downto 0);
signal Vid_data : std_logic_vector(3 downto 0);
signal dcount : std_logic_vector(2 downto 0);
signal screen : std_logic_vector(0 downto 0);
signal vcount : std_logic_vector(8 downto 0);
signal hcount : std_logic_vector(8 downto 0);
signal pxcount : std_logic_vector(8 downto 0);
-- signal vram_wren : std_logic;
begin
pixel_cnt : process(clk_25, RESET)
variable vcnt_front_porch_start : boolean;
variable hcnt_front_porch_start : boolean;
begin
if (RESET = '1') then
hcount <= (others => '0');
vcount <= (others => '0');
elsif rising_edge(clk_25) then
vcnt_front_porch_start := (vcount = 511);
hcnt_front_porch_start := (hcount = 511);
if hcnt_front_porch_start then
hcount <= (others => '0');
else
hcount <= hcount + "1";
end if;
if hcnt_front_porch_start then
if vcnt_front_porch_start then
vcount <= (others => '0');
else
vcount <= vcount + "1";
end if;
end if;
end if;
end process;
-- basic raster gen
p_cnt_compare_comb : process(pcount,lcount)
begin
hterm <= (pcount = (PIXEL_PER_LINE(10 downto 0) - "1"));
vterm <= (lcount = (LINE_PER_FRAME( 9 downto 0) - "1"));
end process;
p_display_cnt : process(clk_25, RESET)
begin
if (RESET = '1') then
pcount <= (others => '0');
lcount <= (others => '0');
dcount <= (others => '0');
elsif rising_edge(clk_25) then
if hterm then
pcount <= (others => '0');
else
pcount <= pcount + "1";
end if;
if pcount > 63 then
pxcount <= pxcount + "1";
raster_active <= '1';
end if;
if pcount > 575 then
raster_active <= '0';
pxcount <= "111111111";
end if;
if hterm then
if vterm then
lcount <= (others => '0');
dcount <= dcount + "1" ;
else
lcount <= lcount + "1";
end if;
end if;
end if;
end process;
p_vsync : process(clk_25, RESET)
variable vcnt_eq_front_porch_start : boolean;
variable vcnt_eq_sync_start : boolean;
variable vcnt_eq_back_porch_start : boolean;
begin
if (RESET = '1') then
v_sync <= '1';
v_blank <= '0';
elsif rising_edge(clk_25) then
vcnt_eq_front_porch_start := (lcount = (V_FRONT_PORCH_START(9 downto 0) - "1"));
vcnt_eq_sync_start := (lcount = ( V_SYNC_START(9 downto 0) - "1"));
vcnt_eq_back_porch_start := (lcount = ( V_BACK_PORCH_START(9 downto 0) - "1"));
if vcnt_eq_sync_start and hterm then
v_sync <= '0';
elsif vcnt_eq_back_porch_start and hterm then
v_sync <= '1';
end if;
if vcnt_eq_front_porch_start and hterm then
v_blank <= '1';
elsif vterm and hterm then
v_blank <= '0';
end if;
end if;
end process;
p_hsync : process(clk_25, RESET)
variable hcnt_eq_front_porch_start : boolean;
variable hcnt_eq_sync_start : boolean;
variable hcnt_eq_back_porch_start : boolean;
begin
if (RESET = '1') then
h_sync <= '1';
h_blank <= '1'; -- 0
elsif rising_edge(clk_25) then
hcnt_eq_front_porch_start := (pcount = ( H_FRONT_PORCH_START(10 downto 0) - "1"));
hcnt_eq_sync_start := (pcount = ( H_SYNC_START(10 downto 0) - "1"));
hcnt_eq_back_porch_start := (pcount = ( H_BACK_PORCH_START(10 downto 0) - "1"));
if hcnt_eq_sync_start then
h_sync <= '0';
elsif hcnt_eq_back_porch_start then
h_sync <= '1';
end if;
if hcnt_eq_front_porch_start then
h_blank <= '1';
elsif hterm then
h_blank <= '0';
end if;
end if;
end process;
p_active_video : process(h_blank, v_blank, raster_active, lcount, pxcount)
begin
-- raster_active <= not(h_blank or v_blank);
if raster_active = '1' then
Y_Vid <= not (lcount(8 downto 0) and lcount(8 downto 0)) ;
else
Y_Vid <= "111111111";
end if;
if raster_active = '1' then
X_Vid <= pxcount(8 downto 0);
else
X_Vid <= "111111111";
end if;
end process;
p_video_out : process
begin
wait until rising_edge(clk_25);
if raster_active = '1' then
case vid_out is
when "0000" => video_r <= "0000";video_g <= "0000";video_b <= "0000";
when "0001" => video_r <= "0001";video_g <= "0001";video_b <= "0001";
when "0010" => video_r <= "0011";video_g <= "0011";video_b <= "0011";
when "0011" => video_r <= "0011";video_g <= "0011";video_b <= "0011";
when "0100" => video_r <= "0011";video_g <= "0011";video_b <= "0111";
when "0101" => video_r <= "0011";video_g <= "0011";video_b <= "0111";
when "0110" => video_r <= "0011";video_g <= "0011";video_b <= "0111";
when "0111" => video_r <= "0011";video_g <= "0011";video_b <= "0111";
-- when "1000" => video_r <= "0111";video_g <= "0111";video_b <= "0111";
when "1000" => video_r <= "0011";video_g <= "0011";video_b <= "0111";
--when "1001" => video_r <= "0111";video_g <= "0111";video_b <= "0111";
when "1001" => video_r <= "0011";video_g <= "0011";video_b <= "0111";
when "1010" => video_r <= "0111";video_g <= "0111";video_b <= "0111";
when "1011" => video_r <= "0111";video_g <= "0111";video_b <= "0111";
when "1100" => video_r <= "1111";video_g <= "1111";video_b <= "1111";
when "1101" => video_r <= "1111";video_g <= "1111";video_b <= "1111";
when "1110" => video_r <= "1111";video_g <= "1111";video_b <= "1111";
when others => video_r <= "1111";video_g <= "1111";video_b <= "1111";
end case;
VIDEO_R_OUT <= video_r;
VIDEO_G_OUT <= video_g;
VIDEO_B_OUT <= video_b;
else -- blank
VIDEO_R_OUT <= "0000";
VIDEO_G_OUT <= "0000";
VIDEO_B_OUT <= "0000";
end if;
VID_DE <= not(v_blank or h_blank);
VSYNC_OUT <= v_sync;
HSYNC_OUT <= h_sync;
VID_HBLANK <= h_blank;
VID_VBLANK <= v_blank;
end process;
up_addr <= (Y_Vid(8 downto 0) & X_Vid(8 downto 0));
clear_ram : process(clk_25, RESET)
variable state : integer range 0 to 4;
variable beam_ena_r : std_logic := '0';
begin
if RESET = '1' then
beam_ena_r := '0';
elsif rising_edge(clk_25) then
vram_wren <= '0' after 2 ns;
if dcount = "000" then
screen <= "0";
dw_addr <= "0" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1));
if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then
if Z_VECTOR(3 downto 0) = "0000" then
vid_data <= "0000";
vram_wren <= '0';
else
vid_data <= Z_VECTOR(3 downto 0);
vram_wren <= '1';
end if;
end if;
end if;
if dcount = "001" then
screen <= "0";
dw_addr <= "1" & (vcount ) & hcount;
vid_data <= "0000";
vram_wren <= '1';
end if;
if dcount = "010" then
screen <= "0";
dw_addr <= "0" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1));
if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then
if Z_VECTOR(3 downto 0) = "0000" then
vid_data <= "0000";
vram_wren <= '0';
else
vid_data <= Z_VECTOR(3 downto 0);
vram_wren <= '1';
end if;
end if;
end if;
if dcount = "011" then
screen <= "0";
dw_addr <= "1" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1));
if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then
if Z_VECTOR(3 downto 0) = "0000" then
vid_data <= "0000";
vram_wren <= '0';
else
vid_data <= Z_VECTOR(3 downto 0);
vram_wren <= '1';
end if;
end if;
end if;
if dcount = "100" then
screen <= "1";
dw_addr <= "1" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1));
if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then
if Z_VECTOR(3 downto 0) = "0000" then
vid_data <= "0000";
vram_wren <= '0';
else
vid_data <= Z_VECTOR(3 downto 0);
vram_wren <= '1';
end if;
end if;
end if;
if dcount = "101" then
screen <= "1";
dw_addr <= "0" & (vcount ) & hcount;
vid_data <= "0000";
vram_wren <= '1';
end if;
if dcount = "110" then
screen <= "1";
dw_addr <= "1" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1));
if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then
if Z_VECTOR(3 downto 0) = "0000" then
vid_data <= "0000";
vram_wren <= '0';
else
vid_data <= Z_VECTOR(3 downto 0);
vram_wren <= '1';
end if;
end if;
end if;
if dcount = "111" then
screen <= "1";
dw_addr <= "0" & ((Y_VECTOR(9 downto 1) ) & X_VECTOR(9 downto 1));
if BEAM_ON = '1' and beam_ena_r = '0' and BEAM_ENA = '1' then
if Z_VECTOR(3 downto 0) = "0000" then
vid_data <= "0000";
vram_wren <= '0';
else
vid_data <= Z_VECTOR(3 downto 0);
vram_wren <= '1';
end if;
end if;
end if;
beam_ena_r := beam_ena;
end if;
end process;
--video_rgb : work.dpram generic map (19,4)
--port map(
-- clock_a => clk_25,
-- wren_a => vram_wren,
-- address_a => dw_addr(18 downto 0),
-- data_a => vid_data,
-- clock_b => clk_25,
-- address_b => (screen & up_addr(17 downto 0)),
--);
vram_write_addr <= dw_addr(18 downto 0);
vram_write_data <= vid_data;
vram_read_addr <= screen & up_addr(17 downto 0);
vid_out <= vram_read_data;
-- job done !
end architecture RTL;

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--
-- A simulation model of Lunar Lander hardware
-- James Sweet 2019
-- This is not endorsed by fpgaarcade, please do not bother MikeJ with support requests
--
-- Built upon model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LLANDER_RAM is
port (
ADDR : in std_logic_vector(9 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
RW_L : in std_logic;
CS_L : in std_logic; -- used for write enable gate only
ENA : in std_logic; -- ditto
CLK : in std_logic
);
end;
architecture RTL of LLANDER_RAM is
signal we : std_logic;
begin
r1 : Entity work.gen_ram
generic map(
dWidth => 4,
aWidth => 10)
port map(
clk => clk,
we => we,
addr => ADDR(9 downto 0),
d => DIN(7 downto 4),
q => DOUT(7 downto 4)
);
r0 : Entity work.gen_ram
generic map(
dWidth => 4,
aWidth => 10)
port map(
clk => clk,
we => we,
addr => ADDR(9 downto 0),
d => DIN(3 downto 0),
q => DOUT(3 downto 0)
);
p_we : process(RW_L, CS_L, ENA)
begin
we <= (not CS_L) and (not RW_L) and ENA;
end process;
end architecture RTL;

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--
-- A simulation model of Lunar Lander hardware
-- James Sweet 2019
-- This is not endorsed by fpgaarcade, please do not bother MikeJ with support requests
--
-- Built upon model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
--
-- Notes :
--
-- Button shorts input to ground when pressed
--
-- ToDo:
-- Model sound effects for thump-thump, ship and saucer fire and saucer warble
-- Add player control switching and screen flip for cocktail mode
-- General cleanup
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LLANDER_TOP is
port (
ROT_LEFT_L : in std_logic;
ROT_RIGHT_L : in std_logic;
ABORT_L : in std_logic;
GAME_SEL_L : in std_logic;
START_L : in std_logic;
COIN1_L : in std_logic;
COIN2_L : in std_logic;
--
THRUST : in std_logic_vector(7 downto 0);
--
DIAG_STEP_L : in std_logic;
SLAM_L : in std_logic;
SELF_TEST_L : in std_logic;
--
START_SEL_L : out std_logic;
LAMP2 : out std_logic;
LAMP3 : out std_logic;
LAMP4 : out std_logic;
LAMP5 : out std_logic;
AUDIO_OUT : out std_logic_vector(7 downto 0);
VIDEO_R_OUT : out std_logic_vector(3 downto 0);
VIDEO_G_OUT : out std_logic_vector(3 downto 0);
VIDEO_B_OUT : out std_logic_vector(3 downto 0);
HSYNC_OUT : out std_logic;
VSYNC_OUT : out std_logic;
VGA_DE : out std_logic;
VID_HBLANK : out std_logic;
VID_VBLANK : out std_logic;
DIP : in std_logic_vector(7 downto 0);
RESET_L : in std_logic;
-- ref clock in
clk_6 : in std_logic;
clk_25 : in std_logic;
vram_write_addr : out std_logic_vector(18 downto 0);
vram_write_data : out std_logic_vector(3 downto 0);
vram_read_addr : out std_logic_vector(18 downto 0);
vram_read_data : in std_logic_vector(3 downto 0);
vram_wren : out std_logic
);
end;
architecture RTL of LLANDER_TOP is
signal RAM_ADDR_A : std_logic_vector(18 downto 0);
signal RAM_ADDR_B : std_logic_vector(15 downto 0); -- same as above
signal RAM_WE_L : std_logic;
signal RAM_ADV_L : std_logic;
signal RAM_OE_L : std_logic;
signal RAM_DO : std_logic_vector(31 downto 0);
signal RAM_DI : std_logic_vector(31 downto 0);
signal ram_we : std_logic;
signal reset_dll_h : std_logic;
signal delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal reset_6_l : std_logic;
signal reset_6 : std_logic;
signal clk_cnt : std_logic_vector(2 downto 0) := "000";
signal x_vector : std_logic_vector(9 downto 0);
signal y_vector : std_logic_vector(9 downto 0);
signal y_vector_w_offset : std_logic_vector(9 downto 0);
signal z_vector : std_logic_vector(3 downto 0);
signal beam_on : std_logic;
signal beam_ena : std_logic;
signal ram_addr_int : std_logic_vector(18 downto 0);
signal ram_we_l_int : std_logic;
signal ram_adv_l_int : std_logic;
signal ram_oe_l_int : std_logic;
signal ram_dout_oe_l : std_logic;
signal ram_dout_oe_l_reg : std_logic;
signal ram_dout : std_logic_vector(31 downto 0);
signal ram_dout_reg : std_logic_vector(31 downto 0);
signal ram_din : std_logic_vector(31 downto 0);
begin
--
-- Note about clocks
--
-- (the original uses a 6.048 MHz clock, so 40 / 6 - slightly slower)
--
reset_dll_h <= not RESET_L;
reset_6 <= reset_dll_h;
p_delay : process(RESET_L, clk_6)
begin
if (RESET_L = '0') then
delay_count <= x"00"; -- longer delay for cpu
reset_6_l <= '0';
elsif rising_edge(clk_6) then
if (delay_count(7 downto 0) = (x"FF")) then
delay_count <= (x"FF");
reset_6_l <= '1';
else
delay_count <= delay_count + "1";
reset_6_l <= '0';
end if;
end if;
end process;
LLander: entity work.llander
port map(
clk_6 => clk_6,
clk_25 => clk_25,
reset_6_l => reset_6_l,
dip => DIP,
rot_left_l => rot_left_l,
rot_right_l => rot_right_l,
abort_l => abort_l,
game_sel_l => game_sel_l,
start_l => start_l,
coin1_l => coin1_l,
coin2_l => coin2_l,
thrust => thrust,
diag_step_l => diag_step_l,
slam_l => '1', --switches(15),
self_test_l =>self_test_l,
start_sel_l => start_sel_l,
lamp2 => lamp2,
lamp3 => lamp3,
lamp4 => lamp4,
lamp5 => lamp5,
coin_ctr => open,
audio_out => AUDIO_OUT,
x_vector => x_vector,
y_vector => y_vector,
z_vector => z_vector,
beam_on => beam_on,
BEAM_ENA => beam_ena
);
y_vector_w_offset<= y_vector+100;
u_DW : entity work.LLANDER_DW
port map (
RESET => reset_6,
clk_25 => clk_25,
clk_6 => clk_6,
X_VECTOR => x_vector,
Y_VECTOR => y_vector_w_offset,-- AJS move up y_vector,
Z_VECTOR => z_vector,
BEAM_ON => beam_on,
BEAM_ENA => beam_ena,
VIDEO_R_OUT => VIDEO_R_OUT,
VIDEO_G_OUT => VIDEO_G_OUT,
VIDEO_B_OUT => VIDEO_B_OUT,
HSYNC_OUT => HSYNC_OUT,
VSYNC_OUT => VSYNC_OUT,
VID_DE => VGA_DE,
VID_HBLANK => VID_HBLANK,
VID_VBLANK => VID_VBLANK,
vram_write_addr => vram_write_addr,
vram_write_data => vram_write_data,
vram_read_addr => vram_read_addr,
vram_read_data => vram_read_data,
vram_wren => vram_wren
);
end RTL;

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--
-- A simulation model of Lunar Lander hardware
-- James Sweet 2019
-- This is not endorsed by fpgaarcade, please do not bother MikeJ with support requests
--
-- Built upon model of Asteroids Deluxe hardware
-- Copyright (c) MikeJ - May 2004
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity LLANDER_VG is
port (
C_ADDR : in std_logic_vector(15 downto 0);
C_DIN : in std_logic_vector( 7 downto 0);
C_DOUT : out std_logic_vector( 7 downto 0);
C_RW_L : in std_logic;
VMEM_L : in std_logic;
DMA_GO_L : in std_logic;
DMA_RESET_L : in std_logic;
HALT_OP : out std_logic;
X_VECTOR : out std_logic_vector(9 downto 0);
Y_VECTOR : out std_logic_vector(9 downto 0);
Z_VECTOR : out std_logic_vector(3 downto 0);
BEAM_ON : out std_logic;
ENA_1_5M : in std_logic;
ENA_1_5M_E : in std_logic;
RESET_L : in std_logic;
CLK_6 : in std_logic;
Clk_25 : in std_logic
);
end;
architecture RTL of LLANDER_VG is
type slv_array12 is array (natural range <>) of std_logic_vector(11 downto 0);
signal state : std_logic_vector(3 downto 0);
signal next_state : std_logic_vector(3 downto 0);
signal state_halt : std_logic;
--
signal dma_ld_l : std_logic;
signal dma_ld_l_t1 : std_logic;
signal dma_push_l : std_logic;
signal blank_l : std_logic;
signal latch_l : std_logic_vector(3 downto 0);
signal halt_strobe_l : std_logic;
signal go_strobe_l : std_logic;
--
signal stop : std_logic;
signal go : std_logic;
signal halt : std_logic;
signal offset : std_logic_vector(3 downto 0);
signal timer : std_logic_vector(3 downto 0);
signal scale : std_logic_vector(3 downto 0);
signal scale_reg : std_logic_vector(3 downto 0);
signal reg_addr : std_logic_vector(3 downto 0);
signal new_reg_addr : std_logic_vector(3 downto 0);
signal alphanum_l : std_logic;
signal timer_load : std_logic_vector(9 downto 0);
signal timer_counter : std_logic_vector(11 downto 0);
signal dvx_bus : std_logic_vector(11 downto 0);
signal dvy_bus : std_logic_vector(11 downto 0);
--
signal xpos_bus : std_logic_vector(11 downto 0);
signal ypos_bus : std_logic_vector(11 downto 0);
signal adma_bus : std_logic_vector(12 downto 1);
signal adma0 : std_logic;
signal load_bus : std_logic_vector(12 downto 1);
signal vram1_l : std_logic;
signal vram2_l : std_logic;
signal vrom1_l : std_logic;
signal vrom2_l : std_logic;
signal vrom3_l : std_logic;
signal vram1_t1_l : std_logic;
signal vram2_t1_l : std_logic;
signal vrom1_t1_l : std_logic;
signal vrom2_t1_l : std_logic;
signal vrom3_t1_l : std_logic;
signal am_bus : std_logic_vector(12 downto 0);
signal vw_l : std_logic;
-- ratemul
signal ratemul_reg : std_logic_vector(9 downto 0);
signal ratemulx_op : std_logic;
signal ratemulx_reg_and : std_logic_vector(9 downto 0);
signal ratemulx_clock_g : std_logic;
signal ratemulx_rate_out : std_logic_vector(9 downto 0);
--
signal ratemuly_op : std_logic;
signal ratemuly_reg_and : std_logic_vector(9 downto 0);
signal ratemuly_clock_g : std_logic;
signal ratemuly_rate_out : std_logic_vector(9 downto 0);
--
signal stack_reg : slv_array12(3 downto 0) := (others => (others => '0'));
signal ram_din : std_logic_vector(7 downto 0);
signal ram_dout_1 : std_logic_vector(7 downto 0);
signal ram_dout_2 : std_logic_vector(7 downto 0);
signal rom_dout_1 : std_logic_vector(7 downto 0);
signal rom_dout_2 : std_logic_vector(7 downto 0);
signal rom_dout_3 : std_logic_vector(7 downto 0);
signal memory_dout : std_logic_vector(7 downto 0);
begin
p_halt_go : process(RESET_L, CLK_6)
begin
if (RESET_L = '0') then
halt <= '1';
go <= '0';
elsif rising_edge(CLK_6) then
-- slight rejig here from j-k of original
if (DMA_RESET_L = '0') then
halt <= '1';
elsif (DMA_GO_L = '0') then
halt <= '0';
elsif (halt_strobe_l = '0') then
halt <= timer(0);
end if;
if (halt = '1') then
go <= '0';
elsif (go_strobe_l = '0') then
go <= '1';
elsif (stop = '1') then
go <= '0';
end if;
end if;
end process;
HALT_OP <= halt;
--
-- state machine
--
p_next_state : process(state, timer, go, halt)
variable go_halt : std_logic;
begin
-- this lot used to be in a rom with
--
--addr(7) := not( go or halt);
--addr(6) := timer(2) and timer(3);
--addr(5) := timer(1) and timer(3);
--addr(4) := timer(0) and timer(3);
--addr(3 downto 0) := state;
go_halt := go or halt;
next_state <= x"0";
case state is
when x"0" => if (go_halt = '1') then
next_state <= x"0";
else
next_state <= x"9";
end if;
when x"1" => if (go_halt = '1') then
next_state <= x"1";
else
next_state <= x"2";
end if;
when x"2" => next_state <= x"D";
when x"3" => next_state <= x"D";
when x"4" => next_state <= x"5";
when x"5" => next_state <= x"6";
when x"6" => next_state <= x"7";
when x"7" => next_state <= x"D";
when x"8" => if (timer = x"B") then
next_state <= x"B";
else
next_state <= x"9";
end if;
when x"9" => next_state <= x"D";
when x"A" => next_state <= x"1";
when x"B" => if (timer = x"A") then
next_state <= x"D";
else
next_state <= x"0";
end if;
when x"C" => if (timer = x"B") or (timer = x"C") then
next_state <= x"8";
elsif (timer = x"D") or (timer = x"E") then
next_state <= x"9";
elsif (timer = x"F") then
next_state <= x"A";
else
next_state <= x"F";
end if;
when x"D" => next_state <= x"C";
when x"E" => if (timer = x"A") then
next_state <= x"B";
else
next_state <= x"A";
end if;
when x"F" => next_state <= x"E";
when others => null;
end case;
end process;
p_state_machine : process(RESET_L, CLK_6)
begin
if (RESET_L = '0') then
state <= "0000";
state_halt <= '0';
elsif rising_edge(CLK_6) then
if (DMA_RESET_L = '0') then
state <= "0000";
state_halt <= '0';
elsif (ENA_1_5M = '1') then
if (vmem_l = '1') or (state(2) = '0') then
state <= next_state;
state_halt <= halt;
end if;
end if;
end if;
end process;
p_state_decode : process(state, state_halt, vmem_l, ENA_1_5M_E)
variable dec : std_logic_vector(7 downto 0);
begin
dec := "11111111";
-- if start(2) is low, ignore vmem_l
if (state(3) = '1') and ((vmem_l = '1') or (state(2) = '0')) and (ENA_1_5M_E = '1') then
case state(2 downto 0) is
when "000" => dec := "11111110";
when "001" => dec := "11111101";
when "010" => dec := "11111011";
when "011" => dec := "11110111";
when "100" => dec := "11101111";
when "101" => dec := "11011111";
when "110" => dec := "10111111";
when "111" => dec := "01111111";
when others => null;
end case;
end if;
adma0 <= state(0);
blank_l <= not (state(3) or state_halt);
-- following stobes are used on ena_1_5 early, so must not be clock enables on ena_1_5.
latch_l(3) <= dec(7);
latch_l(2) <= dec(6);
latch_l(1) <= dec(5);
latch_l(0) <= dec(4);
halt_strobe_l <= dec(3);
go_strobe_l <= dec(2);
dma_ld_l <= dec(1);
dma_push_l <= dec(0);
end process;
--
-- Program counter / stack
--
p_dmald : process(timer, CLK_6)
begin
if (timer(0) = '0') then
dma_ld_l_t1 <= '0';
elsif rising_edge(CLK_6) then
dma_ld_l_t1 <= dma_ld_l;
end if;
end process;
p_regaddr_calc : process(timer, reg_addr, dma_ld_l, dma_ld_l_t1, dma_push_l)
variable offset : std_logic_vector(3 downto 0);
begin
-- we need the address early
-- dma_push_l = '0' => store, then inc
-- dma_ld dec, then load pc from stack
if (timer(0) = '1') then -- down
offset := "1111";
else
offset := "0001";
end if;
if ((dma_ld_l = '0') and (dma_ld_l_t1 = '1')) or (dma_push_l = '0') then
new_reg_addr <= reg_addr + offset;
else
new_reg_addr <= reg_addr;
end if;
end process;
p_regaddr : process
begin
wait until rising_edge(CLK_6);
if (DMA_GO_L = '0') then -- reset not in original
reg_addr <= "0000";
else
reg_addr <= new_reg_addr ;
end if;
end process;
p_reg_write : process
begin
wait until rising_edge(CLK_6);
if (dma_push_l = '0') then
case reg_addr(1 downto 0) is
when "00" => stack_reg(0) <= adma_bus;
when "01" => stack_reg(1) <= adma_bus;
when "10" => stack_reg(2) <= adma_bus;
when "11" => stack_reg(3) <= adma_bus;
when others => null;
end case;
end if;
end process;
p_reg_read : process(timer(0), new_reg_addr, dvy_bus, stack_reg)
begin
if (timer(0) = '1') then -- load
load_bus <= stack_reg(0); -- default
case new_reg_addr(1 downto 0) is
when "00" => load_bus <= stack_reg(0);
when "01" => load_bus <= stack_reg(1);
when "10" => load_bus <= stack_reg(2);
when "11" => load_bus <= stack_reg(3);
when others => null;
end case;
else
load_bus <= dvy_bus;
end if;
end process;
p_pc : process
begin
wait until rising_edge(CLK_6);
if (dma_ld_l = '0') then
adma_bus <= load_bus;
else
if (latch_l(0) = '0') or (latch_l(2) = '0') then
adma_bus <= adma_bus + "1";
end if;
end if;
end process;
--
-- address decoder
--
p_addr_sel : process(VMEM_L, adma_bus, adma0, C_ADDR, C_RW_L)
begin
if (VMEM_L = '0') then
am_bus <= C_ADDR(12 downto 0);
vw_l <= C_RW_L;
else
am_bus <= adma_bus & adma0;
vw_l <= '1';
end if;
end process;
p_am_decode : process(am_bus)
begin
vram1_l <= '1';
vram2_l <= '1';
vrom1_l <= '1';
vrom2_l <= '1';
vrom3_l <= '1';
case am_bus(12 downto 10) is
when "000" => vram1_l <= '0';
when "001" => vram2_l <= '0';
when "010" => vrom1_l <= '0';
when "011" => vrom1_l <= '0';
when "100" => vrom2_l <= '0';
when "101" => vrom2_l <= '0';
when "110" => vrom3_l <= '0'; -- AJS?
when "111" => vrom3_l <= '0';
when others => null;
end case;
end process;
p_am_reg : process
begin
wait until rising_edge(CLK_6);
vram1_t1_l <= vram1_l;
vram2_t1_l <= vram2_l;
vrom1_t1_l <= vrom1_l;
vrom2_t1_l <= vrom2_l;
vrom3_t1_l <= vrom3_l;
end process;
-- only cpu can write to vector ram
ram_din <= C_DIN;
C_DOUT <= memory_dout;
-- vector memory
u_vector_ram_1 : entity work.LLANDER_RAM
port map (
ADDR => am_bus(9 downto 0),
DIN => ram_din,
DOUT => ram_dout_1,
RW_L => vw_l,
CS_L => vram1_l,
ENA => ena_1_5M,
CLK => CLK_6
);
u_vector_ram_2 : entity work.LLANDER_RAM
port map (
ADDR => am_bus(9 downto 0),
DIN => ram_din,
DOUT => ram_dout_2,
RW_L => vw_l,
CS_L => vram2_l,
ENA => ena_1_5M,
CLK => CLK_6
);
u_vector_rom_0 : entity work.LLANDER_VEC_ROM_0
port map (
addr => am_bus(10 downto 0),
data => rom_dout_1,
clk => CLK_6
);
u_vector_rom_1 : entity work.LLANDER_VEC_ROM_1
port map (
addr => am_bus(10 downto 0),
data => rom_dout_2,
clk => CLK_6
);
u_vector_rom_2 : entity work.LLANDER_VEC_ROM_2
port map (
addr => am_bus(10 downto 0),
data => rom_dout_3,
clk => CLK_6
);
p_memory_data_mux : process(vram1_t1_l, vram2_t1_l, vrom1_t1_l, vrom2_t1_l, vrom3_t1_l,ram_dout_1, ram_dout_2, rom_dout_1, rom_dout_2,rom_dout_3)
begin
-- cpu buffer enabled when VMEM_L = 0
memory_dout <= (others => '0');
if (vram1_t1_l = '0') then
memory_dout <= ram_dout_1;
elsif (vram2_t1_l = '0') then
memory_dout <= ram_dout_2;
elsif (vrom1_t1_l = '0') then
memory_dout <= rom_dout_1; -- AJS??
elsif (vrom2_t1_l = '0') then
memory_dout <= rom_dout_2; -- AJS??
elsif (vrom3_t1_l = '0') then
memory_dout <= rom_dout_3; -- AJS??
else
memory_dout <= (others => 'X');
end if;
end process;
--
-- data memory latches
--
p_latch : process
begin
wait until rising_edge(CLK_6);
-- latch3
if ((alphanum_l = '0') and (latch_l(0) = '0')) or (latch_l(3) ='0') then
scale <= memory_dout(7 downto 4);
dvx_bus(11 downto 8) <= memory_dout(3 downto 0);
end if;
-- latch2
if (alphanum_l = '0') then
dvx_bus(7 downto 0) <= x"00";
elsif (latch_l(2) = '0') then
dvx_bus(7 downto 0) <= memory_dout(7 downto 0);
end if;
-- we know we have a sync reset
-- latch1
if (DMA_RESET_L = '0') or (RESET_L = '0') or (dma_go_l = '0') then
timer <= x"0";
dvy_bus(11 downto 8) <= x"0";
elsif (latch_l(1) = '0') then
timer <= memory_dout(7 downto 4);
dvy_bus(11 downto 8) <= memory_dout(3 downto 0);
end if;
-- latch0
if (DMA_RESET_L = '0') or (RESET_L = '0') or (dma_go_l = '0') or (alphanum_l = '0') then
dvy_bus(7 downto 0) <= x"00";
elsif (latch_l(0) = '0') then
dvy_bus(7 downto 0) <= memory_dout(7 downto 0);
end if;
end process;
--
-- vector timer
--
p_scale_reg : process
begin
wait until rising_edge(CLK_6);
if (latch_l(2) = '0') and (timer(3) = '1') and (timer(1) = '1') then
scale_reg <= scale;
end if;
end process;
p_vector_timer : process(timer, dvx_bus, dvy_bus, scale_reg)
variable sel : std_logic;
variable mux : std_logic_vector(3 downto 0);
variable add : std_logic_vector(3 downto 0);
variable dec : std_logic_vector(9 downto 0);
begin
sel := '1';
if (timer = "1111") then
sel := '0';
end if;
alphanum_l <= sel;
if (sel = '0') then
mux := '0' & dvx_bus(11) & not dvx_bus(11) & dvy_bus(11);
else
mux := timer;
end if;
add := scale_reg + mux;
timer_load <= "1111111111";
case add is
when "0000" => timer_load <= "1111111110";
when "0001" => timer_load <= "1111111101";
when "0010" => timer_load <= "1111111011";
when "0011" => timer_load <= "1111110111";
when "0100" => timer_load <= "1111101111";
when "0101" => timer_load <= "1111011111";
when "0110" => timer_load <= "1110111111";
when "0111" => timer_load <= "1101111111";
when "1000" => timer_load <= "1011111111";
when "1001" => timer_load <= "0111111111";
when others => timer_load <= "1111111111";
end case;
end process;
p_vector_timer_counter : process
begin
wait until rising_edge(CLK_6);
if (go = '0') then
timer_counter <= "1" & timer_load & '1';
elsif (ENA_1_5M = '1') then
timer_counter <= timer_counter + "1";
end if;
end process;
p_stop : process(timer_counter)
begin
stop <= '0';
if (timer_counter = x"FFF") then
stop <= '1';
end if;
end process;
--
-- Rate Multipliers
-- vgck is 1.5Mhz clock
--
p_ratemul_reg : process(go, CLK_6)
begin
-- share a reg here
if (go = '0') then
ratemul_reg <= (others => '0');
elsif rising_edge(CLK_6) then
if (ENA_1_5M = '1') then
ratemul_reg <= ratemul_reg + "1";
end if;
end if;
end process;
p_ratemulx_and : process(ratemul_reg, ratemulx_reg_and)
begin
ratemulx_reg_and(0) <= ratemul_reg(0);
for i in 1 to 9 loop
ratemulx_reg_and(i) <= ratemul_reg(i) and ratemulx_reg_and(i-1);
end loop;
end process;
p_ratemuly_and : process(ratemul_reg, ratemuly_reg_and)
begin
ratemuly_reg_and(0) <= ratemul_reg(0);
for i in 1 to 9 loop
ratemuly_reg_and(i) <= ratemul_reg(i) and ratemuly_reg_and(i-1);
end loop;
end process;
p_ratemulx_rate : process(ratemulx_reg_and, ratemul_reg, dvx_bus)
begin
ratemulx_rate_out(0) <= (not ratemul_reg(0)) and dvx_bus(9);
for i in 1 to 9 loop
ratemulx_rate_out(i) <= (not ratemul_reg(i)) and ratemulx_reg_and(i-1) and dvx_bus(9-i);
end loop;
end process;
p_ratemuly_rate : process(ratemuly_reg_and, ratemul_reg, dvy_bus)
begin
ratemuly_rate_out(0) <= (not ratemul_reg(0)) and dvy_bus(9);
for i in 1 to 9 loop
ratemuly_rate_out(i) <= (not ratemul_reg(i)) and ratemuly_reg_and(i-1) and dvy_bus(9-i);
end loop;
end process;
p_ratemul_op : process
begin
wait until rising_edge(CLK_6);
-- we can afford a register here as the enables are every 4 clocks
if (go = '0') then -- clear
ratemulx_op <= '0';
ratemuly_op <= '0';
else
ratemulx_op <= '1';
if (ratemulx_rate_out = "0000000000") then
ratemulx_op <= '0';
end if;
ratemuly_op <= '1';
if (ratemuly_rate_out = "0000000000") then
ratemuly_op <= '0';
end if;
end if;
end process;
--
-- x/y position counter
--
p_x_pos : process
begin
wait until rising_edge(CLK_6);
if (timer(0) = '0') and (halt_strobe_l = '0') then
xpos_bus <= dvx_bus(11 downto 0);
elsif (ENA_1_5M = '1') and (go = '1') and (ratemulx_op = '1') then
if (dvx_bus(10) = '0') then
xpos_bus <= xpos_bus + "1";
else
xpos_bus <= xpos_bus - "1";
end if;
end if;
end process;
p_y_pos : process
begin
wait until rising_edge(CLK_6);
if (timer(0) = '0') and (halt_strobe_l = '0') then
ypos_bus <= dvy_bus(11 downto 0);
elsif (ENA_1_5M = '1') and (go = '1') and (ratemuly_op = '1') then
if (dvy_bus(10) = '0') then
ypos_bus <= ypos_bus + "1";
else
ypos_bus <= ypos_bus - "1";
end if;
end if;
end process;
--
-- output stages
--
p_output : process(RESET_L, CLK_6)
begin
if (RESET_L = '0') then
X_VECTOR <= "1000000000";
Y_VECTOR <= "1000000000";
Z_VECTOR <= "0000";
BEAM_ON <= '0';
elsif rising_edge(CLK_6) then
-- clamp beam at edges
if (xpos_bus(10) = '0') then
X_VECTOR <= xpos_bus(9 downto 0);
else
for i in 0 to 9 loop
X_VECTOR(i) <= not xpos_bus(11);
end loop;
end if;
if (ypos_bus(10) = '0') then
Y_VECTOR <= ypos_bus(9 downto 0);
else
for i in 0 to 9 loop
Y_VECTOR(i) <= not ypos_bus(11);
end loop;
end if;
BEAM_ON <= '0';
Z_VECTOR <= "0000";
if (xpos_bus(11 downto 10) = "00") and
(ypos_bus(11 downto 10) = "00") then
BEAM_ON <= '1';
if (blank_l = '1') then
Z_VECTOR <= scale;
end if;
end if;
end if;
end process;
end architecture RTL;

180
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/ovo.vhd Normal file
View File

@@ -0,0 +1,180 @@
--------------------------------------------------------------------------------
-- Overlay
--------------------------------------------------------------------------------
-- DO 10/2017
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.base_pack.ALL;
ENTITY ovo IS
GENERIC (
COLS : natural :=32;
LINES : natural :=2;
RGB : unsigned(23 DOWNTO 0) :=x"FFFFFF");
PORT (
-- VGA IN
i_r : IN uv8;
i_g : IN uv8;
i_b : IN uv8;
i_hs : IN std_logic;
i_vs : IN std_logic;
i_de : IN std_logic;
i_en : IN std_logic;
i_clk : IN std_logic;
-- VGA_OUT
o_r : OUT uv8;
o_g : OUT uv8;
o_b : OUT uv8;
o_hs : OUT std_logic;
o_vs : OUT std_logic;
o_de : OUT std_logic;
-- Control
ena : IN std_logic; -- Overlay ON/OFF
-- Probes
in0 : IN unsigned(0 TO COLS*5-1);
in1 : IN unsigned(0 TO COLS*5-1)
);
END ENTITY ovo;
--##############################################################################
ARCHITECTURE rtl OF ovo IS
TYPE arr_slv8 IS ARRAY (natural RANGE <>) OF uv8;
CONSTANT chars : arr_slv8 :=(
x"3E", x"63", x"73", x"7B", x"6F", x"67", x"3E", x"00", -- 0
x"0C", x"0E", x"0C", x"0C", x"0C", x"0C", x"3F", x"00", -- 1
x"1E", x"33", x"30", x"1C", x"06", x"33", x"3F", x"00", -- 2
x"1E", x"33", x"30", x"1C", x"30", x"33", x"1E", x"00", -- 3
x"38", x"3C", x"36", x"33", x"7F", x"30", x"78", x"00", -- 4
x"3F", x"03", x"1F", x"30", x"30", x"33", x"1E", x"00", -- 5
x"1C", x"06", x"03", x"1F", x"33", x"33", x"1E", x"00", -- 6
x"3F", x"33", x"30", x"18", x"0C", x"0C", x"0C", x"00", -- 7
x"1E", x"33", x"33", x"1E", x"33", x"33", x"1E", x"00", -- 8
x"1E", x"33", x"33", x"3E", x"30", x"18", x"0E", x"00", -- 9
x"0C", x"1E", x"33", x"33", x"3F", x"33", x"33", x"00", -- A
x"3F", x"66", x"66", x"3E", x"66", x"66", x"3F", x"00", -- B
x"3C", x"66", x"03", x"03", x"03", x"66", x"3C", x"00", -- C
x"1F", x"36", x"66", x"66", x"66", x"36", x"1F", x"00", -- D
x"7F", x"46", x"16", x"1E", x"16", x"46", x"7F", x"00", -- E
x"7F", x"46", x"16", x"1E", x"16", x"06", x"0F", x"00", -- F
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", --' ' 10
x"00", x"00", x"3F", x"00", x"00", x"3F", x"00", x"00", -- = 11
x"00", x"0C", x"0C", x"3F", x"0C", x"0C", x"00", x"00", -- + 12
x"00", x"00", x"00", x"3F", x"00", x"00", x"00", x"00", -- - 13
x"18", x"0C", x"06", x"03", x"06", x"0C", x"18", x"00", -- < 14
x"06", x"0C", x"18", x"30", x"18", x"0C", x"06", x"00", -- > 15
x"08", x"1C", x"36", x"63", x"41", x"00", x"00", x"00", -- ^ 16
x"08", x"1C", x"36", x"63", x"41", x"00", x"00", x"00", -- v 17
x"18", x"0C", x"06", x"06", x"06", x"0C", x"18", x"00", -- ( 18
x"06", x"0C", x"18", x"18", x"18", x"0C", x"06", x"00", -- ) 19
x"00", x"0C", x"0C", x"00", x"00", x"0C", x"0C", x"00", -- : 1A
x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"00", -- . 1B
x"00", x"00", x"00", x"00", x"00", x"0C", x"0C", x"06", -- , 1C
x"1E", x"33", x"30", x"18", x"0C", x"00", x"0C", x"00", -- ? 1D
x"18", x"18", x"18", x"00", x"18", x"18", x"18", x"00", -- | 1E
x"36", x"36", x"7F", x"36", x"7F", x"36", x"36", x"00"); -- # 1F
SIGNAL vcpt,hcpt,hcpt2 : natural RANGE 0 TO 4095;
SIGNAL vin0,vin1 : unsigned(0 TO COLS*5-1);
SIGNAL t_r,t_g,t_b : uv8;
SIGNAL t_hs,t_vs,t_de : std_logic;
SIGNAL col : uv8;
SIGNAL de : std_logic;
SIGNAL in0s,in1s : unsigned(in0'range);
BEGIN
in0s<=in0 WHEN rising_edge(i_clk);
in1s<=in1 WHEN rising_edge(i_clk);
----------------------------------------------------------
Megamix:PROCESS(i_clk) IS
VARIABLE vin_v : unsigned(0 TO COLS*5-1);
VARIABLE char_v : unsigned(4 DOWNTO 0);
BEGIN
IF rising_edge(i_clk) THEN
IF i_en='1' THEN
----------------------------------
-- Propagate VGA signals. 2 cycles delay
t_r<=i_r;
t_g<=i_g;
t_b<=i_b;
t_hs<=i_hs;
t_vs<=i_vs;
t_de<=i_de;
o_r<=t_r;
o_g<=t_g;
o_b<=t_b;
o_hs<=t_hs;
o_vs<=t_vs;
o_de<=t_de;
----------------------------------
-- Latch sampled values during vertical sync
IF i_vs='1' THEN
vin0<=in0s;
vin1<=in1s;
END IF;
----------------------------------
IF i_vs='1' THEN
vcpt<=0;
de<='0';
ELSIF i_hs='1' AND t_hs='0' AND de='1' THEN
vcpt<=(vcpt+1) MOD 4096;
END IF;
----------------------------------
IF (vcpt/8) MOD 2=0 THEN
vin_v:=vin0;
ELSE
vin_v:=vin1;
END IF;
IF i_hs='1' THEN
hcpt<=0;
ELSIF i_de='1' THEN
hcpt<=(hcpt+1) MOD 4096;
de<='1';
END IF;
hcpt2<=hcpt;
----------------------------------
-- Pick characters
IF hcpt<COLS * 8 AND vcpt<LINES * 8 THEN
char_v:=vin_v((hcpt/8)*5 TO (hcpt/8)*5+4);
ELSE
char_v:="10000"; -- " " : Blank character
END IF;
col<=chars(to_integer(char_v)*8+(vcpt MOD 8));
----------------------------------
-- Insert Overlay
IF ena='1' THEN
IF col(hcpt2 MOD 8)='1' THEN
o_r<=rgb(23 DOWNTO 16);
o_g<=rgb(15 DOWNTO 8);
o_b<=rgb( 7 DOWNTO 0);
END IF;
END IF;
END IF;
END IF;
END PROCESS Megamix;
END ARCHITECTURE rtl;

220
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/fg_sp_dulport_rom.v → Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/p2ram.v
View File

@@ -1,10 +1,10 @@
// megafunction wizard: %ROM: 2-PORT%
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: fg_sp_dulport_rom.v
// File Name: p2ram.v
// Megafunction Name(s):
// altsyncram
//
@@ -36,94 +36,77 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fg_sp_dulport_rom (
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b);
module p2ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input [12:0] address_a;
input [12:0] address_b;
input clock_a;
input clock_b;
output [31:0] q_a;
output [31:0] q_b;
input clock;
input [3:0] data;
input [16:0] rdaddress;
input [16:0] wraddress;
input wren;
output [3:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [31:0] sub_wire3 = 32'h0;
wire [31:0] q_b = sub_wire0[31:0];
wire [31:0] q_a = sub_wire1[31:0];
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (sub_wire2),
.address_b (address_b),
.clock1 (clock_b),
.data_b (sub_wire3),
.wren_b (sub_wire2),
.address_a (address_a),
.data_a (sub_wire3),
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.q_a (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({4{1'b1}}),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
`ifdef NO_PLI
altsyncram_component.init_file = "./rom/gfx1.rif"
`else
altsyncram_component.init_file = "./rom/gfx1.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.numwords_a = 131072,
altsyncram_component.numwords_b = 131072,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 17,
altsyncram_component.widthad_b = 17,
altsyncram_component.width_a = 4,
altsyncram_component.width_b = 4,
altsyncram_component.width_byteena_a = 1;
endmodule
@@ -137,8 +120,8 @@ endmodule
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
@@ -149,91 +132,84 @@ endmodule
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "524288"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./rom/gfx1.hex"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INIT_FILE STRING "./rom/gfx1.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "131072"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "131072"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 13 0 INPUT NODEFVAL "address_a[12..0]"
// Retrieval info: USED_PORT: address_b 0 0 13 0 INPUT NODEFVAL "address_b[12..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 13 0 address_a 0 0 13 0
// Retrieval info: CONNECT: @address_b 0 0 13 0 address_b 0 0 13 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 GND 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 GND 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 GND 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fg_sp_dulport_rom_bb.v TRUE
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 17 0 INPUT NODEFVAL "rdaddress[16..0]"
// Retrieval info: USED_PORT: wraddress 0 0 17 0 INPUT NODEFVAL "wraddress[16..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 17 0 wraddress 0 0 17 0
// Retrieval info: CONNECT: @address_b 0 0 17 0 rdaddress 0 0 17 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q_b 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL p2ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL p2ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL p2ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL p2ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL p2ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL p2ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

365
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/pll.v Normal file
View File

@@ -0,0 +1,365 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 27,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 50,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 27,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 25,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 9,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 2,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

38
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/rom/LLANDER_DVG_ROM.vhd Normal file
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@@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity LLANDER_DVG_ROM is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of LLANDER_DVG_ROM is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"01",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"0F",X"0C",X"0A",X"0E",
X"00",X"01",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"0F",X"0C",X"0A",X"0E",
X"00",X"01",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"0D",X"0F",X"0C",X"0B",X"0E",
X"00",X"01",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"0B",X"0D",X"01",X"00",X"08",X"0C",X"0A",X"0E",
X"00",X"01",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"08",X"0C",X"0A",X"0E",
X"00",X"01",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"09",X"0C",X"0A",X"0E",
X"00",X"01",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"09",X"0C",X"0A",X"0E",
X"00",X"01",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"0A",X"0C",X"0A",X"0E",
X"09",X"02",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"0F",X"0C",X"0A",X"0E",
X"09",X"02",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"0F",X"0C",X"0A",X"0E",
X"09",X"02",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"0D",X"0F",X"0C",X"0B",X"0E",
X"09",X"02",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"0B",X"0D",X"01",X"00",X"08",X"0C",X"0A",X"0E",
X"09",X"02",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"08",X"0C",X"0A",X"0E",
X"09",X"02",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"09",X"0C",X"0A",X"0E",
X"09",X"02",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"09",X"0C",X"0A",X"0E",
X"09",X"02",X"0D",X"0D",X"05",X"06",X"07",X"0D",X"09",X"0D",X"01",X"00",X"0A",X"0C",X"0A",X"0E");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/rom/LLANDER_PROG_ROM_0.vhd Normal file
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@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity LLANDER_PROG_ROM_0 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of LLANDER_PROG_ROM_0 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"6B",X"20",X"13",X"62",X"A9",X"80",X"85",X"5D",X"24",X"97",X"30",X"0F",X"A9",X"00",X"85",X"22",
X"85",X"97",X"24",X"5D",X"10",X"4C",X"20",X"13",X"62",X"D0",X"28",X"A5",X"22",X"D0",X"21",X"20",
X"13",X"62",X"A9",X"F0",X"A2",X"08",X"20",X"5F",X"79",X"A2",X"00",X"86",X"23",X"86",X"A4",X"86",
X"A5",X"A9",X"11",X"85",X"63",X"A9",X"20",X"A6",X"98",X"D0",X"01",X"4A",X"85",X"22",X"D0",X"03",
X"20",X"35",X"62",X"20",X"A9",X"73",X"A2",X"2C",X"A0",X"CA",X"A5",X"21",X"F0",X"04",X"A2",X"A0",
X"A0",X"C3",X"A5",X"22",X"29",X"20",X"F0",X"04",X"A2",X"00",X"A0",X"F0",X"8E",X"00",X"40",X"8C",
X"01",X"40",X"A2",X"40",X"A0",X"04",X"A5",X"86",X"4A",X"90",X"04",X"A2",X"42",X"A0",X"84",X"86",
X"28",X"84",X"27",X"A5",X"22",X"29",X"20",X"D0",X"2D",X"20",X"95",X"67",X"20",X"39",X"65",X"20",
X"67",X"65",X"20",X"AD",X"65",X"A5",X"22",X"29",X"10",X"D0",X"1B",X"24",X"22",X"10",X"1D",X"A5",
X"62",X"29",X"0F",X"F0",X"0B",X"A5",X"29",X"85",X"27",X"A5",X"2A",X"85",X"28",X"20",X"95",X"75",
X"20",X"D6",X"68",X"4C",X"CE",X"60",X"20",X"7E",X"68",X"4C",X"CE",X"60",X"20",X"9D",X"66",X"24",
X"22",X"50",X"18",X"A5",X"23",X"D0",X"0B",X"A5",X"86",X"29",X"0F",X"C9",X"08",X"D0",X"03",X"20",
X"09",X"65",X"20",X"9E",X"68",X"20",X"FF",X"67",X"4C",X"CE",X"60",X"20",X"9F",X"79",X"A0",X"DE",
X"A9",X"4B",X"A2",X"06",X"20",X"A6",X"7E",X"AD",X"00",X"20",X"29",X"02",X"F0",X"FE",X"20",X"2D",
X"65",X"A0",X"02",X"A2",X"F0",X"A5",X"86",X"4A",X"90",X"04",X"A2",X"E1",X"A0",X"42",X"8E",X"03",
X"40",X"8C",X"02",X"40",X"8D",X"00",X"30",X"E6",X"86",X"A2",X"00",X"AD",X"00",X"20",X"29",X"04",
X"D0",X"02",X"A2",X"20",X"A9",X"1F",X"20",X"53",X"79",X"20",X"E6",X"62",X"20",X"14",X"64",X"24",
X"22",X"30",X"37",X"50",X"1F",X"20",X"32",X"6B",X"20",X"3C",X"63",X"20",X"71",X"6B",X"20",X"1B",
X"75",X"A5",X"01",X"C9",X"10",X"D0",X"02",X"A9",X"0F",X"4A",X"09",X"01",X"AA",X"A9",X"30",X"20",
X"53",X"79",X"D0",X"0D",X"A9",X"20",X"A2",X"00",X"20",X"53",X"79",X"A5",X"22",X"29",X"20",X"D0",
X"09",X"20",X"68",X"6C",X"20",X"4F",X"6D",X"20",X"1C",X"71",X"A5",X"22",X"F0",X"5B",X"20",X"AB",
X"62",X"24",X"22",X"30",X"33",X"70",X"55",X"A2",X"00",X"A5",X"86",X"29",X"10",X"D0",X"02",X"A2",
X"10",X"A9",X"0F",X"20",X"5F",X"79",X"2C",X"00",X"24",X"30",X"06",X"A9",X"40",X"85",X"25",X"D0",
X"04",X"06",X"25",X"B0",X"0D",X"24",X"5D",X"10",X"0C",X"20",X"13",X"62",X"A9",X"10",X"85",X"22",
X"D0",X"03",X"4C",X"40",X"60",X"4C",X"62",X"60",X"24",X"62",X"50",X"0E",X"24",X"5C",X"10",X"04",
X"24",X"5D",X"30",X"06",X"20",X"68",X"6C",X"20",X"4F",X"6D",X"A5",X"86",X"4A",X"B0",X"E6",X"E6",
X"56",X"10",X"E2",X"06",X"56",X"A5",X"62",X"85",X"5D",X"4C",X"08",X"60",X"A5",X"5D",X"30",X"28",
X"20",X"AA",X"64",X"24",X"97",X"30",X"0C",X"A5",X"8D",X"C9",X"05",X"90",X"03",X"4C",X"01",X"60",
X"4C",X"62",X"60",X"2C",X"05",X"24",X"30",X"06",X"A9",X"40",X"85",X"68",X"D0",X"F2",X"06",X"68",
X"90",X"EE",X"A9",X"64",X"85",X"56",X"D0",X"E8",X"20",X"E0",X"6B",X"A5",X"5D",X"85",X"62",X"0A",
X"D0",X"07",X"A0",X"00",X"A9",X"50",X"20",X"13",X"63",X"20",X"90",X"6B",X"20",X"94",X"76",X"A2",
X"00",X"86",X"AF",X"86",X"B0",X"86",X"B1",X"A0",X"0A",X"96",X"57",X"88",X"10",X"FB",X"A9",X"20",
X"20",X"53",X"79",X"06",X"22",X"A9",X"01",X"85",X"56",X"A9",X"0A",X"85",X"61",X"A9",X"41",X"85",
X"63",X"D0",X"AD",X"8D",X"00",X"3E",X"A2",X"08",X"86",X"02",X"BD",X"0E",X"78",X"95",X"06",X"BD",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/rom/LLANDER_PROG_ROM_1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity LLANDER_PROG_ROM_1 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of LLANDER_PROG_ROM_1 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"03",X"86",X"41",X"B5",X"33",X"85",X"37",X"0A",X"0A",X"85",X"8B",X"A2",X"4E",X"A9",X"06",X"A0",
X"03",X"24",X"4E",X"70",X"04",X"A9",X"42",X"A0",X"0F",X"84",X"3E",X"20",X"76",X"68",X"A6",X"4F",
X"86",X"3D",X"20",X"E4",X"7E",X"A5",X"27",X"85",X"2B",X"A5",X"28",X"85",X"2C",X"A6",X"37",X"BD",
X"54",X"6C",X"85",X"8B",X"A2",X"47",X"A9",X"00",X"24",X"4E",X"70",X"04",X"A2",X"4E",X"A9",X"7E",
X"20",X"76",X"68",X"20",X"A4",X"7E",X"A5",X"86",X"29",X"10",X"D0",X"0A",X"A0",X"03",X"B1",X"2B",
X"29",X"0F",X"91",X"2B",X"10",X"1A",X"A9",X"65",X"A0",X"07",X"20",X"C9",X"7E",X"A6",X"37",X"BD",
X"45",X"6C",X"0A",X"69",X"A4",X"A8",X"A9",X"57",X"20",X"C9",X"7E",X"A9",X"18",X"20",X"4F",X"7A",
X"A6",X"41",X"CA",X"10",X"8C",X"60",X"18",X"65",X"8B",X"A8",X"8A",X"69",X"00",X"60",X"20",X"2D",
X"7F",X"A2",X"00",X"A9",X"16",X"20",X"34",X"7A",X"A2",X"1C",X"A9",X"00",X"20",X"34",X"7A",X"A2",
X"20",X"20",X"32",X"7A",X"A9",X"AD",X"20",X"57",X"7B",X"A9",X"17",X"4C",X"4F",X"7A",X"A5",X"90",
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X"4C",X"A9",X"00",X"85",X"40",X"4C",X"A4",X"6E",X"86",X"32",X"84",X"31",X"24",X"4E",X"70",X"26",
X"A5",X"02",X"0A",X"A8",X"A2",X"00",X"B1",X"31",X"10",X"01",X"CA",X"18",X"65",X"0F",X"85",X"1D",
X"8A",X"65",X"10",X"85",X"1E",X"C8",X"A2",X"00",X"B1",X"31",X"10",X"01",X"CA",X"18",X"65",X"0D",
X"A8",X"8A",X"65",X"0E",X"D0",X"0C",X"A5",X"0F",X"85",X"1D",X"A5",X"10",X"85",X"1E",X"A4",X"0D",
X"A5",X"0E",X"29",X"0F",X"85",X"20",X"84",X"1F",X"60",X"A5",X"19",X"38",X"E5",X"15",X"85",X"3D");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/rom/LLANDER_PROG_ROM_2.vhd Normal file
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@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity LLANDER_PROG_ROM_2 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of LLANDER_PROG_ROM_2 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"A5",X"17",X"49",X"FF",X"A8",X"A5",X"18",X"49",X"FF",X"AA",X"C8",X"D0",X"01",X"E8",X"98",X"18",
X"65",X"1B",X"A8",X"8A",X"A2",X"00",X"65",X"1C",X"10",X"05",X"98",X"49",X"FF",X"A8",X"CA",X"86",
X"40",X"60",X"20",X"F9",X"6F",X"98",X"A4",X"3D",X"20",X"C0",X"70",X"A5",X"1D",X"38",X"E5",X"15",
X"A4",X"77",X"20",X"EF",X"70",X"86",X"37",X"A4",X"76",X"20",X"F1",X"70",X"18",X"65",X"37",X"85",
X"37",X"24",X"40",X"30",X"0E",X"18",X"65",X"17",X"85",X"48",X"A5",X"18",X"69",X"00",X"85",X"49",
X"4C",X"60",X"70",X"38",X"A5",X"17",X"E5",X"37",X"85",X"48",X"A5",X"18",X"E9",X"00",X"85",X"49",
X"A6",X"1F",X"A5",X"20",X"20",X"9B",X"70",X"10",X"04",X"A2",X"8F",X"86",X"5D",X"60",X"20",X"F9",
X"6F",X"A5",X"3D",X"20",X"C0",X"70",X"A5",X"17",X"38",X"E5",X"1F",X"A4",X"77",X"20",X"EF",X"70",
X"86",X"37",X"A4",X"76",X"20",X"F1",X"70",X"18",X"65",X"37",X"85",X"37",X"18",X"65",X"15",X"85",
X"48",X"A5",X"16",X"69",X"00",X"85",X"49",X"A6",X"1D",X"A5",X"1E",X"85",X"4B",X"A9",X"80",X"24",
X"49",X"10",X"14",X"A5",X"48",X"49",X"FF",X"85",X"48",X"A5",X"49",X"49",X"FF",X"85",X"49",X"E6",
X"48",X"D0",X"02",X"E6",X"49",X"A9",X"00",X"85",X"4C",X"A0",X"00",X"84",X"4D",X"4C",X"02",X"6D",
X"84",X"75",X"20",X"D1",X"70",X"86",X"77",X"A2",X"00",X"86",X"78",X"20",X"D5",X"70",X"86",X"76",
X"60",X"85",X"78",X"A9",X"00",X"A0",X"07",X"26",X"78",X"2A",X"B0",X"0E",X"C5",X"75",X"90",X"02",
X"E5",X"75",X"88",X"10",X"F2",X"26",X"78",X"A6",X"78",X"60",X"E5",X"75",X"38",X"B0",X"F3",X"85",
X"43",X"84",X"42",X"A5",X"43",X"48",X"49",X"FF",X"85",X"43",X"A9",X"00",X"85",X"44",X"85",X"45",
X"A2",X"08",X"06",X"43",X"B0",X"06",X"65",X"42",X"90",X"02",X"E6",X"45",X"CA",X"D0",X"07",X"AA",
X"68",X"85",X"43",X"A5",X"45",X"60",X"0A",X"26",X"45",X"90",X"E7",X"55",X"A9",X"00",X"85",X"55",
X"85",X"57",X"A9",X"0F",X"24",X"4E",X"50",X"02",X"A9",X"03",X"85",X"37",X"A5",X"08",X"24",X"5A",
X"10",X"0D",X"C9",X"20",X"B0",X"1A",X"20",X"2C",X"73",X"B0",X"15",X"C6",X"4F",X"90",X"0B",X"C9",
X"E0",X"90",X"0D",X"20",X"1B",X"73",X"90",X"08",X"E6",X"4F",X"A5",X"4F",X"25",X"37",X"85",X"4F",
X"24",X"4E",X"50",X"03",X"4C",X"3E",X"72",X"A5",X"0A",X"24",X"5C",X"10",X"0A",X"C9",X"40",X"B0",
X"03",X"20",X"54",X"73",X"4C",X"03",X"72",X"C9",X"A5",X"90",X"F9",X"20",X"FE",X"72",X"C9",X"02",
X"90",X"06",X"D0",X"0A",X"E0",X"08",X"B0",X"06",X"20",X"3D",X"73",X"4C",X"03",X"72",X"24",X"5D",
X"10",X"03",X"4C",X"39",X"72",X"A5",X"0F",X"18",X"65",X"51",X"85",X"51",X"A5",X"10",X"29",X"03",
X"65",X"4F",X"29",X"0F",X"AA",X"4A",X"66",X"51",X"4A",X"66",X"51",X"18",X"69",X"02",X"29",X"03",
X"85",X"4F",X"8A",X"29",X"0C",X"48",X"0A",X"0A",X"AA",X"BD",X"E2",X"51",X"38",X"E5",X"53",X"85",
X"48",X"BD",X"E3",X"51",X"E5",X"54",X"85",X"49",X"A9",X"80",X"85",X"4C",X"A0",X"00",X"A6",X"0D",
X"A5",X"0E",X"29",X"0F",X"20",X"FE",X"6C",X"4A",X"66",X"4A",X"4A",X"66",X"4A",X"85",X"4B",X"68",
X"AA",X"BD",X"BC",X"4B",X"85",X"48",X"BD",X"BD",X"4B",X"85",X"49",X"A9",X"00",X"85",X"50",X"85",
X"52",X"85",X"53",X"85",X"54",X"85",X"09",X"85",X"07",X"85",X"4C",X"20",X"04",X"6D",X"84",X"0A",
X"4A",X"66",X"0A",X"66",X"09",X"4A",X"66",X"0A",X"66",X"09",X"A9",X"80",X"85",X"08",X"A9",X"40",
X"85",X"4E",X"60",X"20",X"FE",X"72",X"09",X"00",X"D0",X"2B",X"E0",X"02",X"B0",X"27",X"C0",X"02",
X"B0",X"23",X"A5",X"02",X"38",X"E9",X"07",X"C9",X"03",X"B0",X"1E",X"A5",X"61",X"A2",X"80",X"C9",
X"04",X"90",X"06",X"C9",X"08",X"B0",X"12",X"A2",X"C0",X"A5",X"5F",X"C9",X"04",X"B0",X"0A",X"8A",
X"05",X"5D",X"85",X"5D",X"60",X"24",X"5D",X"10",X"04",X"A9",X"8F",X"85",X"5D",X"60",X"A5",X"0A",
X"24",X"5C",X"30",X"1A",X"C9",X"A5",X"90",X"2A",X"20",X"3D",X"73",X"F0",X"10",X"C9",X"02",X"90",
X"0C",X"20",X"2D",X"65",X"20",X"96",X"6B",X"A2",X"FF",X"9A",X"4C",X"40",X"60",X"60",X"A5",X"53",
X"05",X"54",X"F0",X"0E",X"20",X"54",X"73",X"B0",X"F4",X"A9",X"00",X"85",X"52",X"85",X"53",X"85",
X"54",X"60",X"20",X"FE",X"72",X"A8",X"D0",X"F9",X"E0",X"60",X"B0",X"F5",X"A5",X"0F",X"18",X"65",
X"51",X"85",X"51",X"A5",X"10",X"65",X"4F",X"29",X"03",X"AA",X"06",X"51",X"2A",X"06",X"51",X"2A",
X"48",X"38",X"E9",X"02",X"29",X"0F",X"85",X"4F",X"8A",X"0A",X"0A",X"AA",X"BD",X"BC",X"4B",X"85",
X"48",X"BD",X"BD",X"4B",X"85",X"49",X"A9",X"80",X"85",X"4C",X"A5",X"0E",X"A6",X"0D",X"A0",X"00",
X"20",X"FE",X"6C",X"06",X"4A",X"2A",X"06",X"4A",X"2A",X"85",X"4B",X"A9",X"A3",X"A2",X"78",X"85",
X"49",X"86",X"48",X"20",X"04",X"6D",X"A9",X"18",X"85",X"48",X"A9",X"A1",X"85",X"49",X"A9",X"00",
X"85",X"4C",X"85",X"4E",X"85",X"07",X"85",X"09",X"85",X"50",X"85",X"52",X"20",X"04",X"6D",X"68",
X"29",X"0C",X"0A",X"AA",X"BD",X"22",X"52",X"85",X"48",X"BD",X"23",X"52",X"85",X"49",X"20",X"04",
X"6D",X"85",X"54",X"84",X"53",X"A9",X"80",X"85",X"08",X"A9",X"9E",X"85",X"0A",X"60",X"A0",X"FF",
X"A5",X"7E",X"A6",X"7D",X"C5",X"80",X"90",X"12",X"D0",X"0C",X"A4",X"7F",X"C4",X"7D",X"B0",X"0A",
X"A6",X"7F",X"A4",X"7D",X"90",X"04",X"A5",X"80",X"A6",X"7F",X"60",X"20",X"6B",X"73",X"A5",X"50",
X"18",X"65",X"3D",X"85",X"50",X"A5",X"51",X"65",X"3E",X"85",X"51",X"60",X"20",X"6B",X"73",X"A5",
X"50",X"38",X"E5",X"3D",X"85",X"50",X"A5",X"51",X"E5",X"3E",X"85",X"51",X"60",X"20",X"8A",X"73",
X"A5",X"52",X"18",X"65",X"3F",X"85",X"52",X"A5",X"53",X"65",X"40",X"85",X"53",X"A5",X"54",X"69",
X"00",X"85",X"54",X"60",X"20",X"8A",X"73",X"A5",X"52",X"38",X"E5",X"3F",X"85",X"52",X"A5",X"53",
X"E5",X"40",X"85",X"53",X"A5",X"54",X"E9",X"00",X"85",X"54",X"60",X"A9",X"80",X"85",X"55",X"A5",
X"5F",X"85",X"3D",X"A9",X"00",X"85",X"3E",X"A5",X"5E",X"A2",X"02",X"24",X"4E",X"70",X"02",X"A2",
X"04",X"0A",X"26",X"3D",X"26",X"3E",X"CA",X"D0",X"F8",X"60",X"A9",X"80",X"85",X"57",X"A5",X"61",
X"85",X"3F",X"A9",X"00",X"85",X"40",X"A5",X"60",X"A2",X"02",X"24",X"4E",X"70",X"02",X"A2",X"04",
X"0A",X"26",X"3F",X"26",X"40",X"CA",X"D0",X"F8",X"60",X"A9",X"BA",X"85",X"64",X"A9",X"51",X"85",
X"65",X"A9",X"45",X"85",X"28",X"A9",X"6B",X"85",X"69",X"A9",X"00",X"85",X"27",X"85",X"6A",X"85",
X"37",X"85",X"38",X"85",X"39",X"A9",X"F0",X"85",X"2B",X"A9",X"44",X"85",X"2C",X"20",X"03",X"75",
X"A0",X"00",X"B1",X"64",X"AA",X"C8",X"B1",X"64",X"C9",X"A0",X"90",X"12",X"C9",X"D0",X"90",X"25",
X"F0",X"4F",X"91",X"27",X"88",X"8A",X"49",X"08",X"91",X"27",X"C8",X"C8",X"D0",X"E4",X"38",X"E9",
X"20",X"91",X"27",X"88",X"8A",X"91",X"27",X"C8",X"C8",X"B1",X"64",X"91",X"27",X"C8",X"B1",X"64",
X"91",X"27",X"C8",X"D0",X"CD",X"29",X"0F",X"85",X"3A",X"86",X"3B",X"88",X"20",X"F8",X"74",X"C8",
X"C8",X"98",X"A0",X"00",X"18",X"65",X"64",X"91",X"69",X"E6",X"69",X"A5",X"65",X"69",X"00",X"91",
X"69",X"E6",X"69",X"A5",X"3B",X"0A",X"85",X"64",X"A5",X"3A",X"2A",X"09",X"40",X"85",X"65",X"D0",
X"A1",X"88",X"20",X"F8",X"74",X"A0",X"00",X"C6",X"69",X"B1",X"69",X"85",X"65",X"C6",X"69",X"B1",
X"69",X"85",X"64",X"A6",X"69",X"E0",X"6B",X"D0",X"89",X"E6",X"37",X"A2",X"04",X"E4",X"37",X"D0",
X"81",X"A9",X"00",X"85",X"37",X"91",X"27",X"C8",X"A9",X"D0",X"91",X"27",X"C8",X"20",X"F8",X"74",
X"E6",X"39",X"A2",X"04",X"E4",X"39",X"F0",X"03",X"4C",X"CD",X"73",X"A9",X"F0",X"85",X"64",X"A9",
X"44",X"85",X"65",X"A5",X"38",X"18",X"65",X"2B",X"85",X"2B",X"D0",X"02",X"E6",X"2C",X"A0",X"07",
X"B1",X"64",X"91",X"2B",X"88",X"10",X"F9",X"A9",X"7E",X"85",X"64",X"A9",X"4E",X"85",X"65",X"A9",
X"00",X"85",X"27",X"A9",X"47",X"85",X"28",X"A0",X"00",X"A2",X"00",X"B1",X"64",X"E0",X"01",X"D0",
X"05",X"38",X"E9",X"20",X"D0",X"16",X"E0",X"07",X"D0",X"12",X"29",X"03",X"85",X"37",X"88",X"B1",
X"64",X"46",X"37",X"6A",X"46",X"37",X"6A",X"91",X"27",X"C8",X"A9",X"04",X"91",X"27",X"E8",X"8A",
X"29",X"07",X"AA",X"C8",X"C0",X"20",X"90",X"D3",X"A5",X"21",X"F0",X"2B",X"A2",X"05",X"86",X"37",
X"0A",X"AA",X"CA",X"CA",X"A9",X"40",X"85",X"27",X"A9",X"47",X"85",X"28",X"BD",X"6A",X"5E",X"BC",
X"69",X"5E",X"20",X"A4",X"7E",X"A6",X"65",X"A4",X"64",X"20",X"F2",X"79",X"A5",X"2C",X"A4",X"2B",
X"20",X"CD",X"7E",X"C6",X"37",X"10",X"EE",X"60",X"98",X"18",X"65",X"27",X"85",X"27",X"90",X"02",
X"E6",X"28",X"60",X"A5",X"28",X"4A",X"29",X"0F",X"09",X"C0",X"AA",X"A5",X"27",X"6A",X"A4",X"38",
X"91",X"2B",X"8A",X"C8",X"91",X"2B",X"C8",X"84",X"38",X"60",X"A8",X"A2",X"03",X"86",X"39",X"A2",
X"02",X"B5",X"5F",X"B4",X"5E",X"84",X"37",X"A0",X"09",X"86",X"3A",X"AA",X"20",X"C6",X"79",X"48",
X"8A",X"A6",X"39",X"95",X"A7",X"94",X"A8",X"68",X"95",X"A6",X"A6",X"3A",X"A0",X"02",X"05",X"94",
X"05",X"93",X"F0",X"07",X"B5",X"5A",X"0A",X"A9",X"00",X"2A",X"A8",X"8A",X"4A",X"AA",X"94",X"9A",
X"A9",X"00",X"85",X"39",X"A6",X"3A",X"CA",X"CA",X"10",X"C7",X"20",X"FE",X"72",X"86",X"37",X"24",
X"4E",X"50",X"06",X"06",X"37",X"2A",X"06",X"37",X"2A",X"AA",X"A4",X"37",X"20",X"C2",X"79",X"85",
X"AF",X"86",X"B0",X"84",X"B1",X"60",X"A2",X"15",X"24",X"5D",X"70",X"0A",X"A2",X"05",X"A5",X"5D",
X"29",X"0F",X"D0",X"02",X"A2",X"50",X"F8",X"8A",X"18",X"65",X"A4",X"85",X"A4",X"A5",X"A5",X"69",
X"00",X"85",X"A5",X"D8",X"60",X"A2",X"0C",X"A9",X"00",X"85",X"8F",X"8A",X"4A",X"A8",X"B9",X"8D",
X"76",X"C5",X"56",X"90",X"70",X"86",X"3A",X"20",X"2F",X"76",X"E0",X"0C",X"D0",X"03",X"18",X"65",
X"3D",X"20",X"BF",X"76",X"86",X"19",X"84",X"1A",X"A6",X"3A",X"E8",X"20",X"2F",X"76",X"CA",X"E0",
X"0C",X"D0",X"03",X"18",X"65",X"3F",X"20",X"BF",X"76",X"86",X"1B",X"84",X"1C",X"98",X"10",X"0B",
X"49",X"FF",X"A8",X"8A",X"49",X"FF",X"AA",X"E8",X"D0",X"01",X"C8",X"C0",X"04",X"B0",X"3A",X"20",
X"43",X"78",X"A0",X"00",X"A6",X"3A",X"E0",X"0C",X"D0",X"13",X"A5",X"56",X"29",X"07",X"0A",X"AA",
X"BD",X"9E",X"4E",X"91",X"27",X"C8",X"BD",X"9F",X"4E",X"91",X"27",X"D0",X"13",X"20",X"2D",X"76",
X"98",X"A4",X"37",X"91",X"27",X"C8",X"E8",X"20",X"2D",X"76",X"98",X"CA",X"A4",X"37",X"91",X"27",
X"20",X"38",X"78",X"A6",X"3A",X"CA",X"CA",X"10",X"82",X"A5",X"56",X"49",X"7F",X"C9",X"40",X"90",
X"0B",X"4A",X"4A",X"4A",X"09",X"08",X"AA",X"A9",X"20",X"4C",X"53",X"79",X"60",X"84",X"37",X"A5",
X"91",X"F0",X"1B",X"C9",X"02",X"90",X"10",X"F0",X"07",X"BD",X"7F",X"76",X"BC",X"10",X"4F",X"60",
X"BD",X"71",X"76",X"BC",X"04",X"4F",X"60",X"BD",X"63",X"76",X"BC",X"F8",X"4E",X"60",X"BD",X"55",
X"76",X"BC",X"EC",X"4E",X"60",X"00",X"FE",X"FF",X"FF",X"FE",X"00",X"FF",X"00",X"00",X"02",X"02",
X"FF",X"00",X"03",X"02",X"01",X"00",X"01",X"FC",X"01",X"FF",X"FF",X"02",X"00",X"00",X"FF",X"00",
X"02",X"FF",X"00",X"FD",X"00",X"01",X"00",X"FF",X"FF",X"00",X"FF",X"03",X"00",X"00",X"03",X"01",
X"FF",X"FB",X"00",X"01",X"FF",X"03",X"01",X"FF",X"FD",X"01",X"01",X"00",X"03",X"5D",X"60",X"64",
X"6D",X"70",X"74",X"7F",X"A5",X"61",X"4A",X"4A",X"4A",X"C9",X"08",X"90",X"02",X"A9",X"07",X"85",
X"3F",X"A5",X"5F",X"4A",X"4A",X"C9",X"08",X"90",X"02",X"A9",X"07",X"24",X"5A",X"30",X"05",X"49",
X"FF",X"18",X"69",X"01",X"85",X"3D",X"A5",X"74",X"4A",X"4A",X"29",X"03",X"85",X"91",X"60",X"A0",
X"00",X"85",X"38",X"0A",X"A5",X"56",X"85",X"37",X"90",X"02",X"A0",X"FF",X"84",X"39",X"A2",X"00",
X"A0",X"00",X"46",X"37",X"B0",X"03",X"D0",X"0A",X"60",X"18",X"8A",X"65",X"38",X"AA",X"98",X"65",
X"39",X"A8",X"06",X"38",X"26",X"39",X"4C",X"D2",X"76",X"00",X"32",X"5F",X"9A",X"B5",X"CD",X"EE",
X"FB",X"FF",X"00",X"80",X"C0",X"40",X"00",X"02",X"05",X"08",X"0B",X"0D",X"0F",X"10",X"11",X"12",
X"13",X"14",X"16",X"18",X"1A",X"1C",X"FF",X"EE",X"0C",X"EB",X"08",X"EA",X"04",X"E9",X"FF",X"EA",
X"FB",X"EB",X"F8",X"ED",X"F3",X"F1",X"F0",X"F5",X"EE",X"F8",X"EB",X"F8",X"00",X"F9",X"FD",X"F9",
X"FC",X"FA",X"FB",X"F8",X"00",X"F8",X"FF",X"F8",X"FD",X"F9",X"FC",X"F8",X"00",X"F9",X"FE",X"F9",
X"FD",X"FA",X"FC",X"F8",X"00",X"F8",X"FF",X"F4",X"12",X"F1",X"10",X"ED",X"0D",X"EB",X"08",X"EA",
X"05",X"E9",X"01",X"EA",X"FC",X"EB",X"F8",X"EE",X"F5",X"F0",X"F1",X"F2",X"EE",X"F8",X"EA",X"FB",
X"EA",X"FD",X"EA",X"ED",X"F3",X"F1",X"F0",X"F7",X"EE",X"F8",X"EB",X"FD",X"EA",X"03",X"EA",X"05",
X"EA",X"08",X"EA",X"04",X"EE",X"FC",X"F9",X"FD",X"F8",X"FF",X"F8",X"01",X"F8",X"FC",X"FA",X"FD",
X"F9",X"FE",X"F9",X"00",X"F7",X"01",X"F8",X"FD",X"F8",X"F9",X"FC",X"F9",X"FA",X"FB",X"FA",X"FC",
X"F9",X"FD",X"F9",X"EA",X"FC",X"EB",X"F8",X"03",X"F9",X"04",X"F9",X"05",X"F9",X"06",X"FB",X"FB",
X"EA",X"FD",X"EA",X"03",X"EA",X"08",X"EB",X"0C",X"EE",X"0F",X"F0",X"13",X"F3",X"15",X"F8",X"16",
X"FB",X"17",X"FF",X"16",X"04",X"10",X"F1",X"12",X"F4",X"15",X"F8",X"16",X"FC",X"03",X"F9",X"04",
X"F9",X"05",X"FA",X"07",X"FA",X"07",X"FC",X"02",X"F8",X"FF",X"F8",X"00",X"F7",X"02",X"F9",X"03",
X"F9",X"04",X"FA",X"FF",X"F8",X"01",X"F8",X"08",X"FE",X"08",X"FF",X"08",X"00",X"07",X"02",X"07",
X"FC",X"07",X"FD",X"08",X"00",X"08",X"01",X"0C",X"EE",X"0F",X"F0",X"13",X"F3",X"15",X"F8",X"16",
X"FB",X"17",X"FF",X"16",X"04",X"15",X"08",X"12",X"F4",X"15",X"F8",X"16",X"FC",X"17",X"01",X"16",
X"05",X"15",X"08",X"13",X"0D",X"0F",X"10",X"0B",X"12",X"08",X"FF",X"08",X"00",X"06",X"FC",X"07");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/rom/LLANDER_PROG_ROM_3.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity LLANDER_PROG_ROM_3 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of LLANDER_PROG_ROM_3 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"FD",X"07",X"FE",X"06",X"FB",X"07",X"FC",X"3C",X"45",X"BC",X"45",X"5E",X"46",X"B4",X"46",X"00",
X"10",X"80",X"AA",X"00",X"32",X"10",X"00",X"BF",X"90",X"04",X"29",X"0F",X"F0",X"05",X"29",X"0F",
X"18",X"69",X"01",X"08",X"0A",X"A0",X"00",X"AA",X"BD",X"A2",X"57",X"91",X"27",X"BD",X"A3",X"57",
X"C8",X"91",X"27",X"20",X"38",X"78",X"28",X"60",X"98",X"38",X"65",X"27",X"85",X"27",X"90",X"02",
X"E6",X"28",X"60",X"A5",X"1A",X"C9",X"80",X"90",X"11",X"49",X"FF",X"85",X"1A",X"A5",X"19",X"49",
X"FF",X"69",X"00",X"85",X"19",X"90",X"02",X"E6",X"1A",X"38",X"26",X"37",X"A5",X"1C",X"C9",X"80",
X"90",X"11",X"49",X"FF",X"85",X"1C",X"A5",X"1B",X"49",X"FF",X"69",X"00",X"85",X"1B",X"90",X"02",
X"E6",X"1C",X"38",X"26",X"37",X"A5",X"19",X"C5",X"1B",X"A5",X"1A",X"E5",X"1C",X"A2",X"00",X"B0",
X"02",X"A2",X"02",X"B5",X"1A",X"A0",X"09",X"C9",X"02",X"B0",X"09",X"88",X"16",X"19",X"F0",X"03",
X"2A",X"10",X"F4",X"2A",X"95",X"1A",X"98",X"0A",X"66",X"37",X"2A",X"66",X"37",X"2A",X"0A",X"85",
X"37",X"8A",X"49",X"02",X"AA",X"C0",X"09",X"B0",X"07",X"C8",X"16",X"19",X"36",X"1A",X"10",X"F5",
X"A0",X"00",X"A5",X"1B",X"91",X"27",X"A5",X"37",X"29",X"FC",X"05",X"1C",X"C8",X"91",X"27",X"A5",
X"19",X"C8",X"91",X"27",X"A5",X"37",X"29",X"02",X"0A",X"05",X"8F",X"05",X"1A",X"C8",X"91",X"27",
X"4C",X"38",X"78",X"A2",X"02",X"BD",X"01",X"24",X"0A",X"B5",X"B7",X"29",X"1F",X"B0",X"37",X"F0",
X"10",X"C9",X"1B",X"B0",X"0A",X"A8",X"A5",X"BA",X"29",X"07",X"C9",X"07",X"98",X"90",X"02",X"E9",
X"01",X"95",X"B7",X"AD",X"00",X"20",X"29",X"04",X"D0",X"04",X"A9",X"F0",X"85",X"B4",X"A5",X"B4",
X"F0",X"08",X"C6",X"B4",X"A9",X"00",X"95",X"B7",X"95",X"B3",X"18",X"B5",X"B3",X"F0",X"23",X"D6",
X"B3",X"D0",X"1F",X"38",X"B0",X"1C",X"C9",X"1B",X"B0",X"09",X"B5",X"B7",X"69",X"20",X"90",X"D1",
X"F0",X"01",X"18",X"A9",X"1F",X"B0",X"CA",X"95",X"B7",X"B5",X"B3",X"F0",X"01",X"38",X"A9",X"78",
X"95",X"B3",X"90",X"04",X"F6",X"B6",X"E6",X"B2",X"CA",X"CA",X"10",X"99",X"E6",X"BA",X"A5",X"BA",
X"4A",X"A5",X"B2",X"B0",X"0C",X"F0",X"0A",X"C9",X"10",X"B0",X"02",X"69",X"FF",X"69",X"EF",X"85",
X"B2",X"0A",X"60",X"25",X"89",X"86",X"3C",X"05",X"3C",X"8D",X"00",X"3C",X"85",X"89",X"60",X"25",
X"88",X"86",X"3C",X"05",X"3C",X"8D",X"00",X"32",X"85",X"88",X"60",X"AD",X"03",X"28",X"29",X"03",
X"AA",X"BD",X"9B",X"79",X"85",X"99",X"A2",X"00",X"EE",X"00",X"58",X"F0",X"06",X"AD",X"02",X"28",
X"29",X"03",X"AA",X"86",X"21",X"38",X"AD",X"01",X"28",X"2A",X"2A",X"2D",X"00",X"28",X"29",X"0F",
X"69",X"00",X"C9",X"09",X"90",X"02",X"A9",X"00",X"85",X"98",X"60",X"01",X"04",X"05",X"06",X"A2",
X"0C",X"A5",X"98",X"18",X"69",X"18",X"20",X"34",X"7A",X"A9",X"17",X"20",X"4F",X"7A",X"A9",X"05",
X"20",X"4F",X"7A",X"A5",X"86",X"29",X"20",X"F0",X"07",X"A2",X"00",X"A9",X"04",X"4C",X"34",X"7A",
X"60",X"00",X"84",X"37",X"A0",X"0F",X"86",X"38",X"A9",X"00",X"85",X"92",X"85",X"93",X"85",X"94",
X"F8",X"06",X"37",X"26",X"38",X"A5",X"92",X"65",X"92",X"85",X"92",X"A5",X"93",X"65",X"93",X"85",
X"93",X"A5",X"94",X"65",X"94",X"85",X"94",X"88",X"10",X"E7",X"A4",X"94",X"A6",X"93",X"A5",X"92",
X"D8",X"60",X"86",X"2C",X"84",X"2B",X"A9",X"00",X"4A",X"A8",X"B1",X"2B",X"85",X"39",X"29",X"7F",
X"AA",X"98",X"0A",X"A8",X"BD",X"A2",X"57",X"91",X"27",X"C8",X"BD",X"A3",X"57",X"91",X"27",X"C8",
X"98",X"24",X"39",X"10",X"E3",X"18",X"65",X"27",X"85",X"27",X"90",X"02",X"E6",X"28",X"98",X"4A",
X"65",X"2B",X"85",X"2B",X"90",X"02",X"E6",X"2C",X"60",X"A9",X"17",X"20",X"4F",X"7A",X"A9",X"03",
X"D0",X"1D",X"A9",X"80",X"48",X"8A",X"18",X"69",X"0C",X"A8",X"A9",X"55",X"69",X"00",X"A6",X"27",
X"86",X"2F",X"A6",X"28",X"86",X"30",X"20",X"CD",X"7E",X"20",X"10",X"7F",X"68",X"30",X"58",X"C9",
X"18",X"90",X"03",X"0A",X"D0",X"48",X"48",X"A6",X"21",X"F0",X"10",X"CA",X"7D",X"A1",X"5F",X"AA",
X"BD",X"A4",X"5F",X"A2",X"00",X"0A",X"90",X"0F",X"CA",X"B0",X"0C",X"E9",X"08",X"C9",X"0C",X"B0",
X"13",X"AA",X"BD",X"6D",X"69",X"A2",X"00",X"18",X"A0",X"02",X"71",X"2F",X"91",X"2F",X"8A",X"C8",
X"71",X"2F",X"91",X"2F",X"68",X"0A",X"C9",X"30",X"B0",X"14",X"A6",X"21",X"F0",X"10",X"CA",X"18",
X"7D",X"00",X"58",X"AA",X"BC",X"04",X"58",X"BD",X"05",X"58",X"AA",X"4C",X"F2",X"79",X"AA",X"BC",
X"2B",X"69",X"BD",X"2C",X"69",X"D0",X"F3",X"60",X"48",X"8A",X"48",X"98",X"48",X"D8",X"AD",X"00",
X"2C",X"38",X"E5",X"83",X"B0",X"04",X"C6",X"83",X"A9",X"00",X"C5",X"84",X"90",X"04",X"E6",X"84",
X"A5",X"84",X"AA",X"38",X"E5",X"82",X"90",X"0A",X"4A",X"4A",X"F0",X"0A",X"86",X"82",X"E6",X"85",
X"D0",X"04",X"69",X"03",X"30",X"F6",X"E6",X"74",X"A5",X"73",X"C9",X"03",X"B0",X"0D",X"8D",X"00",
X"34",X"A5",X"00",X"45",X"C1",X"45",X"C2",X"C9",X"85",X"F0",X"03",X"4C",X"EB",X"7A",X"20",X"D3",
X"78",X"90",X"06",X"A2",X"20",X"A9",X"FF",X"D0",X"04",X"A9",X"DF",X"A2",X"00",X"20",X"5F",X"79",
X"24",X"22",X"50",X"2F",X"C6",X"87",X"D0",X"2B",X"A9",X"FA",X"85",X"87",X"E6",X"8D",X"F8",X"18",
X"A2",X"00",X"A0",X"02",X"A9",X"08",X"75",X"9E",X"95",X"9E",X"A9",X"00",X"E8",X"88",X"10",X"F6",
X"A5",X"9C",X"18",X"69",X"01",X"C9",X"60",X"90",X"02",X"A9",X"00",X"85",X"9C",X"A5",X"9D",X"69",
X"00",X"85",X"9D",X"D8",X"A5",X"22",X"D0",X"0E",X"A5",X"74",X"A2",X"1F",X"4A",X"90",X"02",X"A2",
X"10",X"A9",X"00",X"20",X"5F",X"79",X"C6",X"8A",X"D0",X"06",X"A9",X"06",X"85",X"8A",X"E6",X"73",
X"68",X"A8",X"68",X"AA",X"68",X"40",X"00",X"A0",X"02",X"38",X"08",X"88",X"84",X"38",X"18",X"65",
X"38",X"28",X"AA",X"08",X"86",X"37",X"B5",X"00",X"4A",X"4A",X"4A",X"4A",X"28",X"20",X"18",X"78",
X"A5",X"38",X"D0",X"01",X"18",X"A6",X"37",X"B5",X"00",X"20",X"18",X"78",X"A6",X"37",X"CA",X"C6",
X"38",X"10",X"E0",X"60",X"A2",X"FF",X"9A",X"D8",X"A9",X"00",X"8D",X"00",X"3C",X"AA",X"95",X"00",
X"E8",X"D0",X"FB",X"AD",X"00",X"20",X"4A",X"4A",X"B0",X"03",X"4C",X"B9",X"7B",X"A9",X"85",X"85",
X"00",X"85",X"C1",X"85",X"C2",X"A9",X"FF",X"85",X"83",X"A9",X"06",X"85",X"8A",X"A9",X"02",X"85",
X"9A",X"85",X"9B",X"8D",X"00",X"34",X"4C",X"01",X"60",X"A2",X"11",X"9A",X"8A",X"85",X"00",X"A0",
X"00",X"A2",X"01",X"C8",X"B9",X"00",X"00",X"D0",X"23",X"E8",X"D0",X"F7",X"BA",X"8A",X"8D",X"00",
X"34",X"C8",X"D9",X"00",X"00",X"D0",X"12",X"A2",X"00",X"96",X"00",X"C8",X"D0",X"05",X"0A",X"A2",
X"00",X"B0",X"0A",X"AA",X"9A",X"96",X"00",X"D0",X"D8",X"59",X"00",X"00",X"AA",X"8A",X"A0",X"10",
X"29",X"0F",X"F0",X"02",X"A0",X"20",X"8A",X"A2",X"10",X"29",X"F0",X"F0",X"02",X"A2",X"20",X"98",
X"9A",X"AA",X"8E",X"00",X"3C",X"A0",X"0C",X"A2",X"64",X"2C",X"00",X"20",X"70",X"FB",X"2C",X"00",
X"20",X"50",X"FB",X"8D",X"00",X"34",X"CA",X"D0",X"F0",X"C0",X"05",X"D0",X"03",X"8E",X"00",X"3C",
X"88",X"D0",X"E4",X"A8",X"30",X"05",X"09",X"80",X"BA",X"10",X"D7",X"C9",X"90",X"D0",X"05",X"BA",
X"E0",X"10",X"F0",X"06",X"8D",X"00",X"34",X"4C",X"34",X"7C",X"A2",X"FF",X"9A",X"20",X"59",X"7E",
X"A8",X"91",X"27",X"C8",X"D0",X"FB",X"E6",X"28",X"A6",X"28",X"E0",X"48",X"90",X"F3",X"20",X"59",
X"7E",X"A9",X"11",X"85",X"37",X"84",X"BC",X"91",X"27",X"98",X"AA",X"C8",X"F0",X"06",X"B1",X"27",
X"D0",X"2B",X"F0",X"F7",X"8A",X"A8",X"A5",X"37",X"8D",X"00",X"34",X"D1",X"27",X"D0",X"1C",X"A9",
X"00",X"91",X"27",X"A5",X"37",X"C8",X"D0",X"03",X"0A",X"B0",X"06",X"85",X"37",X"91",X"27",X"D0",
X"D8",X"E6",X"28",X"A5",X"28",X"C9",X"48",X"90",X"C8",X"B0",X"1E",X"51",X"27",X"A2",X"00",X"48",
X"29",X"F0",X"F0",X"02",X"A2",X"02",X"68",X"29",X"0F",X"F0",X"01",X"E8",X"8A",X"A6",X"28",X"E0",
X"44",X"90",X"02",X"0A",X"0A",X"05",X"BC",X"85",X"BC",X"A5",X"BC",X"8D",X"00",X"32",X"A9",X"03",
X"85",X"56",X"18",X"A9",X"10",X"66",X"BC",X"08",X"90",X"01",X"0A",X"8D",X"00",X"3C",X"A0",X"50",
X"20",X"7F",X"7E",X"8E",X"00",X"3C",X"A0",X"28",X"20",X"7F",X"7E",X"28",X"C6",X"56",X"10",X"E3",
X"66",X"BC",X"8D",X"00",X"34",X"D0",X"FB",X"A9",X"48",X"85",X"2C",X"20",X"59",X"7E",X"85",X"2B",
X"85",X"BC",X"85",X"BB",X"20",X"2D",X"7F",X"A9",X"12",X"20",X"62",X"7E",X"A2",X"37",X"8A",X"0A",
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X"98",X"B0",X"2E",X"F0",X"2B",X"85",X"BC",X"86",X"39",X"A9",X"34",X"38",X"E5",X"39",X"4A",X"85",
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X"AE",X"7F",X"7F",X"AC",X"7E",X"7F",X"20",X"F2",X"79",X"A9",X"00",X"85",X"56",X"85",X"39",X"85",
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X"00",X"34",X"A2",X"14",X"2C",X"00",X"20",X"70",X"FB",X"2C",X"00",X"20",X"50",X"FB",X"CA",X"D0",
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X"0F",X"F8",X"CB",X"FB",X"90",X"A1",X"00",X"02",X"00",X"90",X"00",X"00",X"0F",X"FD",X"F4",X"A1",
X"76",X"01",X"00",X"70",X"00",X"00",X"38",X"32",X"2E",X"00",X"32",X"AA",X"34",X"7F",X"76",X"7F",
X"11",X"12",X"14",X"18",X"00",X"01",X"03",X"07",X"0F",X"00",X"80",X"A1",X"00",X"02",X"00",X"90",
X"00",X"00",X"20",X"73",X"20",X"C3",X"07",X"E0",X"00",X"A0",X"00",X"00",X"00",X"90",X"00",X"00",
X"FF",X"92",X"FF",X"C2",X"FC",X"77",X"FC",X"C3",X"FE",X"87",X"FE",X"C7",X"FE",X"83",X"FE",X"C7",
X"FC",X"73",X"FC",X"C3",X"FF",X"96",X"FF",X"C2",X"FF",X"92",X"01",X"00",X"FF",X"96",X"FF",X"C6",
X"FC",X"73",X"FC",X"C7",X"FE",X"83",X"FE",X"C3",X"FE",X"87",X"FE",X"C3",X"FC",X"77",X"FC",X"C7",
X"FF",X"92",X"FF",X"C6",X"80",X"A1",X"00",X"02",X"00",X"90",X"00",X"00",X"06",X"C0",X"00",X"B0",
X"08",X"C0",X"00",X"D0",X"0A",X"C0",X"00",X"D0",X"CB",X"FB",X"CF",X"FB",X"00",X"D0",X"8A",X"7F",
X"98",X"7F",X"D4",X"7F",X"0E",X"3C",X"1A",X"00",X"57",X"00",X"A8",X"7A",X"84",X"7B",X"84",X"7B");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/rom/LLANDER_VEC_ROM_0.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity LLANDER_VEC_ROM_0 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of LLANDER_VEC_ROM_0 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"80",X"27",X"00",X"05",X"80",X"22",X"80",X"C6",X"80",X"22",X"00",X"C0",X"80",X"22",X"80",X"C2",
X"00",X"20",X"80",X"C2",X"80",X"26",X"80",X"C2",X"80",X"26",X"00",X"C0",X"80",X"26",X"80",X"C6",
X"00",X"20",X"80",X"C6",X"00",X"D0",X"00",X"36",X"40",X"04",X"C7",X"F2",X"80",X"22",X"80",X"C4",
X"C2",X"F3",X"80",X"20",X"80",X"C2",X"C3",X"F6",X"80",X"26",X"80",X"C0",X"C6",X"F7",X"80",X"24",
X"80",X"C6",X"00",X"D0",X"40",X"36",X"00",X"00",X"80",X"21",X"80",X"C7",X"80",X"22",X"00",X"C5",
X"80",X"23",X"80",X"C1",X"00",X"21",X"80",X"C2",X"80",X"25",X"80",X"C3",X"80",X"26",X"00",X"C1",
X"80",X"27",X"80",X"C5",X"00",X"25",X"80",X"C6",X"00",X"D0",X"00",X"36",X"80",X"00",X"80",X"20",
X"80",X"C7",X"00",X"22",X"80",X"C5",X"80",X"23",X"80",X"C0",X"80",X"21",X"00",X"C2",X"80",X"24",
X"80",X"C3",X"00",X"26",X"80",X"C1",X"80",X"27",X"80",X"C4",X"80",X"25",X"00",X"C6",X"00",X"D0",
X"05",X"FE",X"C5",X"F9",X"80",X"23",X"00",X"C0",X"C1",X"F9",X"00",X"20",X"80",X"C3",X"C1",X"FD",
X"80",X"27",X"00",X"C0",X"C5",X"FD",X"00",X"20",X"80",X"C7",X"00",X"D0",X"00",X"36",X"C0",X"04",
X"80",X"21",X"00",X"C6",X"80",X"23",X"80",X"C4",X"00",X"22",X"80",X"C1",X"80",X"20",X"80",X"C3",
X"80",X"25",X"00",X"C2",X"80",X"27",X"80",X"C0",X"00",X"26",X"80",X"C5",X"80",X"24",X"80",X"C7",
X"00",X"D0",X"00",X"36",X"40",X"04",X"00",X"21",X"80",X"C6",X"80",X"23",X"80",X"C5",X"80",X"22",
X"00",X"C1",X"80",X"21",X"80",X"C3",X"00",X"25",X"80",X"C2",X"80",X"27",X"80",X"C1",X"80",X"26",
X"00",X"C5",X"80",X"25",X"80",X"C7",X"00",X"D0",X"00",X"36",X"40",X"00",X"80",X"20",X"80",X"C6",
X"C6",X"F3",X"80",X"22",X"80",X"C0",X"C3",X"F2",X"80",X"24",X"80",X"C2",X"C2",X"F7",X"80",X"26",
X"80",X"C4",X"C7",X"F6",X"00",X"D0",X"00",X"C4",X"C0",X"33",X"40",X"05",X"80",X"26",X"00",X"C0",
X"80",X"26",X"00",X"00",X"80",X"26",X"00",X"C0",X"00",X"10",X"00",X"C7",X"C0",X"33",X"00",X"C0",
X"00",X"10",X"00",X"C3",X"00",X"10",X"00",X"07",X"C6",X"F9",X"00",X"F1",X"C0",X"FD",X"60",X"46",
X"00",X"00",X"C0",X"FD",X"00",X"F1",X"C2",X"F9",X"00",X"F9",X"80",X"25",X"00",X"C7",X"40",X"33",
X"00",X"C0",X"80",X"25",X"00",X"C3",X"80",X"21",X"00",X"07",X"00",X"D0",X"13",X"C4",X"80",X"24",
X"80",X"06",X"80",X"22",X"80",X"C4",X"80",X"22",X"80",X"04",X"80",X"22",X"80",X"C4",X"00",X"15",
X"00",X"C7",X"C0",X"37",X"C0",X"C0",X"00",X"11",X"00",X"C3",X"00",X"15",X"00",X"07",X"80",X"26",
X"80",X"C7",X"00",X"16",X"00",X"01",X"C5",X"F2",X"60",X"42",X"80",X"04",X"C0",X"F9",X"00",X"F5",
X"C0",X"34",X"40",X"C2",X"C0",X"36",X"80",X"00",X"00",X"26",X"80",X"C6",X"40",X"33",X"C0",X"C4",
X"00",X"25",X"80",X"C3",X"00",X"21",X"80",X"07",X"00",X"D0",X"22",X"C4",X"40",X"33",X"C0",X"06",
X"80",X"26",X"00",X"C1",X"80",X"26",X"00",X"01",X"80",X"26",X"00",X"C1",X"00",X"15",X"00",X"C7",
X"C0",X"33",X"80",X"C5",X"00",X"11",X"00",X"C3",X"00",X"15",X"00",X"07",X"40",X"30",X"00",X"C6",
X"00",X"12",X"00",X"05",X"C1",X"F6",X"40",X"46",X"C0",X"00",X"C1",X"F6",X"00",X"12",X"00",X"05",
X"C3",X"F3",X"05",X"F2",X"80",X"26",X"00",X"C6",X"40",X"33",X"40",X"C5",X"80",X"24",X"80",X"C3",
X"80",X"20",X"80",X"07",X"00",X"D0",X"35",X"C4",X"80",X"25",X"00",X"06",X"00",X"22",X"80",X"C5",
X"00",X"22",X"80",X"05",X"00",X"22",X"80",X"C5",X"00",X"15",X"00",X"C7",X"40",X"37",X"80",X"C2",
X"C1",X"F1",X"05",X"F5",X"40",X"36",X"00",X"C5",X"00",X"06",X"00",X"02",X"C5",X"F1",X"40",X"42",
X"A0",X"05",X"C5",X"F2",X"00",X"16",X"00",X"01",X"40",X"30",X"40",X"C2",X"40",X"36",X"C0",X"01",
X"00",X"27",X"80",X"C5",X"80",X"32",X"00",X"C6",X"80",X"20",X"80",X"C3",X"80",X"24",X"80",X"07",
X"00",X"D0",X"48",X"C4",X"01",X"FD",X"C5",X"F9",X"05",X"F9",X"C5",X"F9",X"C5",X"F5",X"C3",X"FF",
X"C1",X"F1",X"05",X"F5",X"00",X"36",X"C0",X"C4",X"00",X"06",X"00",X"02",X"C5",X"F1",X"C0",X"33",
X"C0",X"07",X"C5",X"F1",X"00",X"06",X"00",X"02",X"C0",X"30",X"00",X"C2",X"40",X"36",X"40",X"02",
X"C5",X"F7",X"80",X"32",X"C0",X"C6",X"00",X"21",X"80",X"C3",X"00",X"25",X"80",X"07",X"00",X"D0",
X"56",X"C4",X"80",X"31",X"00",X"06",X"80",X"25",X"00",X"C2",X"80",X"25",X"00",X"02",X"80",X"25",
X"00",X"C2",X"C5",X"F5",X"40",X"32",X"00",X"C7",X"C1",X"F1",X"05",X"F5",X"C6",X"FD",X"00",X"02",
X"00",X"06",X"C1",X"F5",X"00",X"37",X"C0",X"03",X"C2",X"F5",X"00",X"11",X"00",X"06",X"40",X"32",
X"80",X"C0",X"00",X"12",X"00",X"07",X"80",X"27",X"80",X"C4",X"00",X"32",X"C0",X"C6",X"80",X"21",
X"80",X"C3",X"80",X"25",X"80",X"07",X"00",X"D0",X"69",X"C4",X"00",X"25",X"80",X"02",X"00",X"21",
X"80",X"C6",X"00",X"21",X"80",X"06",X"00",X"21",X"80",X"C6",X"00",X"17",X"00",X"C5",X"80",X"35",
X"C0",X"C3",X"00",X"13",X"00",X"C1",X"00",X"17",X"00",X"05",X"40",X"36",X"00",X"C0",X"01",X"F0",
X"C5",X"F8",X"00",X"41",X"60",X"06",X"C5",X"F1",X"00",X"06",X"00",X"02",X"00",X"23",X"80",X"C3",
X"00",X"35",X"C0",X"02",X"80",X"27",X"00",X"C0",X"40",X"31",X"00",X"C7",X"00",X"22",X"80",X"C2",
X"00",X"26",X"80",X"06",X"00",X"D0",X"7C",X"C4",X"80",X"24",X"80",X"02",X"80",X"20",X"80",X"C6",
X"80",X"20",X"80",X"06",X"80",X"20",X"80",X"C6",X"00",X"17",X"00",X"C5",X"60",X"44",X"00",X"C2",
X"00",X"13",X"00",X"C0",X"00",X"17",X"00",X"00",X"40",X"36",X"80",X"C0",X"01",X"F0",X"C5",X"F8",
X"80",X"40",X"60",X"06",X"C6",X"F1",X"00",X"15",X"00",X"02",X"80",X"23",X"80",X"C2",X"80",X"34",
X"00",X"03",X"80",X"27",X"00",X"C1",X"C0",X"30",X"80",X"C7",X"80",X"22",X"00",X"C2",X"80",X"26",
X"00",X"C6",X"00",X"D0",X"00",X"C4",X"00",X"20",X"80",X"C6",X"00",X"17",X"00",X"C0",X"00",X"30",
X"C0",X"C3",X"00",X"13",X"00",X"C0",X"00",X"20",X"80",X"C6",X"C0",X"34",X"80",X"06",X"C5",X"FE",
X"05",X"F0",X"C1",X"F8",X"00",X"40",X"60",X"02",X"C1",X"F8",X"05",X"F0",X"C5",X"FA",X"05",X"F8",
X"00",X"27",X"80",X"C1",X"00",X"30",X"40",X"C7",X"00",X"23",X"80",X"C1",X"00",X"27",X"80",X"05",
X"00",X"D0",X"8B",X"C4",X"AE",X"C4",X"D5",X"C4",X"FB",X"C4",X"21",X"C5",X"40",X"C5",X"64",X"C5",
X"8B",X"C5",X"B2",X"C5",X"AA",X"A2",X"40",X"00",X"00",X"70",X"00",X"00",X"E8",X"A0",X"00",X"00",
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X"00",X"06",X"00",X"06",X"C0",X"30",X"00",X"A6",X"00",X"26",X"80",X"07",X"00",X"D0",X"00",X"13",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"53");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/rom/LLANDER_VEC_ROM_1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity LLANDER_VEC_ROM_1 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of LLANDER_VEC_ROM_1 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"44",X"C8",X"4C",X"C8",X"52",X"C8",X"56",X"C8",X"00",X"D0",X"5B",X"C8",X"62",X"C8",X"00",X"D0",
X"68",X"C8",X"6F",X"C8",X"00",X"D0",X"7C",X"C8",X"82",X"C8",X"86",X"C8",X"4C",X"C8",X"00",X"D0",
X"8D",X"C8",X"62",X"C8",X"00",X"D0",X"92",X"C8",X"98",X"C8",X"9D",X"C8",X"00",X"D0",X"5B",X"C8",
X"A6",X"C8",X"D1",X"C8",X"AD",X"C8",X"00",X"D0",X"44",X"C8",X"86",X"C8",X"B2",X"C8",X"00",X"D0",
X"6F",X"C8",X"AA",X"F8",X"4C",X"C8",X"AA",X"F8",X"C4",X"C8",X"00",X"D0",X"56",X"C8",X"4C",X"C8",
X"7C",X"C8",X"56",X"C8",X"AA",X"FE",X"00",X"D0",X"BC",X"C8",X"82",X"C8",X"68",X"C8",X"00",X"D0",
X"B2",X"C8",X"C4",X"C8",X"86",X"C8",X"00",X"60",X"00",X"A2",X"00",X"D0",X"C9",X"C8",X"CE",X"C8",
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X"D1",X"C8",X"AD",X"C8",X"AA",X"FA",X"00",X"D0",X"AA",X"F8",X"00",X"56",X"80",X"A0",X"AA",X"F8",
X"00",X"56",X"80",X"A0",X"A9",X"F8",X"00",X"D0",X"00",X"67",X"40",X"A0",X"00",X"67",X"C0",X"A0",
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X"A9",X"FE",X"AA",X"FE",X"00",X"D0",X"AA",X"F8",X"AA",X"FA",X"80",X"53",X"00",X"A2",X"80",X"52",
X"00",X"A2",X"00",X"D0",X"AA",X"FA",X"A9",X"FA",X"AA",X"FA",X"A9",X"FA",X"AA",X"F9",X"00",X"D0",
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X"AA",X"F8",X"00",X"D0",X"00",X"62",X"C0",X"A0",X"AB",X"F2",X"00",X"D0",X"AB",X"F6",X"00",X"56",
X"80",X"A1",X"00",X"66",X"80",X"A0",X"AB",X"FE",X"00",X"D0",X"AA",X"FE",X"00",X"60",X"00",X"A2",
X"AA",X"FA",X"00",X"D0",X"80",X"62",X"80",X"A0",X"00",X"62",X"80",X"A0",X"AA",X"F9",X"00",X"D0",
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X"00",X"63",X"80",X"A0",X"00",X"62",X"00",X"A0",X"00",X"D0",X"00",X"52",X"80",X"A0",X"00",X"52",
X"80",X"A1",X"00",X"D0",X"00",X"56",X"80",X"A0",X"80",X"67",X"40",X"A1",X"00",X"D0",X"00",X"70",
X"00",X"A2",X"00",X"70",X"00",X"A2",X"00",X"D0",X"00",X"63",X"80",X"A0",X"00",X"62",X"00",X"A1",
X"00",X"62",X"80",X"A0",X"A9",X"F8",X"00",X"D0",X"00",X"56",X"80",X"A0",X"00",X"56",X"80",X"A1",
X"00",X"D0",X"40",X"64",X"00",X"A2",X"C0",X"64",X"00",X"A2",X"00",X"D0",X"00",X"70",X"00",X"A2",
X"00",X"D0",X"00",X"62",X"40",X"A0",X"80",X"62",X"C0",X"A0",X"AA",X"F9",X"00",X"D0",X"AA",X"FA",
X"00",X"62",X"80",X"A0",X"00",X"52",X"80",X"A2",X"00",X"D0",X"00",X"C8",X"05",X"C8",X"08",X"C8",
X"0B",X"C8",X"10",X"C8",X"13",X"C8",X"17",X"C8",X"1C",X"C8",X"20",X"C8",X"26",X"C8",X"B7",X"C8",
X"2C",X"C8",X"30",X"C8",X"36",X"C8",X"39",X"C8",X"3F",X"C8",X"00",X"C8",X"05",X"C8",X"08",X"C8",
X"0B",X"C8",X"80",X"03",X"00",X"00",X"80",X"01",X"00",X"00",X"90",X"02",X"00",X"00",X"40",X"02",
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X"00",X"00",X"40",X"04",X"00",X"00",X"80",X"02",X"00",X"00",X"40",X"00",X"00",X"00",X"40",X"00",
X"00",X"00",X"C0",X"01",X"00",X"00",X"60",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"80",X"02",
X"00",X"00",X"68",X"03",X"68",X"01",X"78",X"02",X"28",X"02",X"C8",X"00",X"58",X"01",X"48",X"03",
X"88",X"05",X"28",X"04",X"68",X"02",X"28",X"00",X"28",X"00",X"A8",X"01",X"48",X"00",X"28",X"00",
X"68",X"02",X"92",X"00",X"00",X"62",X"00",X"02",X"88",X"F8",X"40",X"83",X"40",X"04",X"78",X"F8",
X"00",X"70",X"00",X"03",X"88",X"F8",X"80",X"77",X"80",X"04",X"98",X"F8",X"00",X"86",X"80",X"00",
X"00",X"D0",X"40",X"82",X"C0",X"00",X"98",X"F8",X"80",X"76",X"80",X"00",X"78",X"F8",X"00",X"76",
X"00",X"02",X"00",X"D0",X"08",X"FA",X"98",X"F8",X"00",X"83",X"C0",X"00",X"78",X"F8",X"00",X"77",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"37");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Atari Vector/LunarLander_MiST/rtl/rom/LLANDER_VEC_ROM_2.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity LLANDER_VEC_ROM_2 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of LLANDER_VEC_ROM_2 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"30",X"60",X"00",X"94",X"58",X"C6",X"58",X"FA",X"58",X"2E",X"59",X"48",X"59",X"79",X"59",
X"9C",X"59",X"10",X"5A",X"36",X"5A",X"86",X"5A",X"D2",X"5A",X"0C",X"5B",X"4E",X"5B",X"82",X"5B",
X"EA",X"5B",X"36",X"5C",X"8D",X"5C",X"A6",X"5C",X"EC",X"5C",X"6A",X"5D",X"AA",X"5D",X"ED",X"5D",
X"02",X"5E",X"23",X"5E",X"A5",X"58",X"D7",X"58",X"0B",X"59",X"35",X"59",X"5D",X"59",X"82",X"59",
X"C5",X"59",X"1D",X"5A",X"55",X"5A",X"9C",X"5A",X"E4",X"5A",X"21",X"5B",X"5F",X"5B",X"A3",X"5B",
X"06",X"5C",X"47",X"5C",X"AD",X"5C",X"C5",X"5C",X"18",X"5D",X"7C",X"5D",X"C4",X"5D",X"F4",X"5D",
X"0E",X"5E",X"38",X"5E",X"B1",X"58",X"E7",X"58",X"1A",X"59",X"3D",X"59",X"6B",X"59",X"8B",X"59",
X"F1",X"59",X"2B",X"5A",X"70",X"5A",X"B1",X"5A",X"FA",X"5A",X"39",X"5B",X"71",X"5B",X"C4",X"5B",
X"22",X"5C",X"6C",X"5C",X"CE",X"5C",X"E3",X"5C",X"3C",X"5D",X"83",X"5D",X"DA",X"5D",X"FB",X"5D",
X"1A",X"5E",X"51",X"5E",X"16",X"34",X"34",X"3E",X"46",X"1E",X"38",X"00",X"3A",X"3E",X"38",X"00",
X"3A",X"3C",X"16",X"38",X"BC",X"34",X"3E",X"2C",X"3A",X"16",X"38",X"00",X"3A",X"3C",X"16",X"38",
X"BC",X"3A",X"3C",X"16",X"38",X"3C",X"2A",X"30",X"32",X"1E",X"34",X"20",X"1E",X"00",X"1C",X"38",
X"3E",X"1E",X"1A",X"2A",X"1E",X"B0",X"1A",X"16",X"38",X"18",X"3E",X"38",X"16",X"30",X"3C",X"00",
X"1C",X"26",X"2E",X"26",X"30",X"3E",X"9E",X"34",X"32",X"1A",X"32",X"00",X"1A",X"32",X"2E",X"18",
X"3E",X"3A",X"3C",X"26",X"18",X"2C",X"9E",X"3C",X"38",X"1E",X"26",X"18",X"3A",X"3C",X"32",X"20",
X"20",X"00",X"22",X"1E",X"24",X"3C",X"00",X"16",X"3E",X"BA",X"34",X"2C",X"3E",X"3A",X"00",X"1C",
X"1E",X"00",X"1A",X"16",X"38",X"18",X"3E",X"38",X"16",X"30",X"BC",X"3A",X"26",X"30",X"00",X"1A",
X"32",X"2E",X"18",X"3E",X"3A",X"3C",X"26",X"18",X"2C",X"9E",X"3C",X"38",X"1E",X"26",X"18",X"3A",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

BIN
Arcade_MiST/NinjaKun_MiST/Snapshot/NinjaKun_MiST.rbf
View File

Binary file not shown.

358
Arcade_MiST/NinjaKun_MiST/mister/Arcade-NinjaKun.sv
View File

@@ -1,358 +0,0 @@
//============================================================================
// Arcade: Ninja-Kun -- Majyo no Bouken --
//
// Original implimentation and port to MiSTer by MiSTer-X 2019
//============================================================================
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [44:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output VGA_CLK,
//Multiple resolutions are supported using different VGA_CE rates.
//Must be based on CLK_VIDEO
output VGA_CE,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
//Base video clock. Usually equals to CLK_SYS.
output HDMI_CLK,
//Multiple resolutions are supported using different HDMI_CE rates.
//Must be based on CLK_VIDEO
output HDMI_CE,
output [7:0] HDMI_R,
output [7:0] HDMI_G,
output [7:0] HDMI_B,
output HDMI_HS,
output HDMI_VS,
output HDMI_DE, // = ~(VBlank | HBlank)
output [1:0] HDMI_SL, // scanlines fx
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
output [7:0] HDMI_ARX,
output [7:0] HDMI_ARY,
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S // 1 - signed audio samples, 0 - unsigned
);
assign LED_USER = ioctl_download;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign HDMI_ARX = status[1] ? 8'd16 : 8'd4;
assign HDMI_ARY = status[1] ? 8'd9 : 8'd3;
`include "build_id.v"
localparam CONF_STR = {
"A.NinjaKun;;",
"F,rom;", // allow loading of alternate ROMs
"-;",
"O1,Aspect Ratio,Original,Wide;",
"-;",
"O8,Difficulty,Normal,Hard;",
"O9A,Lives,4,3,2,5;",
"OB,1st Extra,30000,40000;",
"OCD,2nd Extra (Every),50000,70000,90000,None;",
"OF,Allow Continue,No,Yes;",
"OG,Free Play,No,Yes;",
"OH,Endless(If Free Play),No,Yes;",
"OE,Demo Sound,Off,On;",
"OI,Name Letters,8,3;",
"-;",
"R0,Reset;",
"J1,Shot,Jump,Start 1P,Start 2P,Coin;",
"V,v",`BUILD_DATE
};
`define CABINET 1'b0 // Upright=0,Table=1
`define DIFFICULTY ~status[8] // Hard=0,Normal=1
`define LIVES ~status[10:9] // 00=5,01=2,10=3,11=4
`define EXTEND1ST ~status[11] // 40000=0,30000=1
`define EXTEND2ND ~status[13:12] // None,30000,50000,70000
`define DEMOSOUND ~status[14] // On=0,Off=1
`define ALLOW_CONTINUE ~status[15] // Yes=0,NO=1
`define FREEPLAY ~status[16] // Yes=0,No=1
`define ENDLESS ~status[17] // Yes=0,No=1 (If FreePlay)
`define NAMELETTERS ~status[18] // 3Letters=0,8Letters=1
`define COINAGE 3'b111 // 1C/1C
wire bCabinet = `CABINET; // (upright only)
//////////////////// CLOCKS ///////////////////
wire clk_hdmi;
wire clk_49M;
wire clk_sys = clk_49M;
pll pll
(
.rst(0),
.refclk(CLK_50M),
.outclk_0(clk_49M),
.outclk_1(clk_hdmi)
);
///////////////////////////////////////////////////
wire [31:0] status;
wire [1:0] buttons;
wire forced_scandoubler;
wire ioctl_download;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [10:0] ps2_key;
wire [15:0] joystk1, joystk2;
hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.conf_str(CONF_STR),
.buttons(buttons),
.status(status),
.forced_scandoubler(forced_scandoubler),
.ioctl_download(ioctl_download),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.joystick_0(joystk1),
.joystick_1(joystk2),
.ps2_key(ps2_key)
);
wire pressed = ps2_key[9];
wire [8:0] code = ps2_key[8:0];
always @(posedge clk_sys) begin
reg old_state;
old_state <= ps2_key[10];
if(old_state != ps2_key[10]) begin
casex(code)
'hX75: btn_up <= pressed; // up
'hX72: btn_down <= pressed; // down
'hX6B: btn_left <= pressed; // left
'hX74: btn_right <= pressed; // right
'h029: btn_trig1 <= pressed; // space
'h014: btn_trig2 <= pressed; // ctrl
'h005: btn_one_player <= pressed; // F1
'h006: btn_two_players <= pressed; // F2
// JPAC/IPAC/MAME Style Codes
'h016: btn_start_1 <= pressed; // 1
'h01E: btn_start_2 <= pressed; // 2
'h02E: btn_coin_1 <= pressed; // 5
'h036: btn_coin_2 <= pressed; // 6
'h02D: btn_up_2 <= pressed; // R
'h02B: btn_down_2 <= pressed; // F
'h023: btn_left_2 <= pressed; // D
'h034: btn_right_2 <= pressed; // G
'h01C: btn_trig1_2 <= pressed; // A
'h01B: btn_trig2_2 <= pressed; // S
endcase
end
end
reg btn_up = 0;
reg btn_down = 0;
reg btn_right = 0;
reg btn_left = 0;
reg btn_trig1 = 0;
reg btn_trig2 = 0;
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_start_1 = 0;
reg btn_start_2 = 0;
reg btn_coin_1 = 0;
reg btn_coin_2 = 0;
reg btn_up_2 = 0;
reg btn_down_2 = 0;
reg btn_left_2 = 0;
reg btn_right_2 = 0;
reg btn_trig1_2 = 0;
reg btn_trig2_2 = 0;
wire m_up2 = btn_up_2 | joystk2[3];
wire m_down2 = btn_down_2 | joystk2[2];
wire m_left2 = btn_left_2 | joystk2[1];
wire m_right2 = btn_right_2 | joystk2[0];
wire m_trig21 = btn_trig1_2 | joystk2[4];
wire m_trig22 = btn_trig2_2 | joystk2[5];
wire m_start1 = btn_one_player | joystk1[6] | joystk2[6] | btn_start_1;
wire m_start2 = btn_two_players | joystk1[7] | joystk2[7] | btn_start_2;
wire m_up1 = btn_up | joystk1[3] | (bCabinet ? 1'b0 : m_up2);
wire m_down1 = btn_down | joystk1[2] | (bCabinet ? 1'b0 : m_down2);
wire m_left1 = btn_left | joystk1[1] | (bCabinet ? 1'b0 : m_left2);
wire m_right1 = btn_right | joystk1[0] | (bCabinet ? 1'b0 : m_right2);
wire m_trig11 = btn_trig1 | joystk1[4] | (bCabinet ? 1'b0 : m_trig21);
wire m_trig12 = btn_trig2 | joystk1[5] | (bCabinet ? 1'b0 : m_trig22);
wire m_coin1 = btn_one_player | btn_coin_1 | joystk1[8];
wire m_coin2 = btn_two_players| btn_coin_2 | joystk2[8];
wire m_coin = m_coin1|m_coin2;
///////////////////////////////////////////////////
wire hblank, vblank;
wire ce_vid;
wire hs, vs;
wire [3:0] r,g,b;
reg ce_pix;
always @(posedge clk_hdmi) begin
reg old_clk;
old_clk <= ce_vid;
ce_pix <= old_clk & ~ce_vid;
end
arcade_rotate_fx #(256,192,12) arcade_video
(
.*,
.clk_video(clk_hdmi),
.RGB_in({r,g,b}),
.HBlank(hblank),
.VBlank(vblank),
.HSync(~hs),
.VSync(~vs),
.fx(0),
.no_rotate(1'b1)
);
wire PCLK;
wire [8:0] HPOS,VPOS;
wire [11:0] POUT;
HVGEN hvgen
(
.HPOS(HPOS),.VPOS(VPOS),.PCLK(PCLK),.iRGB(POUT),
.oRGB({b,g,r}),.HBLK(hblank),.VBLK(vblank),.HSYN(hs),.VSYN(vs)
);
assign ce_vid = PCLK;
wire [15:0] AOUT;
assign AUDIO_L = AOUT;
assign AUDIO_R = AOUT;
assign AUDIO_S = 1'b0; // unsigned
///////////////////////////////////////////////////
wire [7:0] iDSW1 = {`DIFFICULTY,`DEMOSOUND,`EXTEND2ND,`EXTEND1ST,`LIVES, `CABINET}; // 8'b1_0_01_1_10_0;
wire [7:0] iDSW2 = {`ENDLESS,`FREEPLAY,1'b0,`ALLOW_CONTINUE,`NAMELETTERS,`COINAGE}; // 8'b1_1_0_0_1_111;
wire [7:0] iCTR1 = ~{ 2'b11, m_start1, 1'b0, m_trig11, m_trig12, m_right1, m_left1 };
wire [7:0] iCTR2 = ~{ ~m_coin,1'b1, m_start2, 1'b0, m_trig21, m_trig22, m_right2, m_left2 };
wire iRST = RESET | status[0] | buttons[1] | ioctl_download;
wire [7:0] oPIX;
assign POUT = {{oPIX[7:6],oPIX[1:0]},{oPIX[5:4],oPIX[1:0]},{oPIX[3:2],oPIX[1:0]}};
FPGA_NINJAKUN GameCore
(
.RESET(iRST),.MCLK(clk_49M),
.CTR1(iCTR1),.CTR2(iCTR2),
.DSW1(iDSW1),.DSW2(iDSW2),
.PH(HPOS),.PV(VPOS),
.PCLK(PCLK),.POUT(oPIX),
.SNDOUT(AOUT),
.ROMCL(clk_sys),.ROMAD(ioctl_addr),.ROMDT(ioctl_dout),.ROMEN(ioctl_wr)
);
endmodule
module HVGEN
(
output [8:0] HPOS,
output [8:0] VPOS,
input PCLK,
input [11:0] iRGB,
output reg [11:0] oRGB,
output reg HBLK = 1,
output reg VBLK = 1,
output reg HSYN = 1,
output reg VSYN = 1
);
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
assign HPOS = hcnt-16;
assign VPOS = vcnt-16;
always @(posedge PCLK) begin
case (hcnt)
15: begin HBLK <= 0; hcnt <= hcnt+1; end
272: begin HBLK <= 1; hcnt <= hcnt+1; end
311: begin HSYN <= 0; hcnt <= hcnt+1; end
342: begin HSYN <= 1; hcnt <= 471; end
511: begin hcnt <= 0;
case (vcnt)
15: begin VBLK <= 0; vcnt <= vcnt+1; end
207: begin VBLK <= 1; vcnt <= vcnt+1; end
226: begin VSYN <= 0; vcnt <= vcnt+1; end
233: begin VSYN <= 1; vcnt <= 483; end
511: begin vcnt <= 0; end
default: vcnt <= vcnt+1;
endcase
end
default: hcnt <= hcnt+1;
endcase
oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
end
endmodule

674
Arcade_MiST/NinjaKun_MiST/mister/LICENSE
View File

@@ -1,674 +0,0 @@
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74
Arcade_MiST/NinjaKun_MiST/mister/README.txt
View File

@@ -1,74 +0,0 @@
---------------------------------------------------------------------------------
--
-- Arcade: Ninja-Kun port to MiSTer by MiSTer-X
-- 20 October 2019
--
---------------------------------------------------------------------------------
-- FPGA Ninja-Kun for Spartan-6
------------------------------------------------
-- Copyright (c) 2011 MiSTer-X
---------------------------------------------------------------------------------
-- T80/T80s - Version : 0242
-----------------------------
-- Z80 compatible microprocessor core
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---------------------------------------------------------------------------------
-- YM2149 (AY-3-8910)
-- Copyright (c) MikeJ - Jan 2005
---------------------------------------------------------------------------------
--
--
-- Keyboard inputs :
--
-- F2 : Coin + Start 2 players
-- F1 : Coin + Start 1 player
-- UP,DOWN,LEFT,RIGHT arrows : Movements
-- SPACE : Shot
-- CTRL : Jump
--
-- MAME/IPAC/JPAC Style Keyboard inputs:
-- 5 : Coin 1
-- 6 : Coin 2
-- 1 : Start 1 Player
-- 2 : Start 2 Players
-- R,F,D,G : Player 2 Movements
-- A : Player 2 Shot
-- S : Player 2 Jump
--
-- Joystick support.
--
--
-- known bug: Sometimes BG screen glitches.
--
---------------------------------------------------------------------------------
-- 23 October 2019
---------------------------------------------------------------------------------
-- FIXED: Analog video is shifted to right.
---------------------------------------------------------------------------------
*** Attention ***
ROM is not included. In order to use this arcade, you need to provide a correct ROM file.
Find this zip file somewhere. You need to find the file exactly as required.
Do not rename other zip files even if they also represent the same game - they are not compatible!
The name of zip is taken from M.A.M.E. project, so you can get more info about
hashes and contained files there.
To generate the ROM using Windows:
1) Copy the zip into "releases" directory
2) Execute bat file - it will show the name of zip file containing required files.
3) Put required zip into the same directory and execute the bat again.
4) If everything will go without errors or warnings, then you will get the a.*.rom file.
5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
To generate the ROM using Linux/MacOS:
1) Copy the zip into "releases" directory
2) Execute build_rom.sh
3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
To generate the ROM using MiSTer:
1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/
2) Using OSD execute build_rom.sh
3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file

45
Arcade_MiST/NinjaKun_MiST/mister/build_rom.bat
View File

@@ -1,45 +0,0 @@
@powershell -NoProfile -ExecutionPolicy Unrestricted "$s=[scriptblock]::create((gc \"%~f0\"|?{$_.readcount -gt 1})-join\"`n\");&$s" %*&goto:eof
#==============================================================
$zip="ninjakun.zip"
$ifiles=`
"ninja-6.7n","ninja-7.7p","ninja-8.7s","ninja-9.7t",`
"ninja-10.2c","ninja-11.2d","ninja-12.4c","ninja-13.4d",`
"ninja-1.7a","ninja-2.7b","ninja-3.7d","ninja-4.7e",`
"ninja-5.7h","ninja-2.7b","ninja-3.7d","ninja-4.7e"
$ofile="a.ninjakun.rom"
$ofileMd5sumValid="99e80f22f7a77cf1d574ce89486b385f"
if (!(Test-Path "./$zip")) {
echo "Error: Cannot find $zip file."
echo ""
echo "Put $zip into the same directory."
}
else {
Expand-Archive -Path "./$zip" -Destination ./tmp/ -Force
cd tmp
Get-Content $ifiles -Enc Byte -Read 512 | Set-Content "../$ofile" -Enc Byte
cd ..
Remove-Item ./tmp -Recurse -Force
$ofileMD5sumCurrent=(Get-FileHash -Algorithm md5 "./$ofile").Hash.toLower()
if ($ofileMD5sumCurrent -ne $ofileMd5sumValid) {
echo "Expected checksum: $ofileMd5sumValid"
echo " Actual checksum: $ofileMd5sumCurrent"
echo ""
echo "Error: Generated $ofile is invalid."
echo ""
echo "This is more likely due to incorrect $zip content."
}
else {
echo "Checksum verification passed."
echo ""
echo "Copy $ofile into root of SD card along with the rbf file."
}
}
echo ""
echo ""
pause

4
Arcade_MiST/NinjaKun_MiST/mister/build_rom.ini
View File

@@ -1,4 +0,0 @@
zip=ninjakun.zip
ifiles=(ninja-6.7n ninja-7.7p ninja-8.7s ninja-9.7t ninja-10.2c ninja-11.2d ninja-12.4c ninja-13.4d ninja-1.7a ninja-2.7b ninja-3.7d ninja-4.7e ninja-5.7h ninja-2.7b ninja-3.7d ninja-4.7e)
ofile=a.ninjakun.rom
ofileMd5sumValid=99e80f22f7a77cf1d574ce89486b385f

100
Arcade_MiST/NinjaKun_MiST/mister/build_rom.sh
View File

@@ -1,100 +0,0 @@
#!/bin/bash
exit_with_error() {
echo -e "\nERROR:\n${1}\n"
exit 1
}
check_dependencies() {
if [[ $OSTYPE == darwin* ]]; then
for j in unzip md5 cat cut; do
command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
done
else
for j in unzip md5sum cat cut; do
command -v ${j} > /dev/null 2>&1 || exit_with_error "This script requires\n${j}"
done
fi
}
check_permissions () {
if [ ! -w ${BASEDIR} ]; then
exit_with_error "Cannot write to\n${BASEDIR}"
fi
}
read_ini () {
if [ ! -f ${BASEDIR}/build_rom.ini ]; then
exit_with_error "Missing build_rom.ini"
else
source ${BASEDIR}/build_rom.ini
fi
}
uncompress_zip() {
if [ -f ${BASEDIR}/${zip} ]; then
tmpdir=tmp.`date +%Y%m%d%H%M%S%s`
unzip -qq -d ${BASEDIR}/${tmpdir}/ ${BASEDIR}/${zip}
if [ $? != 0 ] ; then
rm -rf ${BASEDIR}/$tmpdir
exit_with_error "Something went wrong\nwhen extracting\n${zip}"
fi
else
exit_with_error "Cannot find ${zip}"
fi
}
generate_rom() {
for i in "${ifiles[@]}"; do
# ensure provided zip contains required files
if [ ! -f "${BASEDIR}/${tmpdir}/${i}" ]; then
rm -rf ${BASEDIR}/$tmpdir
exit_with_error "Provided ${zip}\nis missing required file:\n\n${i}"
else
cat ${BASEDIR}/${tmpdir}/${i} >> ${BASEDIR}/${tmpdir}/${ofile}
fi
done
}
validate_rom() {
if [[ $OSTYPE == darwin* ]]; then
ofileMd5sumCurrent=$(md5 -r ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
else
ofileMd5sumCurrent=$(md5sum ${BASEDIR}/${tmpdir}/${ofile}|cut -f 1 -d " ")
fi
if [[ "${ofileMd5sumValid}" != "${ofileMd5sumCurrent}" ]]; then
echo -e "\nExpected checksum:\n${ofileMd5sumValid}"
echo -e "Actual checksum:\n${ofileMd5sumCurrent}"
mv ${BASEDIR}/${tmpdir}/${ofile} .
rm -rf ${BASEDIR}/$tmpdir
exit_with_error "Generated ${ofile}\nis invalid.\nThis is more likely\ndue to incorrect\n${zip} content."
else
mv ${BASEDIR}/${tmpdir}/${ofile} ${BASEDIR}/.
rm -rf ${BASEDIR}/$tmpdir
echo -e "\nChecksum verification passed\n\nCopy the ${ofile}\ninto root of SD card\nalong with the rbf file.\n"
fi
}
BASEDIR=$(dirname "$0")
echo "Generating ROM ..."
## verify dependencies
check_dependencies
## verify write permissions
check_permissions
## load ini
read_ini
## extract package
uncompress_zip
## build rom
generate_rom
## verify rom
validate_rom

80
Arcade_MiST/NinjaKun_MiST/mister/ninjakun_romarb.v
View File

@@ -1,80 +0,0 @@
// Copyright (c) 2011 MiSTer-X
module NINJAKUN_ROMARB
(
input CLK,
input [12:0] FGCAD,
output [31:0] FGCDT,
input [12:0] BGCAD,
output [31:0] BGCDT,
input [12:0] SPCAD,
output [31:0] SPCDT,
output reg [2:0] PHASE,
input [14:0] CP0AD,
output [7:0] CP0DT,
input [14:0] CP1AD,
output [7:0] CP1DT
);
wire CL = ~CLK;
always @( posedge CL ) PHASE <= PHASE+1;
NJFGROM sprom( CL, SPCAD, SPCDT );
NJFGROM fgrom( CL, FGCAD, FGCDT );
NJBGROM bgrom( CL, BGCAD, BGCDT );
NJCPU0I cpu0i( CL, CP0AD, CP0DT );
NJCPU1I cpu1i( CL, {(CP1AD[14]|CP1AD[13]),CP1AD[12:0]}, CP1DT );
endmodule
module NINJAKUN_CPUMUX
(
input CLK24M,
input [2:0] PHASE,
input [15:0] CP0AD,
input [7:0] CP0OD,
output [7:0] CP0ID,
input CP0RD,
input CP0WR,
input [15:0] CP1AD,
input [7:0] CP1OD,
output [7:0] CP1ID,
input CP1RD,
input CP1WR,
output [15:0] CPADR,
output [7:0] CPODT,
input [7:0] CPIDT,
output CPRED,
output CPWRT
);
reg CSIDE;
reg [7:0] CP0D, CP1D;
always @( posedge CLK24M ) begin
case (PHASE)
4: begin CP1D <= CPIDT; CSIDE <= 0; end
0: begin CP0D <= CPIDT; CSIDE <= 1; end
default:;
endcase
end
assign CPADR = CSIDE ? CP1AD : CP0AD;
assign CPODT = CSIDE ? CP1OD : CP0OD;
assign CPRED = CSIDE ? CP1RD : CP0RD;
assign CPWRT = CSIDE ? CP1WR : CP0WR;
assign CP0ID = CSIDE ? CP0D : CPIDT;
assign CP1ID = CSIDE ? CPIDT : CP1D;
endmodule

7
Arcade_MiST/NinjaKun_MiST/mister/rommap.txt
View File

@@ -1,7 +0,0 @@
00000-07FFF GFX1-0,1,2,3
08000-0FFFF GFX2-0,1,2,3
10000-17FFF CPU0-0,1,2,3
18000-1FFFF CPU1-0,CPU0-1,2,3
[EOF]

103
Arcade_MiST/NinjaKun_MiST/mister/roms.v
View File

@@ -1,103 +0,0 @@
// Copyright (c) 2019 MiSTer-X
module DLROM #(parameter AW,parameter DW)
(
input CL0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CL1,
input [(AW-1):0] AD1,
input [(DW-1):0] DI1,
input WE1
);
reg [(DW-1):0] core[0:((2**AW)-1)];
always @(posedge CL0) DO0 <= core[AD0];
always @(posedge CL1) if (WE1) core[AD1] <= DI1;
endmodule
module NJFGROM
(
input CL,
input [12:0] AD,
output [31:0] DT,
input ROMCL,
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
wire ROME = ROMEN & (ROMAD[16:15]==2'b00);
wire ROME0 = ROME & ~ROMAD[13];
wire ROME1 = ROME & ROMAD[13];
DLROM #(13,8) R0(CL,AD,DT[ 7: 0], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ~ROMAD[0]);
DLROM #(13,8) R1(CL,AD,DT[15: 8], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ~ROMAD[0]);
DLROM #(13,8) R2(CL,AD,DT[23:16], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ROMAD[0]);
DLROM #(13,8) R3(CL,AD,DT[31:24], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ROMAD[0]);
endmodule
module NJBGROM
(
input CL,
input [12:0] AD,
output [31:0] DT,
input ROMCL,
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
wire ROME = ROMEN & (ROMAD[16:15]==2'b01);
wire ROME0 = ROME & ~ROMAD[13];
wire ROME1 = ROME & ROMAD[13];
DLROM #(13,8) R0(CL,AD,DT[ 7: 0], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ~ROMAD[0]);
DLROM #(13,8) R1(CL,AD,DT[15: 8], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ~ROMAD[0]);
DLROM #(13,8) R2(CL,AD,DT[23:16], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME0 & ROMAD[0]);
DLROM #(13,8) R3(CL,AD,DT[31:24], ROMCL,{ROMAD[14],ROMAD[12:1]},ROMDT,ROME1 & ROMAD[0]);
endmodule
module NJC0ROM
(
input CL,
input [14:0] AD,
output [7:0] DT,
input ROMCL,
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
DLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b10));
endmodule
module NJC1ROM
(
input CL,
input [14:0] AD,
output [7:0] DT,
input ROMCL,
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
DLROM #(15,8) r(CL,AD,DT,ROMCL,ROMAD,ROMDT,ROMEN & (ROMAD[16:15]==2'b11));
endmodule

246
Arcade_MiST/NinjaKun_MiST/rtl/DPRAM1024.v
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@@ -1,246 +0,0 @@
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DPRAM1024.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DPRAM1024 (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

1073
Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80.vhd
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File diff suppressed because it is too large Load Diff

351
Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_ALU.vhd
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@@ -1,351 +0,0 @@
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

1934
Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_MCode.vhd
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208
Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Pack.vhd
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@@ -1,208 +0,0 @@
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

105
Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80_Reg.vhd
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@@ -1,105 +0,0 @@
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

190
Arcade_MiST/NinjaKun_MiST/rtl/cpu/T80s.vhd
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@@ -1,190 +0,0 @@
--
-- Z80 compatible microprocessor core, synchronous top level
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed read with wait
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80s is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80s;
architecture rtl of T80s is
signal CEN : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end process;
end;

101
Arcade_MiST/NinjaKun_MiST/rtl/dpram_1r1w.vhd
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@@ -1,101 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram_1r1w IS
GENERIC
(
widthad_a : natural;
width_a : natural := 8;
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rdclocken : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
wrclock : IN STD_LOGIC ;
wrclocken : IN STD_LOGIC := '1';
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram_1r1w;
ARCHITECTURE SYN OF dpram_1r1w IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clocken0 : IN STD_LOGIC ;
clocken1 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => "FALSE",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1
)
PORT MAP (
clocken0 => wrclocken,
clocken1 => rdclocken,
wren_a => wren,
clock0 => wrclock,
clock1 => rdclock,
address_a => wraddress,
address_b => rdaddress,
data_a => data,
q_b => sub_wire0
);
END SYN;

116
Arcade_MiST/NinjaKun_MiST/rtl/mems.v
View File

@@ -1,116 +0,0 @@
// Copyright (c) 2011 MiSTer-X
module VDPRAM400x2
(
input CL0,
input [10:0] AD0,
input WR0,
input [7:0] WD0,
output [7:0] RD0,
input CL1,
input [9:0] AD1,
output [15:0] RD1
);
reg A10;
always @( posedge CL0 ) A10 <= AD0[10];
wire [7:0] RD00, RD01;
DPRAM400 LS( CL0, AD0[9:0], WR0 & (~AD0[10]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] );
DPRAM400 HS( CL0, AD0[9:0], WR0 & ( AD0[10]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[15:8] );
assign RD0 = A10 ? RD01 : RD00;
endmodule
module DPRAM800
(
input CL0,
input [10:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [10:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:2047];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule
module DPRAM400
(
input CL0,
input [9:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [9:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:1023];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule
module DPRAM200
(
input CL0,
input [8:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [8:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:511];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule

164
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_video.v
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@@ -1,164 +0,0 @@
// Copyright (c) 2011,19 MiSTer-X
module ninjakun_video
(
input RESET,
input VCLKx4,
input VCLK,
input [8:0] PH,
input [8:0] PV,
output [8:0] PALAD, // Pixel Output (Palet Index)
output [9:0] FGVAD, // FG
input [15:0] FGVDT,
output [9:0] BGVAD, // BG
input [15:0] BGVDT,
input [7:0] BGSCX,
input [7:0] BGSCY,
output [10:0] SPAAD, // Sprite
input [7:0] SPADT,
output VBLK,
input DBGPD, // Palet Display (for Debug)
// output [12:0] sp_rom_addr,
// input [31:0] sp_rom_data,
// output [12:0] fg_rom_addr,
// input [31:0] fg_rom_data,
output [12:0] bg_rom_addr,
input [31:0] bg_rom_data
);
assign VBLK = (PV>=193);
// ROMs
wire SPCFT = 1'b1;
wire [12:0] SPCAD;
wire [31:0] SPCDT;
wire [12:0] FGCAD;
wire [31:0] FGCDT;
wire [12:0] BGCAD;
wire [31:0] BGCDT;
//NJFGROM sprom(~VCLKx4, SPCAD, SPCDT, ROMCL, ROMAD, ROMDT, ROMEN);
//NJFGROM fgrom( ~VCLK, FGCAD, FGCDT, ROMCL, ROMAD, ROMDT, ROMEN);
//NJBGROM bgrom( ~VCLK, BGCAD, BGCDT, ROMCL, ROMAD, ROMDT, ROMEN);
//assign sp_rom_addr = SPCAD;
//assign SPCDT = sp_rom_data;
//assign fg_rom_addr = FGCAD;
//assign FGCDT = fg_rom_data;
/*
static GFXDECODE_START( gfx_ninjakun )
GFXDECODE_ENTRY( "gfx1", 0, layout16x16, 0x200, 16 ) // sprites
GFXDECODE_ENTRY( "gfx1", 0, layout8x8, 0x000, 16 ) // fg tiles
GFXDECODE_ENTRY( "gfx2", 0, layout8x8, 0x100, 16 ) // bg tiles
GFXDECODE_END*/
assign bg_rom_addr = BGCAD;
assign BGCDT = bg_rom_data;
fg1_rom fg1_rom (
.clk(~VCLKx4),//if sprite ? ~VCLKx4 : ~VCLK
.addr(SPCAD),//if sprite ? SPCAD : FGCAD
.data(SPCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0]
);
fg2_rom fg2_rom (
.clk(~VCLKx4),
.addr(SPCAD),
.data(SPCDT[15:8])
);
fg3_rom fg3_rom (
.clk(~VCLKx4),
.addr(SPCAD),
.data(SPCDT[23:16])
);
fg4_rom fg4_rom (
.clk(~VCLKx4),
.addr(SPCAD),
.data(SPCDT[31:24])
);/*
fg1_rom fg1_rom (
.clk(~VCLK),//if sprite ? ~VCLKx4 : ~VCLK
.addr(FGCAD),//if sprite ? SPCAD : FGCAD
.data(FGCDT[7:0])//if sprite ? SPCDT[7:0] : FGCDT[7:0]
);
fg2_rom fg2_rom (
.clk(~VCLK),
.addr(FGCAD),
.data(FGCDT[15:8])
);
fg3_rom fg3_rom (
.clk(~VCLK),
.addr(FGCAD),
.data(FGCDT[23:16])
);
fg4_rom fg4_rom (
.clk(~VCLK),
.addr(FGCAD),
.data(FGCDT[31:24])
);*/
// Fore-Ground Scanline Generator
wire FGPRI;
wire [8:0] FGOUT;
ninjakun_fg fg(
VCLK,
PH, PV,
FGVAD, FGVDT,
FGCAD, FGCDT,
{FGPRI, FGOUT}
);
wire FGOPQ =(FGOUT[3:0]!=0);
wire FGPPQ = FGOPQ & (~FGPRI);
// Back-Ground Scanline Generator
wire [8:0] BGOUT;
ninjakun_bg bg(
VCLK,
PH, PV,
BGSCX, BGSCY,
BGVAD, BGVDT,
BGCAD, BGCDT,
BGOUT
);
// Sprite Scanline Generator
wire [8:0] SPOUT;
ninjakun_sp sp(
VCLKx4, VCLK,
PH, PV,
SPAAD, SPADT,
SPCAD, SPCDT, SPCFT,
SPOUT
);
wire SPOPQ = (SPOUT[3:0]!=0);
// Palet Display (for Debug)
wire [8:0] PDOUT = (PV[7]|PV[8]) ? 0 : {PV[6:2],PH[7:4]};
// Color Mixer
dataselector_4D_9B dataselector_4D_9B(
.OUT(PALAD),
.EN1(DBGPD),
.IN1(PDOUT),
.EN2(FGPPQ),
.IN2(FGOUT),
.EN3(SPOPQ),
.IN3(SPOUT),
.EN4(FGOPQ),
.IN4(FGOUT),
.IND(BGOUT)
);
endmodule

BIN
Arcade_MiST/NinjaKun_MiST/rtl/rom/NINJAKUN.ROM
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BIN
Arcade_MiST/NinjaKun_MiST/rtl/rom/bg.bin
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BIN
Arcade_MiST/NinjaKun_MiST/rtl/rom/cpu1_rom.bin
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BIN
Arcade_MiST/NinjaKun_MiST/rtl/rom/cpu2_rom.bin
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534
Arcade_MiST/NinjaKun_MiST/rtl/rom/fg1_rom.vhd
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@@ -1,534 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity fg1_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of fg1_rom is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99",X"AA",X"AA",X"99",X"99",
X"55",X"55",X"EE",X"EE",X"58",X"88",X"8B",X"BB",X"99",X"9B",X"97",X"78",X"99",X"AA",X"AA",X"AA",
X"55",X"55",X"EE",X"55",X"88",X"88",X"88",X"BB",X"9B",X"BB",X"99",X"AA",X"9A",X"A9",X"99",X"99",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"11",X"11",X"11",X"21",X"21",X"12",X"12",
X"21",X"21",X"22",X"22",X"32",X"32",X"23",X"23",X"32",X"32",X"33",X"33",X"43",X"43",X"34",X"34",
X"43",X"43",X"34",X"34",X"54",X"54",X"45",X"45",X"54",X"54",X"45",X"45",X"65",X"65",X"56",X"56",
X"65",X"65",X"56",X"56",X"76",X"76",X"67",X"67",X"76",X"76",X"67",X"67",X"87",X"87",X"78",X"78",
X"87",X"87",X"78",X"78",X"98",X"98",X"89",X"89",X"98",X"98",X"89",X"89",X"A9",X"A9",X"9A",X"9A",
X"A9",X"A9",X"9A",X"9A",X"BA",X"BA",X"AB",X"AB",X"BA",X"BA",X"AB",X"AB",X"CB",X"CB",X"BC",X"BC",
X"CB",X"CB",X"BC",X"BC",X"DC",X"DC",X"CD",X"CD",X"DC",X"DC",X"CD",X"CD",X"ED",X"ED",X"DE",X"DE",
X"ED",X"ED",X"DE",X"DE",X"FE",X"FE",X"EF",X"EF",X"FE",X"FE",X"EF",X"EF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"40",
X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"4A",X"00",X"AA",X"00",X"DA",X"04",X"AA",X"00",X"AA",
X"4A",X"A4",X"4A",X"AA",X"AA",X"AA",X"AA",X"AD",X"AA",X"AA",X"AD",X"AA",X"AA",X"AA",X"AA",X"AD",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"44",X"00",X"4A",X"00",X"A4",X"00",X"AA",X"04",X"AA",X"44",X"AA",X"AA",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"41",X"00",X"11",X"40",X"11",X"44",X"11",
X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"04",X"00",X"04",X"00",X"04",X"00",X"04",X"00",X"44",
X"44",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"00",X"11",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"44",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"44",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"44",X"44",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"00",X"00",X"40",X"00",X"14",X"00",X"14",X"00",X"14",X"00",X"14",X"00",X"14",X"00",X"14",X"00",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"11",X"40",X"11",X"14",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"DA",X"AA",X"AA",X"AA",X"AA",X"DA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
X"A4",X"11",X"AA",X"33",X"AA",X"44",X"44",X"AA",X"4A",X"44",X"AA",X"33",X"A4",X"33",X"44",X"44",
X"AA",X"DA",X"AA",X"AA",X"AA",X"A4",X"4A",X"4F",X"E4",X"A4",X"E4",X"44",X"5E",X"04",X"5E",X"04",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"44",X"00",X"DD",X"00",X"DD",X"00",X"DD",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"44",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"44",X"DD",X"DD",X"DD",X"4D",X"DD",X"4D",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"44",X"44",X"DD",X"D4",X"DD",X"D4",X"DD",X"D4",
X"FF",X"5E",X"FF",X"5E",X"FF",X"5E",X"FF",X"E5",X"44",X"E5",X"34",X"E5",X"34",X"56",X"34",X"56",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"44",X"44",
X"66",X"88",X"66",X"57",X"66",X"58",X"66",X"55",X"66",X"22",X"66",X"99",X"66",X"BB",X"65",X"99",
X"88",X"88",X"77",X"77",X"58",X"88",X"35",X"55",X"32",X"22",X"39",X"99",X"39",X"BB",X"39",X"99",
X"5E",X"04",X"65",X"04",X"65",X"04",X"65",X"04",X"66",X"44",X"66",X"44",X"66",X"44",X"44",X"E4",
X"00",X"DD",X"00",X"DD",X"00",X"54",X"00",X"C4",X"00",X"C4",X"00",X"C4",X"00",X"C4",X"00",X"C4",
X"00",X"E4",X"00",X"E4",X"00",X"4E",X"00",X"4E",X"00",X"4E",X"00",X"4C",X"00",X"4C",X"00",X"4C",
X"00",X"C4",X"00",X"C4",X"00",X"C4",X"04",X"44",X"49",X"99",X"04",X"BB",X"00",X"55",X"00",X"54",
X"DD",X"DD",X"DD",X"DD",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",
X"DD",X"4D",X"DD",X"4D",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",
X"44",X"44",X"44",X"64",X"44",X"76",X"48",X"88",X"99",X"99",X"44",X"44",X"44",X"44",X"44",X"44",
X"44",X"44",X"44",X"44",X"43",X"44",X"43",X"44",X"99",X"99",X"44",X"44",X"44",X"44",X"44",X"44",
X"DD",X"D4",X"DD",X"D4",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",
X"3C",X"56",X"35",X"66",X"35",X"66",X"35",X"66",X"5E",X"66",X"5E",X"66",X"5E",X"66",X"E5",X"66",
X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"99",X"99",X"BB",X"44",X"44",X"44",X"44",X"44",
X"E5",X"55",X"E5",X"B9",X"55",X"B9",X"55",X"B9",X"55",X"B9",X"35",X"22",X"35",X"55",X"35",X"88",
X"65",X"9B",X"53",X"9B",X"53",X"9B",X"B3",X"9B",X"B3",X"9B",X"B3",X"9B",X"B3",X"9B",X"B3",X"9B",
X"39",X"B9",X"39",X"B9",X"39",X"B9",X"39",X"B9",X"39",X"B9",X"39",X"B9",X"39",X"B9",X"39",X"B9",
X"B3",X"9B",X"B3",X"9B",X"B3",X"9B",X"B3",X"9B",X"B3",X"9B",X"23",X"22",X"53",X"55",X"53",X"88",
X"39",X"B9",X"39",X"B9",X"39",X"B9",X"39",X"B9",X"39",X"B9",X"32",X"22",X"35",X"55",X"35",X"88",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"09",X"00",X"09",X"00",X"9D",X"00",X"9D",
X"00",X"00",X"00",X"00",X"99",X"99",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",
X"00",X"9D",X"00",X"9D",X"00",X"9D",X"00",X"9D",X"00",X"09",X"00",X"09",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"99",X"00",X"DD",X"00",X"DD",X"00",X"DD",X"00",X"DD",X"90",
X"DD",X"90",X"DD",X"90",X"DD",X"90",X"DD",X"90",X"DD",X"90",X"DD",X"90",X"DD",X"90",X"DD",X"90",
X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"99",X"99",
X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"99",X"DD",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"99",X"00",X"BB",X"09",X"BB",X"9B",X"BB",X"9B",X"BB",
X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"D9",X"99",
X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",
X"9B",X"BB",X"9B",X"BB",X"9B",X"BB",X"09",X"BB",X"09",X"BB",X"00",X"BB",X"00",X"9B",X"00",X"09",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

534
Arcade_MiST/NinjaKun_MiST/rtl/rom/fg2_rom.vhd
View File

@@ -1,534 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity fg2_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of fg2_rom is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

534
Arcade_MiST/NinjaKun_MiST/rtl/rom/fg3_rom.vhd
View File

@@ -1,534 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity fg3_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of fg3_rom is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",
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X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

534
Arcade_MiST/NinjaKun_MiST/rtl/rom/fg4_rom.vhd
View File

@@ -1,534 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity fg4_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of fg4_rom is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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X"17",X"00",X"17",X"00",X"17",X"00",X"17",X"00",X"17",X"00",X"17",X"00",X"17",X"00",X"17",X"00",
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X"14",X"14",X"22",X"11",X"11",X"21",X"72",X"04",X"11",X"4E",X"0D",X"D7",X"42",X"4E",X"02",X"01",
X"14",X"40",X"11",X"11",X"41",X"72",X"72",X"20",X"24",X"4B",X"2D",X"04",X"0A",X"2B",X"A4",X"4B",
X"E0",X"E4",X"7D",X"E0",X"0E",X"E7",X"EE",X"1E",X"42",X"7E",X"E0",X"0E",X"E7",X"EE",X"E0",X"EE",
X"A0",X"0D",X"1A",X"7D",X"AA",X"0D",X"B4",X"BD",X"B0",X"AD",X"BB",X"BD",X"BB",X"BD",X"BB",X"DD",
X"DE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",
X"CE",X"DD",X"CE",X"DD",X"CE",X"DD",X"CC",X"DD",X"CC",X"DD",X"CC",X"DD",X"CC",X"DD",X"CC",X"DD",
X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",
X"CC",X"DD",X"CC",X"DD",X"CC",X"DD",X"CC",X"DD",X"CC",X"DD",X"DC",X"DD",X"DC",X"DD",X"DC",X"DD",
X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",
X"DC",X"DD",X"DD",X"DE",X"DD",X"DE",X"DD",X"DE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",
X"DE",X"DD",X"DE",X"DD",X"DE",X"DD",X"DE",X"DD",X"DE",X"DD",X"DE",X"DD",X"1E",X"DD",X"1E",X"D1",
X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DC",X"EE",X"D1",X"EE",X"D1",X"EE",X"16",X"22",
X"BD",X"BB",X"BD",X"BB",X"BD",X"BB",X"BD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",
X"AD",X"BB",X"AD",X"BB",X"AD",X"BB",X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",
X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",
X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",X"AA",X"BB",
X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",
X"AA",X"BB",X"AA",X"AA",X"BA",X"AA",X"BA",X"AA",X"BA",X"AD",X"BA",X"AD",X"BA",X"AD",X"BA",X"AD",
X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"BD",X"BB",X"BD",X"BB",X"BD",X"BB",X"BD",X"BB",X"22",X"BB",
X"BB",X"AD",X"BB",X"AD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"82",X"21",X"22",
X"ED",X"EE",X"EE",X"EE",X"EE",X"EB",X"EE",X"EB",X"EE",X"EB",X"DD",X"EB",X"DE",X"DA",X"DE",X"EB",
X"AB",X"DD",X"AB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"AA",X"DD",X"BB",X"DE",X"BB",X"DD",
X"DE",X"EB",X"DE",X"EE",X"DE",X"EE",X"DE",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"DE",X"DD",X"ED",
X"BB",X"DD",X"BB",X"DD",X"BB",X"DD",X"BB",X"BD",X"BD",X"DD",X"BD",X"DD",X"AD",X"DD",X"BD",X"BD",
X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"CE",
X"BD",X"DD",X"BD",X"DE",X"BD",X"DE",X"DD",X"DE",X"DD",X"DE",X"DD",X"DD",X"DD",X"DD",X"DD",X"EB",
X"DD",X"EE",X"DD",X"EC",X"DD",X"EE",X"DD",X"EE",X"DD",X"DE",X"EB",X"2E",X"12",X"21",X"22",X"22",
X"DD",X"EB",X"DD",X"EB",X"DD",X"DB",X"DD",X"DD",X"DD",X"DD",X"11",X"11",X"22",X"21",X"22",X"22",
X"BD",X"EE",X"BD",X"EE",X"AD",X"EE",X"0D",X"EE",X"AD",X"EE",X"0D",X"EE",X"CD",X"EB",X"DD",X"BB",
X"CC",X"BB",X"B0",X"AE",X"B0",X"EE",X"BA",X"EE",X"AA",X"DE",X"AA",X"DA",X"AA",X"AA",X"AA",X"AA",
X"DD",X"BB",X"DD",X"CC",X"CD",X"AA",X"DD",X"DA",X"DD",X"DA",X"DE",X"DD",X"DE",X"ED",X"22",X"ED",
X"BB",X"AA",X"BB",X"AC",X"CB",X"CC",X"EA",X"0C",X"EE",X"0C",X"EE",X"A0",X"EE",X"A1",X"EE",X"11",
X"BD",X"EE",X"BD",X"EE",X"AD",X"EE",X"0D",X"EE",X"AD",X"EE",X"0D",X"EE",X"CD",X"EB",X"DD",X"BB",
X"CC",X"BB",X"B0",X"AE",X"B0",X"EE",X"BA",X"EE",X"AA",X"DE",X"AA",X"DA",X"AA",X"AA",X"AA",X"AA",
X"DD",X"BB",X"DD",X"CC",X"CD",X"AA",X"DD",X"DA",X"DD",X"DA",X"DE",X"DD",X"DE",X"ED",X"DE",X"ED",
X"BB",X"AA",X"BB",X"AC",X"CB",X"CC",X"EA",X"0C",X"EE",X"0C",X"EE",X"A0",X"EE",X"A0",X"EE",X"A0",
X"CB",X"DE",X"CC",X"DE",X"CC",X"EE",X"CC",X"EE",X"EE",X"CA",X"EE",X"CB",X"EE",X"AC",X"EE",X"AC",
X"0B",X"C0",X"A0",X"CD",X"AB",X"CD",X"0B",X"DD",X"BB",X"DD",X"BB",X"BA",X"CB",X"BB",X"CE",X"BB",
X"DB",X"BC",X"D0",X"BC",X"BB",X"BD",X"BB",X"CD",X"BB",X"CD",X"BB",X"CE",X"BC",X"EE",X"BC",X"EE",
X"EE",X"CC",X"EE",X"AC",X"EE",X"A0",X"DE",X"A0",X"DD",X"CC",X"BD",X"CC",X"CC",X"CC",X"AC",X"CC",
X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"EE",X"DD",X"CE",
X"BD",X"DD",X"BD",X"DE",X"BD",X"DE",X"DD",X"DE",X"DD",X"DE",X"DD",X"DD",X"DD",X"DD",X"DD",X"EB",
X"DD",X"EE",X"DD",X"EC",X"DD",X"EE",X"DD",X"EE",X"DD",X"DE",X"EB",X"1E",X"11",X"11",X"21",X"21",
X"DD",X"EB",X"DD",X"EB",X"DD",X"DB",X"DD",X"DD",X"DD",X"DD",X"11",X"11",X"11",X"11",X"22",X"11",
X"DB",X"DB",X"BD",X"BD",X"DB",X"DC",X"CC",X"CD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"CD",X"CC",
X"DB",X"DB",X"BD",X"CC",X"CC",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DC",X"CC",X"CC",X"DE",
X"CC",X"CD",X"DE",X"DE",X"ED",X"ED",X"DE",X"DE",X"ED",X"ED",X"DE",X"DC",X"DC",X"CB",X"BD",X"BD",
X"ED",X"ED",X"DE",X"DE",X"ED",X"ED",X"DE",X"DE",X"ED",X"CC",X"CD",X"BD",X"DB",X"DB",X"BD",X"BD",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"06",X"00",X"60",X"60",X"00",X"06",X"00",X"06",X"00",X"60",X"00",X"00",X"60",X"00",X"06",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",X"11",
X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",
X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",X"33",
X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",X"44",
X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",
X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",
X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",
X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",X"BB",
X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",
X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",X"DD",
X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",X"EE",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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0
Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qpf → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qpf
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12
Arcade_MiST/NinjaKun_MiST/NinjaKun_MiST.qsf → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/NinjaKun_MiST.qsf
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@@ -245,17 +245,9 @@ set_global_assignment -name VHDL_FILE rtl/rom/fg3_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/fg2_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/fg1_rom.vhd
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VHDL_FILE rtl/cpu/T80s.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name VERILOG_FILE rtl/mems.v
set_global_assignment -name VHDL_FILE rtl/dpram_1r1w.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024.v
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

0
Arcade_MiST/NinjaKun_MiST/Snapshot/NINJAKUN.ROM → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/Snapshot/NINJAKUN.ROM
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0
Arcade_MiST/NinjaKun_MiST/clean.bat → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/clean.bat
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0
Arcade_MiST/NinjaKun_MiST/rtl/NinjaKun_MiST.sv → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/NinjaKun_MiST.sv
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0
Arcade_MiST/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/YM2149_linmix_sep.vhd
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0
Arcade_MiST/Sega Zaxxon Hardware/rtl/build_id.tcl → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/build_id.tcl
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0
Arcade_MiST/NinjaKun_MiST/rtl/dataselector_3D_8B.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_3D_8B.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/dataselector_4D_9B.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_4D_9B.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/dataselector_5D_8B.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dataselector_5D_8B.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/dpram.vhd → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/dpram.vhd
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0
Arcade_MiST/NinjaKun_MiST/rtl/hvgen.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/hvgen.v
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305
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/mems.v Normal file
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@@ -0,0 +1,305 @@
// Copyright (c) 2011 MiSTer-X
module VDPRAM400x2
(
input CL0,
input [10:0] AD0,
input WR0,
input [7:0] WD0,
output [7:0] RD0,
input CL1,
input [9:0] AD1,
output [15:0] RD1
);
reg A10;
always @( posedge CL0 ) A10 <= AD0[10];
wire [7:0] RD00, RD01;
DPRAM400 LS( CL0, AD0[9:0], WR0 & (~AD0[10]), WD0, RD00, CL1, AD1, 1'b0, 8'h0, RD1[ 7:0] );
DPRAM400 HS( CL0, AD0[9:0], WR0 & ( AD0[10]), WD0, RD01, CL1, AD1, 1'b0, 8'h0, RD1[15:8] );
assign RD0 = A10 ? RD01 : RD00;
endmodule
module DPRAM800
(
input CL0,
input [10:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [10:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:2047];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule
module DPRAM400
(
input CL0,
input [9:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [9:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:1023];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule
module DPRAM200
(
input CL0,
input [8:0] AD0,
input WE0,
input [7:0] WD0,
output reg [7:0] RD0,
input CL1,
input [8:0] AD1,
input WE1,
input [7:0] WD1,
output reg [7:0] RD1
);
reg [7:0] core[0:511];
always @( posedge CL0 ) begin
if (WE0) core[AD0] <= WD0;
RD0 <= core[AD0];
end
always @( posedge CL1 ) begin
if (WE1) core[AD1] <= WD1;
RD1 <= core[AD1];
end
endmodule
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DPRAM1024 (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fg_sp_dulport_rom (
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b);
input [12:0] address_a;
input [12:0] address_b;
input clock_a;
input clock_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [31:0] sub_wire3 = 32'h0;
wire [31:0] q_b = sub_wire0[31:0];
wire [31:0] q_a = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (sub_wire2),
.address_b (address_b),
.clock1 (clock_b),
.data_b (sub_wire3),
.wren_b (sub_wire2),
.address_a (address_a),
.data_a (sub_wire3),
.q_b (sub_wire0),
.q_a (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
`ifdef NO_PLI
altsyncram_component.init_file = "./rom/gfx1.rif"
`else
altsyncram_component.init_file = "./rom/gfx1.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule

0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_adec.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_adec.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_bg.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_bg.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_clkgen.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_clkgen.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_cpumux.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_cpumux.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_fg.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_fg.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_input.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_input.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_io_video.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_io_video.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_irqgen.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_irqgen.v
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3
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_main.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_main.v
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@@ -1,5 +1,4 @@
module ninjakun_main
(
module ninjakun_main(
input RESET,
input CLK24M,
input CLK3M,

0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_psg.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_psg.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sadec.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sadec.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_sp.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_sp.v
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0
Arcade_MiST/NinjaKun_MiST/rtl/ninjakun_top.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_top.v
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0
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/ninjakun_video.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/ninjakun_video.v
View File

10
Arcade_MiST/NinjaKun_MiST/rtl/pll.v → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/pll.v
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@@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@@ -179,7 +179,7 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
@@ -209,12 +209,12 @@ endmodule
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"

0
Arcade_MiST/Nova2001_MiST/NinjaKun_MiST/rtl/rom/gfx1.hex → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/gfx1.hex
View File

10
Arcade_MiST/NinjaKun_MiST/rtl/rom/make_rom.bat → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_rom.bat
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@@ -3,10 +3,10 @@ copy /b ninja-5.7h + ninja-2.7b + ninja-3.7d + ninja-4.7e cpu2_rom.bin
copy /b ninja-10.2c + ninja-11.2d + ninja-12.4c + ninja-13.4d bg.bin
copy /b cpu1_rom.bin + cpu2_rom.bin + bg.bin NINJAKUN.ROM
make_vhdl_prom.exe ninja-10.2c fg1_rom.vhd
make_vhdl_prom.exe ninja-11.2d fg2_rom.vhd
make_vhdl_prom.exe ninja-12.4c fg3_rom.vhd
make_vhdl_prom.exe ninja-13.4d fg4_rom.vhd
copy /b ninja-6.7n + ninja-7.7p + ninja-8.7s + ninja-9.7t fg.bin
make_vhdl_prom.exe ninja-6.7n fg1_rom.vhd
make_vhdl_prom.exe ninja-7.7p fg2_rom.vhd
make_vhdl_prom.exe ninja-8.7s fg3_rom.vhd
make_vhdl_prom.exe ninja-9.7t fg4_rom.vhd
pause

0
Arcade_MiST/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/make_vhdl_prom.exe
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0
Arcade_MiST/NinjaKun_MiST/rtl/rom/ninjakun.zip → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/ninjakun.zip
View File

BIN
Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/rom/srec_cat.exe Normal file
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Binary file not shown.

0
Arcade_MiST/NinjaKun_MiST/rtl/sdram.sv → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/sdram.sv
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0
Arcade_MiST/NinjaKun_MiST/rtl/spram.vhd → Arcade_MiST/Nova2001_Hardware/NinjaKun_MiST/rtl/spram.vhd
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