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Merge pull request #100 from gyurco/segasys1

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Sega System 1
This commit is contained in:
Marcel
2020-10-23 19:22:04 +02:00
committed by GitHub
parent f920885e1a 9737c62b40
commit 65f540b5cb
34 changed files with 4659 additions and 0 deletions
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Arcade_MiST/Sega System 1 Hardware/README.txt Normal file
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-- Arcade: SEGA System 1 port to MiST by Slingshot
--
-- Usage:
-- - Create ROM and ARC files from the MRA files in the meta directory
-- using the MRA utility.
-- Example: mra -A -z /path/to/mame/roms "Flicky.mra"
-- - Copy the ROM files to the root of the SD Card
-- - Copy the RBF and ARC files to the same folder on the SD Card
--
-- MRA utility: https://github.com/sebdel/mra-tools-c/
--
-- Keyboard inputs :
--
-- ESC : Coin
-- F2 : Start 2 players
-- F1 : Start 1 player
-- UP,DOWN,LEFT,RIGHT arrows : Movements
-- Left Ctrl : Trig1
-- Left Alt : Trig2
-- SPACE : Trig3
---------------------------------------------------------------------------------
--
-- Arcade: SEGA System 1 for MiSTer by MiSTer-X
-- 07 January 2020
--
---------------------------------------------------------------------------------
-- T80/T80s - Version : 0242
--------------------------------
-- Z80 compatible microprocessor core
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---------------------------------------------------------------------------------
--
-- Keyboard inputs :
--
-- F2 : Coin + Start 2 players
-- F1 : Coin + Start 1 player
-- UP,DOWN,LEFT,RIGHT arrows : Movements
-- SPACE : Trig1
-- CTRL : Trig2
-- ALT : Trig3
--
-- MAME/IPAC/JPAC Style Keyboard inputs:
-- 5 : Coin 1
-- 6 : Coin 2
-- 1 : Start 1 Player
-- 2 : Start 2 Players
-- R,F,D,G : Player 2 Movements
-- A : Player 2 Trig1
-- S : Player 2 Trig2
-- Q : Player 2 Trig3
--
-- Joystick support.
--
---------------------------------------------------------------------------------
-- 2020/01/08 Impl. Trigger 3 (for SEGA Ninja)
---------------------------------------------------------------------------------
*** Attention ***
ROM is not included. In order to use this arcade, you need to provide a correct ROM file.
Find this zip file somewhere. You need to find the file exactly as required.
Do not rename other zip files even if they also represent the same game - they are not compatible!
The name of zip is taken from M.A.M.E. project, so you can get more info about
hashes and contained files there.
How to install:
0. Update MiSTer binary to v200106 or later
1. copy releases/*.mra to /media/fat/_Arcade
2. copy releases/*.rbf to /media/fat/_Arcade/cores
3. copy ROM zip files to /media/fat/_Arcade/mame
Be sure to use the MRA file in "releases" of this repository.
It does not guarantee the operation when using other MRA files.

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Arcade_MiST/Sega System 1 Hardware/Segasys1.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 00:21:03 December 03, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "00:21:03 December 03, 2019"
# Revisions
PROJECT_REVISION = "Segasys1"

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Arcade_MiST/Sega System 1 Hardware/Segasys1.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 02:55:28 May 26, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Segasys1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY Segasys1_MiST
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------------
# start ENTITY(Segasys1_MiST)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Segasys1_MiST)
# ------------------------
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Segasys1_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/HVGEN.v
set_global_assignment -name VERILOG_FILE rtl/SEGASYS1.v
set_global_assignment -name VERILOG_FILE rtl/SEGASYS1_VIDEO.v
set_global_assignment -name VERILOG_FILE rtl/SEGASYS1_SPRITE.v
set_global_assignment -name VERILOG_FILE rtl/SEGASYS1_SOUND.v
set_global_assignment -name VERILOG_FILE rtl/SEGASYS1_PRGDEC.v
set_global_assignment -name VERILOG_FILE rtl/SEGASYS1_MAIN.v
set_global_assignment -name VERILOG_FILE rtl/parts.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
set_global_assignment -name VERILOG_FILE rtl/z80ip.v
set_global_assignment -name VERILOG_FILE rtl/DPRAM1024_11B.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name QIP_FILE ../../common/Sound/sn76489/sn76489.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name SIGNALTAP_FILE output_files/bg.stp
set_global_assignment -name SIGNALTAP_FILE output_files/spr.stp
set_global_assignment -name SIGNALTAP_FILE output_files/dect.stp
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Sega System 1 Hardware/Segasys1.sdc Normal file
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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

37
Arcade_MiST/Sega System 1 Hardware/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

63
Arcade_MiST/Sega System 1 Hardware/meta/4-D Warriors.mra Normal file
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<misterromdescription>
<name>4D Warriors</name>
<mameversion>0216</mameversion>
<setname>4dwarrio</setname>
<mratimestamp>202001100000</mratimestamp>
<year>1985</year>
<manufacturer>Sega</manufacturer>
<category>Shmup</category>
<rbf>segasys1</rbf>
<switches default="FF,FF" base="8">
<dip bits="9,10" name="Lives" ids="Free Play,5,4,3"/>
<dip bits="11,13" name="Bonus at" ids="Never,90k,80k,70k,60k,50k,40k,30k"/>
<dip bits="14" name="Difficulty" ids="Hard,Easy"/>
</switches>
<rom index="1">
<part>04</part>
</rom>
<rom index="0" zip="4dwarrio.zip" md5="3d4c746696e10b81c35b7aa0f0578bd4" type="merged|nonmerged|split">
<part name="4d.116"/>
<part name="4d.109"/>
<part name="4d.96"/>
<part name="4d.120"/>
<part name="4d.120"/>
<part name="4d.117"/>
<part name="4d.04"/>
<part name="4d.110"/>
<part name="4d.05"/>
<group width="32">
<part name="4d.62"/>
<part name="4d.64"/>
<part name="4d.66"/>
<part name="4d.66"/>
</group>
<group width="32">
<part name="4d.61"/>
<part name="4d.63"/>
<part name="4d.65"/>
<part name="4d.65"/>
</group>
<part name="pr5317.76"/>
<part>
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
04 04 04 04 04 04 04 04 04 04 04 04 04 04 04 05
05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 06
06 06 06 06 06 06 06 06 06 06 06 06 06 06 06 07
07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 08
08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 09
09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 0A
0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0B
0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0C
</part>
</rom>
</misterromdescription>

59
Arcade_MiST/Sega System 1 Hardware/meta/Flicky.mra Normal file
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@@ -0,0 +1,59 @@
<misterromdescription>
<name>Flicky (128k Version, 315-5051)</name>
<mameversion>0217</mameversion>
<setname>flicky</setname>
<mratimestamp>202001070000</mratimestamp>
<year>1984</year>
<manufacturer>Sega</manufacturer>
<category>Maze / Cat and Mouse</category>
<category>Platform</category>
<rbf>segasys1</rbf>
<switches default="FF,7C" base="8">
<dip bits="10,11" name="Lives" ids="Infinite,5,4,3"/>
<dip bits="12,13" name="Extend" ids="40k 140k 280k,40k 120k 240k,30k 100k 200k,30k 80k 160k"/>
<dip bits="14" name="Difficulty" ids="Hard,Easy"/>
</switches>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="flicky.zip" md5="1d3e6b48d8123a56b9b579dfba94704b" type="merged|nonmerged|split">
<!-- Main CPU -->
<part name="epr-5978a.116"/>
<part name="epr-5979a.109"/>
<part name="epr-5979a.109"/>
<!-- Sound CPU -->
<part name="epr-5869.120"/>
<part name="epr-5869.120"/>
<!-- Sprites -->
<part name="epr-5855.117"/>
<part name="epr-5856.110"/>
<part name="epr-5855.117"/>
<part name="epr-5856.110"/>
<!-- Tiles -->
<group width="32">
<part name="epr-5868.62"/>
<part name="epr-5866.64"/>
<part name="epr-5864.66"/>
<part name="epr-5864.66"/>
</group>
<group width="32">
<part name="epr-5867.61"/>
<part name="epr-5865.63"/>
<part name="epr-5863.65"/>
<part name="epr-5863.65"/>
</group>
<!-- CLUT -->
<part name="pr-5317.76"/>
<part>
08 88 00 80 a0 80 a8 88 80 00 a0 20 88 80 08 00
a0 80 a8 88 28 08 20 00 28 08 20 00 a0 80 a8 88
08 88 00 80 80 00 a0 20 80 00 a0 20 88 80 08 00
28 08 20 00 28 08 20 00 28 08 20 00 88 80 08 00
08 88 00 80 a8 88 28 08 a8 88 28 08 80 00 a0 20
28 08 20 00 88 80 08 00 a8 88 28 08 88 80 08 00
08 88 00 80 80 00 a0 20 a8 88 28 08 80 00 a0 20
28 08 20 00 28 08 20 00 08 88 00 80 88 80 08 00
</part>
</rom>
</misterromdescription>

55
Arcade_MiST/Sega System 1 Hardware/meta/I'm Sorry.mra Normal file
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@@ -0,0 +1,55 @@
<misterromdescription>
<name>I'm Sorry (315-5110, US)</name>
<mameversion>0217</mameversion>
<setname>imsorry</setname>
<mratimestamp>202001070000</mratimestamp>
<year>1985</year>
<manufacturer>Coreland / Sega</manufacturer>
<category>Maze</category>
<rbf>segasys1</rbf>
<switches default="FF,7E" base="8">
<dip bits="9" name="Demo Sound" ids="On,Off"/>
<dip bits="10,11" name="Lives" ids="Infinite,5,4,3"/>
<dip bits="12,13" name="Extend" ids="None,70000,50000,30000"/>
</switches>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="imsorry.zip" md5="f8c20005acedc939c0a56623189b2b35" type="merged|nonmerged|split">
<part name="epr-6676.116"/>
<part name="epr-6677.109"/>
<part name="epr-6678.96"/>
<part name="epr-6656.120"/>
<part name="epr-6656.120"/>
<part name="epr-6645.117"/>
<part name="epr-6646.04"/>
<part name="epr-6645.117"/>
<part name="epr-6646.04"/>
<group width="32">
<part name="epr-6684.62"/>
<part name="epr-6682.64"/>
<part name="epr-6680.66"/>
<part name="epr-6680.66"/>
</group>
<group width="32">
<part name="epr-6683.61"/>
<part name="epr-6681.63"/>
<part name="epr-6674.65"/>
<part name="epr-6674.65"/>
</group>
<part name="pr-5317.76"/>
<part>
88 08 80 00 00 20 80 a0 00 20 80 a0 88 08 80 00
88 08 a8 28 00 20 80 a0 00 20 80 a0 88 08 a8 28
00 20 80 a0 08 00 88 80 00 20 80 a0 20 28 a0 a8
20 28 a0 a8 00 20 80 a0 20 28 a0 a8 88 08 a8 28
88 08 80 00 08 00 88 80 08 00 88 80 88 08 80 00
08 28 00 20 08 28 00 20 88 08 80 00 08 28 00 20
08 28 00 20 08 00 88 80 08 28 00 20 20 28 a0 a8
20 28 a0 a8 08 28 00 20 20 28 a0 a8 08 28 00 20
</part>
</rom>
</misterromdescription>

59
Arcade_MiST/Sega System 1 Hardware/meta/Mister Viking.mra Normal file
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@@ -0,0 +1,59 @@
<misterromdescription>
<name>Mister Viking (315-5041)</name>
<mameversion>0217</mameversion>
<setname>mrviking</setname>
<mratimestamp>202001070000</mratimestamp>
<year>1984</year>
<manufacturer>Sega</manufacturer>
<category>Fighter / Warriors</category>
<rbf>segasys1</rbf>
<switches default="FF,7E" base="8">
<dip bits="9" name="Maximum Credits" ids="99,9"/>
<dip bits="10,11" name="Lives" ids="Infinite,5,4,3"/>
<dip bits="12,13" name="Extend" ids="40k ev.30k,30k ev.30k,20k 40k ev.30k,10k 30k ev.30k"/>
<dip bits="14" name="Difficulty" ids="Hard,Easy"/>
</switches>
<rom index="1">
<part>06</part>
</rom>
<rom index="0" zip="mrviking.zip" md5="cfbeafcd3f71d2045f81e0401afdc11c" type="merged|nonmerged|split">
<part name="epr-5873.129"/>
<part name="epr-5874.130"/>
<part name="epr-5875.131"/>
<part name="epr-5876.132"/>
<part name="epr-5755.133"/>
<part name="epr-5756.134"/>
<part name="epr-5763.3"/>
<part name="epr-5763.3"/>
<part name="epr-5749.86"/>
<part name="epr-5750.93"/>
<part repeat="0x8000">FF</part>
<group width="32">
<part name="epr-5762.82"/>
<part name="epr-5760.81"/>
<part name="epr-5758.80"/>
<part name="epr-5758.80"/>
</group>
<group width="32">
<part name="epr-5761.65"/>
<part name="epr-5759.64"/>
<part name="epr-5757.63"/>
<part name="epr-5757.63"/>
</group>
<part name="pr-5317.106"/>
<part>
28 a8 08 88 88 80 08 00 88 08 80 00 88 80 08 00
28 08 a8 88 28 a8 08 88 88 08 80 00 88 08 80 00
28 08 a8 88 88 80 08 00 88 80 08 00 28 a8 08 88
a0 80 a8 88 28 08 a8 88 a0 80 a8 88 a0 80 a8 88
88 80 08 00 88 80 08 00 88 08 80 00 88 80 08 00
a0 80 20 00 28 08 a8 88 a0 80 20 00 88 08 80 00
28 08 a8 88 a0 80 20 00 a0 80 20 00 a0 80 20 00
a0 80 a8 88 28 08 a8 88 a0 80 20 00 a0 80 a8 88
</part>
</rom>
</misterromdescription>

56
Arcade_MiST/Sega System 1 Hardware/meta/My Hero.mra Normal file
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@@ -0,0 +1,56 @@
<misterromdescription>
<name>My Hero (US, not encrypted)</name>
<mameversion>0217</mameversion>
<setname>myhero</setname>
<mratimestamp>202001060000</mratimestamp>
<year>1985</year>
<manufacturer>Coreland / Sega</manufacturer>
<category>Fighter / Hero</category>
<rbf>segasys1</rbf>
<switches default="FF,7E" base="8">
<dip bits="9" name="Demo Sound" ids="On,Off"/>
<dip bits="10,11" name="Lives" ids="Infinite,5,4,3"/>
<dip bits="12,13" name="Extend" ids="90000,70000,50000,30000"/>
<dip bits="14" name="Difficulty" ids="Hard,Easy"/>
</switches>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="myhero.zip" md5="08d9e275da478606db8cdeae79b92b5c" type="merged|nonmerged|split">
<part name="epr-6963b.116"/>
<part name="epr-6964a.109"/>
<part name="epr-6927.96"/>
<part name="epr-69xx.120"/>
<part name="epr-69xx.120"/>
<part name="epr-6921.117"/>
<part name="epr-6923.04"/>
<part name="epr-6922.110"/>
<part name="epr-6924.05"/>
<group width="32">
<part name="epr-6966.62"/>
<part name="epr-6960.64"/>
<part name="epr-6958.66"/>
<part name="epr-6958.66"/>
</group>
<group width="32">
<part name="epr-6961.61"/>
<part name="epr-6959.63"/>
<part name="epr-6957.65"/>
<part name="epr-6957.65"/>
</group>
<part name="pr-5317.76"/>
<part>
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
</part>
</rom>
</misterromdescription>

63
Arcade_MiST/Sega System 1 Hardware/meta/Rafflesia.mra Normal file
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@@ -0,0 +1,63 @@
<misterromdescription>
<name>Rafflesia</name>
<mameversion>0216</mameversion>
<setname>raflesia</setname>
<mratimestamp>202001100000</mratimestamp>
<year>1986</year>
<manufacturer>Sega</manufacturer>
<category>Shmup</category>
<rbf>segasys1</rbf>
<switches default="FF,FC" base="8">
<dip bits="9" name="Demo Sound" ids="On,Off"/>
<dip bits="10,11" name="Lives" ids="Free Play,5,4,3"/>
<dip bits="12,13" name="Bonus at" ids="Never,50k 100k 200k,30k 80k 150k,20k 70k 120k"/>
</switches>
<rom index="1">
<part>06</part>
</rom>
<rom index="0" zip="raflesia.zip" md5="96d903a327f9ec40ded22754011dee89" type="merged|nonmerged|split">
<part name="epr-7411.116"/>
<part name="epr-7412.109"/>
<part name="epr-7413.96"/>
<part name="epr-7420.120"/>
<part name="epr-7420.120"/>
<part name="epr-7407.117"/>
<part name="epr-7409.04"/>
<part name="epr-7408.110"/>
<part name="epr-7410.05"/>
<group width="32">
<part name="epr-7419.62"/>
<part name="epr-7417.64"/>
<part name="epr-7415.66"/>
<part name="epr-7415.66"/>
</group>
<group width="32">
<part name="epr-7418.61"/>
<part name="epr-7416.63"/>
<part name="epr-7414.65"/>
<part name="epr-7414.65"/>
</group>
<part name="pr-5317.76"/>
<part>
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
40 10 50 04 44 14 54 01 41 11 51 05 45 15 55 00
04 04 04 04 04 04 04 04 04 04 04 04 04 04 04 05
05 05 05 05 05 05 05 05 05 05 05 05 05 05 05 06
06 06 06 06 06 06 06 06 06 06 06 06 06 06 06 07
07 07 07 07 07 07 07 07 07 07 07 07 07 07 07 08
08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 09
09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 0A
0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0B
0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0B 0C
</part>
</rom>
</misterromdescription>

57
Arcade_MiST/Sega System 1 Hardware/meta/Regulus.mra Normal file
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@@ -0,0 +1,57 @@
<misterromdescription>
<name>Regulus</name>
<mameversion>0216</mameversion>
<setname>regulus</setname>
<mratimestamp>202001100000</mratimestamp>
<year>1983</year>
<manufacturer>Sega</manufacturer>
<category>Shmup</category>
<rbf>segasys1</rbf>
<switches default="FF,7F" base="8">
<dip bits="10,11" name="Lives" ids="Infinite,5,4,3"/>
<dip bits="14" name="Difficulty" ids="Hard,Easy"/>
<dip bits="15" name="Allow Continue" ids="Yes,No"/>
</switches>
<rom index="1">
<part>06</part>
</rom>
<rom index="0" zip="regulus.zip" md5="69bf2d45b0a5e13df70d60ba6505dfad" type="merged|nonmerged|split">
<part name="epr-5640a.129"/>
<part name="epr-5641a.130"/>
<part name="epr-5642a.131"/>
<part name="epr-5643a.132"/>
<part name="epr-5644.133"/>
<part name="epr-5645a.134"/>
<part name="epr-5652.3"/>
<part name="epr-5652.3"/>
<part name="epr-5638.86"/>
<part name="epr-5639.93"/>
<part name="epr-5638.86"/>
<part name="epr-5639.93"/>
<group width="32">
<part name="epr-5651.82"/>
<part name="epr-5649.81"/>
<part name="epr-5647.80"/>
<part name="epr-5647.80"/>
</group>
<group width="32">
<part name="epr-5650.65"/>
<part name="epr-5648.64"/>
<part name="epr-5646.63"/>
<part name="epr-5646.63"/>
</group>
<part name="pr-5317.106"/>
<part>
28 08 a8 88 88 80 08 00 28 08 a8 88 28 a8 08 88
88 80 08 00 88 08 80 00 88 08 80 00 28 a8 08 88
28 08 a8 88 88 80 08 00 88 80 08 00 88 80 08 00
88 08 80 00 88 08 80 00 a0 80 a8 88 a0 80 a8 88
80 a0 00 20 28 08 a8 88 28 a8 08 88 28 08 a8 88
80 a0 00 20 80 a0 00 20 28 a8 08 88 80 a0 00 20
a0 80 a8 88 28 08 a8 88 80 a0 00 20 a0 80 a8 88
a0 80 a8 88 80 a0 00 20 a0 80 a8 88 a0 80 a8 88
</part>
</rom>
</misterromdescription>

56
Arcade_MiST/Sega System 1 Hardware/meta/Sega Ninja.mra Normal file
View File

@@ -0,0 +1,56 @@
<misterromdescription>
<name>Sega Ninja (315-5102)</name>
<mameversion>0217</mameversion>
<setname>seganinj</setname>
<mratimestamp>20200107000000</mratimestamp>
<year>1985</year>
<manufacturer>Sega</manufacturer>
<category>Fighter / Asian</category>
<rbf>segasys1</rbf>
<switches default="FF,7E" base="8">
<dip bits="9" name="Demo Sound" ids="On,Off"/>
<dip bits="10,11" name="Lives" ids="240,4,2,3"/>
<dip bits="12" name="Extend" ids="50k 100k 150k 200k,20k 70k 120k 170k"/>
<dip bits="13" name="Allow Continue" ids="No,Yes"/>
<dip bits="14" name="Difficulty" ids="Hard,Easy"/>
</switches>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="seganinj.zip" md5="2ab698c59d739fdbfc7a267ace9df24f" type="merged|nonmerged|split">
<part name="epr-6594a.116"/>
<part name="epr-6595a.109"/>
<part name="epr-6596a.96"/>
<part name="epr-6559.120"/>
<part name="epr-6559.120"/>
<part name="epr-6546.117"/>
<part name="epr-6548.04"/>
<part name="epr-6547.110"/>
<part name="epr-6549a.05"/>
<group width="32">
<part name="epr-6558.62"/>
<part name="epr-6556.64"/>
<part name="epr-6554.66"/>
<part name="epr-6554.66"/>
</group>
<group width="32">
<part name="epr-6592.61"/>
<part name="epr-6590.63"/>
<part name="epr-6588.65"/>
<part name="epr-6588.65"/>
</group>
<part name="pr-5317.76"/>
<part>
88 a8 80 a0 88 08 80 00 28 a8 08 88 a0 a8 80 88
a8 a0 28 20 a8 a0 28 20 28 a8 08 88 a0 a8 80 88
28 08 a8 88 28 08 a8 88 28 a8 08 88 88 08 80 00
28 08 a8 88 28 08 a8 88 28 a8 08 88 a8 a0 28 20
88 08 80 00 88 a8 80 a0 a0 a8 80 88 28 a8 08 88
a8 a0 28 20 88 a8 80 a0 a8 a0 28 20 28 a8 08 88
28 08 a8 88 88 a8 80 a0 28 08 a8 88 28 08 a8 88
88 a8 80 a0 88 a8 80 a0 a8 a0 28 20 28 08 a8 88
</part>
</rom>
</misterromdescription>

57
Arcade_MiST/Sega System 1 Hardware/meta/Spatter.mra Normal file
View File

@@ -0,0 +1,57 @@
<misterromdescription>
<name>Spatter (315-5xxx)</name>
<mameversion>0217</mameversion>
<setname>spatter</setname>
<mratimestamp>202001070000</mratimestamp>
<year>1984</year>
<manufacturer>Sega</manufacturer>
<category>Maze / Extra</category>
<category>Racing / Bicycle</category>
<rbf>segasys1</rbf>
<switches default="FF,7E" base="8">
<dip bits="9" name="Demo Sound" ids="On,Off"/>
<dip bits="10,11" name="Lives" ids="Infinite,4,2,3"/>
<dip bits="12,13" name="Extend" ids="None,100k only,50k 200k,40k 120k 480k"/>
<dip bits="14" name="Reset Timer and Objects" ids="Yes,No"/>
</switches>
<rom index="1">
<part>04</part>
</rom>
<rom index="0" zip="spatter.zip" md5="4e3dd2f53b76da95ff2c22c42e77d22d" type="merged|nonmerged|split">
<part name="epr-6392.116"/>
<part name="epr-6393.109"/>
<part name="epr-6394.96"/>
<part name="epr-6316.120"/>
<part name="epr-6316.120"/>
<part name="epr-6306.04"/>
<part name="epr-6308.117"/>
<part name="epr-6307.05"/>
<part name="epr-6309.110"/>
<group width="32">
<part name="epr-6328.62"/>
<part name="epr-6326.64"/>
<part name="epr-6324.66"/>
<part name="epr-6324.66"/>
</group>
<group width="32">
<part name="epr-6397.61"/>
<part name="epr-6396.63"/>
<part name="epr-6395.65"/>
<part name="epr-6395.65"/>
</group>
<part name="pr-5317.106"/>
<part>
88 08 80 00 00 08 20 28 28 a8 08 88 28 a8 08 88
28 20 a8 a0 28 20 a8 a0 88 08 80 00 88 08 80 00
00 08 20 28 88 08 80 00 a0 80 20 00 80 88 00 08
88 08 80 00 a0 80 20 00 88 08 80 00 28 20 a8 a0
28 a8 08 88 80 88 00 08 80 88 00 08 00 08 20 28
28 20 a8 a0 28 a8 08 88 00 08 20 28 80 a0 88 a8
80 88 00 08 a0 80 20 00 80 a0 88 a8 a0 80 20 00
a0 80 20 00 80 a0 88 a8 28 20 a8 a0 00 08 20 28
</part>
</rom>
</misterromdescription>

55
Arcade_MiST/Sega System 1 Hardware/meta/TeddyBoy Blues.mra Normal file
View File

@@ -0,0 +1,55 @@
<misterromdescription>
<name>TeddyBoy Blues (315-5115, New Ver.)</name>
<mameversion>0217</mameversion>
<setname>teddybb</setname>
<mratimestamp>202001070000</mratimestamp>
<year>1985</year>
<manufacturer>Sega</manufacturer>
<category>Platform</category>
<rbf>segasys1</rbf>
<switches default="FF,7E" base="8">
<dip bits="9" name="Demo Sound" ids="Off,On"/>
<dip bits="10,11" name="Lives" ids="252,4,2,3"/>
<dip bits="12,13" name="Extend" ids="600k,400k 800k,200k 600k,100k 400k"/>
<dip bits="14" name="Difficulty" ids="Hard,Easy"/>
</switches>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="teddybb.zip" md5="74c131009ccc5d58133c0ebe73a4668c" type="merged|nonmerged|split">
<part name="epr-6768.116"/>
<part name="epr-6769.109"/>
<part name="epr-6770.96"/>
<part name="epr6748x.120"/>
<part name="epr6748x.120"/>
<part name="epr-6735.117"/>
<part name="epr-6737.04"/>
<part name="epr-6736.110"/>
<part name="epr-6738.05"/>
<group width="32">
<part name="epr-6747.62"/>
<part name="epr-6745.64"/>
<part name="epr-6743.66"/>
<part name="epr-6743.66"/>
</group>
<group width="32">
<part name="epr-6746.61"/>
<part name="epr-6744.63"/>
<part name="epr-6742.65"/>
<part name="epr-6742.65"/>
</group>
<part name="pr-5317.76"/>
<part>
20 28 00 08 80 00 a0 20 20 28 00 08 a0 a8 20 28
28 08 a8 88 a0 80 a8 88 a0 a8 20 28 a0 80 a8 88
20 28 00 08 28 08 a8 88 a0 a8 20 28 a0 a8 20 28
a0 80 a8 88 28 08 a8 88 a0 a8 20 28 28 08 a8 88
80 00 a0 20 80 00 a0 20 a0 20 a8 28 a0 a8 20 28
a0 20 a8 28 a0 80 a8 88 a0 80 a8 88 a0 80 a8 88
80 00 a0 20 20 28 00 08 a0 a8 20 28 a0 20 a8 28
80 00 a0 20 a0 80 a8 88 a0 a8 20 28 a0 20 a8 28
</part>
</rom>
</misterromdescription>

58
Arcade_MiST/Sega System 1 Hardware/meta/Up'n Down.mra Normal file
View File

@@ -0,0 +1,58 @@
<misterromdescription>
<name>Up'n Down</name>
<mameversion>0216</mameversion>
<setname>upndown</setname>
<mratimestamp>202001100000</mratimestamp>
<year>1984</year>
<manufacturer>Sega</manufacturer>
<category>Shmup</category>
<rbf>segasys1</rbf>
<switches default="FF,BF" base="8">
<dip bits="9,10" name="Lives" ids="Infinite,5,4,3"/>
<dip bits="11,13" name="Binus at" ids="Never,70k,60k,50k,40k,30k,20k,10k"/>
<dip bits="14,15" name="Difficulty" ids="Hardest,Hard,Medium,Easy"/>
</switches>
<rom index="1">
<part>06</part>
</rom>
<rom index="0" zip="upndown.zip" md5="013c5bfc7a9a7a68e3eeb12c8ce37e8e" type="merged|nonmerged|split">
<part name="epr5516a.129"/>
<part name="epr5517a.130"/>
<part name="epr-5518.131"/>
<part name="epr-5519.132"/>
<part name="epr-5520.133"/>
<part name="epr-5521.134"/>
<part name="epr-5535.3"/>
<part name="epr-5535.3"/>
<part name="epr-5514.86"/>
<part name="epr-5515.93"/>
<part name="epr-5514.86"/>
<part name="epr-5515.93"/>
<group width="32">
<part name="epr-5527.82"/>
<part name="epr-5525.81"/>
<part name="epr-5523.80"/>
<part name="epr-5523.80"/>
</group>
<group width="32">
<part name="epr-5526.65"/>
<part name="epr-5524.64"/>
<part name="epr-5522.63"/>
<part name="epr-5522.63"/>
</group>
<part name="pr-5317.106"/>
<part>
08 88 00 80 a0 20 80 00 a8 a0 28 20 88 a8 80 a0
88 80 08 00 28 08 a8 88 88 a8 80 a0 28 08 a8 88
88 a8 80 a0 a0 20 80 00 a8 a0 28 20 a8 a0 28 20
88 80 08 00 88 a8 80 a0 88 a8 80 a0 88 a8 80 a0
a0 20 80 00 a0 20 80 00 08 88 00 80 28 08 a8 88
88 a8 80 a0 88 80 08 00 88 a8 80 a0 28 08 a8 88
88 a8 80 a0 88 a8 80 a0 88 a8 80 a0 88 a8 80 a0
88 80 08 00 88 80 08 00 08 88 00 80 28 08 a8 88
</part>
</rom>
</misterromdescription>

63
Arcade_MiST/Sega System 1 Hardware/meta/Wonder Boy.mra Normal file
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@@ -0,0 +1,63 @@
<misterromdescription>
<name>Wonder Boy (set 1, 315-5177)</name>
<mameversion>0217</mameversion>
<setname>wboy</setname>
<mratimestamp>20200107000000</mratimestamp>
<year>1986</year>
<manufacturer>Escape (Sega license)</manufacturer>
<category>Platform / Extra</category>
<rbf>segasys1</rbf>
<switches default="FF,7E" base="8">
<dip bits="9" name="Demo Sound" ids="On,Off"/>
<dip bits="10,11" name="Lives" ids="Free Play,5,4,3"/>
<dip bits="12" name="Extend" ids="30k 120k 210k 300k,30k 100k 170k 240k"/>
<dip bits="13" name="Allow Continue" ids="No,Yes"/>
<dip bits="14" name="Difficulty" ids="Hard,Easy"/>
</switches>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="wboy.zip" md5="7cc14dd978cab8fbf13dd4120692086f" type="merged|nonmerged|split">
<part name="epr-7489.116"/>
<part name="epr-7490.109"/>
<part name="epr-7491.96"/>
<part name="epr-7498.120"/>
<part name="epr-7498.120"/>
<part name="epr-7485.117"/>
<part name="epr-7487.04"/>
<part name="epr-7486.110"/>
<part name="epr-7488.05"/>
<group width="32">
<part name="epr-7497.62"/>
<part name="epr-7495.64"/>
<part name="epr-7493.66"/>
<part name="epr-7493.66"/>
</group>
<group width="32">
<part name="epr-7496.61"/>
<part name="epr-7494.63"/>
<part name="epr-7492.65"/>
<part name="epr-7492.65"/>
</group>
<part name="pr-5317.76"/>
<part>
04 54 51 15 40 44 01 51 55 10 44 41 05 55 50 14
41 45 00 50 54 11 45 40 04 54 51 15 40 44 01 51
55 10 44 41 05 55 50 14 41 45 00 50 54 11 45 40
04 54 51 15 40 44 01 51 55 10 44 41 05 55 50 14
04 54 51 15 40 44 01 51 55 10 44 41 05 55 50 14
41 45 00 50 54 11 45 40 04 54 51 15 40 44 01 51
55 10 44 41 05 55 50 14 41 45 00 50 54 11 45 40
04 54 51 15 40 44 01 51 55 10 44 41 05 55 50 14
00 00 00 00 01 01 01 01 01 02 02 02 02 02 03 03
03 03 04 04 04 04 04 05 05 05 05 05 06 06 06 06
06 07 07 07 07 07 08 08 08 08 09 09 09 09 09 0a
0a 0a 0a 0a 0b 0b 0b 0b 0b 0c 0c 0c 0c 0c 0d 0d
08 08 08 08 09 09 09 09 09 0a 0a 0a 0a 0a 0b 0b
0b 0b 0c 0c 0c 0c 0c 0d 0d 0d 0d 0d 0e 0e 0e 0e
0e 0f 0f 0f 0f 0f 10 10 10 10 11 11 11 11 11 12
12 12 12 12 13 13 13 13 13 14 14 14 14 14 15 15
</part>
</rom>
</misterromdescription>

57
Arcade_MiST/Sega System 1 Hardware/meta/buggy/Pitfall II.mra Normal file
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@@ -0,0 +1,57 @@
<misterromdescription>
<name>Pitfall II</name>
<mameversion>0216</mameversion>
<setname>pitfall2</setname>
<mratimestamp>202001100000</mratimestamp>
<year>1985</year>
<manufacturer>Sega</manufacturer>
<category>Maze / Extra</category>
<rbf>segasys1</rbf>
<switches default="FF,DF" base="8">
<dip bits="9" name="Demo Sound" ids="On,Off"/>
<dip bits="10,11" name="Lives" ids="Infinite,5,4,3"/>
<dip bits="12" name="Bonus at" ids="30000 70000,20000 50000"/>
<dip bits="13" name="Allow Continue" ids="Yes,No"/>
<dip bits="14" name="Time" ids="2 Minutes,3 Minutes"/>
</switches>
<rom index="1">
<part>04</part>
</rom>
<rom index="0" zip="pitfall2.zip" md5="07b1a752e7bf1bf17ae773d1b6977bf1" type="merged|nonmerged|split">
<part name="epr-6456a.116"/>
<part name="epr-6457a.109"/>
<part name="epr-6458a.96"/>
<part name="epr-6462.120"/>
<part name="epr-6462.120"/>
<part name="epr-6454a.117"/>
<part name="epr-6455.05"/>
<part name="epr-6454a.117"/>
<part name="epr-6455.05"/>
<group width="32">
<part name="epr-6474a.62"/>
<part name="epr-6472a.64"/>
<part name="epr-6470a.66"/>
<part name="epr-6470a.66"/>
</group>
<group width="32">
<part name="epr-6473a.61"/>
<part name="epr-6471a.63"/>
<part name="epr-6469a.65"/>
<part name="epr-6469a.65"/>
</group>
<part name="pr-5317.76"/>
<part>
a0 80 a8 88 a0 80 a8 88 08 88 28 a8 28 a8 20 a0
a0 80 a8 88 a0 80 a8 88 a0 a8 20 28 a0 a8 20 28
a0 80 a8 88 20 00 a0 80 28 a8 20 a0 20 00 a0 80
a0 a8 20 28 a0 a8 20 28 28 a8 20 a0 a0 a8 20 28
20 00 a0 80 80 88 a0 a8 80 88 a0 a8 80 88 a0 a8
a0 a8 20 28 a0 80 a8 88 80 88 a0 a8 28 a8 20 a0
20 00 a0 80 80 88 a0 a8 80 88 a0 a8 20 00 a0 80
a0 a8 20 28 a0 80 a8 88 80 88 a0 a8 28 a8 20 a0
</part>
</rom>
</misterromdescription>

60
Arcade_MiST/Sega System 1 Hardware/meta/buggy/Starjacker.mra Normal file
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@@ -0,0 +1,60 @@
<misterromdescription>
<name>Star Jacker</name>
<mameversion>0216</mameversion>
<setname>starjack</setname>
<mratimestamp>202001100000</mratimestamp>
<year>1983</year>
<manufacturer>Sega</manufacturer>
<category>Shmup</category>
<rbf>segasys1</rbf>
<switches default="FF,BF" base="8">
<dip bits="9,10" name="Lives" ids="Infinite,5,4,3"/>
<dip bits="11,13" name="Bonus at" ids="50k +every 60k,40k +every 50k,30k +every 40k,20k +every 30k,Every 50k,Every 40k,Every 30k,Every 20k"/>
<dip bits="14,15" name="Difficulty" ids="Hardest,Hard,Medium,Easy"/>
</switches>
<rom index="1">
<part>06</part>
</rom>
<rom index="0" zip="starjack.zip" md5="406ae0d7a61a6a09deaef8a3a8b6d67f" type="merged|nonmerged|split">
<part name="epr-5320b.129"/>
<part name="epr-5321a.130"/>
<part name="epr-5322a.131"/>
<part name="epr-5323.132"/>
<part name="epr-5324.133"/>
<part name="epr-5325.134"/>
<part name="epr-5332.3"/>
<part name="epr-5332.3"/>
<part name="epr-5318.86"/>
<part name="epr-5319.93"/>
<part name="epr-5318.86"/>
<part name="epr-5319.93"/>
<group width="32">
<part name="epr-5331.82"/>
<part name="epr-5329.81"/>
<part name="epr-5327.80"/>
<part name="epr-5327.80"/>
</group>
<group width="32">
<part name="epr-5330.65"/>
<part name="epr-5328.64"/>
<part name="epr-5326.63"/>
<part name="epr-5326.63"/>
</group>
<part name="pr-5317.106"/>
<part>
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
</part>
</rom>
</misterromdescription>

244
Arcade_MiST/Sega System 1 Hardware/rtl/DPRAM1024_11B.v Normal file
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@@ -0,0 +1,244 @@
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DPRAM1024_11B.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module DPRAM1024_11B (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL DPRAM1024_11B_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

67
Arcade_MiST/Sega System 1 Hardware/rtl/HVGEN.v Normal file
View File

@@ -0,0 +1,67 @@
// Copyright (c) 2019 MiSTer-X
module HVGEN
(
output [8:0] HPOS,
output [8:0] VPOS,
input CLK,
input PCLK_EN,
input [14:0] iRGB,
output reg [14:0] oRGB,
output reg HBLK = 1,
output reg VBLK = 1,
output reg HSYN = 1,
output reg VSYN = 1,
input H240,
input [8:0] HOFFS,
input [8:0] VOFFS
);
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
assign HPOS = hcnt-9'd16;
assign VPOS = vcnt;
wire [8:0] HS_B = 9'd288+(HOFFS*2'd2);
wire [8:0] HS_E = 9'd32+(HS_B);
wire [8:0] HS_N = 9'd447+(HS_E-9'd320);
wire [8:0] VS_B = 9'd226+(VOFFS*3'd4);
wire [8:0] VS_E = 9'd4+(VS_B);
wire [8:0] VS_N = 9'd481+(VS_E-9'd230);
always @(posedge CLK) begin
if (PCLK_EN) begin
hcnt <= hcnt + 1'd1;
case (hcnt)
25: HBLK <= H240;
37: HBLK <= 0;
277: HBLK <= H240;
281: HBLK <= 1;
511: begin
hcnt <= 0;
case (vcnt)
223: begin VBLK <= 1; vcnt <= vcnt+9'd1; end
511: begin VBLK <= 0; vcnt <= 0; end
default: vcnt <= vcnt+9'd1;
endcase
end
default: hcnt <= hcnt+9'd1;
endcase
if (hcnt==HS_B) begin HSYN <= 0; end
if (hcnt==HS_E) begin HSYN <= 1; hcnt <= HS_N; end
if (vcnt==VS_B) begin VSYN <= 0; end
if (vcnt==VS_E) begin VSYN <= 1; vcnt <= VS_N; end
oRGB <= (HBLK|VBLK) ? 12'h0 : iRGB;
end
end
endmodule

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/********************************************************************
FPGA Implimentation of SEGA System 1,2 (Top Module)
Copyright (c) 2017,19 MiSTer-X
*********************************************************************/
module SEGASYSTEM1
(
input clk48M,
input reset,
input [7:0] INP0,
input [7:0] INP1,
input [7:0] INP2,
input [7:0] DSW0,
input [7:0] DSW1,
input [8:0] PH, // PIXEL H
input [8:0] PV, // PIXEL V
output PCLK_EN,
output [7:0] POUT, // PIXEL OUT
output [15:0] SOUT, // Sound Out (PCM)
output [15:0] cpu_rom_addr,
input [7:0] cpu_rom_do,
output [12:0] snd_rom_addr,
input [7:0] snd_rom_do,
output [13:0] tile_rom_addr,
input [31:0] tile_rom_do,
output [17:0] spr_rom_addr,
input [7:0] spr_rom_do,
input ROMCL, // Downloaded ROM image
input [24:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
// CPU
wire [15:0] CPUAD;
wire [7:0] CPUDO,VIDDO,SNDNO,VIDMD;
wire CPUWR,VIDCS,VBLK;
wire SNDRQ;
SEGASYS1_MAIN Main (
.RESET(reset),
.INP0(INP0),.INP1(INP1),.INP2(INP2),
.DSW0(DSW0),.DSW1(DSW1),
.CLK48M(clk48M),
.CPUAD(CPUAD),.CPUDO(CPUDO),.CPUWR(CPUWR),
.VBLK(VBLK),.VIDCS(VIDCS),.VIDDO(VIDDO),
.SNDRQ(SNDRQ),.SNDNO(SNDNO),
.VIDMD(VIDMD),
.cpu_rom_addr(cpu_rom_addr),
.cpu_rom_do(cpu_rom_do),
.ROMCL(ROMCL),.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN)
);
// Video
wire [7:0] OPIX;
SEGASYS1_VIDEO Video (
.RESET(reset),.VCLKx8(clk48M),
.PH(PH),.PV(PV),.VFLP(VIDMD[7]),
.VBLK(VBLK),.PCLK_EN(PCLK_EN),.RGB8(OPIX),.PALDSW(1'b0),
.cpu_ad(CPUAD),.cpu_wr(CPUWR),.cpu_dw(CPUDO),
.cpu_rd(VIDCS),.cpu_dr(VIDDO),
.tile_rom_addr(tile_rom_addr), .tile_rom_do(tile_rom_do),
.spr_rom_addr(spr_rom_addr), .spr_rom_do(spr_rom_do),
.ROMCL(ROMCL),.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN)
);
assign POUT = VIDMD[4] ? 8'd0 : OPIX;
// Sound
SEGASYS1_SOUND Sound(
clk48M, reset, SNDNO, SNDRQ, SOUT,
snd_rom_addr, snd_rom_do
);
endmodule

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// Copyright (c) 2017,19 MiSTer-X
`define EN_MCPU0 (ROMAD[17:15]==3'b00_0 )
`define EN_MCPU8 (ROMAD[17:14]==4'b00_10)
module SEGASYS1_MAIN
(
input CLK48M,
input RESET,
input [7:0] INP0,
input [7:0] INP1,
input [7:0] INP2,
input [7:0] DSW0,
input [7:0] DSW1,
input VBLK,
input VIDCS,
input [7:0] VIDDO,
output [15:0] CPUAD,
output [7:0] CPUDO,
output CPUWR,
output reg SNDRQ,
output reg [7:0] SNDNO,
output reg [7:0] VIDMD,
output [15:0] cpu_rom_addr,
input [7:0] cpu_rom_do,
input ROMCL, // Downloaded ROM image
input [24:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
reg [3:0] clkdiv;
always @(posedge CLK48M) clkdiv <= clkdiv+1'd1;
wire CLK3M_EN = clkdiv[2:0] == 0;
wire AXSCL = CLK48M;
wire CPUCL_EN = CLK3M_EN;
wire [7:0] CPUDI;
wire CPURD;
wire cpu_m1;
wire cpu_mreq, cpu_iorq;
wire _cpu_rd, _cpu_wr;
Z80IP maincpu(
.reset(RESET),
.clk(CLK48M),
.clk_en(CPUCL_EN),
.adr(CPUAD),
.data_in(CPUDI),
.data_out(CPUDO),
.m1(cpu_m1),
.mx(cpu_mreq),
.ix(cpu_iorq),
.rd(_cpu_rd),
.wr(_cpu_wr),
.intreq(VBLK),
.nmireq(1'b0)
);
assign CPUWR = _cpu_wr & cpu_mreq;
assign CPURD = _cpu_rd & cpu_mreq;
// Input Port
wire cpu_cs_port;
wire [7:0] cpu_rd_port;
SEGASYS1_IPORT port(CPUAD,cpu_iorq, INP0,INP1,INP2, DSW0,DSW1, cpu_cs_port,cpu_rd_port);
// Program ROM
wire cpu_cs_mrom0 = (CPUAD[15] == 1'b0 ) & cpu_mreq;
wire cpu_cs_mrom1 = (CPUAD[15:14] == 2'b10) & cpu_mreq;
wire [7:0] cpu_rd_mrom0;
wire [7:0] cpu_rd_mrom1;
wire [14:0] rad;
wire [7:0] rdt;
SEGASYS1_PRGDEC decr(AXSCL,cpu_m1,CPUAD,cpu_rd_mrom0, rad,rdt, ROMCL,ROMAD,ROMDT,ROMEN);
assign cpu_rom_addr = CPUAD[15] ? CPUAD[15:0] : {1'b0, rad};
assign rdt = cpu_rom_do;
assign cpu_rd_mrom1 = cpu_rom_do;
//DLROM #(15,8) rom0(AXSCL, rad, rdt, ROMCL,ROMAD,ROMDT,ROMEN & `EN_MCPU0); // ($0000-$7FFF encrypted)
//DLROM #(14,8) rom1(CPUCLn,CPUAD,cpu_rd_mrom1, ROMCL,ROMAD,ROMDT,ROMEN & `EN_MCPU8); // ($8000-$BFFF non-encrypted)
// Work RAM
wire [7:0] cpu_rd_mram;
wire cpu_cs_mram = (CPUAD[15:12] == 4'b1100) & cpu_mreq;
SRAM_4096 mainram(CLK48M, CPUAD[11:0], cpu_rd_mram, cpu_cs_mram & CPUWR, CPUDO );
// Video mode latch & Sound Request
wire cpu_cs_sreq = ((CPUAD[7:0] == 8'h14)|(CPUAD[7:0] == 8'h18)) & cpu_iorq;
wire cpu_cs_vidm = ((CPUAD[7:0] == 8'h15)|(CPUAD[7:0] == 8'h19)) & cpu_iorq;
wire cpu_wr_sreq = cpu_cs_sreq & _cpu_wr;
wire cpu_wr_vidm = cpu_cs_vidm & _cpu_wr;
always @(posedge CLK48M or posedge RESET) begin
if (RESET) begin
VIDMD <= 0;
SNDRQ <= 0;
SNDNO <= 0;
end
else begin
if (cpu_wr_vidm) VIDMD <= CPUDO;
if (cpu_wr_sreq) begin SNDNO <= CPUDO; SNDRQ <= 1'b1; end else SNDRQ <= 1'b0;
end
end
// CPU data selector
dataselector6 mcpudisel(
CPUDI,
VIDCS, VIDDO,
cpu_cs_vidm, VIDMD,
cpu_cs_port, cpu_rd_port,
cpu_cs_mram, cpu_rd_mram,
cpu_cs_mrom0, cpu_rd_mrom0,
cpu_cs_mrom1, cpu_rd_mrom1,
8'hFF
);
endmodule
module SEGASYS1_IPORT
(
input [15:0] CPUAD,
input CPUIO,
input [7:0] INP0,
input [7:0] INP1,
input [7:0] INP2,
input [7:0] DSW0,
input [7:0] DSW1,
output DV,
output [7:0] OD
);
wire cs_port1 = (CPUAD[4:2] == 3'b0_00) & CPUIO;
wire cs_port2 = (CPUAD[4:2] == 3'b0_01) & CPUIO;
wire cs_portS = (CPUAD[4:2] == 3'b0_10) & CPUIO;
wire cs_portA = (CPUAD[4:2] == 3'b0_11) & ~CPUAD[0] & CPUIO;
wire cs_portB =(((CPUAD[4:2] == 3'b0_11) & CPUAD[0]) | (CPUAD[4:2] == 3'b1_00)) & CPUIO;
wire [7:0] inp;
dataselector5 dsel(
inp,
cs_port1,INP0,
cs_port2,INP1,
cs_portS,INP2,
cs_portA,DSW0,
cs_portB,DSW1,
8'hFF
);
assign DV = cs_port1|cs_port2|cs_portS|cs_portA|cs_portB;
assign OD = inp;
endmodule

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// Copyright (c) 2017,19 MiSTer-X
`define DECTBLADRS (25'h30100)
`define EN_DEC1TBL (ROMAD[17:7]==11'b11_0000_0001_0) // $30100
`define EN_DEC2XOR (ROMAD[17:7]==11'b11_0000_0001_0) // $30100
`define EN_DEC2SWP (ROMAD[17:7]==11'b11_0000_0001_1) // $30180
module SEGASYS1_PRGDEC
(
input clk,
input mrom_m1, // connect to CPU
input [14:0] mrom_ad,
output [7:0] mrom_dt,
output [14:0] rad, // connect to ROM
input [7:0] rdt,
input ROMCL, // Downloaded ROM image
input [24:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
wire [7:0] od0,od1;
wire [14:0] dum;
SEGASYS1_DECT1 t1(clk,mrom_m1,mrom_ad, od0, rad,rdt, ROMCL,ROMAD,ROMDT,ROMEN);
SEGASYS1_DECT2 t2(clk,mrom_m1,mrom_ad, od1, dum,rdt, ROMCL,ROMAD,ROMDT,ROMEN);
// Type Detect and switch
reg [15:0] cnt0,cnt2;
always @(posedge ROMCL) begin
if (ROMEN) begin
if (ROMAD>=`DECTBLADRS) begin
cnt2 <= (ROMDT>=8'd24) ? 16'd0 : (cnt2+1'd1);
cnt0 <= (ROMDT!=8'd0 ) ? 16'd0 : (cnt0+1'd1);
end
else begin
cnt2 <= 0;
cnt0 <= 0;
end
end
end
assign mrom_dt = (cnt0>=128) ? rdt : (cnt2>=128) ? od1 : od0;
endmodule
//----------------------------------------
// Program ROM Decryptor (Type 1)
//----------------------------------------
module SEGASYS1_DECT1
(
input clk,
input mrom_m1, // connect to CPU
input [14:0] mrom_ad,
output reg [7:0] mrom_dt,
output [14:0] rad, // connect to ROM
input [7:0] rdt,
input ROMCL, // Downloaded ROM image
input [24:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
reg [15:0] madr;
wire [7:0] mdat = rdt;
wire f = mdat[7];
wire [7:0] xorv = { f, 1'b0, f, 1'b0, f, 3'b000 };
wire [7:0] andv = ~(8'hA8);
wire [1:0] decidx0 = { mdat[5], mdat[3] } ^ { f, f };
wire [6:0] decidx = { madr[12], madr[8], madr[4], madr[0], ~madr[15], decidx0 };
wire [7:0] dectbl;
wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv );
DLROM #(7,8) dect( clk, decidx, dectbl, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC1TBL );
reg phase = 1'b0;
always @( negedge clk ) begin
if ( phase ) mrom_dt <= mdec;
else madr <= { mrom_m1, mrom_ad };
phase <= ~phase;
end
assign rad = madr[14:0];
endmodule
//----------------------------------------
// Program ROM Decryptor (Type 2)
//----------------------------------------
module SEGASYS1_DECT2
(
input clk,
input mrom_m1, // connect to CPU
input [14:0] mrom_ad,
output reg [7:0] mrom_dt,
output [14:0] rad, // connect to ROM
input [7:0] rdt,
input ROMCL, // Downloaded ROM image
input [24:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
`define bsw(A,B,C,D) {v[7],v[A],v[5],v[B],v[3],v[C],v[1],v[D]}
function [7:0] bswp;
input [4:0] m;
input [7:0] v;
case (m)
0: bswp = `bsw(6,4,2,0);
1: bswp = `bsw(4,6,2,0);
2: bswp = `bsw(2,4,6,0);
3: bswp = `bsw(0,4,2,6);
4: bswp = `bsw(6,2,4,0);
5: bswp = `bsw(6,0,2,4);
6: bswp = `bsw(6,4,0,2);
7: bswp = `bsw(2,6,4,0);
8: bswp = `bsw(4,2,6,0);
9: bswp = `bsw(4,6,0,2);
10: bswp = `bsw(6,0,4,2);
11: bswp = `bsw(0,6,4,2);
12: bswp = `bsw(4,0,6,2);
13: bswp = `bsw(0,4,6,2);
14: bswp = `bsw(6,2,0,4);
15: bswp = `bsw(2,6,0,4);
16: bswp = `bsw(0,6,2,4);
17: bswp = `bsw(2,0,6,4);
18: bswp = `bsw(0,2,6,4);
19: bswp = `bsw(4,2,0,6);
20: bswp = `bsw(2,4,0,6);
21: bswp = `bsw(4,0,2,6);
22: bswp = `bsw(2,0,4,6);
23: bswp = `bsw(0,2,4,6);
default: bswp = 0;
endcase
endfunction
reg [15:0] madr;
wire [7:0] sd,xd;
wire [6:0] ix = {madr[14],madr[12],madr[9],madr[6],madr[3],madr[0],~madr[15]};
DLROM #(7,8) xort(clk,ix,xd, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC2XOR);
DLROM #(7,8) swpt(clk,ix,sd, ROMCL,ROMAD,ROMDT,ROMEN & `EN_DEC2SWP);
reg phase = 1'b0;
always @( negedge clk ) begin
if ( phase ) mrom_dt <= (bswp(sd,rdt) ^ xd);
else madr <= { mrom_m1, mrom_ad };
phase <= ~phase;
end
assign rad = madr[14:0];
endmodule

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// Copyright (c) 2017,19 MiSTer-X
`define EN_SCPU (ROMAD[17:13]==5'b00_110) // $0C000-$0DFFF
module SEGASYS1_SOUND
(
input clk48M,
input reset,
input [7:0] sndno,
input sndstart,
output [15:0] sndout,
output [12:0] snd_rom_addr,
input [7:0] snd_rom_do
);
//----------------------------------
// ClockGen
//----------------------------------
wire clk8M_en,clk4M_en,clk2M_en;
SndClkGen clkgen(clk48M,clk8M_en,clk4M_en,clk2M_en);
//----------------------------------
// Z80 (1.5625MHz)
//----------------------------------
wire [15:0] cpu_ad;
wire [7:0] cpu_di, cpu_do;
wire cpu_mreq, cpu_iorq, cpu_rd, cpu_wr;
wire cpu_irq, cpu_nmi;
wire cpu_irqa, cpu_nmia;
wire cpu_mw, cpu_cs_rom, cpu_cs_ram, cpu_wr_ram, cpu_cs_psg0, cpu_cs_psg1, cpu_cs_com;
SndADec adec(
cpu_mreq, cpu_wr, cpu_mw,
cpu_ad, cpu_cs_rom, cpu_cs_ram, cpu_wr_ram, cpu_cs_psg0, cpu_cs_psg1, cpu_cs_com
);
Z80IP cpu(
.clk(clk48M),
.clk_en(clk4M_en & cpuwait_n),
.reset(reset),
.adr(cpu_ad),
.data_in(cpu_di),
.data_out(cpu_do),
.intreq(cpu_irq),
.intack(cpu_irqa),
.nmireq(cpu_nmi),
.nmiack(cpu_nmia),
.mx(cpu_mreq),
.ix(cpu_iorq),
.rd(cpu_rd),
.wr(cpu_wr)
);
wire [7:0] rom_dt; // ROM
wire [7:0] ram_do; // RAM
wire [7:0] comlatch; // Sound Command Latch
assign snd_rom_addr = cpu_ad[12:0];
assign rom_dt = snd_rom_do;
//DLROM #(13,8) subir( cpuclkx2, cpu_ad[12:0], rom_dt, ROMCL,ROMAD,ROMDT,ROMEN & `EN_SCPU );
SRAM_2048 wram( clk48M, cpu_ad[10:0], ram_do, cpu_wr_ram, cpu_do );
dataselector3 scpudisel(
cpu_di,
cpu_cs_rom, rom_dt,
cpu_cs_ram, ram_do,
cpu_cs_com, comlatch,
8'hFF
);
SndPlayReq sndreq (
clk48M, clk8M_en, reset,
sndno, sndstart,
cpu_irq, cpu_irqa,
cpu_nmi, cpu_nmia,
comlatch
);
//----------------------------------
// PSGs
//----------------------------------
wire [7:0] psg0out, psg1out;
wire psg0wait, psg1wait;
wire cpuwait_n = psg0wait & psg1wait;
sn76489_top psg0(
.clock_i(clk48M),
.clock_en_i(clk2M_en),
.res_n_i(~reset),
.ce_n_i(~(cpu_cs_psg0 & cpu_mreq)),
.we_n_i(~cpu_wr),
.d_i(cpu_do),
.ready_o(psg0wait),
.aout_o(psg0out)
);
sn76489_top psg1(
.clock_i(clk48M),
.clock_en_i(clk4M_en),
.res_n_i(~reset),
.ce_n_i(~(cpu_cs_psg1 & cpu_mreq)),
.we_n_i(~cpu_wr),
.d_i(cpu_do),
.ready_o(psg1wait),
.aout_o(psg1out)
);
wire [8:0] psgout = psg0out + psg1out;
assign sndout = { psgout, 6'h0 };
endmodule
module SndClkGen
(
input clk48M,
output clk8M_en,
output clk4M_en,
output clk2M_en
);
reg [4:0] count;
always @( posedge clk48M ) begin
count <= count + 1'd1;
if (count == 23) count <= 0;
end
assign clk2M_en = count == 0;
assign clk4M_en = count == 0 || count == 12;
assign clk8M_en = count == 0 || count == 6 || count == 12 || count == 18;
endmodule
module SndADec
(
input cpu_mx,
input cpu_wr,
output cpu_mw,
input [15:0] cpu_ad,
output cpu_cs_rom,
output cpu_cs_ram,
output cpu_wr_ram,
output cpu_cs_psg0,
output cpu_cs_psg1,
output cpu_cs_com
);
assign cpu_mw = cpu_mx & cpu_wr;
assign cpu_cs_rom = ( cpu_ad[15] == 1'b0 );
assign cpu_cs_psg0 = ( cpu_ad[15:12] == 4'HA );
assign cpu_cs_psg1 = ( cpu_ad[15:12] == 4'HC );
assign cpu_cs_com = ( cpu_ad[15:12] == 4'HE );
assign cpu_cs_ram = ( cpu_ad[15:12] == 4'h8 );
assign cpu_wr_ram = cpu_cs_ram & cpu_mw;
endmodule
//----------------------------------
// Play Request & IRQ Generator
//----------------------------------
module SndPlayReq
(
input clk,
input clk8_en,
input reset,
input [7:0] sndno,
input sndstart,
output reg cpu_irq,
input cpu_irqa,
output reg cpu_nmi,
input cpu_nmia,
output reg [7:0] comlatch
);
reg [16:0] timercnt;
reg psndstart;
always @( posedge clk or posedge reset ) begin
if ( reset ) begin
cpu_nmi <= 0;
cpu_irq <= 0;
comlatch <= 0;
timercnt <= 0;
psndstart <= 0;
end
else if (clk8_en) begin
if ( cpu_irqa ) cpu_irq <= 1'b0;
if ( cpu_nmia ) cpu_nmi <= 1'b0;
if ( ( psndstart ^ sndstart ) & sndstart ) begin
comlatch <= sndno;
cpu_nmi <= 1'b1;
end
psndstart <= sndstart;
if ( timercnt == 33333 ) cpu_irq <= 1'b1;
if ( timercnt == 66666 ) cpu_irq <= 1'b1;
timercnt <= ( timercnt == 66666 ) ? 17'd0 : (timercnt+1'd1); // 1/60sec
end
end
endmodule

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// Copyright (c) 2017,19 MiSTer-X
module SEGASYS1_SPRITE
(
input VCLKx8,
input VCLKx4,
input VCLK,
input VCLKx4_EN,
input VCLK_EN,
input [8:0] PH,
input [8:0] PV,
output [9:0] sprad,
input [15:0] sprdt,
output [17:0] sprchad,
input [7:0] sprchdt,
output reg sprcoll,
output reg [9:0] sprcoll_ad,
output reg [10:0] sprpx
);
wire [8:0] HPOS = PH;
wire [8:0] VPOS = PV;
wire HB = HPOS[8];
reg [5:0] spr_num;
reg [2:0] spr_ofs;
reg [1:0] phaseHB;
reg [7:0] svpos;
reg [5:0] hitsprnum [0:31];
reg [7:0] hitsprvps [0:31];
reg [4:0] hits;
reg [3:0] phaseHD;
reg [4:0] hitr;
reg [7:0] yofs;
reg [8:0] xpos;
reg [2:0] bank;
reg [15:0] stride;
reg [15:0] srcadrs;
reg [3:0] waitcnt;
reg [7:0] rdat;
reg [10:0] wdat;
reg hflip;
reg nowflip;
reg we;
wire [15:0] srca = sprdt[15:0] + (stride * yofs);
wire [10:0] col0 = { 2'b00, spr_num[4:0], nowflip ? rdat[3:0] : rdat[7:4] };
wire [10:0] col1 = { 2'b00, spr_num[4:0], nowflip ? rdat[7:4] : rdat[3:0] };
wire [10:0] _prevpix;
reg [10:0] prevpix;
wire side = VPOS[0];
wire [10:0] opix;
reg [9:0] rad0,rad1=1;
LineBuf lbuf(
VCLKx8, rad0, (rad0==rad1), opix,
VCLKx8, {~side,xpos}, wdat, we & (wdat[3:0] != 4'h0), _prevpix
);
always @(posedge VCLKx8) begin
rad0 <= {side,HPOS};
if (VCLK_EN) begin
sprpx <= opix;
rad1 <= rad0;
end
end
assign sprad = { spr_num, spr_ofs };
assign sprchad = { bank, srcadrs[14:0] };
wire [9:0] sprcoll_adr = { spr_num[4:0], prevpix[8:4] };
`define SPSTART 0
`define SPEND 31
always @ ( posedge VCLKx8 ) if (VCLKx4_EN) begin
// in H-Blank
if ( HB ) begin
phaseHD <= 0;
we <= 1'b0;
sprcoll <= 1'b0;
case ( phaseHB )
// initialize
2'h0: begin
svpos <= VPOS+1'd1;
spr_num <= `SPSTART;
spr_ofs <= 0;
hits <= 0;
phaseHB <= 2'h1;
end
// check v-hit
2'h1: begin
if ( sprdt[7:0] != 8'hFF ) begin
if ( ( svpos >= sprdt[7:0] ) & ( svpos < sprdt[15:8] ) ) begin
hitsprnum[hits] <= spr_num;
hitsprvps[hits] <= (svpos-sprdt[7:0])+1'd1;
hits <= hits+1'd1;
end
end
phaseHB <= ( spr_num == `SPEND ) ? 2'h2 : 2'h1;
spr_num <= spr_num+1'd1;
end
default:;
endcase
end
// in H-Disp
else begin
phaseHB <= 0;
case ( phaseHD )
// initialize
0: begin
hitr <= 0;
we <= 1'b0;
sprcoll <= 1'b0;
phaseHD <= ( hits > 0 ) ? 1 : 15;
end
// get hit sprite number
1: begin
spr_num <= hitsprnum[hitr];
spr_ofs <= 1;
phaseHD <= 2;
end
// get yofs/xpos/bank
2: begin
yofs <= hitsprvps[hitr];
xpos <= ((sprdt[9:0]+1)/2)+14;
bank <= { sprdt[13], sprdt[14], sprdt[15] };
spr_ofs <= 2;
phaseHD <= 3;
end
// get stride
3: begin
stride <= sprdt;
spr_ofs <= 3;
phaseHD <= 4;
end
// get srcadrs & calc chiprom address
4: begin
srcadrs <= srca;
hflip <= srca[15];
waitcnt <= 8; // wait for sprite data after address setup
phaseHD <= 6;
end
// rendering to linebuf
6: begin
if (waitcnt == 0) begin
sprcoll <= 1'b0;
we <= 1'b0;
rdat <= sprchdt;
nowflip <= srcadrs[15];
srcadrs <= hflip ? (srcadrs-1) : (srcadrs+1);
if ((hflip && !srcadrs[0]) || (!hflip && srcadrs[0])) waitcnt <= 6; // assume 16 bit words are cached
phaseHD <= 7;
end else
waitcnt <= waitcnt - 1'd1;
end
7: begin
prevpix <= _prevpix;
if ( col0[3:0] != 4'hF ) begin
wdat <= col0;
we <= 1'b1;
phaseHD <= 8;
end
else begin
we <= 1'b0;
phaseHD <= 14;
end
end
8: begin
// sprite collide process
we <= 1'b0;
if ( col0[3:0] != 4'h0 ) begin
if ( prevpix[3:0] != 4'h0 ) begin
sprcoll <= 1'b1;
sprcoll_ad <= sprcoll_adr;
end
end
xpos <= xpos+1;
phaseHD <= 9;
end
9: begin
prevpix <= _prevpix;
sprcoll <= 1'b0;
if ( col1[3:0] != 4'hF ) begin
wdat <= col1;
we <= 1'b1;
phaseHD <= 10;
end
else begin
we <= 1'b0;
phaseHD <= 14;
end
end
10: begin
// sprite collide process
we <= 1'b0;
if ( col1[3:0] != 4'h0 ) begin
if ( prevpix[3:0] != 4'h0 ) begin
sprcoll <= 1'b1;
sprcoll_ad <= sprcoll_adr;
end
end
xpos <= xpos+1;
//waitcnt <= 5;
phaseHD <= 6;
end
// process next hit sprite
14: begin
sprcoll <= 1'b0;
we <= 1'b0;
phaseHD <= ( hitr == (hits-1) ) ? 15 : 1;
hitr <= hitr+1;
end
default: begin
we <= 1'b0;
sprcoll <= 1'b0;
end
endcase
end
end
endmodule

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// Copyright (c) 2017,19 MiSTer-X
`define EN_SPRITE (ROMAD[17:16]==2'b01) // $10000-$1FFFF
`define EN_TILE00 (ROMAD[17:13]==5'b10_000) // $20000-$21FFF
`define EN_TILE01 (ROMAD[17:13]==5'b10_001) // $22000-$23FFF
`define EN_TILE02 (ROMAD[17:13]==5'b10_010) // $24000-$25FFF
`define EN_TILE10 (ROMAD[17:13]==5'b10_100) // $28000-$29FFF
`define EN_TILE11 (ROMAD[17:13]==5'b10_101) // $2A000-$2BFFF
`define EN_TILE12 (ROMAD[17:13]==5'b10_110) // $2C000-$2DFFF
`define EN_CLUT (ROMAD[17:8]==10'b11_0000_0000) // $30000-$300FF
module SEGASYS1_VIDEO
(
input RESET,
input VCLKx8,
input [8:0] PH,
input [8:0] PV,
input VFLP,
output VBLK,
output PCLK,
output PCLK_EN,
output [7:0] RGB8,
input PALDSW,
input [15:0] cpu_ad,
input cpu_wr,
input [7:0] cpu_dw,
output cpu_rd,
output [7:0] cpu_dr,
output reg [13:0] tile_rom_addr,
input [31:0] tile_rom_do,
output [17:0] spr_rom_addr,
input [7:0] spr_rom_do,
input ROMCL, // Downloaded ROM image
input [24:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
reg [2:0] clkdiv;
always @(posedge VCLKx8) clkdiv <= clkdiv+1'd1;
wire VCLKx4 = clkdiv[0];
wire VCLK = clkdiv[2];
wire VCLK_EN = clkdiv == 0;
wire VCLKx4_EN = !clkdiv[0];
assign PCLK = VCLK;
assign PCLK_EN = VCLK_EN;
// CPU Interface
wire [10:0] palno;
wire [7:0] palout;
wire [9:0] sprad;
wire [15:0] sprdt;
wire [9:0] vram0ad;
wire [15:0] vram0dt;
wire [9:0] vram1ad;
wire [15:0] vram1dt;
wire [5:0] mixcoll_ad;
wire mixcoll;
wire [9:0] sprcoll_ad;
wire sprcoll;
wire [15:0] scrx;
wire [7:0] scry;
VIDCPUINTF intf(
RESET,
VCLKx8,
cpu_ad, cpu_wr, cpu_dw,
cpu_rd, cpu_dr,
palno, palout,
sprad, sprdt,
vram0ad, vram0dt,
vram1ad, vram1dt,
mixcoll_ad, mixcoll,
sprcoll_ad, sprcoll,
scrx, scry
);
// HV Coordinate Generator
wire [8:0] HPOS, VPOS;
wire [8:0] BG0HP, BG0VP;
wire [8:0] BG1HP, BG1VP;
VIDHVGEN hv(
PH, PV,
scrx, scry,
HPOS, VPOS,
BG0HP, BG0VP,
BG1HP, BG1VP,
VBLK
);
// Sprite Engine
wire [10:0] SPRPX;
wire [17:0] sprchad;
wire [7:0] sprchdt;
//DLROM #(16,8) sprchr(VCLKx8,sprchad,sprchdt, ROMCL,ROMAD,ROMDT,ROMEN & `EN_SPRITE );
assign spr_rom_addr = sprchad;
assign sprchdt = spr_rom_do;
SEGASYS1_SPRITE sprite(
.VCLKx8(VCLKx8),
.VCLKx4(VCLKx4),.VCLK(VCLK),
.VCLKx4_EN(VCLKx4_EN), .VCLK_EN(VCLK_EN),
.PH(HPOS),.PV(VPOS),
.sprad(sprad),.sprdt(sprdt),
.sprchad(sprchad),.sprchdt(sprchdt),
.sprcoll(sprcoll),.sprcoll_ad(sprcoll_ad),
.sprpx(SPRPX)
);
// BG Scanline Generator
wire [10:0] BG0PX, BG1PX;
wire [13:0] tile0ad, tile1ad, tilead;
reg [23:0] tile0dt, tile1dt, tile0dt_r;
always @(posedge VCLKx8) begin
if (VCLK_EN) begin
if (HPOS[2:0] == 3'b000) begin
tile_rom_addr <= tile0ad;
tile1dt <= tile_rom_do[23:0];
tile0dt <= tile0dt_r;
end
if (HPOS[2:0] == 3'b100) begin
tile_rom_addr <= tile1ad;
tile0dt_r <= tile_rom_do[23:0];
end
end
end
BGGEN bg0(VCLKx8,VCLK_EN,BG0HP,BG0VP,vram0ad,vram0dt,tile0ad,tile0dt,BG0PX);
BGGEN bg1(VCLKx8,VCLK_EN,BG1HP,BG1VP,vram1ad,vram1dt,tile1ad,tile1dt,BG1PX);
// Color Mixer & RGB Output
wire [7:0] cltidx,cltval;
DLROM #(8,8) clut(VCLKx8, cltidx, cltval, ROMCL,ROMAD,ROMDT,ROMEN & `EN_CLUT );
COLMIX cmix(
VCLKx8, VCLK_EN,
BG0PX, BG1PX, SPRPX,
PALDSW, HPOS, VPOS,
cltidx, cltval,
mixcoll, mixcoll_ad,
palno, palout,
RGB8
);
endmodule
//----------------------------------
// CPU Interface
//----------------------------------
module VIDCPUINTF
(
input RESET,
input clk,
input [15:0] cpu_ad,
input cpu_wr,
input [7:0] cpu_dw,
output cpu_rd,
output [7:0] cpu_dr,
input [10:0] palno,
output [7:0] palout,
input [9:0] sprad,
output [15:0] sprdt,
input [9:0] vram0ad,
output [15:0] vram0dt,
input [9:0] vram1ad,
output [15:0] vram1dt,
input [5:0] mixcoll_ad,
input mixcoll,
input [9:0] sprcoll_ad,
input sprcoll,
output reg [15:0] scrx,
output reg [7:0] scry
);
// CPU Address Decoders
wire cpu_cs_palram;
wire cpu_cs_spram;
wire cpu_cs_mixcoll;
wire cpu_cs_sprcoll;
wire cpu_cs_vram0;
wire cpu_cs_vram1;
wire cpu_wr_palram;
wire cpu_wr_spram;
wire cpu_wr_mixcoll;
wire cpu_wr_mixcollclr;
wire cpu_wr_sprcoll;
wire cpu_wr_sprcollclr;
wire cpu_wr_vram0;
wire cpu_wr_vram1;
wire cpu_wr_scrreg;
VIDADEC adecs(
cpu_ad,
cpu_wr,
cpu_cs_palram,
cpu_cs_spram,
cpu_cs_mixcoll,
cpu_cs_sprcoll,
cpu_cs_vram0,
cpu_cs_vram1,
cpu_wr_palram,
cpu_wr_spram,
cpu_wr_mixcoll,
cpu_wr_mixcollclr,
cpu_wr_sprcoll,
cpu_wr_sprcollclr,
cpu_wr_vram0,
cpu_wr_vram1,
cpu_wr_scrreg,
cpu_rd
);
// Scroll Register
always @ ( posedge clk or posedge RESET) begin
if (RESET) begin
scrx <= 0;
scry <= 0;
end
else begin
if (cpu_wr_scrreg) begin
case(cpu_ad[7:0])
8'hBD: scry <= cpu_dw;
8'hFC: scrx[ 7:0] <= cpu_dw;
8'hFD: scrx[15:8] <= cpu_dw;
default:;
endcase
end
end
end
// Palette RAM
wire [7:0] cpu_rd_palram;
DPRAM2048 palram(
clk, cpu_ad[10:0], cpu_dw, cpu_wr_palram,
clk, palno, palout, cpu_rd_palram
);
// Sprite Attribute RAM
wire [7:0] cpu_rd_spram;
DPRAM2048_8_16 sprram(
clk, cpu_ad[10:0], cpu_dw, cpu_wr_spram,
clk, sprad, sprdt, cpu_rd_spram
);
// Collision RAM (Mixer & Sprite)
wire [7:0] cpu_rd_mixcoll;
wire [7:0] cpu_rd_sprcoll;
COLLRAM_M mixc(
clk,cpu_ad[5:0],cpu_wr_mixcoll,cpu_wr_mixcollclr,cpu_rd_mixcoll,mixcoll_ad,mixcoll
);
COLLRAM_S sprc(
clk,cpu_ad[9:0],cpu_wr_sprcoll,cpu_wr_sprcollclr,cpu_rd_sprcoll,sprcoll_ad,sprcoll
);
// VRAM
wire [7:0] cpu_rd_vram0, cpu_rd_vram1;
VRAM vram0(
clk, cpu_ad[10:0], cpu_rd_vram0, cpu_dw, cpu_wr_vram0,
clk, vram0ad, vram0dt
);
VRAM vram1(
clk, cpu_ad[10:0], cpu_rd_vram1, cpu_dw, cpu_wr_vram1,
clk, vram1ad, vram1dt
);
// CPU Read Data Selector
dataselector6 videodsel(
cpu_dr,
cpu_cs_palram, cpu_rd_palram,
cpu_cs_vram0, cpu_rd_vram0,
cpu_cs_vram1, cpu_rd_vram1,
cpu_cs_spram, cpu_rd_spram,
cpu_cs_sprcoll, cpu_rd_sprcoll,
cpu_cs_mixcoll, cpu_rd_mixcoll,
8'hFF
);
endmodule
//----------------------------------
// HV Coordinate Generator
//----------------------------------
module VIDHVGEN
(
input [8:0] PH,
input [8:0] PV,
input [15:0] scrx,
input [7:0] scry,
output [8:0] HPOS,
output [8:0] VPOS,
output [8:0] BG0HP,
output [8:0] BG0VP,
output [8:0] BG1HP,
output [8:0] BG1VP,
output VBLK
);
assign VBLK = (PV == 9'd224) & (PH <= 9'd64);
assign HPOS = PH+1'd1;
assign VPOS = PV;
wire [7:0] BGHSCR = scrx[9:1]+4'd14;
wire [7:0] BGVSCR = scry;
assign BG0HP = (HPOS-BGHSCR)+8'd3;
assign BG0VP = (VPOS+BGVSCR);
assign BG1HP = HPOS+8'd3;
assign BG1VP = VPOS;
endmodule
//----------------------------------
// CPU Address Decoders
//----------------------------------
module VIDADEC
(
input [15:0] cpu_ad,
input cpu_wr,
output cpu_cs_palram,
output cpu_cs_spram,
output cpu_cs_mixcoll,
output cpu_cs_sprcoll,
output cpu_cs_vram0,
output cpu_cs_vram1,
output cpu_wr_palram,
output cpu_wr_spram,
output cpu_wr_mixcoll,
output cpu_wr_mixcollclr,
output cpu_wr_sprcoll,
output cpu_wr_sprcollclr,
output cpu_wr_vram0,
output cpu_wr_vram1,
output cpu_wr_scrreg,
output cpu_rd
);
assign cpu_cs_palram = (cpu_ad[15:11] == 5'b1101_1 );
assign cpu_cs_spram = (cpu_ad[15:11] == 5'b1101_0 );
assign cpu_cs_mixcoll = (cpu_ad[15:10] == 6'b1111_00 );
wire cpu_cs_mixcollclr = (cpu_ad[15:10] == 6'b1111_01 );
assign cpu_cs_sprcoll = (cpu_ad[15:10] == 6'b1111_10 );
wire cpu_cs_sprcollclr = (cpu_ad[15:10] == 6'b1111_11 );
assign cpu_cs_vram0 = (cpu_ad[15:11] == 5'b1110_0 );
assign cpu_cs_vram1 = (cpu_ad[15:11] == 5'b1110_1 );
wire cpu_cs_scrreg = (cpu_ad[15: 8] == 8'b1110_1111);
assign cpu_wr_palram = cpu_cs_palram & cpu_wr;
assign cpu_wr_spram = cpu_cs_spram & cpu_wr;
assign cpu_wr_mixcoll = cpu_cs_mixcoll & cpu_wr;
assign cpu_wr_mixcollclr = cpu_cs_mixcollclr & cpu_wr;
assign cpu_wr_sprcoll = cpu_cs_sprcoll & cpu_wr;
assign cpu_wr_sprcollclr = cpu_cs_sprcollclr & cpu_wr;
assign cpu_wr_vram0 = cpu_cs_vram0 & cpu_wr;
assign cpu_wr_vram1 = cpu_cs_vram1 & cpu_wr;
assign cpu_wr_scrreg = cpu_cs_scrreg & cpu_wr;
assign cpu_rd = cpu_cs_palram |
cpu_cs_vram0 |
cpu_cs_vram1 |
cpu_cs_spram |
cpu_cs_sprcoll |
cpu_cs_mixcoll ;
endmodule
//----------------------------------
// BG Scanline Generator
//----------------------------------
module BGGEN
(
input CLK,
input VCLK_EN,
input [8:0] HP,
input [8:0] VP,
output [9:0] VRAMAD,
input [15:0] VRAMDT,
output [13:0] TILEAD,
input [23:0] TILEDT,
output [10:0] OPIX
);
assign VRAMAD = { VP[7:3], HP[7:3] };
assign TILEAD = { VRAMDT[15], VRAMDT[10:0], VP[2:0] };
reg [31:0] BGREG;
reg [7:0] BG_COL, BG_COL1;
wire [23:0] BGCD = BGREG[23:0];
wire [7:0] BGPN = BGREG[31:24];
wire [31:0] BGPIX;
always @( posedge CLK ) begin
if (VCLK_EN) begin
BGREG <= BGPIX;
if (HP[2:0] == 0) begin
BG_COL1 <= VRAMDT[12:5];
BG_COL <= BG_COL1;
end
end
end
dataselector1_32 pixsft(
BGPIX,
( HP[2:0] != 0 ),{ BGPN, BGCD[22:0], 1'b0 },
{ BG_COL/*VRAMDT[12:5]*/, TILEDT }
);
assign OPIX = { BGPN, BGCD[7], BGCD[15], BGCD[23] };
endmodule
//----------------------------------
// Color Mixer & RGB Output
//----------------------------------
module COLMIX
(
input CLK,
input VCLK_EN,
input [10:0] BG0PX,
input [10:0] BG1PX,
input [10:0] SPRPX,
input PALDSW,
input [8:0] HPOS,
input [8:0] VPOS,
output [7:0] cltidx,
input [7:0] cltval,
output mixcoll,
output [5:0] mixcoll_ad,
output [10:0] palno,
input [7:0] palout,
output reg [7:0] RGB8
);
assign cltidx = { 1'b0,
BG0PX[10:9],(BG0PX[2:0]==0),
BG1PX[10:9],(BG1PX[2:0]==0),
(SPRPX[3:0]==0)
};
assign mixcoll = ~(cltval[2]);
assign mixcoll_ad = { cltval[3], SPRPX[8:4] };
wire [10:0] palno_i;
dataselector2_11 colsel(
palno_i,
cltval[1], ( 11'h400 | BG0PX[8:0] ),
cltval[0], ( 11'h200 | BG1PX[8:0] ),
( 11'h000 | SPRPX[8:0] )
);
wire [10:0] palno_d = {HPOS[7],VPOS[7:2],HPOS[6:3]};
assign palno = PALDSW ? palno_d : palno_i;
always @(posedge CLK ) if (VCLK_EN) RGB8 <= palout;
endmodule
//----------------------------------
// Collision RAM
//----------------------------------
module COLLRAM_M
(
input clk,
input [5:0] cpu_ad,
input cpu_wr_coll,
input cpu_wr_collclr,
output [7:0] cpu_rd_coll,
input [5:0] coll_ad,
input coll
);
reg [63:0] core;
reg coll_rd, coll_sm;
always @(posedge clk) begin
if (cpu_wr_coll) core[cpu_ad] <= 1'b0; else if (coll) core[coll_ad] <= 1'b1;
if (cpu_wr_collclr) coll_sm <= 1'b0; else if (coll) coll_sm <= 1'b1;
end
always @(posedge clk) coll_rd <= core[cpu_ad];
assign cpu_rd_coll = { coll_sm, 6'b111111, coll_rd };
endmodule
module COLLRAM_S
(
input clk,
input [9:0] cpu_ad,
input cpu_wr_coll,
input cpu_wr_collclr,
output [7:0] cpu_rd_coll,
input [9:0] coll_ad,
input coll
);
reg [1023:0] core;
reg coll_rd, coll_sm;
always @(posedge clk) begin
if (cpu_wr_coll ) core[cpu_ad] <= 1'b0; else if (coll) core[coll_ad] <= 1'b1;
if (cpu_wr_collclr) coll_sm <= 1'b0; else if (coll) coll_sm <= 1'b1;
end
always @(posedge clk) coll_rd <= core[cpu_ad];
assign cpu_rd_coll = { coll_sm, 6'b111111, coll_rd };
endmodule

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module Segasys1_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl/build_id.v"
`define CORE_NAME "FLICKY"
localparam CONF_STR = {
`CORE_NAME,";ROM;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"DIP;",
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire [7:0] INP0 = ~{m_left, m_right,m_up, m_down,1'b0,m_fireB,m_fireA,m_fireC};
wire [7:0] INP1 = ~{m_left2,m_right2,m_up2, m_down2,1'b0,m_fire2B,m_fire2A,m_fire2C};
wire [7:0] INP2 = ~{2'b00,m_two_players, m_one_player,3'b000, m_coin1};
wire [7:0] DSW0 = status[15: 8];
wire [7:0] DSW1 = status[23:16];
wire [6:0] core_mod; // [0]=SYS1/SYS2,[1]=H/V,[2]=H256/H240
wire [1:0] orientation = { 1'b0, core_mod[1] };
assign LED = ~ioctl_downl;
assign SDRAM_CLK = sdram_clk;
assign SDRAM_CKE = 1;
assign AUDIO_R = AUDIO_L;
wire clk_sys, sdram_clk;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.c0(clk_sys),//48
.c1(sdram_clk),//96
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire key_pressed;
wire key_strobe;
wire [7:0] key_code;
wire scandoublerD;
wire ypbpr;
wire no_csync;
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.core_mod (core_mod ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire [15:0] audio;
wire [15:0] rom_addr;
wire [15:0] rom_do;
wire [15:0] spr_rom_addr;
wire [15:0] spr_rom_do;
wire [12:0] snd_rom_addr;
wire [15:0] snd_rom_do;
wire [13:0] tile_rom_addr;
wire [23:0] tile_rom_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
reg port1_req, port2_req;
wire [24:0] tl_ioctl_addr = ioctl_addr - 18'h20000;
sdram #(96) sdram(
.*,
.init_n ( pll_locked ),
.clk ( sdram_clk ),
// port1 used for main + sound CPUs
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[15:1]}), // offset 0
.cpu1_q ( rom_do ),
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h6000 + snd_rom_addr[12:1]) ), // offset c000
.cpu2_q ( snd_rom_do ),
.cpu3_addr ( ioctl_downl ? 16'hffff : (16'h8000 + spr_rom_addr[15:1]) ), // offset 10000
.cpu3_q ( spr_rom_do ),
// port2 for backround tiles
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( tl_ioctl_addr[23:1] ),
.port2_ds ( {tl_ioctl_addr[0], ~tl_ioctl_addr[0]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.sp_addr ( ioctl_downl ? 15'h7fff : tile_rom_addr ),
.sp_q ( tile_rom_do )
);
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge sdram_clk) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
SEGASYSTEM1 System1_Top(
.clk48M(clk_sys),
.reset(reset),
.INP0(INP0),
.INP1(INP1),
.INP2(INP2),
.DSW0(DSW0),
.DSW1(DSW1),
.PH(HPOS),
.PV(VPOS),
.PCLK_EN(PCLK_EN),
.POUT(POUT),
.cpu_rom_addr(rom_addr),
.cpu_rom_do( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.snd_rom_addr(snd_rom_addr),
.snd_rom_do(snd_rom_addr[0] ? snd_rom_do[15:8] : snd_rom_do[7:0] ),
.spr_rom_addr(spr_rom_addr),
.spr_rom_do(spr_rom_addr[0] ? spr_rom_do[15:8] : spr_rom_do[7:0] ),
.tile_rom_addr(tile_rom_addr),
.tile_rom_do(tile_rom_do),
.ROMCL(clk_sys),
.ROMAD(ioctl_addr[17:0]),
.ROMDT( ioctl_dout ),
.ROMEN( ioctl_wr ),
.SOUT(audio)
);
wire PCLK_EN;
wire [8:0] HPOS,VPOS;
wire [7:0] POUT;
wire [7:0] HOFFS = 8'd16;
wire [7:0] VOFFS = 0;
wire hs, vs;
wire [2:0] g, r;
wire [1:0] b;
HVGEN hvgen
(
.HPOS(HPOS),.VPOS(VPOS),.CLK(clk_sys),.PCLK_EN(PCLK_EN),.iRGB(POUT),
.oRGB({b,g,r}),.HBLK(),.VBLK(),.HSYN(hs),.VSYN(vs),
.H240(core_mod[2]),.HOFFS(HOFFS),.VOFFS(VOFFS)
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( r ),
.G ( g ),
.B ( {b, b[1]} ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.ce_divider ( 1'b0 ),
.blend ( blend ),
.rotate ( {1'b0, rotate} ),
.scandoubler_disable(scandoublerD ),
.scanlines ( scanlines ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
dac #(
.C_bits(16))
dac(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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Arcade_MiST/Sega System 1 Hardware/rtl/dpram.vhd Normal file
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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- dpram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity dpram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk_a : in std_logic;
we_a : in std_logic := '0';
addr_a : in std_logic_vector((aWidth-1) downto 0);
d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_a : out std_logic_vector((dWidth-1) downto 0);
clk_b : in std_logic;
we_b : in std_logic := '0';
addr_b : in std_logic_vector((aWidth-1) downto 0);
d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_b : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of dpram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
process(clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
ram(to_integer(unsigned(addr_a))) <= d_a;
end if;
q_a <= ram(to_integer(unsigned(addr_a)));
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
if we_b = '1' then
ram(to_integer(unsigned(addr_b))) <= d_b;
end if;
q_b <= ram(to_integer(unsigned(addr_b)));
end if;
end process;
end architecture;

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// Copyright (c) 2017,19 MiSTer-X
module DLROM #(parameter AW,parameter DW)
(
input CL0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CL1,
input [(AW-1):0] AD1,
input [(DW-1):0] DI1,
input WE1
);
reg [(DW-1):0] core[0:((2**AW)-1)];
always @(posedge CL0) DO0 <= core[AD0];
always @(posedge CL1) if (WE1) core[AD1] <= DI1;
endmodule
//----------------------------------
// 2K SRAM
//----------------------------------
module SRAM_2048( CL, ADRS, OUT, WR, IN );
input CL;
input [10:0] ADRS;
output [7:0] OUT;
input WR;
input [7:0] IN;
reg [7:0] ramcore [0:2047];
reg [7:0] OUT;
always @( posedge CL ) begin
if (WR) ramcore[ADRS] <= IN;
else OUT <= ramcore[ADRS];
end
endmodule
//----------------------------------
// 4K SRAM
//----------------------------------
module SRAM_4096(
input clk,
input [11:0] adrs,
output reg [7:0] out,
input wr,
input [7:0] in
);
reg [7:0] ramcore [0:4095];
always @( posedge clk ) begin
if (wr) ramcore[adrs] <= in;
else out <= ramcore[adrs];
end
endmodule
//----------------------------------
// DualPort RAM
//----------------------------------
module DPRAM2048
(
input clk0,
input [10:0] adr0,
input [7:0] dat0,
input wen0,
input clk1,
input [10:0] adr1,
output reg [7:0] dat1,
output reg [7:0] dtr0
);
reg [7:0] core [0:2047];
always @( posedge clk0 ) begin
if (wen0) core[adr0] <= dat0;
else dtr0 <= core[adr0];
end
always @( posedge clk1 ) begin
dat1 <= core[adr1];
end
endmodule
module DPRAM1024
(
input clk0,
input [9:0] adr0,
input [7:0] dat0,
input wen0,
input clk1,
input [9:0] adr1,
output reg [7:0] dat1,
output reg [7:0] dtr0
);
reg [7:0] core [0:1023];
always @( posedge clk0 ) begin
if (wen0) core[adr0] <= dat0;
else dtr0 <= core[adr0];
end
always @( posedge clk1 ) begin
dat1 <= core[adr1];
end
endmodule
module DPRAM2048_8_16
(
input clk0,
input [10:0] adr0,
input [7:0] dat0,
input wen0,
input clk1,
input [9:0] adr1,
output [15:0] dat1,
output [7:0] dtr0
);
wire [7:0] do0, do1;
wire [7:0] doH, doL;
DPRAM1024 core0( clk0, adr0[10:1], dat0, wen0 & (~adr0[0]), clk1, adr1, doL, do0 );
DPRAM1024 core1( clk0, adr0[10:1], dat0, wen0 & adr0[0], clk1, adr1, doH, do1 );
assign dtr0 = adr0[0] ? do1 : do0;
assign dat1 = { doH, doL };
endmodule
//----------------------------------
// VRAM
//----------------------------------
module VRAMs
(
input clk0,
input [9:0] adr0,
output reg [7:0] dat0,
input [7:0] dtw0,
input wen0,
input clk1,
input [9:0] adr1,
output reg [7:0] dat1
);
reg [7:0] core [0:1023];
always @( posedge clk0 ) begin
if (wen0) core[adr0] <= dtw0;
else dat0 <= core[adr0];
end
always @( posedge clk1 ) begin
dat1 <= core[adr1];
end
endmodule
module VRAM
(
input clk0,
input [10:0] adr0,
output [7:0] dat0,
input [7:0] dtw0,
input wen0,
input clk1,
input [9:0] adr1,
output [15:0] dat1
);
wire even = ~adr0[0];
wire odd = adr0[0];
wire [7:0] do00, do01, do10, do11;
VRAMs ram0( clk0, adr0[10:1], do00, dtw0, wen0 & even, clk1, adr1, do10 );
VRAMs ram1( clk0, adr0[10:1], do01, dtw0, wen0 & odd, clk1, adr1, do11 );
assign dat0 = adr0[0] ? do01 : do00;
assign dat1 = { do11, do10 };
endmodule
//----------------------------------
// ScanLine Buffer
//----------------------------------
module LineBuf
(
input clkr,
input [9:0] radr,
input clre,
output [10:0] rdat,
input clkw,
input [9:0] wadr,
input [10:0] wdat,
input we,
output [10:0] rdat1
);
DPRAM1024_11B core (
radr,wadr,
clkr,clkw,
16'h0,{5'h0,wdat},
clre,we,
rdat,rdat1
);
endmodule
//----------------------------------
// Data Selector (32bits)
//----------------------------------
module dataselector1_32(
output [31:0] oDATA,
input iSEL0,
input [31:0] iDATA0,
input [31:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
dData;
endmodule
//----------------------------------
// Data Selector 3 to 1
//----------------------------------
module dataselector3(
output [7:0] oDATA,
input iSEL0, input [7:0] iDATA0,
input iSEL1, input [7:0] iDATA1,
input iSEL2, input [7:0] iDATA2,
input [7:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
iSEL1 ? iDATA1 :
iSEL2 ? iDATA2 :
dData;
endmodule
//----------------------------------
// Data Selector 2 to 1 (11bits)
//----------------------------------
module dataselector2_11(
output [10:0] oDATA,
input iSEL0, input [10:0] iDATA0,
input iSEL1, input [10:0] iDATA1,
input [10:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
iSEL1 ? iDATA1 :
dData;
endmodule
//----------------------------------
// Data Selector 5 to 1
//----------------------------------
module dataselector5(
output [7:0] oDATA,
input iSEL0, input [7:0] iDATA0,
input iSEL1, input [7:0] iDATA1,
input iSEL2, input [7:0] iDATA2,
input iSEL3, input [7:0] iDATA3,
input iSEL4, input [7:0] iDATA4,
input [7:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
iSEL1 ? iDATA1 :
iSEL2 ? iDATA2 :
iSEL3 ? iDATA3 :
iSEL4 ? iDATA4 :
dData;
endmodule
//----------------------------------
// Data Selector 6 to 1
//----------------------------------
module dataselector6(
output [7:0] oDATA,
input iSEL0, input [7:0] iDATA0,
input iSEL1, input [7:0] iDATA1,
input iSEL2, input [7:0] iDATA2,
input iSEL3, input [7:0] iDATA3,
input iSEL4, input [7:0] iDATA4,
input iSEL5, input [7:0] iDATA5,
input [7:0] dData
);
assign oDATA = iSEL0 ? iDATA0 :
iSEL1 ? iDATA1 :
iSEL2 ? iDATA2 :
iSEL3 ? iDATA3 :
iSEL4 ? iDATA4 :
iSEL5 ? iDATA5 :
dData;
endmodule

337
Arcade_MiST/Sega System 1 Hardware/rtl/pll_mist.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_mist.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_mist (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 32,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "96.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "32"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

357
Arcade_MiST/Sega System 1 Hardware/rtl/sdram.sv Normal file
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@@ -0,0 +1,357 @@
//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output reg [15:0] port1_q,
input [16:1] cpu1_addr,
output reg [15:0] cpu1_q,
input [16:1] cpu2_addr,
output reg [15:0] cpu2_q,
input [16:1] cpu3_addr,
output reg [15:0] cpu3_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output reg [31:0] port2_q,
input [16:2] sp_addr,
output reg [31:0] sp_q
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
2 words burst, CL2
cmd issued registered
0 RAS0 cas1 - data0 read burst terminated
1 ras0
2 data1 returned
3 CAS0 data1 returned
4 RAS1 cas0
5 ras1
6 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_DS1b = 3'd0;
localparam STATE_READ1b = 3'd4;
localparam STATE_LAST = 3'd6;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[3];
reg [24:1] addr_latch_next[2];
reg [16:1] addr_last[4];
reg [16:2] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1 = 3'd1;
localparam PORT_CPU2 = 3'd2;
localparam PORT_CPU3 = 3'd3;
localparam PORT_SP = 3'd1;
localparam PORT_REQ = 3'd4;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 8'd0, cpu1_addr };
end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 8'd0, cpu2_addr };
end else if (cpu3_addr != addr_last[PORT_CPU3]) begin
next_port[0] = PORT_CPU3;
addr_latch_next[0] = { 8'd0, cpu3_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT1: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (sp_addr != addr_last2[PORT_SP]) begin
next_port[1] = PORT_SP;
addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][16:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
port1_state <= port1_req;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port2_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
PORT_CPU2: begin cpu2_q <= sd_din; end
PORT_CPU3: begin cpu3_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: port2_q[15:0] <= sd_din;
PORT_SP : sp_q[15:0] <= sd_din;
default: ;
endcase;
end
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if(t == STATE_READ1b && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
PORT_SP : begin sp_q[31:16] <= sd_din; end
default: ;
endcase;
end
end
end
endmodule

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Arcade_MiST/Sega System 1 Hardware/rtl/z80ip.v Normal file
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// Copyright (c) 2017,19 MiSTer-X
module Z80IP
(
input reset,
input clk,
input clk_en,
output [15:0] adr,
input [7:0] data_in,
output [7:0] data_out,
output m1,
output mx,
output ix,
output rd,
output wr,
input intreq,
output intack,
input nmireq,
output nmiack
);
wire i_mreq, i_iorq, i_rd, i_wr, i_rfsh, i_m1;
T80s cpu
(
.CLK(clk),
.CEN(clk_en),
.RESET_n(~reset),
.INT_n(~intreq),
.NMI_n(~nmireq),
.MREQ_n(i_mreq),
.IORQ_n(i_iorq),
.RFSH_n(i_rfsh),
.RD_n(i_rd),
.WR_n(i_wr),
.A(adr),
.DI(data_in),
.DO(data_out),
.WAIT_n(1'b1),
.BUSRQ_n(1'b1),
.BUSAK_n(),
.HALT_n(),
.M1_n(i_m1)
);
wire mreq = (~i_mreq) & (i_rfsh);
wire iorq = ~i_iorq;
wire rdr = ~i_rd;
wire wrr = ~i_wr;
assign intack = (adr==16'h38) & mx & rdr;
assign nmiack = (adr==16'h66) & mx & rdr;
assign m1 = ~i_m1;
assign mx = mreq;
assign ix = iorq;
assign rd = rdr;
assign wr = wrr;
endmodule