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79
Arcade_MiST/Konami Framebuffer/Meta/Tutankham (Bootleg).mra
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<misterromdescription>
<name>Tutankham (Bootleg)</name>
<region>World</region>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<version></version>
<alternative></alternative>
<platform></platform>
<series>Tutankham</series>
<year>1982</year>
<manufacturer>Bootleg</manufacturer>
<category>Maze</category>
<setname>tutankhmb</setname>
<parent>tutankhm</parent>
<mameversion>0220</mameversion>
<rbf>Tutankham</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical (cw)</rotation>
<flip>no</flip>
<players>2 (alternating)</players>
<joystick>4-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<button_names></button_names>
<switches default="00,34">
<dip bits="0,3" name="Credits A" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/7cr,1c/6cr,2c/1cr,2c/3cr,3c/1cr,2c/5cr,3c/2cr,3c/4cr,4c/3cr,4c/1cr,Free Play"/>
<dip bits="4,7" name="Credits B" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/6cr,1c/7cr,2c/1cr,2c/3cr,2c/5cr,3c/1cr,3c/2cr,3c/4cr,4c/1cr,4c/3cr,Free Play"/>
<dip bits="8,9" name="Lives" ids="3,4,5,255 (Cheat)"/>
<dip bits="10" name="Cabinet type" ids="Cocktail,Upright"/>
<dip bits="11" name="Bonus" ids="10K/50K+,20K/60K+"/>
<dip bits="12,14" name="Difficulty" ids="1 (Easiest),2,3,4,5,6,7,8 (Hardest)"/>
<dip bits="15" name="Attract mode sound" ids="Off,On"/>
</switches>
<rom index="0" md5="none" zip="tutankhm.zip|tutankhmb.zip">
<!-- Main program ROMs (0x0000-0x5FFF, 6x 4KB) -->
<part crc="37794533" name="t1.1h"/>
<part crc="a0f02c85" name="m2.2h"/>
<part crc="0c41e644" name="t3.3h"/>
<part crc="bd06fad0" name="m4.4h"/>
<part crc="bf9fd9b0" name="m5.5h"/>
<part crc="39cd1b22" name="t6.6h"/>
<!-- Banked graphics ROMs (0x6000-0xEFFF, 9x 4KB) -->
<part crc="55deafe2" name="t7.1i"/>
<part crc="6615eff3" name="c2.2i"/>
<part crc="a10d4444" name="c3.3i"/>
<part crc="58cd143c" name="c4.4i"/>
<part crc="d7e7ae95" name="c5.5i"/>
<part crc="dcde1109" name="t12.6i"/>
<part crc="c7250b9a" name="t13.7i"/>
<part crc="685a623e" name="t14.8i"/>
<part crc="8ea9c6a6" name="c9.9i"/>
</rom>
<rom index="1" md5="none" zip="tutankhm.zip|tutankhmb.zip">
<!-- Sound board ROMs (8KB total) -->
<part crc="b52d01fa" name="s1.7a"/>
<part crc="9db5c0ce" name="s2.8a"/>
</rom>
<rom index="2"></rom>
<rom index="3" md5="none">
<part>
01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
00 00 AB 08 00 28 00 F1
00 00 A9 8B 00 03 00 01
</part>
</rom>
<rom index="4"></rom>
<nvram index="4" size="43"></nvram>
<remark></remark>
<mratimestamp>20260207000000</mratimestamp>
</misterromdescription>

79
Arcade_MiST/Konami Framebuffer/Meta/Tutankham (Stern).mra
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<misterromdescription>
<name>Tutankham (Stern)</name>
<region>World</region>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<version></version>
<alternative></alternative>
<platform></platform>
<series>Tutankham</series>
<year>1982</year>
<manufacturer>Stern</manufacturer>
<category>Maze</category>
<setname>tutankhms</setname>
<parent>tutankhm</parent>
<mameversion>0220</mameversion>
<rbf>Tutankham</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical (cw)</rotation>
<flip>no</flip>
<players>2 (alternating)</players>
<joystick>4-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<button_names></button_names>
<switches default="00,34">
<dip bits="0,3" name="Credits A" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/7cr,1c/6cr,2c/1cr,2c/3cr,3c/1cr,2c/5cr,3c/2cr,3c/4cr,4c/3cr,4c/1cr,Free Play"/>
<dip bits="4,7" name="Credits B" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/6cr,1c/7cr,2c/1cr,2c/3cr,2c/5cr,3c/1cr,3c/2cr,3c/4cr,4c/1cr,4c/3cr,Free Play"/>
<dip bits="8,9" name="Lives" ids="3,4,5,255 (Cheat)"/>
<dip bits="10" name="Cabinet type" ids="Cocktail,Upright"/>
<dip bits="11" name="Bonus" ids="10K/50K+,20K/60K+"/>
<dip bits="12,14" name="Difficulty" ids="1 (Easiest),2,3,4,5,6,7,8 (Hardest)"/>
<dip bits="15" name="Attract mode sound" ids="Off,On"/>
</switches>
<rom index="0" md5="none" zip="tutankhm.zip|tutankhms.zip">
<!-- Main program ROMs (0x0000-0x5FFF, 6x 4KB) -->
<part crc="da18679f" name="m1.1h"/>
<part crc="a0f02c85" name="m2.2h"/>
<part crc="2d62d7b1" name="3a.3h"/>
<part crc="bd06fad0" name="m4.4h"/>
<part crc="bf9fd9b0" name="m5.5h"/>
<part crc="c43b3865" name="a6.6h"/>
<!-- Banked graphics ROMs (0x6000-0xEFFF, 9x 4KB) -->
<part crc="7eb59b21" name="c1.1i"/>
<part crc="6615eff3" name="c2.2i"/>
<part crc="a10d4444" name="c3.3i"/>
<part crc="58cd143c" name="c4.4i"/>
<part crc="d7e7ae95" name="c5.5i"/>
<part crc="91f62b82" name="c6.6i"/>
<part crc="afd0a81f" name="c7.7i"/>
<part crc="dabb609b" name="c8.8i"/>
<part crc="8ea9c6a6" name="c9.9i"/>
</rom>
<rom index="1" md5="none" zip="tutankhm.zip|tutankhms.zip">
<!-- Sound board ROMs (8KB total) -->
<part crc="b52d01fa" name="s1.7a"/>
<part crc="9db5c0ce" name="s2.8a"/>
</rom>
<rom index="2"></rom>
<rom index="3" md5="none">
<part>
01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
00 00 AB 08 00 28 00 F1
00 00 A9 8B 00 03 00 01
</part>
</rom>
<rom index="4"></rom>
<nvram index="4" size="43"></nvram>
<remark></remark>
<mratimestamp>20260207000000</mratimestamp>
</misterromdescription>

78
Arcade_MiST/Konami Framebuffer/Meta/Tutankham II.mra
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<misterromdescription>
<name>Tutankham II</name>
<region>World</region>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<version></version>
<alternative></alternative>
<platform></platform>
<series>Tutankham</series>
<year>2026</year>
<manufacturer>Rodimus</manufacturer>
<category>Maze</category>
<setname>tutankhm2</setname>
<parent>tutankhm</parent>
<mameversion>0220</mameversion>
<rbf>Tutankham</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical (cw)</rotation>
<flip>no</flip>
<players>2 (alternating)</players>
<joystick>4-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<button_names></button_names>
<switches default="00,34">
<dip bits="0,3" name="Credits A" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/7cr,1c/6cr,2c/1cr,2c/3cr,3c/1cr,2c/5cr,3c/2cr,3c/4cr,4c/3cr,4c/1cr,Free Play"/>
<dip bits="4,7" name="Credits B" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/6cr,1c/7cr,2c/1cr,2c/3cr,2c/5cr,3c/1cr,3c/2cr,3c/4cr,4c/1cr,4c/3cr,Free Play"/>
<dip bits="8,9" name="Lives" ids="3,4,5,255 (Cheat)"/>
<dip bits="10" name="Cabinet type" ids="Cocktail,Upright"/>
<dip bits="11" name="Bonus" ids="10K/50K+,20K/60K+"/>
<dip bits="12,14" name="Difficulty" ids="1 (Easiest),2,3,4,5,6,7,8 (Hardest)"/>
<dip bits="15" name="Attract mode sound" ids="Off,On"/>
</switches>
<rom index="0" md5="none" zip="tutankhm.zip|tutankhm2.zip">
<!-- Main program ROMs (0x0000-0x5FFF, 6x 4KB) -->
<part name="tut2.1h"/>
<part name="tut2.2h"/>
<part name="tut2.3h"/>
<part name="tut2.4h"/>
<part name="tut2.5h"/>
<part name="tut2.6h"/>
<!-- Banked graphics ROMs (0x6000-0xEFFF, 9x 4KB) -->
<part name="tut2.1i"/>
<part name="tut2.2i"/>
<part name="tut2.3i"/>
<part name="tut2.4i"/>
<part name="tut2.5i"/>
<part name="tut2.6i"/>
<part name="tut2.7i"/>
<part name="tut2.8i"/>
<part name="tut2.9i"/>
</rom>
<rom index="1" md5="none" zip="tutankhm.zip|tutankhm2.zip">
<!-- Sound board ROMs (8KB total) -->
<part crc="b52d01fa" name="s1.7a"/>
<part crc="9db5c0ce" name="s2.8a"/>
</rom>
<rom index="2"></rom>
<rom index="3" md5="none">
<part>
01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
00 00 88 A6 00 2D 03 54
</part>
</rom>
<rom index="4"></rom>
<nvram index="4" size="45"></nvram>
<remark></remark>
<mratimestamp>20260213000000</mratimestamp>
</misterromdescription>

78
Arcade_MiST/Konami Framebuffer/Meta/Tutankham.mra
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<misterromdescription>
<name>Tutankham</name>
<region>World</region>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<version></version>
<alternative></alternative>
<platform></platform>
<series>Tutankham</series>
<year>1982</year>
<manufacturer>Konami</manufacturer>
<category>Maze</category>
<setname>tutankhm</setname>
<parent>tutankhm</parent>
<mameversion>0220</mameversion>
<rbf>Tutankham</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical (cw)</rotation>
<flip>no</flip>
<players>2 (alternating)</players>
<joystick>4-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<button_names></button_names>
<switches default="00,34">
<dip bits="0,3" name="Credits A" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/7cr,1c/6cr,2c/1cr,2c/3cr,3c/1cr,2c/5cr,3c/2cr,3c/4cr,4c/3cr,4c/1cr,Free Play"/>
<dip bits="4,7" name="Credits B" ids="1c/1cr,1c/2cr,1c/3cr,1c/4cr,1c/5cr,1c/6cr,1c/7cr,2c/1cr,2c/3cr,2c/5cr,3c/1cr,3c/2cr,3c/4cr,4c/1cr,4c/3cr,Free Play"/>
<dip bits="8,9" name="Lives" ids="3,4,5,255 (Cheat)"/>
<dip bits="10" name="Cabinet type" ids="Cocktail,Upright"/>
<dip bits="11" name="Bonus" ids="10K/50K+,20K/60K+"/>
<dip bits="12,14" name="Difficulty" ids="1 (Easiest),2,3,4,5,6,7,8 (Hardest)"/>
<dip bits="15" name="Attract mode sound" ids="Off,On"/>
</switches>
<rom index="0" md5="none" zip="tutankhm.zip">
<!-- Main program ROMs (0x0000-0x5FFF, 6x 4KB) -->
<part crc="da18679f" name="m1.1h"/>
<part crc="a0f02c85" name="m2.2h"/>
<part crc="ea03a1ab" name="3j.3h"/>
<part crc="bd06fad0" name="m4.4h"/>
<part crc="bf9fd9b0" name="m5.5h"/>
<part crc="fe079c5b" name="j6.6h"/>
<!-- Banked graphics ROMs (0x6000-0xEFFF, 9x 4KB) -->
<part crc="7eb59b21" name="c1.1i"/>
<part crc="6615eff3" name="c2.2i"/>
<part crc="a10d4444" name="c3.3i"/>
<part crc="58cd143c" name="c4.4i"/>
<part crc="d7e7ae95" name="c5.5i"/>
<part crc="91f62b82" name="c6.6i"/>
<part crc="afd0a81f" name="c7.7i"/>
<part crc="dabb609b" name="c8.8i"/>
<part crc="8ea9c6a6" name="c9.9i"/>
</rom>
<rom index="1" md5="none" zip="tutankhm.zip">
<!-- Sound board ROMs (8KB total) -->
<part crc="b52d01fa" name="s1.7a"/>
<part crc="9db5c0ce" name="s2.8a"/>
</rom>
<rom index="2"></rom>
<rom index="3" md5="none">
<part>
01 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 00 00
00 00 88 A6 00 2D 03 54
</part>
</rom>
<rom index="4"></rom>
<nvram index="4" size="45"></nvram>
<remark></remark>
<mratimestamp>20260213000000</mratimestamp>
</misterromdescription>

49
Arcade_MiST/Konami Framebuffer/README.MD
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---------------------------------------------------------------------------------
--
-- Arcade: Tutankham port to MiSTer by Rodimus
-- 09 February 2026
--
---------------------------------------------------------------------------------
-- A simulation model of Tutankham hardware
-- Copyright (c) Rodimus - February 2026
-- Based on the Time Pilot Core (Same exact Sound Board)
---------------------------------------------------------------------------------
--
-- Support screen and controls rotation on HDMI output.
-- Only controls are rotated on VGA output.
--
--
-- Joystick support : A - fire right, B - fire left, X - flash bomb, select - coin up, start - 1 player start, left shoulder - pause, right shoulder - 2 player start
--
----------------------------------------------
Hiscore save/load:
Highscore saving is untested.
To save your hiscores manually, press the 'Save Settings' option in the OSD. Hiscores will be automatically loaded when the core is started.
To enable automatic saving of hiscores, turn on the 'Autosave Hiscores' option and press the 'Save Settings' option in the OSD. Hiscores will then be automatically saved (if they have changed) any time the OSD is opened.
Hiscore data is stored in /media/fat/config/nvram/ as ```<mra filename>.nvm```
---------------------------------------------------------------------------------
*** Attention ***
ROMs are not included. In order to use this arcade, you need to provide the
correct ROMs.
To simplify the process .mra files are provided in the releases folder, that
specifies the required ROMs with checksums. The ROMs .zip filename refers to the
corresponding file of the M.A.M.E. project.
Please refer to https://github.com/MiSTer-devel/Main_MiSTer/wiki/Arcade-Roms for
information on how to setup and use the environment.
Quickreference for folders and file placement:
/_Arcade/<game name>.mra
/_Arcade/cores/<game rbf>.rbf
/_Arcade/mame/<mame rom>.zip
/_Arcade/hbmame/<hbmame rom>.zip

30
Arcade_MiST/Konami Framebuffer/Tutankham.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 17:44:51 March 04, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "17:44:51 March 04, 2019"
# Revisions
PROJECT_REVISION = "Tutankham"

274
Arcade_MiST/Konami Framebuffer/Tutankham.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 16:55:52 February 22, 2026
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Tutankham_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham_TOP.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tutankham_CPU.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TimePilot_SND.sv
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rom_loader.sv
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
set_global_assignment -name VERILOG_FILE rtl/jtframe_frac_cen.v
set_global_assignment -name VHDL_FILE rtl/dpram_dc.vhd
set_global_assignment -name QIP_FILE rtl/custom/tut_custom.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/blitter.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE ../../common/CPU/MC6809/mc6809.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../common/Sound/JT49/jt49.qip
set_global_assignment -name QIP_FILE ../../common/Sound/JT49/filter/jt49_filters.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_46 -to UART_TX
set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name TOP_LEVEL_ENTITY Tutankham
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/custom.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# -----------------------
# start ENTITY(Tutankham)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Tutankham)
# ---------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

53
Arcade_MiST/Konami Framebuffer/Tutankham.sdc
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@@ -1,53 +0,0 @@
#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
#
#************************************************************
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
# SDRAM delays
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1

593
Arcade_MiST/Konami Framebuffer/Useful Information/Arcade-Tutankham.sv
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@@ -1,593 +0,0 @@
//============================================================================
//
// Port to MiSTer.
// Copyright (C) 2026 Rodimus
//
// Tutankham for MiSTer
// Based on Time Pilot core, original design Copyright (C) 2017 Dar
// Initial port to MiSTer Copyright (C) 2017 Sorgelig
// Updated port to MiSTer Copyright (C) 2021 Ace,
// Ash Evans (aka ElectronAsh/OzOnE), Artemio Urbina and Kitrinx (aka Rysha)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [48:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
output [12:0] VIDEO_ARX,
output [12:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER, // Force VGA scaler
output VGA_DISABLE, // analog out is off
input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,
output HDMI_FREEZE,
output HDMI_BLACKOUT,
output HDMI_BOB_DEINT,
`ifdef MISTER_FB
// Use framebuffer in DDRAM (USE_FB=1 in qsf)
// FB_FORMAT:
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// [3] : 0=16bits 565 1=16bits 1555
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
//
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output FB_FORCE_BLANK,
`ifdef MISTER_FB_PALETTE
// Palette control for 8bit modes.
// Ignored for other video modes.
output FB_PAL_CLK,
output [7:0] FB_PAL_ADDR,
output [23:0] FB_PAL_DOUT,
input [23:0] FB_PAL_DIN,
output FB_PAL_WR,
`endif
`endif
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
// I/O board button press simulation (active high)
// b[1]: user button
// b[0]: osd button
output [1:0] BUTTONS,
input CLK_AUDIO, // 24.576 MHz
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
//ADC
inout [3:0] ADC_BUS,
//SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
`ifdef MISTER_DUAL_SDRAM
//Secondary SDRAM
//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
input SDRAM2_EN,
output SDRAM2_CLK,
output [12:0] SDRAM2_A,
output [1:0] SDRAM2_BA,
inout [15:0] SDRAM2_DQ,
output SDRAM2_nCS,
output SDRAM2_nCAS,
output SDRAM2_nRAS,
output SDRAM2_nWE,
`endif
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..6 - USR2..USR6
// Set USER_OUT to 1 to read from USER_IN.
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS
);
assign ADC_BUS = 'Z;
assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
assign VGA_F1 = 0;
assign VGA_SCALER = 0;
assign VGA_DISABLE = 0;
assign FB_FORCE_BLANK = 0;
assign HDMI_FREEZE = 0;
assign HDMI_BLACKOUT = 0;
assign HDMI_BOB_DEINT = 0;
wire signed [15:0] audio;
assign AUDIO_L = audio;
assign AUDIO_R = audio;
assign AUDIO_S = 1;
assign AUDIO_MIX = 0;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign LED_USER = ioctl_download;
assign BUTTONS = 0;
///////////////////////////////////////////////////
wire [1:0] ar = status[14:13];
assign VIDEO_ARX = status[12] ? ((!ar) ? 12'd16 : (ar - 1'd1)) : ((!ar) ? 12'd14 : (ar - 1'd1));
assign VIDEO_ARY = status[12] ? ((!ar) ? 12'd14 : 12'd0) : ((!ar) ? 12'd16 : 12'd0);
`include "build_id.v"
localparam CONF_STR = {
"TUTANKHAM;;",
"ODE,Aspect Ratio,Original,Full screen,[ARC1],[ARC2];",
"OC,Orientation,Vert,Horz;",
"OB,Flip Vertical,Off,On;",
"OFH,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
"OL,Game Speed,Native,60Hz Adjust;",
"-;",
"H1OR,Autosave Hiscores,Off,On;",
"P1,Pause Options;",
"P1OP,Pause when OSD is open,On,Off;",
"P1OQ,Dim video after 10s,On,Off;",
"-;",
"DIP;",
"-;",
"P2,Screen Centering;",
"P2O36,H Center,0,-1,-2,-3,-4,-5,-6,-7,+7,+6,+5,+4,+3,+2,+1;",
"P2O7A,V Center,0,-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12;",
"-;",
"R0,Reset;",
"J1,Fire Left,Fire Right,Flash Bomb,Coin,Start 1P,Start 2P,Pause;",
"jn,B,A,X,Select,Start,R,L;",
"V,v",`BUILD_DATE
};
wire forced_scandoubler;
wire [1:0] buttons;
wire [31:0] status;
wire [10:0] ps2_key;
wire ioctl_download;
wire ioctl_upload;
wire ioctl_upload_req;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [7:0] ioctl_din;
wire [15:0] joystick_0, joystick_1;
wire [15:0] joy = joystick_0 | joystick_1;
wire [21:0] gamma_bus;
wire direct_video;
hps_io #(.CONF_STR(CONF_STR)) hps_io
(
.clk_sys(CLK_49M),
.HPS_BUS(HPS_BUS),
.EXT_BUS(),
.gamma_bus(gamma_bus),
.direct_video(direct_video),
.video_rotated(video_rotated),
.forced_scandoubler(forced_scandoubler),
.buttons(buttons),
.status(status),
.status_menumask({~hs_configured,direct_video}),
.ioctl_download(ioctl_download),
.ioctl_upload(ioctl_upload),
.ioctl_upload_req(ioctl_upload_req),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_din(ioctl_din),
.ioctl_index(ioctl_index),
.joystick_0(joystick_0),
.joystick_1(joystick_1),
.ps2_key(ps2_key)
);
//////////////////// CLOCKS ///////////////////
wire CLK_49M;
wire locked;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(CLK_49M),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
.locked(locked)
);
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;
wire cfg_waitrequest;
reg cfg_write;
reg [5:0] cfg_address;
reg [31:0] cfg_data;
//Reconfigure PLL to apply an ~1% underclock to Tutankham to bring video timings in spec for 60Hz VSync (sourced from Genesis core)
pll_cfg pll_cfg
(
.mgmt_clk(CLK_50M),
.mgmt_reset(0),
.mgmt_waitrequest(cfg_waitrequest),
.mgmt_read(0),
.mgmt_readdata(),
.mgmt_write(cfg_write),
.mgmt_address(cfg_address),
.mgmt_writedata(cfg_data),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
always @(posedge CLK_50M) begin
reg underclock = 0, underclock2 = 0;
reg [2:0] state = 0;
reg underclock_r;
underclock <= status[21];
underclock2 <= underclock;
cfg_write <= 0;
if(underclock2 == underclock && underclock2 != underclock_r) begin
state <= 1;
underclock_r <= underclock2;
end
if(!cfg_waitrequest) begin
if(state)
state <= state + 3'd1;
case(state)
1: begin
cfg_address <= 0;
cfg_data <= 0;
cfg_write <= 1;
end
5: begin
cfg_address <= 7;
cfg_data <= underclock_r ? 3268298314 : 3639383488;
cfg_write <= 1;
end
7: begin
cfg_address <= 2;
cfg_data <= 0;
cfg_write <= 1;
end
endcase
end
end
wire reset = RESET | status[0] | buttons[1];
/////////////////// Keyboard //////////////////
reg btn_up = 0;
reg btn_down = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_fire = 0;
reg btn_coin1 = 0;
reg btn_coin2 = 0;
reg btn_1p_start = 0;
reg btn_2p_start = 0;
reg btn_pause = 0;
reg btn_service = 0;
wire pressed = ps2_key[9];
wire [7:0] code = ps2_key[7:0];
always @(posedge CLK_49M) begin
reg old_state;
old_state <= ps2_key[10];
if(old_state != ps2_key[10]) begin
case(code)
'h16: btn_1p_start <= pressed; // 1
'h1E: btn_2p_start <= pressed; // 2
'h2E: btn_coin1 <= pressed; // 5
'h36: btn_coin2 <= pressed; // 6
'h46: btn_service <= pressed; // 9
'h4D: btn_pause <= pressed; // P
'h75: btn_up <= pressed; // up
'h72: btn_down <= pressed; // down
'h6B: btn_left <= pressed; // left
'h74: btn_right <= pressed; // right
'h14: btn_fire <= pressed; // ctrl
endcase
end
end
////////////////// Arcade Buttons/Interfaces ///////////////////////////
//Player 1 — 4-way movement joystick (D-pad / left stick)
wire m_up1 = btn_up | joystick_0[3];
wire m_down1 = btn_down | joystick_0[2];
wire m_left1 = btn_left | joystick_0[1];
wire m_right1 = btn_right | joystick_0[0];
//Player 1 — 2-way fire joystick (B=fire left, A=fire right)
wire m_fire1_l = btn_fire | joystick_0[4]; // B button = fire left
wire m_fire1_r = joystick_0[5]; // A button = fire right
wire m_flash1 = joystick_0[6]; // X button = flash bomb
//Player 2 — 4-way movement (second controller D-pad)
wire m_up2 = joystick_1[3];
wire m_down2 = joystick_1[2];
wire m_left2 = joystick_1[1];
wire m_right2 = joystick_1[0];
//Player 2 — 2-way fire
wire m_fire2_l = joystick_1[4];
wire m_fire2_r = joystick_1[5];
wire m_flash2 = joystick_1[6];
//Start/coin
wire m_start1 = btn_1p_start | joystick_0[8]; // Start button
wire m_start2 = btn_2p_start | joystick_0[9]; // R shoulder
wire m_coin1 = btn_coin1 | joystick_0[7]; // Select button
wire m_coin2 = btn_coin2;
wire m_pause = btn_pause | joystick_0[10]; // L shoulder (handled by framework)
// PAUSE SYSTEM
wire pause_cpu;
wire [23:0] rgb_out;
pause #(8,8,8,49) pause
(
.*,
.clk_sys(CLK_49M),
.user_button(m_pause),
.pause_request(hs_pause),
.options(~status[26:25])
);
// DIP SWITCHES
reg [7:0] dip_sw[8]; // Active-LOW
always @(posedge CLK_49M) begin
if(ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3])
dip_sw[ioctl_addr[2:0]] <= ioctl_dout;
end
/////////////// Video ////////////////
wire hblank, vblank;
wire hs, vs;
wire [4:0] r_out, g_out, b_out;
//Adjust color tones for the final output so they better match an original
//Tutankham PCB (credit: Paulb-nl)
wire [7:0] r = (r_out[0] ? 8'h19 : 8'h00) +
(r_out[1] ? 8'h24 : 8'h00) +
(r_out[2] ? 8'h35 : 8'h00) +
(r_out[3] ? 8'h40 : 8'h00) +
(r_out[4] ? 8'h4D : 8'h00);
wire [7:0] g = (g_out[0] ? 8'h19 : 8'h00) +
(g_out[1] ? 8'h24 : 8'h00) +
(g_out[2] ? 8'h35 : 8'h00) +
(g_out[3] ? 8'h40 : 8'h00) +
(g_out[4] ? 8'h4D : 8'h00);
wire [7:0] b = (b_out[0] ? 8'h19 : 8'h00) +
(b_out[1] ? 8'h24 : 8'h00) +
(b_out[2] ? 8'h35 : 8'h00) +
(b_out[3] ? 8'h40 : 8'h00) +
(b_out[4] ? 8'h4D : 8'h00);
wire ce_pix;
wire rotate_ccw = 0;
wire no_rotate = status[12] | direct_video;
wire flip = status[11] | ~no_rotate;
screen_rotate screen_rotate(.*);
arcade_video #(256,24) arcade_video
(
.*,
.clk_video(CLK_49M),
.RGB_in(rgb_out),
.HBlank(hblank),
.VBlank(vblank),
.HSync(~hs),
.VSync(~vs),
.fx(status[17:15])
);
//Instantiate Tutankham top-level module
Tutankham TUT_inst
(
.reset(~reset), // input reset
.clk_49m(CLK_49M), // input clk_49m
.coin({~m_coin2, ~m_coin1}), // input [1:0] coin
.start_buttons({~m_start2, ~m_start1}), // input [1:0] start_buttons
.p1_joystick({~m_right1, ~m_left1, ~m_down1, ~m_up1}),
.p2_joystick({~m_right2, ~m_left2, ~m_down2, ~m_up2}),
.p1_fire(~m_fire1_l),
.p2_fire(~m_fire2_l),
.m_fire1_l(m_fire1_l),
.m_fire1_r(m_fire1_r),
.m_flash1(m_flash1),
.m_fire2_l(m_fire2_l),
.m_fire2_r(m_fire2_r),
.m_flash2(m_flash2),
.btn_service(~btn_service),
.dip_sw({~dip_sw[1], ~dip_sw[0]}), // input [15:0] dip_sw
.h_center(status[6:3]), // Screen centering
.v_center(status[10:7]),
.video_hsync(hs), // output video_hsync
.video_vsync(vs), // output video_vsync
.video_vblank(vblank), // output video_vblank
.video_hblank(hblank), // output video_hblank
.ce_pix(ce_pix), // output ce_pix
.video_r(r_out), // output [4:0] video_r
.video_g(g_out), // output [4:0] video_g
.video_b(b_out), // output [4:0] video_b
.sound(audio), // output [15:0] sound
.ioctl_addr(ioctl_addr),
.ioctl_wr(ioctl_wr),
.ioctl_data(ioctl_dout),
.ioctl_index(ioctl_index),
.pause(pause_cpu),
//Flag to signal that Tutankham has been underclocked to normalize video timings in order to maintain consistent sound timings and pitch
.underclock(status[21]),
.hs_address(hs_address),
.hs_data_out(hs_data_out),
.hs_data_in(hs_data_in),
.hs_write(hs_write_enable)
);
// HISCORE SYSTEM
// --------------
wire [15:0]hs_address;
wire [7:0] hs_data_in;
wire [7:0] hs_data_out;
wire hs_write_enable;
wire hs_access_read;
wire hs_access_write;
wire hs_pause;
wire hs_configured;
hiscore #(
.HS_ADDRESSWIDTH(16),
.CFG_ADDRESSWIDTH(3),
.CFG_LENGTHWIDTH(2)
) hi (
.*,
.clk(CLK_49M),
.paused(pause_cpu),
.autosave(status[27]),
.ram_address(hs_address),
.data_from_ram(hs_data_out),
.data_to_ram(hs_data_in),
.data_from_hps(ioctl_dout),
.data_to_hps(ioctl_din),
.ram_write(hs_write_enable),
.ram_intent_read(hs_access_read),
.ram_intent_write(hs_access_write),
.pause_cpu(hs_pause),
.configured(hs_configured)
);
endmodule

715
Arcade_MiST/Konami Framebuffer/Useful Information/MemoryMap.txt
View File

@@ -1,715 +0,0 @@
| ROM | Address Range | Size | Description | Notes |
|--------|-----------------|-------|---------------------------------|----------------------------|
| m1.1h | 0xA000-0xA2D0 | 721B | Unknown (Code/Data) | Unknown |
| m1.1h | 0xA2D1-0xA2E0 | 16B | Map 1 Palette Data | Used for Map 1 Wall Colors |
| m1.1h | 0xA2E1-0xA2F0 | 16B | Map 2 Palette Data | Used for Map 2 Wall Colors |
| m1.1h | 0xA2F1-0xA300 | 16B | Map 3 Palette Data | Used for Map 3 Wall Colors |
| m1.1h | 0xA301-0xA310 | 16B | Map 4 Palette Data | Used for Map 4 Wall Colors |
| m1.1h | 0xA311-0xA320 | 16B | High Score Palette Data | Used for High Score Screen |
| m1.1h | 0xA321-0xA330 | 16B | UI Palette Data | Used for Title Screen |
| m1.1h | 0xA331-0xA340 | 16B | UI Palette Data | Used for Player Start |
| m1.1h | 0xA341-0xA49F | 351B | Unknown (Code/Data) | |
| m1.1h | 0xA4A0-0xA4A2 | 3B | HIGH SCORE | 03 58 40 (035840) |
| m1.1h | 0xA4A3-0xA4A5 | 3B | 1ST Score | 03 58 40 (035840) |
| m1.1h | 0xA4A6-0xA4A8 | 3B | 1ST Name | 48 54 41 (HTA in ASCII) |
| m1.1h | 0xA4A9-0xA4AB | 3B | 2ND Score | 03 40 60 (034060) |
| m1.1h | 0xA4AC-0xA4AE | 3B | 2ND Name | 4D 4E 55 (MNU in ASCII) |
| m1.1h | 0xA4AF-0xA4B1 | 3B | 3RD Score | 03 38 60 (033860) |
| m1.1h | 0xA4B2-0xA4B4 | 3B | 3RD Name | 53 49 53 (SIS in ASCII) |
| m1.1h | 0xA4B5-0xA4B7 | 3B | 4TH Score | 02 96 60 (029660) |
| m1.1h | 0xA4B8-0xA4BA | 3B | 4TH Name | 4B 4B 4F (KKO in ASCII) |
| m1.1h | 0xA4BB-0xA4BD | 3B | 5TH Score | 02 34 60 (023460) |
| m1.1h | 0xA4BE-0xA4C0 | 3B | 5TH Name | 59 4E 41 (YNA in ASCII) |
| m1.1h | 0xA4C1-0xA4C3 | 3B | 6TH Score | 01 58 60 (015860) |
| m1.1h | 0xA4C4-0xA4C6 | 3B | 6TH Name | 46 55 4A (FUJ in ASCII) |
| m1.1h | 0xA4C7-0xA4C9 | 3B | 7TH Score | 01 20 60 (012060) |
| m1.1h | 0xA4CA-0xA4CC | 3B | 7TH Name | 4D 41 54 (MAT in ASCII) |
| m1.1h | 0xA4CD-0xA4CD | 1B | 1ST Stage | 02 (Level 3) |
| m1.1h | 0xA4CE-0xA4CE | 1B | 2ND Stage | 02 (Level 3) |
| m1.1h | 0xA4CF-0xA4CF | 1B | 3RD Stage | 02 (Level 3) |
| m1.1h | 0xA4D0-0xA4D0 | 1B | 4TH Stage | 01 (Level 2) |
| m1.1h | 0xA4D1-0xA4D1 | 1B | 5TH Stage | 01 (Level 2) |
| m1.1h | 0xA4D2-0xA4D2 | 1B | 6TH Stage | 01 (Level 2) |
| m1.1h | 0xA4D3-0xA4D3 | 1B | 7TH Stage | 01 (Level 2) |
| m1.1h | 0xA4D4-0xA4D5 | 2B | Coin Mech A - 1 Coin/1 Credit | 01 01 (DS 1 - xxxx0000) |
| m1.1h | 0xA4D6-0xA4D7 | 2B | Coin Mech A - 1 Coin/2 Credits | 01 02 (DS 1 - xxxx0001) |
| m1.1h | 0xA4D8-0xA4D9 | 2B | Coin Mech A - 1 Coin/3 Credits | 01 03 (DS 1 - xxxx0010) |
| m1.1h | 0xA4DA-0xA4DB | 2B | Coin Mech A - 1 Coin/4 Credits | 01 04 (DS 1 - xxxx0011) |
| m1.1h | 0xA4DC-0xA4DD | 2B | Coin Mech A - 1 Coin/5 Credits | 01 05 (DS 1 - xxxx0100) |
| m1.1h | 0xA4DE-0xA4DF | 2B | Coin Mech A - 1 Coin/6 Credits | 01 06 (DS 1 - xxxx0101) |
| m1.1h | 0xA4E0-0xA4E1 | 2B | Coin Mech A - 1 Coin/7 Credits | 01 07 (DS 1 - xxxx0110) |
| m1.1h | 0xA4E2-0xA4E3 | 2B | Coin Mech A - 2 Coins/1 Credit | 02 01 (DS 1 - xxxx0111) |
| m1.1h | 0xA4E4-0xA4E5 | 2B | Coin Mech A - 2 Coins/3 Credits | 02 03 (DS 1 - xxxx1000) |
| m1.1h | 0xA4E6-0xA4E7 | 2B | Coin Mech A - 2 Coins/5 Credits | 02 05 (DS 1 - xxxx1001) |
| m1.1h | 0xA4E8-0xA4E9 | 2B | Coin Mech A - 3 Coins/1 Credit | 03 01 (DS 1 - xxxx1010) |
| m1.1h | 0xA4EA-0xA4EB | 2B | Coin Mech A - 3 Coins/2 Credits | 03 02 (DS 1 - xxxx1011) |
| m1.1h | 0xA4EC-0xA4ED | 2B | Coin Mech A - 3 Coins/4 Credits | 03 04 (DS 1 - xxxx1100) |
| m1.1h | 0xA4EE-0xA4EF | 2B | Coin Mech A - 4 Coins/1 Credit | 04 01 (DS 1 - xxxx1101) |
| m1.1h | 0xA4F0-0xA4F1 | 2B | Coin Mech A - 4 Coins/3 Credits | 04 03 (DS 1 - xxxx1110) |
| m1.1h | 0xA4F2-0xA4F3 | 2B | Coin Mech A - Free Play | 01 00 (DS 1 - xxxx1111) |
| m1.1h | 0xA4F4-0xA4F5 | 2B | Coin Mech B - 1 Coin/1 Credit | 01 01 (DS 1 - 0000xxxx) |
| m1.1h | 0xA4F6-0xA4F7 | 2B | Coin Mech B - 1 Coin/2 Credits | 01 02 (DS 1 - 0001xxxx) |
| m1.1h | 0xA4F8-0xA4F9 | 2B | Coin Mech B - 1 Coin/3 Credits | 01 03 (DS 1 - 0010xxxx) |
| m1.1h | 0xA4FA-0xA4FB | 2B | Coin Mech B - 1 Coin/4 Credits | 01 04 (DS 1 - 0011xxxx) |
| m1.1h | 0xA4FC-0xA4FD | 2B | Coin Mech B - 1 Coin/5 Credits | 01 05 (DS 1 - 0100xxxx) |
| m1.1h | 0xA4FE-0xA4FF | 2B | Coin Mech B - 1 Coin/6 Credits | 01 06 (DS 1 - 0101xxxx) |
| m1.1h | 0xA500-0xA501 | 2B | Coin Mech B - 1 Coin/7 Credits | 01 07 (DS 1 - 0110xxxx) |
| m1.1h | 0xA502-0xA503 | 2B | Coin Mech B - 2 Coins/1 Credit | 02 01 (DS 1 - 0111xxxx) |
| m1.1h | 0xA504-0xA505 | 2B | Coin Mech B - 2 Coins/3 Credits | 02 03 (DS 1 - 1000xxxx) |
| m1.1h | 0xA506-0xA507 | 2B | Coin Mech B - 2 Coins/5 Credits | 02 05 (DS 1 - 1001xxxx) |
| m1.1h | 0xA508-0xA509 | 2B | Coin Mech B - 3 Coins/1 Credit | 03 01 (DS 1 - 1010xxxx) |
| m1.1h | 0xA50A-0xA50B | 2B | Coin Mech B - 3 Coins/2 Credits | 03 02 (DS 1 - 1011xxxx) |
| m1.1h | 0xA50C-0xA50D | 2B | Coin Mech B - 3 Coins/4 Credits | 03 04 (DS 1 - 1100xxxx) |
| m1.1h | 0xA50E-0xA50F | 2B | Coin Mech B - 4 Coins/1 Credit | 04 01 (DS 1 - 1101xxxx) |
| m1.1h | 0xA510-0xA511 | 2B | Coin Mech B - 4 Coins/3 Credits | 04 03 (DS 1 - 1110xxxx) |
| m1.1h | 0xA512-0xA513 | 2B | Coin Mech B - Invalid? | 01 00 (DS 1 - 1111xxxx) |
| m1.1h | 0xA514-0xA553 | 64B | Unknown (Code/Data) | Unknown |
| m1.1h | 0xA554-0xA55D | 10B | Unknown Block Range Start | Unknown purpose |
| m1.1h | 0xA55E-0xA57D | 32B | Unknown Range 1 | Unknown purpose |
| m1.1h | 0xA57E-0xA59D | 32B | Unknown Range 2 | Unknown purpose |
| m1.1h | 0xA59E-0xA5BD | 32B | Unknown Range 3 | Unknown purpose |
| m1.1h | 0xA5BE-0xA5DD | 32B | Unknown Range 4 | Unknown purpose |
| m1.1h | 0xA5DE-0xA5FD | 32B | Unknown Range 5 | Unknown purpose |
| m1.1h | 0xA5FE-0xA61D | 32B | Map Block Range Start | Pointers to map blocks |
| m1.1h | 0xA61E-0xA61F | 2B | Map 1/D1 Logical Map Pointer | BIG-ENDIAN, 0x9000 |
| m1.1h | 0xA620-0xA621 | 2B | Map 1/D1 Visual Map Pointer | BIG-ENDIAN, 0x9000 |
| m1.1h | 0xA622-0xA622 | 1B | Map 1/D1 Enemy Spawn Rate | 0x05-0x08 range |
| m1.1h | 0xA623-0xA623 | 1B | Map 1/D1 Time Limit | Seconds, e.g., 0x3C=60s |
| m1.1h | 0xA624-0xA628 | 5B | Map 1/D1 Unknown Data | Unknown purpose |
| m1.1h | 0xA629-0xA62B | 3B | Map 1/D1 Player Start | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA62C-0xA62E | 3B | Map 1/D1 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA62F-0xA631 | 3B | Map 1/D1 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA632-0xA634 | 3B | Map 1/D1 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA635-0xA635 | 1B | Map 1/D1 Map Width | (Value + 0x01) Screens |
| m1.1h | 0xA636-0xA636 | 1B | Map 1/D1 Ring 1 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA637-0xA63A | 4B | Map 1/D1 Ring 1 - Padding | 00 00 00 00 |
| m1.1h | 0xA63B-0xA63D | 3B | Map 1/D1 Ring 1 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA63E-0xA644 | 7B | Map 1/D1 Ring 1 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA645-0xA645 | 1B | Map 1/D1 Ring 1 - Tile ID | 0x6F |
| m1.1h | 0xA646-0xA646 | 1B | Map 1/D1 Ring 2 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA647-0xA64A | 4B | Map 1/D1 Ring 2 - Padding | 00 00 00 00 |
| m1.1h | 0xA64B-0xA64D | 3B | Map 1/D1 Ring 2 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA64E-0xA654 | 7B | Map 1/D1 Ring 2 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA655-0xA655 | 1B | Map 1/D1 Ring 2 - Tile ID | 0x6F |
| m1.1h | 0xA656-0xA656 | 1B | Map 1/D1 Ring 3 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA657-0xA65A | 4B | Map 1/D1 Ring 3 - Padding | 00 00 00 00 |
| m1.1h | 0xA65B-0xA65D | 3B | Map 1/D1 Ring 3 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA65E-0xA664 | 7B | Map 1/D1 Ring 3 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA665-0xA665 | 1B | Map 1/D1 Ring 3 - Tile ID | 0x6F |
| m1.1h | 0xA666-0xA666 | 1B | Map 1/D1 Ring 4 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA667-0xA66A | 4B | Map 1/D1 Ring 4 - Padding | 00 00 00 00 |
| m1.1h | 0xA66B-0xA66D | 3B | Map 1/D1 Ring 4 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA66E-0xA674 | 7B | Map 1/D1 Ring 4 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA675-0xA675 | 1B | Map 1/D1 Ring 4 - Tile ID | 0x6F |
| m1.1h | 0xA676-0xA676 | 1B | Map 1/D1 Key 1 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA677-0xA67A | 4B | Map 1/D1 Key 1 - Padding | 00 00 00 00 |
| m1.1h | 0xA67B-0xA67D | 3B | Map 1/D1 Key 1 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA67E-0xA684 | 7B | Map 1/D1 Key 1 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA685-0xA685 | 1B | Map 1/D1 Key 1 - Tile ID | 0x70 |
| m1.1h | 0xA686-0xA686 | 1B | Map 1/D1 Key 2 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA687-0xA68A | 4B | Map 1/D1 Key 2 - Padding | 00 00 00 00 |
| m1.1h | 0xA68B-0xA68D | 3B | Map 1/D1 Key 2 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA68E-0xA694 | 7B | Map 1/D1 Key 2 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA695-0xA695 | 1B | Map 1/D1 Key 2 - Tile ID | 0x70 |
| m1.1h | 0xA696-0xA696 | 1B | Map 1/D1 Key 3 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA697-0xA69A | 4B | Map 1/D1 Key 3 - Padding | 00 00 00 00 |
| m1.1h | 0xA69B-0xA69D | 3B | Map 1/D1 Key 3 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA69E-0xA6A4 | 7B | Map 1/D1 Key 3 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA6A5-0xA6A5 | 1B | Map 1/D1 Key 3 - Tile ID | 0x70 |
| m1.1h | 0xA6A6-0xA6A6 | 1B | Map 1/D1 Key 4 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA6A7-0xA6AA | 4B | Map 1/D1 Key 4 - Padding | 00 00 00 00 |
| m1.1h | 0xA6AB-0xA6AD | 3B | Map 1/D1 Key 4 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA6AE-0xA6B4 | 7B | Map 1/D1 Key 4 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA6B5-0xA6B5 | 1B | Map 1/D1 Key 4 - Tile ID | 0x70 |
| m1.1h | 0xA6B6-0xA6B6 | 1B | Map 1/D1 Keyhole 1 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA6B7-0xA6BA | 4B | Map 1/D1 Keyhole 1 - Padding | 00 00 00 00 |
| m1.1h | 0xA6BB-0xA6BD | 3B | Map 1/D1 Keyhole 1 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA6BE-0xA6C4 | 7B | Map 1/D1 Keyhole 1 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA6C5-0xA6C5 | 1B | Map 1/D1 Keyhole 1 - Tile ID | 0x72 |
| m1.1h | 0xA6C6-0xA6C6 | 1B | Map 1/D1 Keyhole 2 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA6C7-0xA6CA | 4B | Map 1/D1 Keyhole 2 - Padding | 00 00 00 00 |
| m1.1h | 0xA6CB-0xA6CD | 3B | Map 1/D1 Keyhole 2 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA6CE-0xA6D4 | 7B | Map 1/D1 Keyhole 2 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA6D5-0xA6D5 | 1B | Map 1/D1 Keyhole 2 - Tile ID | 0x72 |
| m1.1h | 0xA6D6-0xA6D6 | 1B | Map 1/D1 Keyhole 3 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA6D7-0xA6DA | 4B | Map 1/D1 Keyhole 3 - Padding | 00 00 00 00 |
| m1.1h | 0xA6DB-0xA6DD | 3B | Map 1/D1 Keyhole 3 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA6DE-0xA6E4 | 7B | Map 1/D1 Keyhole 3 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA6E5-0xA6E5 | 1B | Map 1/D1 Keyhole 3 - Tile ID | 0x72 |
| m1.1h | 0xA6E6-0xA6E6 | 1B | Map 1/D1 Keyhole 4 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA6E7-0xA6EA | 4B | Map 1/D1 Keyhole 4 - Padding | 00 00 00 00 |
| m1.1h | 0xA6EB-0xA6ED | 3B | Map 1/D1 Keyhole 4 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA6EE-0xA6F4 | 7B | Map 1/D1 Keyhole 4 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA6F5-0xA6F5 | 1B | Map 1/D1 Keyhole 4 - Tile ID | 0x72 |
| m1.1h | 0xA6F6-0xA6F6 | 1B | Map 1/D1 Crown 1 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA6F7-0xA6FA | 4B | Map 1/D1 Crown 1 - Padding | 00 00 00 00 |
| m1.1h | 0xA6FB-0xA6FD | 3B | Map 1/D1 Crown 1 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA6FE-0xA704 | 7B | Map 1/D1 Crown 1 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA705-0xA705 | 1B | Map 1/D1 Crown 1 - Tile ID | 0x62 |
| m1.1h | 0xA706-0xA706 | 1B | Map 1/D1 Crown 2 - Active | 0x00 Inactive/0x01 Active |
| m1.1h | 0xA707-0xA70A | 4B | Map 1/D1 Crown 2 - Padding | 00 00 00 00 |
| m1.1h | 0xA70B-0xA70D | 3B | Map 1/D1 Crown 2 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA70E-0xA714 | 7B | Map 1/D1 Crown 2 - Padding | 00 00 00 00 00 00 00 |
| m1.1h | 0xA715-0xA715 | 1B | Map 1/D1 Crown 2 - Tile ID | 0x62 |
| m1.1h | 0xA716-0xA716 | 1B | Map 1/D1 Separator | Always 0x00 |
| m1.1h | 0xA717-0xA71A | 4B | Map 1/D1 Teleport 1 - Location | BIG-ENDIAN, YY YY BRow TRow|
| m1.1h | 0xA71B-0xA71E | 4B | Map 1/D1 Teleport 1 - Padding | 00 00 00 00 |
| m1.1h | 0xA71F-0xA722 | 4B | Map 1/D1 Teleport 2 - Location | BIG-ENDIAN, YY YY BRow TRow|
| m1.1h | 0xA723-0xA726 | 4B | Map 1/D1 Teleport 2 - Padding | 00 00 00 00 |
| m1.1h | 0xA727-0xA72A | 4B | Map 1/D1 Teleport 3 - Location | BIG-ENDIAN, YY YY BRow TRow|
| m1.1h | 0xA72B-0xA72E | 4B | Map 1/D1 Teleport 3 - Padding | 00 00 00 00 |
| m1.1h | 0xA72F-0xA732 | 4B | Map 1/D1 Teleport 4 - Location | BIG-ENDIAN, YY YY BRow TRow|
| m1.1h | 0xA733-0xA736 | 4B | Map 1/D1 Teleport 4 - Padding | 00 00 00 00 |
| m1.1h | 0xA737-0xA73A | 4B | Map 1/D1 Teleport 5 - Location | BIG-ENDIAN, YY YY BRow TRow|
| m1.1h | 0xA73B-0xA73E | 4B | Map 1/D1 Teleport 5 - Padding | 00 00 00 00 |
| m1.1h | 0xA73F-0xA742 | 4B | Map 1/D1 Teleport 6 - Location | BIG-ENDIAN, YY YY BRow TRow|
| m1.1h | 0xA743-0xA746 | 4B | Map 1/D1 Teleport 6 - Padding | 00 00 00 00 |
| m1.1h | 0xA747-0xA749 | 3B | Map 1/D1 Spawner 1 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA74A-0xA74A | 1B | Map 1/D1 Spawner 1 - Padding | Always 0x00 |
| m1.1h | 0xA74B-0xA74D | 3B | Map 1/D1 Spawner 2 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA74E-0xA74E | 1B | Map 1/D1 Spawner 2 - Padding | Always 0x00 |
| m1.1h | 0xA74F-0xA751 | 3B | Map 1/D1 Spawner 3 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA752-0xA752 | 1B | Map 1/D1 Spawner 3 - Padding | Always 0x00 |
| m1.1h | 0xA753-0xA755 | 3B | Map 1/D1 Spawner 4 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA756-0xA756 | 1B | Map 1/D1 Spawner 4 - Padding | Always 0x00 |
| m1.1h | 0xA757-0xA759 | 3B | Map 1/D1 Spawner 5 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA75A-0xA74A | 1B | Map 1/D1 Spawner 5 - Padding | Always 0x00 |
| m1.1h | 0xA75B-0xA75D | 3B | Map 1/D1 Spawner 6 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA75E-0xA75E | 1B | Map 1/D1 Spawner 6 - Padding | Always 0x00 |
| m1.1h | 0xA75F-0xA761 | 3B | Map 1/D1 Spawner 7 - Location | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA762-0xA762 | 1B | Map 1/D1 Spawner 7 - Padding | Always 0x00 |
| m1.1h | 0xA763-0xA765 | 3B | Map 1/D1 Separator | 00 00 00 |
| m1.1h | 0xA766-0xA767 | 2B | Map 2/D1 Logical Map Pointer | BIG-ENDIAN, 0x9700 |
| m1.1h | 0xA768-0xA769 | 2B | Map 2/D1 Visual Map Pointer | BIG-ENDIAN, 0x9300 |
| m1.1h | 0xA76A-0xA76A | 1B | Map 2/D1 Enemy Spawn Rate | 0x05-0x08 range |
| m1.1h | 0xA76B-0xA76B | 1B | Map 2/D1 Time Limit | Seconds, e.g., 0x5A=90s |
| m1.1h | 0xA76C-0xA770 | 5B | Map 2/D1 Unknown Data | Unknown purpose |
| m1.1h | 0xA771-0xA773 | 3B | Map 2/D1 Player Start | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA774-0xA776 | 3B | Map 2/D1 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA777-0xA779 | 3B | Map 2/D1 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA77A-0xA77C | 3B | Map 2/D1 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA77D-0xA77D | 1B | Map 2/D1 Map Width | (Value + 0x01) Screens |
| m1.1h | 0xA77E-0xA85D | 224B | Map 2/D1 Items Block | See M1/D1 For Breakout |
| m1.1h | 0xA85E-0xA85E | 1B | Map 2/D1 Separator | Always 0x00 |
| m1.1h | 0xA85F-0xA88E | 48B | Map 2/D1 Teleports Block | See M1/D1 For Breakout |
| m1.1h | 0xA88F-0xA8AD | 31B | Map 2/D1 Spawners Block | See M1/D1 For Breakout |
| m1.1h | 0xA8AE-0xA8AF | 2B | Map 3/D1 Logical Map Pointer | BIG-ENDIAN, 0x9000 |
| m1.1h | 0xA8B0-0xA8B1 | 2B | Map 3/D1 Visual Map Pointer | BIG-ENDIAN, 0x9600 |
| m1.1h | 0xA8B2-0xA8B2 | 1B | Map 3/D1 Enemy Spawn Rate | 0x05-0x08 range |
| m1.1h | 0xA8B3-0xA8B3 | 1B | Map 3/D1 Time Limit | Seconds, e.g., 0x8C=140s |
| m1.1h | 0xA8B4-0xA8B8 | 5B | Map 3/D1 Unknown Data | Unknown purpose |
| m1.1h | 0xA8B9-0xA8BB | 3B | Map 3/D1 Player Start | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA8BC-0xA8BE | 3B | Map 3/D1 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA8BF-0xA8C1 | 3B | Map 3/D1 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA8C2-0xA8C4 | 3B | Map 3/D1 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xA8C5-0xA8C5 | 1B | Map 3/D1 Map Width | (Value + 0x01) Screens |
| m1.1h | 0xA8C6-0xA9A5 | 224B | Map 3/D1 Items Block | See M1/D1 For Breakout |
| m1.1h | 0xA9A6-0xA9A6 | 1B | Map 3/D1 Separator | Always 0x00 |
| m1.1h | 0xA9A7-0xA9D6 | 48B | Map 3/D1 Teleports Block | See M1/D1 For Breakout |
| m1.1h | 0xA9D7-0xA9F5 | 31B | Map 3/D1 Spawners Block | See M1/D1 For Breakout |
| m1.1h | 0xA9F6-0xA9F7 | 2B | Map 4/D1 Logical Map Pointer | BIG-ENDIAN, 0x9700 |
| m1.1h | 0xA9F8-0xA9F9 | 2B | Map 4/D1 Visual Map Pointer | BIG-ENDIAN, 0x9900 |
| m1.1h | 0xA9FA-0xA9FA | 1B | Map 4/D1 Enemy Spawn Rate | 0x05-0x08 range |
| m1.1h | 0xA9FB-0xA9FB | 1B | Map 4/D1 Time Limit | Seconds, e.g., 0x8C=140s |
| m1.1h | 0xA9FC-0xAA00 | 5B | Map 4/D1 Unknown Data | Unknown purpose |
| m1.1h | 0xAA01-0xAA03 | 3B | Map 4/D1 Player Start | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAA04-0xAA06 | 3B | Map 4/D1 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAA07-0xAA09 | 3B | Map 4/D1 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAA0A-0xAA0C | 3B | Map 4/D1 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAA0D-0xAA0D | 1B | Map 4/D1 Map Width | (Value + 0x01) Screens |
| m1.1h | 0xAA0E-0xAAED | 224B | Map 4/D1 Items Block | See M1/D1 For Breakout |
| m1.1h | 0xAAEE-0xAAEE | 1B | Map 4/D1 Separator | Always 0x00 |
| m1.1h | 0xAAEF-0xAB1E | 48B | Map 4/D1 Teleports Block | See M1/D1 For Breakout |
| m1.1h | 0xAB1F-0xAB3D | 31B | Map 4/D1 Spawners Block | See M1/D1 For Breakout |
| m1.1h | 0xAB3E-0xAB3F | 2B | Map 1/D2 Logical Map Pointer | BIG-ENDIAN, 0x9000 |
| m1.1h | 0xAB40-0xAB41 | 2B | Map 1/D2 Visual Map Pointer | BIG-ENDIAN, 0x9000 |
| m1.1h | 0xAB42-0xAB42 | 1B | Map 1/D2 Enemy Spawn Rate | 0x05-0x08 range |
| m1.1h | 0xAB43-0xAB43 | 1B | Map 1/D2 Time Limit | Seconds, e.g., 0x3C=60s |
| m1.1h | 0xAB44-0xAB48 | 5B | Map 1/D2 Unknown Data | Unknown purpose |
| m1.1h | 0xAB49-0xAB4B | 3B | Map 1/D2 Player Start | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAB4C-0xAB4E | 3B | Map 1/D2 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAB4F-0xAB51 | 3B | Map 1/D2 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAB52-0xAB54 | 3B | Map 1/D2 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAB55-0xAB55 | 1B | Map 1/D2 Map Width | (Value + 0x01) Screens |
| m1.1h | 0xAB56-0xAC35 | 224B | Map 1/D2 Items Block | See M1/D1 For Breakout |
| m1.1h | 0xAC36-0xAC36 | 1B | Map 1/D2 Separator | Always 0x00 |
| m1.1h | 0xAC37-0xAC66 | 48B | Map 1/D2 Teleports Block | See M1/D1 For Breakout |
| m1.1h | 0xAC67-0xAC85 | 31B | Map 1/D2 Spawners Block | See M1/D1 For Breakout |
| m1.1h | 0xAC86-0xAC87 | 2B | Map 2/D2 Logical Map Pointer | BIG-ENDIAN, 0x9700 |
| m1.1h | 0xAC88-0xAC89 | 2B | Map 2/D2 Visual Map Pointer | BIG-ENDIAN, 0x9300 |
| m1.1h | 0xAC8A-0xAC8A | 1B | Map 2/D2 Enemy Spawn Rate | 0x05-0x08 range |
| m1.1h | 0xAC8B-0xAC8B | 1B | Map 2/D2 Time Limit | Seconds, e.g., 0x5A=90s |
| m1.1h | 0xAC8C-0xAC90 | 5B | Map 2/D2 Unknown Data | Unknown purpose |
| m1.1h | 0xAC91-0xAC93 | 3B | Map 2/D2 Player Start | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAC94-0xAC96 | 3B | Map 2/D2 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAC97-0xAC99 | 3B | Map 2/D2 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAC9A-0xAC9C | 3B | Map 2/D2 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAC9D-0xAC9D | 1B | Map 2/D2 Map Width | (Value + 0x01) Screens |
| m1.1h | 0xAC9E-0xAD7D | 224B | Map 2/D2 Items Block | See M1/D1 For Breakout |
| m1.1h | 0xAD7E-0xAD7E | 1B | Map 2/D2 Separator | Always 0x00 |
| m1.1h | 0xAD7F-0xADAE | 48B | Map 2/D2 Teleports Block | See M1/D1 For Breakout |
| m1.1h | 0xADAF-0xADCD | 31B | Map 2/D2 Spawners Block | See M1/D1 For Breakout |
| m1.1h | 0xADCE-0xADCF | 2B | Map 3/D2 Logical Map Pointer | BIG-ENDIAN, 0x9000 |
| m1.1h | 0xADD0-0xADD1 | 2B | Map 3/D2 Visual Map Pointer | BIG-ENDIAN, 0x9600 |
| m1.1h | 0xADD2-0xADD2 | 1B | Map 3/D2 Enemy Spawn Rate | 0x05-0x08 range |
| m1.1h | 0xADD3-0xADD3 | 1B | Map 3/D2 Time Limit | Seconds, e.g., 0x8C=140s |
| m1.1h | 0xADD4-0xADD8 | 5B | Map 3/D2 Unknown Data | Unknown purpose |
| m1.1h | 0xADD9-0xADDB | 3B | Map 3/D2 Player Start | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xADDC-0xADDE | 3B | Map 3/D2 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xADDF-0xADE1 | 3B | Map 3/D2 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xADE2-0xADE4 | 3B | Map 3/D2 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xADE5-0xADE5 | 1B | Map 3/D2 Map Width | (Value + 0x01) Screens |
| m1.1h | 0xADE6-0xAEC5 | 224B | Map 3/D2 Items Block | See M1/D1 For Breakout |
| m1.1h | 0xAEC6-0xAEC6 | 1B | Map 3/D2 Separator | Always 0x00 |
| m1.1h | 0xAEC7-0xAEF6 | 48B | Map 3/D2 Teleports Block | See M1/D1 For Breakout |
| m1.1h | 0xAEF7-0xAF15 | 31B | Map 3/D2 Spawners Block | See M1/D1 For Breakout |
| m1.1h | 0xAF16-0xAF17 | 2B | Map 4/D2 Logical Map Pointer | BIG-ENDIAN, 0x9700 |
| m1.1h | 0xAF18-0xAF19 | 2B | Map 4/D2 Visual Map Pointer | BIG-ENDIAN, 0x9900 |
| m1.1h | 0xAF1A-0xAF1A | 1B | Map 4/D2 Enemy Spawn Rate | 0x05-0x08 range |
| m1.1h | 0xAF1B-0xAF1B | 1B | Map 4/D2 Time Limit | Seconds, e.g., 0x8C=140s |
| m1.1h | 0xAF1C-0xAF20 | 5B | Map 4/D2 Unknown Data | Unknown purpose |
| m1.1h | 0xAF21-0xAF23 | 3B | Map 4/D2 Player Start | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAF24-0xAF26 | 3B | Map 4/D2 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAF27-0xAF29 | 3B | Map 4/D2 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAF2A-0xAF2C | 3B | Map 4/D2 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m1.1h | 0xAF2D-0xAF2D | 1B | Map 4/D2 Map Width | (Value + 0x01) Screens |
| m1.1h | 0xAF2E-0xAFFF | 210B | Map 4/D2 Items Block | See M1/D1 For Breakout (P1)|
| m2.2h | 0xB000-0xB00D | 14B | Map 4/D2 Items Block | See M1/D1 For Breakout (P2)|
| m2.2h | 0xB00E-0xB00E | 1B | Map 4/D2 Separator | Always 0x00 |
| m2.2h | 0xB00F-0xB03E | 48B | Map 4/D2 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xB03F-0xB05D | 31B | Map 4/D2 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xB05E-0xB05F | 2B | Map 1/D3 Logical Map Pointer | BIG-ENDIAN, 0x9000 |
| m2.2h | 0xB060-0xB061 | 2B | Map 1/D3 Visual Map Pointer | BIG-ENDIAN, 0x9000 |
| m2.2h | 0xB062-0xB062 | 1B | Map 1/D3 Enemy Spawn Rate | 0x05-0x08 range |
| m2.2h | 0xB063-0xB063 | 1B | Map 1/D3 Time Limit | Seconds, e.g., 0x3C=60s |
| m2.2h | 0xB064-0xB068 | 5B | Map 1/D3 Unknown Data | Unknown purpose |
| m2.2h | 0xB069-0xB06B | 3B | Map 1/D3 Player Start | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB06C-0xB06E | 3B | Map 1/D3 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB06F-0xB071 | 3B | Map 1/D3 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB072-0xB074 | 3B | Map 1/D3 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB075-0xB075 | 1B | Map 1/D3 Map Width | (Value + 0x01) Screens |
| m2.2h | 0xB076-0xB155 | 224B | Map 1/D3 Items Block | See M1/D1 For Breakout |
| m2.2h | 0xB156-0xB156 | 1B | Map 1/D3 Separator | Always 0x00 |
| m2.2h | 0xB157-0xB186 | 48B | Map 1/D3 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xB187-0xB1A5 | 31B | Map 1/D3 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xB1A6-0xB1A7 | 2B | Map 2/D3 Logical Map Pointer | BIG-ENDIAN, 0x9700 |
| m2.2h | 0xB1A8-0xB1A9 | 2B | Map 2/D3 Visual Map Pointer | BIG-ENDIAN, 0x9300 |
| m2.2h | 0xB1AA-0xB1AA | 1B | Map 2/D3 Enemy Spawn Rate | 0x05-0x08 range |
| m2.2h | 0xB1AB-0xB1AB | 1B | Map 2/D3 Time Limit | Seconds, e.g., 0x5A=90s |
| m2.2h | 0xB1AC-0xB1B0 | 5B | Map 2/D3 Unknown Data | Unknown purpose |
| m2.2h | 0xB1B1-0xB1B3 | 3B | Map 2/D3 Player Start | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB1B4-0xB1B6 | 3B | Map 2/D3 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB1B7-0xB1B9 | 3B | Map 2/D3 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB1BA-0xB1BC | 3B | Map 2/D3 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB1BD-0xB1BD | 1B | Map 2/D3 Map Width | (Value + 0x01) Screens |
| m2.2h | 0xB1BE-0xB29D | 224B | Map 2/D3 Items Block | See M1/D1 For Breakout |
| m2.2h | 0xB29E-0xB29E | 1B | Map 2/D3 Separator | Always 0x00 |
| m2.2h | 0xB29F-0xB2CE | 48B | Map 2/D3 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xB2CF-0xB2ED | 31B | Map 2/D3 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xB2EE-0xB2EF | 2B | Map 3/D3 Logical Map Pointer | BIG-ENDIAN, 0x9000 |
| m2.2h | 0xB2F0-0xB2F1 | 2B | Map 3/D3 Visual Map Pointer | BIG-ENDIAN, 0x9600 |
| m2.2h | 0xB2F2-0xB2F2 | 1B | Map 3/D3 Enemy Spawn Rate | 0x05-0x08 range |
| m2.2h | 0xB2F3-0xB2F3 | 1B | Map 3/D3 Time Limit | Seconds, e.g., 0x8C=140s |
| m2.2h | 0xB2F4-0xB2F8 | 5B | Map 3/D3 Unknown Data | Unknown purpose |
| m2.2h | 0xB2F9-0xB2FB | 3B | Map 3/D3 Player Start | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB2FC-0xB2FE | 3B | Map 3/D3 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB2FF-0xB301 | 3B | Map 3/D3 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB302-0xB304 | 3B | Map 3/D3 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB305-0xB305 | 1B | Map 3/D3 Map Width | (Value + 0x01) Screens |
| m2.2h | 0xB306-0xB3E5 | 224B | Map 3/D3 Items Block | See M1/D1 For Breakout |
| m2.2h | 0xB3E6-0xB3E6 | 1B | Map 3/D3 Separator | Always 0x00 |
| m2.2h | 0xB3E7-0xB416 | 48B | Map 3/D3 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xB417-0xB435 | 31B | Map 3/D3 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xB436-0xB437 | 2B | Map 4/D3 Logical Map Pointer | BIG-ENDIAN, 0x9700 |
| m2.2h | 0xB438-0xB439 | 2B | Map 4/D3 Visual Map Pointer | BIG-ENDIAN, 0x9900 |
| m2.2h | 0xB43A-0xB43A | 1B | Map 4/D3 Enemy Spawn Rate | 0x05-0x08 range |
| m2.2h | 0xB43B-0xB43B | 1B | Map 4/D3 Time Limit | Seconds, e.g., 0x8C=140s |
| m2.2h | 0xB43C-0xB440 | 5B | Map 4/D3 Unknown Data | Unknown purpose |
| m2.2h | 0xB441-0xB443 | 3B | Map 4/D3 Player Start | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB444-0xB446 | 3B | Map 4/D3 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB447-0xB449 | 3B | Map 4/D3 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB44A-0xB44C | 3B | Map 4/D3 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB44D-0xB44D | 1B | Map 4/D3 Map Width | (Value + 0x01) Screens |
| m2.2h | 0xB44E-0xB52D | 224B | Map 4/D3 Items Block | See M1/D1 For Breakout |
| m2.2h | 0xB52E-0xB52E | 1B | Map 4/D3 Separator | Always 0x00 |
| m2.2h | 0xB52F-0xB55E | 48B | Map 4/D3 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xB55F-0xB57D | 31B | Map 4/D3 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xB57E-0xB57F | 2B | Map 1/D4 Logical Map Pointer | BIG-ENDIAN, 0x9000 |
| m2.2h | 0xB580-0xB581 | 2B | Map 1/D4 Visual Map Pointer | BIG-ENDIAN, 0x9000 |
| m2.2h | 0xB582-0xB582 | 1B | Map 1/D4 Enemy Spawn Rate | 0x05-0x08 range |
| m2.2h | 0xB583-0xB583 | 1B | Map 1/D4 Time Limit | Seconds, e.g., 0x3C=60s |
| m2.2h | 0xB584-0xB588 | 5B | Map 1/D4 Unknown Data | Unknown purpose |
| m2.2h | 0xB589-0xB58B | 3B | Map 1/D4 Player Start | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB58C-0xB58E | 3B | Map 1/D4 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB58F-0xB591 | 3B | Map 1/D4 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB592-0xB594 | 3B | Map 1/D4 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB595-0xB595 | 1B | Map 1/D4 Map Width | (Value + 0x01) Screens |
| m2.2h | 0xB596-0xB675 | 224B | Map 1/D4 Items Block | See M1/D1 For Breakout |
| m2.2h | 0xB676-0xB676 | 1B | Map 1/D4 Separator | Always 0x00 |
| m2.2h | 0xB677-0xB6A6 | 48B | Map 1/D4 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xB6A7-0xB6C5 | 31B | Map 1/D4 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xB6C6-0xB6C7 | 2B | Map 2/D4 Logical Map Pointer | BIG-ENDIAN, 0x9700 |
| m2.2h | 0xB6C8-0xB6C9 | 2B | Map 2/D4 Visual Map Pointer | BIG-ENDIAN, 0x9300 |
| m2.2h | 0xB6CA-0xB6CA | 1B | Map 2/D4 Enemy Spawn Rate | 0x05-0x08 range |
| m2.2h | 0xB6CB-0xB6CB | 1B | Map 2/D4 Time Limit | Seconds, e.g., 0x5A=90s |
| m2.2h | 0xB6CC-0xB6D0 | 5B | Map 2/D4 Unknown Data | Unknown purpose |
| m2.2h | 0xB6D1-0xB6D3 | 3B | Map 2/D4 Player Start | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB6D4-0xB6D6 | 3B | Map 2/D4 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB6D7-0xB6D9 | 3B | Map 2/D4 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB6DA-0xB6DC | 3B | Map 2/D4 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB6DD-0xB6DD | 1B | Map 2/D4 Map Width | (Value + 0x01) Screens |
| m2.2h | 0xB6DE-0xB7BD | 224B | Map 2/D4 Items Block | See M1/D1 For Breakout |
| m2.2h | 0xB7BE-0xB7BE | 1B | Map 2/D4 Separator | Always 0x00 |
| m2.2h | 0xB7BF-0xB7EE | 48B | Map 2/D4 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xB7EF-0xB80D | 31B | Map 2/D4 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xB80E-0xB80F | 2B | Map 3/D4 Logical Map Pointer | BIG-ENDIAN, 0x9000 |
| m2.2h | 0xB810-0xB811 | 2B | Map 3/D4 Visual Map Pointer | BIG-ENDIAN, 0x9600 |
| m2.2h | 0xB812-0xB812 | 1B | Map 3/D4 Enemy Spawn Rate | 0x05-0x08 range |
| m2.2h | 0xB813-0xB813 | 1B | Map 3/D4 Time Limit | Seconds, e.g., 0x8C=140s |
| m2.2h | 0xB814-0xB818 | 5B | Map 3/D4 Unknown Data | Unknown purpose |
| m2.2h | 0xB819-0xB81B | 3B | Map 3/D4 Player Start | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB81C-0xB81E | 3B | Map 3/D4 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB81F-0xB821 | 3B | Map 3/D4 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB822-0xB824 | 3B | Map 3/D4 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB825-0xB825 | 1B | Map 3/D4 Map Width | (Value + 0x01) Screens |
| m2.2h | 0xB826-0xB905 | 224B | Map 3/D4 Items Block | See M1/D1 For Breakout |
| m2.2h | 0xB906-0xB906 | 1B | Map 3/D4 Separator | Always 0x00 |
| m2.2h | 0xB907-0xB936 | 48B | Map 3/D4 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xB937-0xB955 | 31B | Map 3/D4 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xB956-0xB957 | 2B | Map 4/D4 Logical Map Pointer | BIG-ENDIAN, 0x9700 |
| m2.2h | 0xB958-0xB959 | 2B | Map 4/D4 Visual Map Pointer | BIG-ENDIAN, 0x9900 |
| m2.2h | 0xB95A-0xB95A | 1B | Map 4/D4 Enemy Spawn Rate | 0x05-0x08 range |
| m2.2h | 0xB95B-0xB95B | 1B | Map 4/D4 Time Limit | Seconds, e.g., 0x8C=140s |
| m2.2h | 0xB95C-0xB960 | 5B | Map 4/D4 Unknown Data | Unknown purpose |
| m2.2h | 0xB961-0xB963 | 3B | Map 4/D4 Player Start | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB964-0xB966 | 3B | Map 4/D4 Respawn Point 1 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB967-0xB969 | 3B | Map 4/D4 Respawn Point 2 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB96A-0xB96C | 3B | Map 4/D4 Respawn Point 3 | BIG-ENDIAN, YY YY XX |
| m2.2h | 0xB96D-0xB96D | 1B | Map 4/D4 Map Width | (Value + 0x01) Screens |
| m2.2h | 0xB96E-0xBA4D | 224B | Map 4/D4 Items Block | See M1/D1 For Breakout |
| m2.2h | 0xBA4E-0xBA4E | 1B | Map 4/D4 Separator | Always 0x00 |
| m2.2h | 0xBA4F-0xBA7E | 48B | Map 4/D4 Teleports Block | See M1/D1 For Breakout |
| m2.2h | 0xBA7F-0xBA9D | 31B | Map 4/D4 Spawners Block | See M1/D1 For Breakout |
| m2.2h | 0xBA9E-0xBCF6 | 601B | Unknown (Code/Data) | Unknown |
| m2.2h | 0xBCF7-0xBD05 | 15B | Player Animation - Walk Down | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBD06-0xBD14 | 15B | Player Animation - Walk Right | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBD15-0xBD23 | 15B | Player Animation - Walk Left | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBD24-0xBD32 | 15B | Player Animation - Up + Key | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBD33-0xBD41 | 15B | Player Animation - Down + Key | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBD42-0xBD50 | 15B | Player Animation - Right + Key | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBD51-0xBD5F | 15B | Player Animation - Left + Key | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBD60-0xBD6E | 15B | Poison Animation - Unused | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBD6F-0xBDA7 | 57B | Unknown (Code/Data) | Unknown |
| m2.2h | 0xBDA8-0xBDA9 | 2B | Unknown Pointer | BD B2 |
| m2.2h | 0xBDAA-0xBDAB | 2B | Unknown Pointer | BE 02 |
| m2.2h | 0xBDAC-0xBDAD | 2B | Unknown Pointer | BE 52 |
| m2.2h | 0xBDAE-0xBDAF | 2B | Unknown Pointer | BE A9 |
| m2.2h | 0xBDB0-0xBDB1 | 2B | Unknown Pointer | BE A9 |
| m2.2h | 0xBDB2-0xBE01 | 80B | Unknown Data | Unknown |
| m2.2h | 0xBE02-0xBE51 | 80B | Unknown Data | Unknown |
| m2.2h | 0xBE52-0xBEA8 | 87B | Unknown Data | Unknown |
| m2.2h | 0xBEA9-0xBEA9 | 1B | Unknown Data | Unknown |
| m2.2h | 0xBEAA-0xBEB8 | 15B | Player Animation - Walk Up | 6 Tiles, 1 Frame per Tile |
| m2.2h | 0xBEB9-0xBFFF | 327B | Unknown (Code/Data) | Unknown |
| 3j.3h | 0xC000-0xC107 | 264B | Unknown (Code/Data) | Unknown |
| 3j.3h | 0xC108-0xC112 | 11B | Enemy Animation - Snake Left | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC113-0xC11D | 11B | Enemy Animation - Snake Right | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC11E-0xC128 | 11B | Enemy Animation - Vulture Right | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC129-0xC133 | 11B | Enemy Animation - Vulture Left | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC134-0xC144 | 17B | Enemy Animation - Bat | 7 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC145-0xC14F | 11B | Enemy Animation - Dragon Left | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC150-0xC15A | 11B | Enemy Animation - Dragon Right | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC15B-0xC165 | 11B | Enemy Animation - Gryphon Right | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC166-0xC170 | 11B | Enemy Animation - Gryphon Left | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC171-0xC17B | 11B | Enemy Animation - Glaive | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC17C-0xC18A | 15B | Enemy Animation - Poof Cloud | 6 Tiles, 3 Frame per Tile |
| 3j.3h | 0xC18B-0xC195 | 11B | Enemy Animation - Snake Left | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC196-0xC1A0 | 11B | Enemy Animation - Snake Right | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC1A1-0xC1A7 | 7B | Enemy Animation - Explosion 1 | 2 Tiles, 2 Frame per Tile |
| 3j.3h | 0xC1A8-0xC1BA | 19B | Enemy Animation - Explosion 2 | 8 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC1BB-0xC1C5 | 11B | Enemy Animation - Vulture Right | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC1C6-0xC1D0 | 11B | Enemy Animation - Vulture Left | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC1D1-0xC1E1 | 17B | Enemy Animation - Bat | 7 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC1E2-0xC1F2 | 17B | Enemy Animation - Bat | 7 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC1F3-0xC1FD | 11B | Enemy Animation - Snake Right | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC1FE-0xC208 | 11B | Enemy Animation - Snake Left | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC209-0xC213 | 11B | Player Animation - Walk Right | 4 Tiles, 1 Frame per Tile |
| 3j.3h | 0xC214-0xC222 | 15B | Unused Animation | 6 Tiles, 2 Frame per Tile |
| 3j.3h | 0xC223-0xC8ED | 1739B | Unknown (Code/Data) | Unknown |
| 3j.3h | 0xC8EE-0xC8EE | 1B | Reference Table | Unknown purpose |
| 3j.3h | 0xC8EF-0xCE24 | 1658B | Unknown (Code/Data) | Unknown |
| 3j.3h | 0xCE25-0xCE26 | 2B | Copyright Checksum | Konami: 14A3 / Stern: 1A4C |
| 3j.3h | 0xCE27-0xCFFF | 217B | Unknown (Code/Data) | Unknown |
| m4.4h | 0xD000-0xD788 | 1928B | Unknown (Code/Data) | Unknown |
| m4.4h | 0xD789-0xD7B8 | 48B | Monster Point Values Array | (Address - 3 Bytes) |
| m4.4h | 0xD7B9-0xD7BB | 3B | Snake Kill Value | 00 00 20 ( 20 Points) |
| m4.4h | 0xD7BC-0xD7BE | 3B | Vulture Kill Value | 00 00 40 ( 40 Points) |
| m4.4h | 0xD7BF-0xD7C1 | 3B | Bat Kill Value | 00 00 60 ( 60 Points) |
| m4.4h | 0xD7C2-0xD7C4 | 3B | Value 04 | 00 00 40 |
| m4.4h | 0xD7C5-0xD7C7 | 3B | Value 05 | 00 00 50 |
| m4.4h | 0xD7C8-0xD7CA | 3B | Value 06 | 00 01 00 |
| m4.4h | 0xD7CB-0xD7CD | 3B | Value 07 | 00 02 00 |
| m4.4h | 0xD7CE-0xD7D0 | 3B | Key Pickup Value | 00 05 00 ( 500 Points) |
| m4.4h | 0xD7D1-0xD7D3 | 3B | Value 09 | 00 04 00 |
| m4.4h | 0xD7D4-0xD7D6 | 3B | Unlock Keyhole | 00 10 00 |
| m4.4h | 0xD7D7-0xD7D9 | 3B | First Treasure Pickup Value | 00 05 00 ( 500 Points) |
| m4.4h | 0xD7DA-0xD7DC | 3B | Second Treasure Pickup Value | 00 10 00 (1000 Points) |
| m4.4h | 0xD7DD-0xD7DF | 3B | Third Treasure Pickup Value | 00 15 00 (1500 Points) |
| m4.4h | 0xD7E0-0xD7E2 | 3B | Fourth Treasure Pickup Value | 00 20 00 (2000 Points) |
| m4.4h | 0xD7E3-0xD7E5 | 3B | Fifth Treasure Pickup Value | 00 30 00 (3000 Points) |
| m4.4h | 0xD7E6-0xD7E8 | 3B | Sixth Treasure Pickup Value | 00 40 00 (4000 Points) |
| m4.4h | 0xD7E9-0xD7EB | 3B | Value 17 | 00 40 00 |
| m4.4h | 0xD7EC-0xD7EE | 3B | Value 18 | 00 50 00 |
| m4.4h | 0xD7EF-0xD7F1 | 3B | Value 19 | 00 60 00 |
| m4.4h | 0xD7F2-0xD7F4 | 3B | Value 20 | 00 70 00 |
| m4.4h | 0xD7F5-0xD7F7 | 3B | Value 21 | 00 80 00 |
| m4.4h | 0xD7F8-0xD7FA | 3B | Value 22 | 00 90 00 |
| m4.4h | 0xD7FB-0xD7FD | 3B | Value 23 | 00 99 00 |
| m4.4h | 0xD7FE-0xD800 | 3B | Value 24 | 11 00 00 |
| m4.4h | 0xD801-0xD803 | 3B | Likely Invalid Pointer | 0D 22 27 |
| m4.4h | 0xD804-0xD978 | 372B | Unknown (Code/Data) | Unknown |
| m4.4h | 0xD979-0xD980 | 8B | Map Level Block Range | Pointers to map data |
| m4.4h | 0xD981-0xD9A0 | 32B | Map Level Data | 8B per map |
| m4.4h | 0xD9A1-0xDFFF | 1631B | Unknown (Code/Data) | Unknown |
| m5.5h | 0xE000-0xE55F | 1376B | Unknown (Code/Data) | Unknown |
| m5.5h | 0xE560-0xE560 | 1B | Unknown Table | Unknown |
| m5.5h | 0xE561-0xEFFF | 2719B | Unknown (Code/Data) | Unkonwn |
| j6.6h | 0x0000-0x001F | 32B | Font Graphic : 0 | 8×8px, 4bpp |
| j6.6h | 0x0020-0x003F | 32B | Font Graphic : 1 | 8×8px, 4bpp |
| j6.6h | 0x0040-0x005F | 32B | Font Graphic : 2 | 8×8px, 4bpp |
| j6.6h | 0x0060-0x007F | 32B | Font Graphic : 3 | 8×8px, 4bpp |
| j6.6h | 0x0080-0x009F | 32B | Font Graphic : 4 | 8×8px, 4bpp |
| j6.6h | 0x00A0-0x00BF | 32B | Font Graphic : 5 | 8×8px, 4bpp |
| j6.6h | 0x00C0-0x00DF | 32B | Font Graphic : 6 | 8×8px, 4bpp |
| j6.6h | 0x00E0-0x00FF | 32B | Font Graphic : 7 | 8×8px, 4bpp |
| j6.6h | 0x0100-0x011F | 32B | Font Graphic : 8 | 8×8px, 4bpp |
| j6.6h | 0x0120-0x013F | 32B | Font Graphic : 9 | 8×8px, 4bpp |
| j6.6h | 0x0140-0x015F | 32B | Font Graphic : Copyright Symbol | 8×8px, 4bpp |
| j6.6h | 0x0160-0x017F | 32B | Font Graphic : Box | 8×8px, 4bpp |
| j6.6h | 0x0180-0x019F | 32B | Font Graphic : Period (.) | 8×8px, 4bpp |
| j6.6h | 0x01A0-0x01BF | 32B | Font Graphic : Exclamation (!) | 8×8px, 4bpp |
| j6.6h | 0x01C0-0x01DF | 32B | Font Graphic : Question Mark (?)| 8×8px, 4bpp |
| j6.6h | 0x01E0-0x01FF | 32B | Font Graphic : Musical Note | 8×8px, 4bpp |
| j6.6h | 0x0200-0x021F | 32B | Font Graphic : Blank Space ( ) | 8×8px, 4bpp |
| j6.6h | 0x0220-0x023F | 32B | Font Graphic : A | 8×8px, 4bpp |
| j6.6h | 0x0240-0x025F | 32B | Font Graphic : B | 8×8px, 4bpp |
| j6.6h | 0x0260-0x027F | 32B | Font Graphic : C | 8×8px, 4bpp |
| j6.6h | 0x0280-0x029F | 32B | Font Graphic : D | 8×8px, 4bpp |
| j6.6h | 0x02A0-0x02BF | 32B | Font Graphic : E | 8×8px, 4bpp |
| j6.6h | 0x02C0-0x02DF | 32B | Font Graphic : F | 8×8px, 4bpp |
| j6.6h | 0x02E0-0x02FF | 32B | Font Graphic : G | 8×8px, 4bpp |
| j6.6h | 0x0300-0x031F | 32B | Font Graphic : H | 8×8px, 4bpp |
| j6.6h | 0x0320-0x033F | 32B | Font Graphic : I | 8×8px, 4bpp |
| j6.6h | 0x0340-0x035F | 32B | Font Graphic : J | 8×8px, 4bpp |
| j6.6h | 0x0360-0x037F | 32B | Font Graphic : K | 8×8px, 4bpp |
| j6.6h | 0x0380-0x039F | 32B | Font Graphic : L | 8×8px, 4bpp |
| j6.6h | 0x03A0-0x03BF | 32B | Font Graphic : M | 8×8px, 4bpp |
| j6.6h | 0x03C0-0x03DF | 32B | Font Graphic : N | 8×8px, 4bpp |
| j6.6h | 0x03E0-0x03FF | 32B | Font Graphic : O | 8×8px, 4bpp |
| j6.6h | 0x0400-0x041F | 32B | Font Graphic : P | 8×8px, 4bpp |
| j6.6h | 0x0420-0x043F | 32B | Font Graphic : Q | 8×8px, 4bpp |
| j6.6h | 0x0440-0x045F | 32B | Font Graphic : R | 8×8px, 4bpp |
| j6.6h | 0x0460-0x047F | 32B | Font Graphic : S | 8×8px, 4bpp |
| j6.6h | 0x0480-0x049F | 32B | Font Graphic : T | 8×8px, 4bpp |
| j6.6h | 0x04A0-0x04BF | 32B | Font Graphic : U | 8×8px, 4bpp |
| j6.6h | 0x04C0-0x04DF | 32B | Font Graphic : V | 8×8px, 4bpp |
| j6.6h | 0x04E0-0x04FF | 32B | Font Graphic : W | 8×8px, 4bpp |
| j6.6h | 0x0500-0x051F | 32B | Font Graphic : X | 8×8px, 4bpp |
| j6.6h | 0x0520-0x053F | 32B | Font Graphic : Y | 8×8px, 4bpp |
| j6.6h | 0x0540-0x055F | 32B | Font Graphic : Z | 8×8px, 4bpp |
| j6.6h | 0xF560-0xF59F | 64B | Player Weapon/Bullet Sprite | Needs Decode |
| j6.6h | 0xF5A0-0xF5BF | 32B | Player Count Sprite | 8x8px, 4bpp, interleaved |
| j6.6h | 0xF5C0-0xF8EF | 815B | Copyright Graphic | 102x16px,4bpp, interleaved |
| j6.6h | 0xF8F0-0xFB5F | 624B | Timer Banner Graphic | 32x39px, 4bpp, interleaved |
| j6.6h | 0xFB60-0xFBDF | 128B | Smart Bomb/Genie Lamp Sprite | 16x14px, 4bpp, interleaved |
| j6.6h | 0xFBE0-0xFC5F | 128B | Unknown Graphic(s) | Likely UI element |
| j6.6h | 0xFC60-0xFE3F | 480B | Stage Banner Graphic | 30x32px, 4bpp, interleaved |
| j6.6h | 0xFE40-0xFFF7 | 440B | Padding / Unused Bytes (0xFF) | Unprogrammed Bytes |
| j6.6h | 0xFFF8-0xFFF9 | 2B | Code Execution Start Address | Value: A0 06 |
| j6.6h | 0xFFFA-0xFFFD | 4B | Padding / Unused Bytes (0xFF) | Unprogrammed Bytes |
| j6.6h | 0xFFFE-0xFFFF | 2B | Starting ROM Page | Value: A0 00 |
| c1.1i | 0x10000-0x1001F | 32B | Tile 0x00 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10020-0x1003F | 32B | Tile 0x01 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10040-0x1005F | 32B | Tile 0x02 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10060-0x1007F | 32B | Tile 0x03 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10080-0x1009F | 32B | Tile 0x04 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x100A0-0x100BF | 32B | Tile 0x05 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x100C0-0x100DF | 32B | Tile 0x06 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x100E0-0x100FF | 32B | Tile 0x07 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10100-0x1011F | 32B | Tile 0x08 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10120-0x1013F | 32B | Tile 0x09 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10140-0x1015F | 32B | Tile 0x0A - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10160-0x1017F | 32B | Tile 0x0B - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10180-0x1019F | 32B | Tile 0x0C - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x101A0-0x101BF | 32B | Tile 0x0D - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x101C0-0x101DF | 32B | Tile 0x0E - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x101E0-0x101FF | 32B | Tile 0x0F - Spawner Top Center | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10200-0x1021F | 32B | Tile 0x10 - Spawner Top Right | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10220-0x1023F | 32B | Tile 0x11 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10240-0x1025F | 32B | Tile 0x12 - Spawner Mid Right | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10260-0x1027F | 32B | Tile 0x13 - Wall | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10280-0x1029F | 32B | Tile 0x14 - Spawner Bot Right | 16×16px, 4bpp, interleaved |
| c1.1i | 0x102A0-0x102BF | 32B | Tile 0x15 - Spawner Bot Center | 16×16px, 4bpp, interleaved |
| c1.1i | 0x102C0-0x102DF | 32B | Tile 0x16 - Keyhole Rising 1 | 16×16px, 4bpp, interleaved |
| c1.1i | 0x102E0-0x102FF | 32B | Tile 0x17 - Flame (Unused) | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10300-0x1031F | 32B | Tile 0x18 - Spawner Bot Left | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10320-0x1033F | 32B | Tile 0x19 - Flame (Unused) | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10340-0x1035F | 32B | Tile 0x1A - Flame (Unused) | 16×16px, 4bpp, interleaved |
| c1.1i | 0x10360-0x1037F | 32B | Tile 0x1B - Spawner Mid Left | 16×16px, 4bpp, interleaved |
| c1.1h | 0x10380-0x1039F | 32B | Tile 0x1C - Flame (Unused) | 16×16px, 4bpp, interleaved |
| c1.1h | 0x103A0-0x103BF | 32B | Tile 0x1D - Spawner Top Left | 16×16px, 4bpp, interleaved |
| c1.1h | 0x103C0-0x103DF | 32B | Tile 0x1E - Keyhole Rising 2 | 16×16px, 4bpp, interleaved |
| c1.1h | 0x103E0-0x103FF | 32B | Tile 0x1F - Wall | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11000-0x1101F | 32B | Tile 0x20 - Wall | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11020-0x1103F | 32B | Tile 0x21 - Empty Ring Box | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11040-0x1105F | 32B | Tile 0x22 - Empty Key Box | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11060-0x1107F | 32B | Tile 0x23 - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11080-0x1109F | 32B | Tile 0x24 - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x110A0-0x110BF | 32B | Tile 0x25 - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x110C0-0x110DF | 32B | Tile 0x26 - Empty Path | 16×16px, 4bpp, interleaved |
| c2.2i | 0x110E0-0x110FF | 32B | Tile 0x27 - Wall | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11100-0x1111F | 32B | Tile 0x28 - Wall | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11120-0x1113F | 32B | Tile 0x29 - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11140-0x1115F | 32B | Tile 0x2A - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11160-0x1117F | 32B | Tile 0x2B - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11180-0x1119F | 32B | Tile 0x2C - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x111A0-0x111BF | 32B | Tile 0x2D - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x111C0-0x111DF | 32B | Tile 0x2E - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x111E0-0x111FF | 32B | Tile 0x2F - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11200-0x1121F | 32B | Tile 0x30 - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11220-0x1123F | 32B | Tile 0x31 - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11240-0x1125F | 32B | Tile 0x32 - Bat Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11260-0x1127F | 32B | Tile 0x33 - Bat Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11280-0x1129F | 32B | Tile 0x34 - Bat Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x112A0-0x112BF | 32B | Tile 0x35 - Bat Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x112C0-0x112DF | 32B | Tile 0x36 - Cobra Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x112E0-0x112FF | 32B | Tile 0x37 - Cobra Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11300-0x1131F | 32B | Tile 0x38 - Cobra Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11320-0x1133F | 32B | Tile 0x39 - Cobra Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11340-0x1135F | 32B | Tile 0x3A - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11360-0x1137F | 32B | Tile 0x3B - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x11380-0x1139F | 32B | Tile 0x3C - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x113A0-0x113BF | 32B | Tile 0x3D - Player Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x113C0-0x113DF | 32B | Tile 0x3E - Vulture Sprite | 16×16px, 4bpp, interleaved |
| c2.2i | 0x113E0-0x113FF | 32B | Tile 0x3F - Vulture Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12000-0x1201F | 32B | Tile 0x40 - Vulture Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12020-0x1203F | 32B | Tile 0x41 - Vulture Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12040-0x1205F | 32B | Tile 0x42 - Vulture Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12060-0x1207F | 32B | Tile 0x43 - Vulture Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12080-0x1209F | 32B | Tile 0x44 - Vulture Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x120A0-0x120BF | 32B | Tile 0x45 - Vulture Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x120C0-0x120DF | 32B | Tile 0x46 - Cobra Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x120E0-0x120FF | 32B | Tile 0x47 - Cobra Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12100-0x1211F | 32B | Tile 0x48 - Cobra Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12120-0x1213F | 32B | Tile 0x49 - Cobra Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12140-0x1215F | 32B | Tile 0x4A - Empty Crown Box | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12160-0x1217F | 32B | Tile 0x4B - Score Box (Unused) | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12180-0x1219F | 32B | Tile 0x4C - Score Box (Unused) | 16×16px, 4bpp, interleaved |
| c3.3i | 0x121A0-0x121BF | 32B | Tile 0x4D - Keyhole Rising 3 | 16×16px, 4bpp, interleaved |
| c3.3i | 0x121C0-0x121DF | 32B | Tile 0x4E - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x121E0-0x121FF | 32B | Tile 0x4F - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12200-0x1221F | 32B | Tile 0x50 - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12220-0x1223F | 32B | Tile 0x51 - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12240-0x1225F | 32B | Tile 0x52 - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12260-0x1227F | 32B | Tile 0x53 - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12280-0x1229F | 32B | Tile 0x54 - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x122A0-0x122BF | 32B | Tile 0x55 - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x122C0-0x122DF | 32B | Tile 0x56 - Poof Cloud Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x122E0-0x122FF | 32B | Tile 0x57 - Poof Cloud Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12300-0x1231F | 32B | Tile 0x58 - Poof Cloud Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12320-0x1233F | 32B | Tile 0x59 - Poof Cloud Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12340-0x1235F | 32B | Tile 0x5A - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12360-0x1237F | 32B | Tile 0x5B - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x12380-0x1239F | 32B | Tile 0x5C - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x123A0-0x123BF | 32B | Tile 0x5D - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x123C0-0x123DF | 32B | Tile 0x5E - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c3.3i | 0x123E0-0x123FF | 32B | Tile 0x5F - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13000-0x1301F | 32B | Tile 0x60 - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13020-0x1303F | 32B | Tile 0x61 - Player + Key Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13040-0x1305F | 32B | Tile 0x62 - Filled Crown Box | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13060-0x1307F | 32B | Tile 0x63 - Poof Cloud Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13080-0x1309F | 32B | Tile 0x64 - Left Teleport Tile | 16×16px, 4bpp, interleaved |
| c4.4i | 0x130A0-0x130BF | 32B | Tile 0x65 - Right Teleport Tile | 16×16px, 4bpp, interleaved |
| c4.4i | 0x130C0-0x130DF | 32B | Tile 0x66 - Keyhole Rising 4 | 16×16px, 4bpp, interleaved |
| c4.4i | 0x130E0-0x130FF | 32B | Tile 0x67 - Poison (Unused) | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13100-0x1311F | 32B | Tile 0x68 - Poison (Unused) | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13120-0x1313F | 32B | Tile 0x69 - Poison (Unused) | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13140-0x1315F | 32B | Tile 0x6A - Poison (Unused) | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13160-0x1317F | 32B | Tile 0x6B - Explosion Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13180-0x1319F | 32B | Tile 0x6C - Explosion Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x131A0-0x131BF | 32B | Tile 0x6D - Explosion Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x131C0-0x131DF | 32B | Tile 0x6E - Explosion Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x131E0-0x131FF | 32B | Tile 0x6F - Filled Ring Box | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13200-0x1321F | 32B | Tile 0x70 - Filled Key Box | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13220-0x1323F | 32B | Tile 0x71 - Keyhole Rising 5 | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13240-0x1325F | 32B | Tile 0x72 - Keyhole | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13260-0x1327F | 32B | Tile 0x73 - Door Top Left | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13280-0x1329F | 32B | Tile 0x74 - Door Top Center | 16×16px, 4bpp, interleaved |
| c4.4i | 0x132A0-0x132BF | 32B | Tile 0x75 - Door Top Right | 16×16px, 4bpp, interleaved |
| c4.4i | 0x132C0-0x132DF | 32B | Tile 0x76 - Door Mid Left | 16×16px, 4bpp, interleaved |
| c4.4i | 0x132E0-0x132FF | 32B | Tile 0x77 - Door Mid Center | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13300-0x1331F | 32B | Tile 0x78 - Door Mid Right | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13320-0x1333F | 32B | Tile 0x79 - Door Bot Left | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13340-0x1335F | 32B | Tile 0x7A - Door Bot Center | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13360-0x1337F | 32B | Tile 0x7B - Door Bot Right | 16×16px, 4bpp, interleaved |
| c4.4i | 0x13380-0x1339F | 32B | Tile 0x7C - Bat Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x133A0-0x133BF | 32B | Tile 0x7D - Bat Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x133C0-0x133DF | 32B | Tile 0x7E - Bat Sprite | 16×16px, 4bpp, interleaved |
| c4.4i | 0x133E0-0x133FF | 32B | Tile 0x7F - Rock (Unused) | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14000-0x1401F | 32B | Tile 0x80 - 500 Score Box | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14020-0x1403F | 32B | Tile 0x81 - 1000 Score Box | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14040-0x1405F | 32B | Tile 0x82 - 1500 Score Box | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14060-0x1407F | 32B | Tile 0x83 - 2000 Score Box | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14080-0x1409F | 32B | Tile 0x84 - 3000 Score Box | 16×16px, 4bpp, interleaved |
| c5.5i | 0x140A0-0x140BF | 32B | Tile 0x85 - 4000 Score Box | 16×16px, 4bpp, interleaved |
| c5.5i | 0x140C0-0x140DF | 32B | Tile 0x86 - Tut Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x140E0-0x140FF | 32B | Tile 0x87 - Tut Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14100-0x1411F | 32B | Tile 0x88 - Tut Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14120-0x1413F | 32B | Tile 0x89 - Dragon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14140-0x1415F | 32B | Tile 0x8A - Dragon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14160-0x1417F | 32B | Tile 0x8B - Dragon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14180-0x1419F | 32B | Tile 0x8C - Dragon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x141A0-0x141BF | 32B | Tile 0x8D - Dragon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x141C0-0x141DF | 32B | Tile 0x8E - Dragon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x141E0-0x141FF | 32B | Tile 0x8F - Dragon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14200-0x1421F | 32B | Tile 0x90 - Dragon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14220-0x1423F | 32B | Tile 0x91 - Gryphon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14240-0x1425F | 32B | Tile 0x92 - Gryphon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14260-0x1427F | 32B | Tile 0x93 - Gryphon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14280-0x1429F | 32B | Tile 0x94 - Gryphon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x142A0-0x142BF | 32B | Tile 0x95 - Gryphon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x142C0-0x142DF | 32B | Tile 0x96 - Gryphon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x142E0-0x142FF | 32B | Tile 0x97 - Gryphon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14300-0x1431F | 32B | Tile 0x98 - Gryphon Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14320-0x1433F | 32B | Tile 0x99 - Glaive Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14340-0x1435F | 32B | Tile 0x9A - Glaive Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14360-0x1437F | 32B | Tile 0x9B - Glaive Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x14380-0x1439F | 32B | Tile 0x9C - Glaive Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x143A0-0x143BF | 32B | Tile 0x9D - Glaive Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x143C0-0x143DF | 32B | Tile 0x9E - Glaive Sprite | 16×16px, 4bpp, interleaved |
| c5.5i | 0x143E0-0x143FF | 32B | Tile 0x9F - Glaive Sprite | 16×16px, 4bpp, interleaved |
| c6.6i | 0x15000-0x156FF | 1792B | Logical Map 1 (Collisions) | Bank 0x05, mapped to 0x9000|
| c6.6i | 0x15700-0x15DFF | 1792B | Logical Map 2 (Collisions) | Bank 0x05, mapped to 0x9700|
| c6.6i | 0x15E00-0x15EC7 | 200B | Game Title - Lowercase a | 20x20px, 4bpp, interleaved |
| c6.6i | 0x15EC8-0x15FF3 | 300B | Game Title - Lowercase k | 30x20px, 4bpp, interleaved |
| c6.6i | 0x15FF4-0x15FFF | 12B | Padding / Unused Bytes (0xFF) | Unprogrammed Bytes |
| c7.7i | 0x16000-0x166FF | 1792B | Logical Map 3 (Collisions) | Bank 0x06, mapped to 0x9000|
| c7.7i | 0x16700-0x16DFF | 1792B | Logical Map 4 (Collisions) | Bank 0x06, mapped to 0x9700|
| c7.7i | 0x16E00-0x16EC7 | 200B | Game Title - Lowercase n | 20x20px, 4bpp, interleaved |
| c7.7i | 0x16EC8-0x16FF3 | 300B | Game Title - Lowercase h | 30x20px, 4bpp, interleaved |
| c7.7i | 0x16FF4-0x16FFF | 12B | Padding / Unused Bytes (0xFF) | Unprogrammed Bytes |
| c8.8i | 0x17000-0x172FF | 768B | Visual Map 1 (Tile Mapping) | Bank 0x07, mapped to 0x9000|
| c8.8i | 0x17300-0x175FF | 768B | Visual Map 2 (Tile Mapping) | Bank 0x07, mapped to 0x9300|
| c8.8i | 0x17600-0x178FF | 768B | Visual Map 3 (Tile Mapping) | Bank 0x07, mapped to 0x9600|
| c8.8i | 0x17900-0x17BFF | 768B | Visual Map 4 (Tile Mapping) | Bank 0x07, mapped to 0x9900|
| c8.8i | 0x17C00-0x17D76 | 375B | Game Title - Uppercase T | 30x25px, 4bpp, interleaved |
| c8.8i | 0x17D77-0x17E3E | 200B | Game Title - Lowercase u | 20x20px, 4bpp, interleaved |
| c8.8i | 0x17E3F-0x17EF4 | 182B | Game Title - Lowercase t | 26x14px, 4bpp, interleaved |
| c8.8i | 0x17EF5-0x17FF8 | 260B | Game Title - Lowercase m | 20x26px, 4bpp, interleaved |
| c8.8i | 0x17FF9-0x17FFF | 7B | Padding / Unused Bytes (0xFF) | Unprogrammed Bytes |
| c9.9i | 0x18000-0x183DD | 990B | Treasure 1 (Map) | 44x44px, 4bpp, interleaved |
| c9.9i | 0x183DE-0x187BB | 990B | Treasure 2 (Genie Lamp) | 44x44px, 4bpp, interleaved |
| c9.9i | 0x187BC-0x18B99 | 990B | Treasure 3 (Treasure Chest) | 44x44px, 4bpp, interleaved |
| c9.9i | 0x18B9A-0x18F77 | 990B | Treasure 4 (Tutankham Mask) | 44x44px, 4bpp, interleaved |
| c9.9i | 0x18F78-0x18F8D | 22B | Extra Graphics Padding (0x11) | Likely Error Bytes, ignored|
| c9.9i | 0x18F8E-0x18FFF | 114B | Padding / Unused Bytes (0xFF) | Unprogrammed Bytes |

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Arcade_MiST/Konami Framebuffer/Useful Information/Tutankham.pdf
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Arcade_MiST/Konami Framebuffer/Useful Information/jun.txt
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void tutankhm_state::main_map(address_map &map)
{
map(0x0000, 0x7fff).ram().share(m_videoram);
//0x8100 -> Custom 089 D9 Pin 15
map(0x8100, 0x8100).mirror(0x000f).ram().share(m_scroll);
/* a read here produces a 1-0-1 write to line 420 (084).
* This most likely resets some sort of timer implemented by the 084 custom chip
* which would on line 419 trigger a reset.
*/
//0x8720 -> Custom 084 F3 Pin 20
map(0x8120, 0x8120).mirror(0x000f).r("watchdog", FUNC(watchdog_timer_device::reset_r));
//0x8740 -> Custom 089 D9 Pin 11 - Unknown, not used
map(0x8160, 0x8160).mirror(0x000f).portr("DSW2"); // DSW2 (inverted bits)
map(0x8180, 0x8180).mirror(0x000f).portr("IN0"); // IN0 I/O: Coin slots, service, 1P/2P buttons
map(0x81a0, 0x81a0).mirror(0x000f).portr("IN1"); // IN1: Player 1 I/O
map(0x81c0, 0x81c0).mirror(0x000f).portr("IN2"); // IN2: Player 2 I/O
map(0x81e0, 0x81e0).mirror(0x000f).portr("DSW1"); // DSW1 (inverted bits)
map(0x8200, 0x8207).mirror(0x00f8).nopr().w("mainlatch", FUNC(ls259_device::write_d0));
map(0x8300, 0x8300).mirror(0x00ff).w(FUNC(tutankhm_state::bankselect_w));
map(0x8600, 0x8600).mirror(0x00ff).w(FUNC(tutankhm_state::sound_on_w));
map(0x8700, 0x8700).mirror(0x00ff).w(m_timeplt_audio, FUNC(timeplt_audio_device::sound_data_w));
map(0x8800, 0x8fff).ram();
map(0x9000, 0x9fff).bankr(m_mainbank);
map(0xa000, 0xffff).rom();
}
void junofrst_state::main_map(address_map &map)
{
map(0x8010, 0x8010).portr("DSW2");
map(0x801c, 0x801c).r("watchdog", FUNC(watchdog_timer_device::reset_r));
map(0x8020, 0x8020).portr("SYSTEM");
map(0x8024, 0x8024).portr("P1");
map(0x8028, 0x8028).portr("P2");
map(0x802c, 0x802c).portr("DSW1");
map(0x8030, 0x8037).w("mainlatch", FUNC(ls259_device::write_d0));
map(0x8040, 0x8040).w(FUNC(junofrst_state::sh_irqtrigger_w));
map(0x8050, 0x8050).w("soundlatch", FUNC(generic_latch_8_device::write));
map(0x8060, 0x8060).w(FUNC(junofrst_state::bankselect_w));
map(0x8070, 0x8073).w(FUNC(junofrst_state::blitter_w));
map(0x8100, 0x8fff).ram();
map(0x9000, 0x9fff).bankr(m_mainbank);
map(0xa000, 0xffff).rom();
}
void junofrst_state::audio_map(address_map &map)
{
map(0x0000, 0x0fff).rom();
map(0x2000, 0x23ff).ram();
map(0x3000, 0x3000).r("soundlatch", FUNC(generic_latch_8_device::read));
map(0x4000, 0x4000).w("aysnd", FUNC(ay8910_device::address_w));
map(0x4001, 0x4001).r("aysnd", FUNC(ay8910_device::data_r));
map(0x4002, 0x4002).w("aysnd", FUNC(ay8910_device::data_w));
map(0x5000, 0x5000).w("soundlatch2", FUNC(generic_latch_8_device::write));
map(0x6000, 0x6000).w(FUNC(junofrst_state::i8039_irq_w));
}

495
Arcade_MiST/Konami Framebuffer/Useful Information/junofrst.cpp
View File

@@ -1,495 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Chris Hardy
/***************************************************************************
Juno First : memory map same as tutankham with some address changes
Chris Hardy (chrish@kcbbs.gen.nz)
Thanks to Rob Jarret for the original Tutankham memory map on which both the
Juno First emu and the MAME driver is based on.
Juno First memory map by Chris Hardy
Read/Write memory
$0000-$7FFF = Screen RAM (only written to)
$8000-$800f = Palette RAM. BBGGGRRR (D7->D0)
$8100-$8FFF = Work RAM
Write memory
$8030 - interrupt control register D0 = interrupts on or off
$8031 - unknown
$8032 - unknown
$8033 - unknown
$8034 - flip screen x
$8035 - flip screen y
$8040 - Sound CPU req/ack data
$8050 - Sound CPU command data
$8060 - Banked memory page select.
$8070/1 - Blitter source data word
$8072/3 - Blitter destination word. Write to $8073 triggers a blit
Read memory
$8010 - Dipswitch 2
$801c - Watchdog
$8020 - Start/Credit IO
D2 = Credit 1
D3 = Start 1
D4 = Start 2
$8024 - P1 IO
D0 = left
D1 = right
D2 = up
D3 = down
D4 = fire 2
D5 = fire 1
$8028 - P2 IO - same as P1 IO
$802c - Dipswitch 1
$9000->$9FFF Banked Memory - see below
$A000->$BFFF "juno\\JFA_B9.BIN",
$C000->$DFFF "juno\\JFB_B10.BIN",
$E000->$FFFF "juno\\JFC_A10.BIN",
Banked memory - Paged into $9000->$9FFF..
NOTE - In Tutankhm this only contains graphics, in Juno First it also contains code. (which
generally sets up the blitter)
"juno\\JFC1_A4.BIN", $0000->$1FFF
"juno\\JFC2_A5.BIN", $2000->$3FFF
"juno\\JFC3_A6.BIN", $4000->$5FFF
"juno\\JFC4_A7.BIN", $6000->$7FFF
"juno\\JFC5_A8.BIN", $8000->$9FFF
"juno\\JFC6_A9.BIN", $A000->$bFFF
Blitter source graphics
"juno\\JFS3_C7.BIN", $C000->$DFFF
"juno\\JFS4_D7.BIN", $E000->$FFFF
"juno\\JFS5_E7.BIN", $10000->$11FFF
***************************************************************************/
#include "emu.h"
#include "tutankhm.h"
#include "konamipt.h"
#include "konami1.h"
#include "cpu/m6809/m6809.h"
#include "cpu/mcs48/mcs48.h"
#include "cpu/z80/z80.h"
#include "machine/74259.h"
#include "machine/gen_latch.h"
#include "machine/watchdog.h"
#include "sound/ay8910.h"
#include "sound/dac.h"
#include "sound/flt_rc.h"
#include "screen.h"
#include "speaker.h"
namespace {
class junofrst_state : public tutankhm_state
{
public:
junofrst_state(const machine_config &mconfig, device_type type, const char *tag)
: tutankhm_state(mconfig, type, tag)
, m_audiocpu(*this, "audiocpu")
, m_i8039(*this, "mcu")
, m_filter(*this, "filter.0.%u", 0U)
, m_blitrom(*this, "blitrom")
{
}
void junofrst(machine_config &config);
protected:
virtual void machine_start() override ATTR_COLD;
virtual void machine_reset() override ATTR_COLD;
private:
void blitter_w(offs_t offset, uint8_t data);
void sh_irqtrigger_w(uint8_t data);
void i8039_irq_w(uint8_t data);
void i8039_irqen_and_status_w(uint8_t data);
uint8_t portA_r();
void portB_w(uint8_t data);
void _30hz_irq(int state);
void audio_map(address_map &map) ATTR_COLD;
void main_map(address_map &map) ATTR_COLD;
void mcu_io_map(address_map &map) ATTR_COLD;
void mcu_map(address_map &map) ATTR_COLD;
required_device<cpu_device> m_audiocpu;
required_device<i8039_device> m_i8039;
required_device_array<filter_rc_device, 3> m_filter;
required_region_ptr<uint8_t> m_blitrom;
uint8_t m_blitterdata[4]{};
uint8_t m_i8039_status = 0;
uint8_t m_last_irq = 0;
};
/* Juno First Blitter Hardware emulation
Juno First can blit a 16x16 graphics which comes from un-memory mapped graphics roms
$8070->$8071 specifies the destination NIBBLE address
$8072->$8073 specifies the source NIBBLE address
Depending on bit 0 of the source address either the source pixels will be copied to
the destination address, or a zero will be written.
Only source pixels which aren't 0 are copied or cleared.
This allows the game to quickly clear the sprites from the screen
TODO: Does bit 1 of the source address mean something?
We have to mask it off otherwise the "Juno First" logo on the title screen is wrong.
*/
void junofrst_state::blitter_w(offs_t offset, uint8_t data)
{
m_blitterdata[offset] = data;
/* blitter is triggered by $8073 */
if (offset == 3)
{
offs_t src = ((m_blitterdata[2] << 8) | m_blitterdata[3]) & 0xfffc;
offs_t dest = (m_blitterdata[0] << 8) | m_blitterdata[1];
bool const copy = BIT(m_blitterdata[3], 0);
/* 16x16 graphics */
for (int i = 0; i < 16; i++)
{
for (int j = 0; j < 16; j++)
{
uint8_t data;
if (BIT(src, 0))
data = m_blitrom[src >> 1] & 0x0f;
else
data = m_blitrom[src >> 1] >> 4;
src++;
/* if there is a source pixel either copy the pixel or clear the pixel depending on the copy flag */
if (data)
{
if (!copy)
data = 0;
if (BIT(dest, 0))
m_videoram[dest >> 1] = (m_videoram[dest >> 1] & 0x0f) | (data << 4);
else
m_videoram[dest >> 1] = (m_videoram[dest >> 1] & 0xf0) | data;
}
dest++;
}
dest += 240;
}
}
}
uint8_t junofrst_state::portA_r()
{
/* main xtal 14.318MHz, divided by 8 to get the CPU clock, further */
/* divided by 1024 to get this timer */
/* (divide by (1024/2), and not 1024, because the CPU cycle counter is */
/* incremented every other state change of the clock) */
int const timer = (m_audiocpu->total_cycles() / (1024 / 2)) & 0x0f;
/* low three bits come from the 8039 */
return (timer << 4) | m_i8039_status;
}
void junofrst_state::portB_w(uint8_t data)
{
for (int i = 0; i < 3; i++)
{
int C = 0;
if (BIT(data, 0))
C += 47000; /* 47000pF = 0.047uF */
if (BIT(data, 1))
C += 220000; /* 220000pF = 0.22uF */
data >>= 2;
m_filter[i]->filter_rc_set_RC(filter_rc_device::LOWPASS_3R, 1000, 2200, 200, CAP_P(C));
}
}
void junofrst_state::sh_irqtrigger_w(uint8_t data)
{
if (m_last_irq == 0 && data == 1)
{
/* setting bit 0 low then high triggers IRQ on the sound CPU */
m_audiocpu->set_input_line_and_vector(0, HOLD_LINE, 0xff); // Z80
}
m_last_irq = data;
}
void junofrst_state::i8039_irq_w(uint8_t data)
{
m_i8039->set_input_line(0, ASSERT_LINE);
}
void junofrst_state::i8039_irqen_and_status_w(uint8_t data)
{
if (BIT(~data, 7))
m_i8039->set_input_line(0, CLEAR_LINE);
m_i8039_status = (data & 0x70) >> 4;
}
void junofrst_state::main_map(address_map &map)
{
map(0x0000, 0x7fff).ram().share(m_videoram);
map(0x8000, 0x800f).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
map(0x8010, 0x8010).portr("DSW2");
map(0x801c, 0x801c).r("watchdog", FUNC(watchdog_timer_device::reset_r));
map(0x8020, 0x8020).portr("SYSTEM");
map(0x8024, 0x8024).portr("P1");
map(0x8028, 0x8028).portr("P2");
map(0x802c, 0x802c).portr("DSW1");
map(0x8030, 0x8037).w("mainlatch", FUNC(ls259_device::write_d0));
map(0x8040, 0x8040).w(FUNC(junofrst_state::sh_irqtrigger_w));
map(0x8050, 0x8050).w("soundlatch", FUNC(generic_latch_8_device::write));
map(0x8060, 0x8060).w(FUNC(junofrst_state::bankselect_w));
map(0x8070, 0x8073).w(FUNC(junofrst_state::blitter_w));
map(0x8100, 0x8fff).ram();
map(0x9000, 0x9fff).bankr(m_mainbank);
map(0xa000, 0xffff).rom();
}
void junofrst_state::audio_map(address_map &map)
{
map(0x0000, 0x0fff).rom();
map(0x2000, 0x23ff).ram();
map(0x3000, 0x3000).r("soundlatch", FUNC(generic_latch_8_device::read));
map(0x4000, 0x4000).w("aysnd", FUNC(ay8910_device::address_w));
map(0x4001, 0x4001).r("aysnd", FUNC(ay8910_device::data_r));
map(0x4002, 0x4002).w("aysnd", FUNC(ay8910_device::data_w));
map(0x5000, 0x5000).w("soundlatch2", FUNC(generic_latch_8_device::write));
map(0x6000, 0x6000).w(FUNC(junofrst_state::i8039_irq_w));
}
void junofrst_state::mcu_map(address_map &map)
{
map(0x0000, 0x0fff).rom();
}
void junofrst_state::mcu_io_map(address_map &map)
{
map(0x00, 0xff).r("soundlatch2", FUNC(generic_latch_8_device::read));
}
static INPUT_PORTS_START( junofrst )
PORT_START("SYSTEM")
KONAMI8_SYSTEM_UNK
PORT_START("P1")
KONAMI8_MONO_B213_UNK
PORT_START("P2")
KONAMI8_COCKTAIL_B213_UNK
PORT_START("DSW1")
KONAMI_COINAGE_LOC(DEF_STR( Free_Play ), "No Coin B", SW1)
/* "No Coin B" = coins produce sound, but no effect on coin counter */
PORT_START("DSW2")
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:1,2")
PORT_DIPSETTING( 0x03, "3" )
PORT_DIPSETTING( 0x02, "4" )
PORT_DIPSETTING( 0x01, "5" )
PORT_DIPSETTING( 0x00, "256 (Cheat)")
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3")
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
PORT_DIPUNUSED_DIPLOC( 0x08, IP_ACTIVE_LOW, "SW2:4" )
PORT_DIPNAME( 0x70, 0x70, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:5,6,7")
PORT_DIPSETTING( 0x70, "1 (Easiest)" )
PORT_DIPSETTING( 0x60, "2" )
PORT_DIPSETTING( 0x50, "3" )
PORT_DIPSETTING( 0x40, "4" )
PORT_DIPSETTING( 0x30, "5" )
PORT_DIPSETTING( 0x20, "6" )
PORT_DIPSETTING( 0x10, "7" )
PORT_DIPSETTING( 0x00, "8 (Hardest)" )
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
void junofrst_state::machine_start()
{
// note that base class version is not called
m_mainbank->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x1000);
save_item(NAME(m_i8039_status));
save_item(NAME(m_last_irq));
save_item(NAME(m_irq_toggle));
save_item(NAME(m_irq_enable));
save_item(NAME(m_flipscreen_x));
save_item(NAME(m_flipscreen_y));
save_item(NAME(m_blitterdata));
}
void junofrst_state::machine_reset()
{
// note that base class version is not called
m_i8039_status = 0;
m_last_irq = 0;
m_blitterdata[0] = 0;
m_blitterdata[1] = 0;
m_blitterdata[2] = 0;
m_blitterdata[3] = 0;
m_irq_toggle = 0;
}
void junofrst_state::_30hz_irq(int state)
{
/* flip flops cause the interrupt to be signalled every other frame */
if (state)
{
m_irq_toggle ^= 1;
if (m_irq_toggle && m_irq_enable)
m_maincpu->set_input_line(0, ASSERT_LINE);
}
}
void junofrst_state::junofrst(machine_config &config)
{
/* basic machine hardware */
KONAMI1(config, m_maincpu, 18.432_MHz_XTAL / 12); // 1.536 MHz
m_maincpu->set_addrmap(AS_PROGRAM, &junofrst_state::main_map);
Z80(config, m_audiocpu, 14.318181_MHz_XTAL / 8); // 1.78975 MHz
m_audiocpu->set_addrmap(AS_PROGRAM, &junofrst_state::audio_map);
I8039(config, m_i8039, 8_MHz_XTAL);
m_i8039->set_addrmap(AS_PROGRAM, &junofrst_state::mcu_map);
m_i8039->set_addrmap(AS_IO, &junofrst_state::mcu_io_map);
m_i8039->p1_out_cb().set("dac", FUNC(dac_byte_interface::data_w));
m_i8039->p2_out_cb().set(FUNC(junofrst_state::i8039_irqen_and_status_w));
ls259_device &mainlatch(LS259(config, "mainlatch")); // B3
mainlatch.q_out_cb<0>().set(FUNC(junofrst_state::irq_enable_w));
mainlatch.q_out_cb<1>().set(FUNC(junofrst_state::coin_counter_2_w));
mainlatch.q_out_cb<2>().set(FUNC(junofrst_state::coin_counter_1_w));
mainlatch.q_out_cb<3>().set_nop();
mainlatch.q_out_cb<4>().set(FUNC(junofrst_state::flip_screen_x_w)); // HFF
mainlatch.q_out_cb<5>().set(FUNC(junofrst_state::flip_screen_y_w)); // VFLIP
WATCHDOG_TIMER(config, "watchdog");
/* video hardware */
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(GALAXIAN_PIXEL_CLOCK, GALAXIAN_HTOTAL, GALAXIAN_HBEND, GALAXIAN_HBSTART, GALAXIAN_VTOTAL, GALAXIAN_VBEND, GALAXIAN_VBSTART);
PALETTE(config, m_palette).set_format(1, tutankhm_state::raw_to_rgb_func, 16);
m_screen->set_screen_update(FUNC(junofrst_state::screen_update_scramble));
m_screen->screen_vblank().set(FUNC(junofrst_state::_30hz_irq));
/* sound hardware */
SPEAKER(config, "speaker").front_center();
GENERIC_LATCH_8(config, "soundlatch");
GENERIC_LATCH_8(config, "soundlatch2");
ay8910_device &aysnd(AY8910(config, "aysnd", 14.318181_MHz_XTAL / 8));
aysnd.port_a_read_callback().set(FUNC(junofrst_state::portA_r));
aysnd.port_b_write_callback().set(FUNC(junofrst_state::portB_w));
aysnd.add_route(0, "filter.0.0", 0.30);
aysnd.add_route(1, "filter.0.1", 0.30);
aysnd.add_route(2, "filter.0.2", 0.30);
DAC_8BIT_R2R(config, "dac", 0).add_route(ALL_OUTPUTS, "speaker", 0.25); // 100K (R56-63)/200K (R64-71) ladder network
FILTER_RC(config, m_filter[0]).add_route(ALL_OUTPUTS, "speaker", 1.0);
FILTER_RC(config, m_filter[1]).add_route(ALL_OUTPUTS, "speaker", 1.0);
FILTER_RC(config, m_filter[2]).add_route(ALL_OUTPUTS, "speaker", 1.0);
}
ROM_START( junofrst )
ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) /* code + space for decrypted opcodes */
ROM_LOAD( "jfa_b9.bin", 0x0a000, 0x2000, CRC(f5a7ab9d) SHA1(9603e797839290f8e1f93ccff9cc820604cc49ab) ) /* program ROMs */
ROM_LOAD( "jfb_b10.bin", 0x0c000, 0x2000, CRC(f20626e0) SHA1(46f58bdc1a613124e2c148b61f774fcc6c232868) )
ROM_LOAD( "jfc_a10.bin", 0x0e000, 0x2000, CRC(1e7744a7) SHA1(bee69833af886436016560295cddf0c8b4c5e771) )
ROM_LOAD( "jfc1_a4.bin", 0x10000, 0x2000, CRC(03ccbf1d) SHA1(02b45fe3c51bdc940919aac68136a121ed9bee18) ) /* graphic and code ROMs (banked) */
ROM_LOAD( "jfc2_a5.bin", 0x12000, 0x2000, CRC(cb372372) SHA1(a48e7de08647cbece7787c287217eac7e7a7510b) )
ROM_LOAD( "jfc3_a6.bin", 0x14000, 0x2000, CRC(879d194b) SHA1(3c7af8767c9ce908fa1761180c6e585823216d8a) )
ROM_LOAD( "jfc4_a7.bin", 0x16000, 0x2000, CRC(f28af80b) SHA1(4d0e247e729365476dd3996c7d1f2a19fc83d773) )
ROM_LOAD( "jfc5_a8.bin", 0x18000, 0x2000, CRC(0539f328) SHA1(c532aaed7f9e6f564e3df0dc6d8fdbee6ed721a2) )
ROM_LOAD( "jfc6_a9.bin", 0x1a000, 0x2000, CRC(1da2ad6e) SHA1(de997d1b2ff6671088b57192bc9f1279359fad5d) )
ROM_REGION( 0x1000, "audiocpu", 0 ) /* 4k for Z80 sound CPU code */
ROM_LOAD( "jfs1_j3.bin", 0x0000, 0x1000, CRC(235a2893) SHA1(b90251c4971f7ba12e407f86c32723d513d6b4a0) )
ROM_REGION( 0x1000, "mcu", 0 ) /* 8039 */
ROM_LOAD( "jfs2_p4.bin", 0x0000, 0x1000, CRC(d0fa5d5f) SHA1(9d0730d1d037bf96b0c933a32355602bf2d735dd) )
ROM_REGION( 0x6000, "blitrom", 0 ) /* BLTROM, used at runtime */
ROM_LOAD( "jfs3_c7.bin", 0x00000, 0x2000, CRC(aeacf6db) SHA1(f99ef9f9153d7a83e1881d9181faac99cb8c8a57) )
ROM_LOAD( "jfs4_d7.bin", 0x02000, 0x2000, CRC(206d954c) SHA1(65494766676f18d8b5ae9a54cee00790e7b1e67e) )
ROM_LOAD( "jfs5_e7.bin", 0x04000, 0x2000, CRC(1eb87a6e) SHA1(f5471b9f6f1fa6d6e5d76300d89f71da3129516a) )
ROM_END
ROM_START( junofrstg )
ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) /* code + space for decrypted opcodes */
ROM_LOAD( "jfg_a.9b", 0x0a000, 0x2000, CRC(8f77d1c5) SHA1(d47fcdbc47673c228661a3528fff0c691c76df9e) ) /* program ROMs */
ROM_LOAD( "jfg_b.10b", 0x0c000, 0x2000, CRC(cd645673) SHA1(25994210a8a424bdf2eca3efa19e7eeffc097cec) )
ROM_LOAD( "jfg_c.10a", 0x0e000, 0x2000, CRC(47852761) SHA1(eeef814b6ad681d4c2274f0a69d1ed9c5c1b9118) )
ROM_LOAD( "jfgc1.4a", 0x10000, 0x2000, CRC(90a05ae6) SHA1(0aa835e1d33ab0433189b329b791c952e69103c1) ) /* graphic and code ROMs (banked) */
ROM_LOAD( "jfc2_a5.bin", 0x12000, 0x2000, CRC(cb372372) SHA1(a48e7de08647cbece7787c287217eac7e7a7510b) )
ROM_LOAD( "jfc3_a6.bin", 0x14000, 0x2000, CRC(879d194b) SHA1(3c7af8767c9ce908fa1761180c6e585823216d8a) )
ROM_LOAD( "jfgc4.7a", 0x16000, 0x2000, CRC(e8864a43) SHA1(52b04e69036622abeb6ec99ac3daeda6a2572994) )
ROM_LOAD( "jfc5_a8.bin", 0x18000, 0x2000, CRC(0539f328) SHA1(c532aaed7f9e6f564e3df0dc6d8fdbee6ed721a2) )
ROM_LOAD( "jfc6_a9.bin", 0x1a000, 0x2000, CRC(1da2ad6e) SHA1(de997d1b2ff6671088b57192bc9f1279359fad5d) )
ROM_REGION( 0x1000, "audiocpu", 0 ) /* 4k for Z80 sound CPU code */
ROM_LOAD( "jfs1_j3.bin", 0x0000, 0x1000, CRC(235a2893) SHA1(b90251c4971f7ba12e407f86c32723d513d6b4a0) )
ROM_REGION( 0x1000, "mcu", 0 ) /* 8039 */
ROM_LOAD( "jfs2_p4.bin", 0x0000, 0x1000, CRC(d0fa5d5f) SHA1(9d0730d1d037bf96b0c933a32355602bf2d735dd) )
ROM_REGION( 0x6000, "blitrom", 0 ) /* BLTROM, used at runtime */
ROM_LOAD( "jfs3_c7.bin", 0x00000, 0x2000, CRC(aeacf6db) SHA1(f99ef9f9153d7a83e1881d9181faac99cb8c8a57) )
ROM_LOAD( "jfs4_d7.bin", 0x02000, 0x2000, CRC(206d954c) SHA1(65494766676f18d8b5ae9a54cee00790e7b1e67e) )
ROM_LOAD( "jfs5_e7.bin", 0x04000, 0x2000, CRC(1eb87a6e) SHA1(f5471b9f6f1fa6d6e5d76300d89f71da3129516a) )
ROM_END
} // Anonymous namespace
GAME( 1983, junofrst, 0, junofrst, junofrst, junofrst_state, empty_init, ROT90, "Konami", "Juno First", MACHINE_SUPPORTS_SAVE )
GAME( 1983, junofrstg, junofrst, junofrst, junofrst, junofrst_state, empty_init, ROT90, "Konami (Gottlieb license)", "Juno First (Gottlieb)", MACHINE_SUPPORTS_SAVE )

448
Arcade_MiST/Konami Framebuffer/Useful Information/tutankhm.cpp
View File

@@ -1,448 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Mirko Buffoni
/***************************************************************************
Tutankham
driver by Mirko Buffoni
based on original work by Rob Jarrett
I include here the document based on Rob Jarrett's research because it's
really exhaustive.
Sound board: uses the same board as Pooyan.
Note:
* The sound board uses a 14.318 MHz xtal.
* The cpu/video board uses a 18.432 MHz xtal.
Todo:
* Discrete filters
* Starfield
Custom Chip 084 (Starfield generation)
----------------------
NE555 1Hz | 10 24 | VCC
| |
| |
18Mhz 401 | 1 19 | 419 Reset Enable
6MHz 109 | 2 |
256H* 403 | 3 Custom 084 |
Vblank* 404 | 4 |
/SYNC* 405 | 5 18 | Blue
Aux. Enable 406 | 6 17 | Blue
Stars Enable 407 | 7 |
Horz.Flip HFF | 8 16 | Green
GND | 11 15 | Green
| |
H8Q 423 | 23 14 | Red
V1 422 | 22 13 | Red
V2 421 | 21 |
0x8120 420 | 20 |
----------------------
line 420 seems to be related to 419 which is connect to reset circuit -> watchdog
There are two star fields implemented here. The active one can be selected in
Machine Configuration.
a) Scramble Starfield
1/3 star width like scramble/galaxian, starfield code same as scramble.
This one is similar to the Konami starfield video below.
b) Bootleg Starfield
Guru provided schematics of a daughter-board which on a Konami bootleg replaced
custom chip 084. This starfield matches the starfield (picture) of this bootleg.
None of the two alterntives reproduces the star field which can be observed in
the Stern videos below.
FIXME: For an exact emulation we need a 084 at some time.
FIXME: The Konami video below is different from tutankhm. Looks like we
are missing an early board dump
Starfield videos ....
Konami
https://www.youtube.com/watch?v=YwVjJtQK2n4
Stern
https://www.youtube.com/watch?v=g6nv6jHFP80
https://www.youtube.com/watch?v=D_hmvFi2ehw
https://www.youtube.com/watch?v=EZNqH-JPzPM
https://www.youtube.com/watch?v=1MPvSIEIpFU
*/
/***************************************************************************/
#include "emu.h"
#include "tutankhm.h"
#include "konamipt.h"
#include "cpu/m6809/m6809.h"
#include "machine/74259.h"
#include "machine/watchdog.h"
#include "screen.h"
#include "speaker.h"
/*************************************
*
* Interrupts
*
*************************************/
void tutankhm_state::vblank_irq(int state)
{
// flip flops cause the interrupt to be signalled every other frame
if (state)
{
m_irq_toggle ^= 1;
if (m_irq_toggle && m_irq_enable)
m_maincpu->set_input_line(0, ASSERT_LINE);
}
}
void tutankhm_state::irq_enable_w(int state)
{
m_irq_enable = state;
if (!m_irq_enable)
m_maincpu->set_input_line(0, CLEAR_LINE);
}
/*************************************
*
* Bank selection
*
*************************************/
void tutankhm_state::bankselect_w(uint8_t data)
{
m_mainbank->set_entry(data & 0x0f);
}
/*************************************
*
* Outputs
*
*************************************/
void tutankhm_state::coin_counter_1_w(int state)
{
machine().bookkeeping().coin_counter_w(0, state);
}
void tutankhm_state::coin_counter_2_w(int state)
{
machine().bookkeeping().coin_counter_w(1, state);
}
void tutankhm_state::sound_on_w(uint8_t data)
{
m_timeplt_audio->sh_irqtrigger_w(0);
m_timeplt_audio->sh_irqtrigger_w(1);
}
/*************************************
*
* Main CPU memory handlers
*
*************************************/
void tutankhm_state::main_map(address_map &map)
{
map(0x0000, 0x7fff).ram().share(m_videoram);
map(0x8000, 0x800f).mirror(0x00f0).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
//0x8100 -> Custom 089 D9 Pin 15
map(0x8100, 0x8100).mirror(0x000f).ram().share(m_scroll);
/* a read here produces a 1-0-1 write to line 420 (084).
* This most likely resets some sort of timer implemented by the 084 custom chip
* which would on line 419 trigger a reset.
*/
//0x8720 -> Custom 084 F3 Pin 20
map(0x8120, 0x8120).mirror(0x000f).r("watchdog", FUNC(watchdog_timer_device::reset_r));
//0x8740 -> Custom 089 D9 Pin 11 - Unknown, not used
map(0x8160, 0x8160).mirror(0x000f).portr("DSW2"); // DSW2 (inverted bits)
map(0x8180, 0x8180).mirror(0x000f).portr("IN0"); // IN0 I/O: Coin slots, service, 1P/2P buttons
map(0x81a0, 0x81a0).mirror(0x000f).portr("IN1"); // IN1: Player 1 I/O
map(0x81c0, 0x81c0).mirror(0x000f).portr("IN2"); // IN2: Player 2 I/O
map(0x81e0, 0x81e0).mirror(0x000f).portr("DSW1"); // DSW1 (inverted bits)
map(0x8200, 0x8207).mirror(0x00f8).nopr().w("mainlatch", FUNC(ls259_device::write_d0));
map(0x8300, 0x8300).mirror(0x00ff).w(FUNC(tutankhm_state::bankselect_w));
map(0x8600, 0x8600).mirror(0x00ff).w(FUNC(tutankhm_state::sound_on_w));
map(0x8700, 0x8700).mirror(0x00ff).w(m_timeplt_audio, FUNC(timeplt_audio_device::sound_data_w));
map(0x8800, 0x8fff).ram();
map(0x9000, 0x9fff).bankr(m_mainbank);
map(0xa000, 0xffff).rom();
}
/*************************************
*
* Port definitions
*
*************************************/
static INPUT_PORTS_START( tutankhm )
PORT_START("DSW2")
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:1,2")
PORT_DIPSETTING( 0x03, "3" )
PORT_DIPSETTING( 0x01, "4" )
PORT_DIPSETTING( 0x02, "5" )
PORT_DIPSETTING( 0x00, "255 (Cheat)")
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3")
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:4")
PORT_DIPSETTING( 0x08, "30000" )
PORT_DIPSETTING( 0x00, "40000" )
PORT_DIPNAME( 0x30, 0x20, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:5,6")
PORT_DIPSETTING( 0x30, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x20, DEF_STR( Normal ) )
PORT_DIPSETTING( 0x10, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
PORT_DIPNAME( 0x40, 0x40, "Flash Bomb" ) PORT_DIPLOCATION("SW2:7")
PORT_DIPSETTING( 0x40, "1 per Life" )
PORT_DIPSETTING( 0x00, "1 per Game" )
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("IN0")
KONAMI8_SYSTEM_UNK
PORT_START("IN1")
KONAMI8_MONO_4WAY_B123_UNK
PORT_MODIFY("IN1")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_LEFT ) PORT_2WAY
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_RIGHT ) PORT_2WAY
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P1 Flash Bomb")
PORT_START("IN2")
KONAMI8_COCKTAIL_4WAY_B123_UNK
PORT_MODIFY("IN2")
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_LEFT ) PORT_2WAY PORT_COCKTAIL
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_RIGHT ) PORT_2WAY PORT_COCKTAIL
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL PORT_NAME("P2 Flash Bomb")
PORT_START("DSW1")
KONAMI_COINAGE_LOC(DEF_STR( Free_Play ), "No Coin B", SW1)
// "No Coin B" = coins produce sound, but no effect on coin counter
PORT_START("STARS")
PORT_CONFNAME( 0x01, 0x01, "Starfield selection" )
PORT_CONFSETTING( 0x00, "Konami HW bootleg (6MHz stars)" )
PORT_CONFSETTING( 0x01, "Scramble implementation" )
INPUT_PORTS_END
/*************************************
*
* Machine drivers
*
*************************************/
void tutankhm_state::machine_start()
{
m_mainbank->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x1000);
m_star_mode = 0;
save_item(NAME(m_irq_toggle));
save_item(NAME(m_irq_enable));
save_item(NAME(m_flipscreen_x));
save_item(NAME(m_flipscreen_y));
//rgb_t m_star_color[64];
//std::unique_ptr<uint8_t[]> m_stars;
save_item(NAME(m_stars_enabled));
save_item(NAME(m_stars_blink_state));
save_item(NAME(m_star_mode));
}
void tutankhm_state::machine_reset()
{
m_irq_toggle = 0;
}
void tutankhm_state::tutankhm(machine_config &config)
{
// basic machine hardware
MC6809E(config, m_maincpu, XTAL(18'432'000)/12); // 1.5 MHz ???
m_maincpu->set_addrmap(AS_PROGRAM, &tutankhm_state::main_map);
ls259_device &mainlatch(LS259(config, "mainlatch")); // C3
mainlatch.q_out_cb<0>().set(FUNC(tutankhm_state::irq_enable_w));
mainlatch.q_out_cb<1>().set_nop(); // PAY OUT - not used
mainlatch.q_out_cb<2>().set(FUNC(tutankhm_state::coin_counter_2_w));
mainlatch.q_out_cb<3>().set(FUNC(tutankhm_state::coin_counter_1_w));
mainlatch.q_out_cb<4>().set(FUNC(tutankhm_state::stars_enable_w));
mainlatch.q_out_cb<5>().set(m_timeplt_audio, FUNC(timeplt_audio_device::mute_w));
mainlatch.q_out_cb<6>().set(FUNC(tutankhm_state::flip_screen_x_w));
mainlatch.q_out_cb<7>().set(FUNC(tutankhm_state::flip_screen_y_w));
WATCHDOG_TIMER(config, "watchdog");
// video hardware
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(GALAXIAN_PIXEL_CLOCK, GALAXIAN_HTOTAL, GALAXIAN_HBEND, GALAXIAN_HBSTART, GALAXIAN_VTOTAL, GALAXIAN_VBEND, GALAXIAN_VBSTART);
PALETTE(config, m_palette).set_format(1, tutankhm_state::raw_to_rgb_func, 16);
m_screen->set_screen_update(FUNC(tutankhm_state::screen_update));
m_screen->screen_vblank().set(FUNC(tutankhm_state::vblank_irq));
// sound hardware
TIMEPLT_AUDIO(config, m_timeplt_audio);
// blinking frequency is determined by 555 counter with Ra=100k, Rb=10k, C=10uF
TIMER(config, "stars").configure_periodic(FUNC(tutankhm_state::scramble_stars_blink_timer), PERIOD_OF_555_ASTABLE(100000, 10000, 0.00001));
}
/*************************************
*
* ROM definitions
*
*************************************/
/*
Tutankham
CPU/Video Board: KT-3203-1B
Sound Board: KT-5112-2B
*/
ROM_START( tutankhm )
// ROMS located on the KT-3203-1B board.
ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) // 64k for M6809 CPU code + 64k for ROM banks
ROM_LOAD( "m1.1h", 0x0a000, 0x1000, CRC(da18679f) SHA1(8d2a3665db937d0e1d19300ae22277d9db61fcbc) ) // program ROMs
ROM_LOAD( "m2.2h", 0x0b000, 0x1000, CRC(a0f02c85) SHA1(29a78b3ffd6b597772953543b02dd59acf5af38c) )
ROM_LOAD( "3j.3h", 0x0c000, 0x1000, CRC(ea03a1ab) SHA1(27a3cca0595bac642caaf9ee2f276814442c8721) ) // Name guessed
ROM_LOAD( "m4.4h", 0x0d000, 0x1000, CRC(bd06fad0) SHA1(bd10bbb413d8dd362072522e902575d819fa8336) )
ROM_LOAD( "m5.5h", 0x0e000, 0x1000, CRC(bf9fd9b0) SHA1(458ea2ff5eedaaa02e32444dd6004d2eaadbdeab) )
ROM_LOAD( "j6.6h", 0x0f000, 0x1000, CRC(fe079c5b) SHA1(0757490aaa1cea4f4bbe1230d811a0d917f59e52) ) // Name guessed
ROM_LOAD( "c1.1i", 0x10000, 0x1000, CRC(7eb59b21) SHA1(664d3e08df0f3d6690838810b6fe273eec3b7821) ) // graphic ROMs (banked) -- only 9 of 12 are filled
ROM_LOAD( "c2.2i", 0x11000, 0x1000, CRC(6615eff3) SHA1(e8455eab03f66642880595cfa0e9be285bf9fad0) )
ROM_LOAD( "c3.3i", 0x12000, 0x1000, CRC(a10d4444) SHA1(683899e1014ee075b16d9d2610c3c5b5c4efedb6) )
ROM_LOAD( "c4.4i", 0x13000, 0x1000, CRC(58cd143c) SHA1(e4ab27c09858cede478f4ed3ac6d7392e383a470) )
ROM_LOAD( "c5.5i", 0x14000, 0x1000, CRC(d7e7ae95) SHA1(7068797770a6c42dc733b253bf6b7376eb6e071e) )
ROM_LOAD( "c6.6i", 0x15000, 0x1000, CRC(91f62b82) SHA1(2a78039ee63226978544142727d00d1ccc6d2ab4) )
ROM_LOAD( "c7.7i", 0x16000, 0x1000, CRC(afd0a81f) SHA1(cf10308a0fa4ffabd0deeb186b5602468028ff92) )
ROM_LOAD( "c8.8i", 0x17000, 0x1000, CRC(dabb609b) SHA1(773b99b670db41a9de58d14b51f81ce0c446ca84) )
ROM_LOAD( "c9.9i", 0x18000, 0x1000, CRC(8ea9c6a6) SHA1(fe1b299f8760fc5418179d3569932ee2c4dff461) )
// the other banks (1900-1fff) are empty
// ROMS located on the KT-5112-2B board.
ROM_REGION( 0x3000, "timeplt_audio:tpsound", ROMREGION_ERASE00 ) // 12k for Z80 sound CPU code
ROM_LOAD( "s1.7a", 0x0000, 0x1000, CRC(b52d01fa) SHA1(9b6cf9ea51d3a87c174f34d42a4b1b5f38b48723) )
ROM_LOAD( "s2.8a", 0x1000, 0x1000, CRC(9db5c0ce) SHA1(b5bc1d89a7f7d7a0baae64390c37ee11f69a0e76) )
ROM_END
/*
A PCB picture shows the following label format:
TUTANKHAM (C)
RA1 1I (25)
1982 STERN
Visible ROM labels on the KT-3203-1B PCB:
TUTANKHAM RA1 1I (25) 1982 STERN
TUTANKHAM RA1 2I (25) 1982 STERN
TUTANKHAM RA1 3I (25) 1982 STERN
TUTANKHAM RA1 4I (25) 1982 STERN
TUTANKHAM RA1 5I (25) 1982 STERN
TUTANKHAM RA1 6I (25) 1982 STERN
TUTANKHAM RA1 7I (25) 1982 STERN
TUTANKHAM RA1 8I (25) 1982 STERN
TUTANKHAM RA1 9I (25) 1982 STERN
ROMs labels on the KT-5112-2B PCB:
TUTANKHAM RA1 8A (26) 1982 STERN (in socket 7A)
TUTANKHAM RA1 10E (25) 1982 STERN (in socket 8A)
*/
ROM_START( tutankhms )
// ROMS located on the KT-3203-1B board.
ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) // 64k for M6809 CPU code + 64k for ROM banks
ROM_LOAD( "m1.1h", 0x0a000, 0x1000, CRC(da18679f) SHA1(8d2a3665db937d0e1d19300ae22277d9db61fcbc) ) // program ROMs
ROM_LOAD( "m2.2h", 0x0b000, 0x1000, CRC(a0f02c85) SHA1(29a78b3ffd6b597772953543b02dd59acf5af38c) )
ROM_LOAD( "3a.3h", 0x0c000, 0x1000, CRC(2d62d7b1) SHA1(910718f36735f2614cda0c3a1abdfa995d82dbd2) )
ROM_LOAD( "m4.4h", 0x0d000, 0x1000, CRC(bd06fad0) SHA1(bd10bbb413d8dd362072522e902575d819fa8336) )
ROM_LOAD( "m5.5h", 0x0e000, 0x1000, CRC(bf9fd9b0) SHA1(458ea2ff5eedaaa02e32444dd6004d2eaadbdeab) )
ROM_LOAD( "a6.6h", 0x0f000, 0x1000, CRC(c43b3865) SHA1(3112cf831c5b6318337e591ccb0003aeab722652) )
ROM_LOAD( "c1.1i", 0x10000, 0x1000, CRC(7eb59b21) SHA1(664d3e08df0f3d6690838810b6fe273eec3b7821) ) // graphic ROMs (banked) -- only 9 of 12 are filled
ROM_LOAD( "c2.2i", 0x11000, 0x1000, CRC(6615eff3) SHA1(e8455eab03f66642880595cfa0e9be285bf9fad0) )
ROM_LOAD( "c3.3i", 0x12000, 0x1000, CRC(a10d4444) SHA1(683899e1014ee075b16d9d2610c3c5b5c4efedb6) )
ROM_LOAD( "c4.4i", 0x13000, 0x1000, CRC(58cd143c) SHA1(e4ab27c09858cede478f4ed3ac6d7392e383a470) )
ROM_LOAD( "c5.5i", 0x14000, 0x1000, CRC(d7e7ae95) SHA1(7068797770a6c42dc733b253bf6b7376eb6e071e) )
ROM_LOAD( "c6.6i", 0x15000, 0x1000, CRC(91f62b82) SHA1(2a78039ee63226978544142727d00d1ccc6d2ab4) )
ROM_LOAD( "c7.7i", 0x16000, 0x1000, CRC(afd0a81f) SHA1(cf10308a0fa4ffabd0deeb186b5602468028ff92) )
ROM_LOAD( "c8.8i", 0x17000, 0x1000, CRC(dabb609b) SHA1(773b99b670db41a9de58d14b51f81ce0c446ca84) )
ROM_LOAD( "c9.9i", 0x18000, 0x1000, CRC(8ea9c6a6) SHA1(fe1b299f8760fc5418179d3569932ee2c4dff461) )
// the other banks (1900-1fff) are empty
// ROMS located on the KT-5112-2B board.
ROM_REGION( 0x3000, "timeplt_audio:tpsound", ROMREGION_ERASE00 ) // 12k for Z80 sound CPU code
ROM_LOAD( "s1.7a", 0x0000, 0x1000, CRC(b52d01fa) SHA1(9b6cf9ea51d3a87c174f34d42a4b1b5f38b48723) )
ROM_LOAD( "s2.8a", 0x1000, 0x1000, CRC(9db5c0ce) SHA1(b5bc1d89a7f7d7a0baae64390c37ee11f69a0e76) )
ROM_END
/*
Tutankham bootleg.
CPU/Video Board: TK-707A
Sound Board: TK-707B
*/
ROM_START( tutankhmb )
// ROMS located on the TK-707A board.
ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASE00 ) // 64k for M6809 CPU code + 64k for ROM banks
ROM_LOAD( "t1.1h", 0x0a000, 0x1000, CRC(37794533) SHA1(cd69b625bfb0ffa54bd07528967edcba64375d15) ) // program ROMs
ROM_LOAD( "t2.2h", 0x0b000, 0x1000, CRC(a0f02c85) SHA1(29a78b3ffd6b597772953543b02dd59acf5af38c) )
ROM_LOAD( "t3.3h", 0x0c000, 0x1000, CRC(0c41e644) SHA1(01b3bd6decfff21dbd7c5c799a3e077a157ca13b) )
ROM_LOAD( "t4.4h", 0x0d000, 0x1000, CRC(bd06fad0) SHA1(bd10bbb413d8dd362072522e902575d819fa8336) )
ROM_LOAD( "t5.5h", 0x0e000, 0x1000, CRC(bf9fd9b0) SHA1(458ea2ff5eedaaa02e32444dd6004d2eaadbdeab) )
ROM_LOAD( "t6.6h", 0x0f000, 0x1000, CRC(39cd1b22) SHA1(fe93ffd1f9e17a7d54235f20f62fb7958c5e35b8) )
ROM_LOAD( "t7.1i", 0x10000, 0x1000, CRC(55deafe2) SHA1(15475346b009936a4c17bf0b334a8e3f43b6c903) ) // graphic ROMs (banked) -- only 9 of 12 are filled
ROM_LOAD( "t8.2i", 0x11000, 0x1000, CRC(6615eff3) SHA1(e8455eab03f66642880595cfa0e9be285bf9fad0) )
ROM_LOAD( "t9.3i", 0x12000, 0x1000, CRC(a10d4444) SHA1(683899e1014ee075b16d9d2610c3c5b5c4efedb6) )
ROM_LOAD( "t10.4i", 0x13000, 0x1000, CRC(58cd143c) SHA1(e4ab27c09858cede478f4ed3ac6d7392e383a470) )
ROM_LOAD( "t11.5i", 0x14000, 0x1000, CRC(d7e7ae95) SHA1(7068797770a6c42dc733b253bf6b7376eb6e071e) )
ROM_LOAD( "t12.6i", 0x15000, 0x1000, CRC(dcde1109) SHA1(737b5a715e7705db9d38507d5c9f4b2d52c2c08f) )
ROM_LOAD( "t13.7i", 0x16000, 0x1000, CRC(c7250b9a) SHA1(fb7b00dcd1361e2d0e20801b439734e13ca68f94) )
ROM_LOAD( "t14.8i", 0x17000, 0x1000, CRC(685a623e) SHA1(6879edbc3ef0a854d08a8c2d9850970c2a54162f) )
ROM_LOAD( "t15.9i", 0x18000, 0x1000, CRC(8ea9c6a6) SHA1(fe1b299f8760fc5418179d3569932ee2c4dff461) )
// the other banks (1900-1fff) are empty
// ROMS located on the TK-707B board.
ROM_REGION( 0x3000, "timeplt_audio:tpsound", ROMREGION_ERASE00 ) // 12k for Z80 sound CPU code
ROM_LOAD( "t16.7a", 0x0000, 0x1000, CRC(b52d01fa) SHA1(9b6cf9ea51d3a87c174f34d42a4b1b5f38b48723) )
ROM_LOAD( "t17.8a", 0x1000, 0x1000, CRC(9db5c0ce) SHA1(b5bc1d89a7f7d7a0baae64390c37ee11f69a0e76) )
ROM_END
/*************************************
*
* Game drivers
*
*************************************/
GAME( 1982, tutankhm, 0, tutankhm, tutankhm, tutankhm_state, empty_init, ROT90, "Konami", "Tutankham", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS)
GAME( 1982, tutankhms, tutankhm, tutankhm, tutankhm, tutankhm_state, empty_init, ROT90, "Konami (Stern Electronics license)", "Tutankham (Stern Electronics)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS)
GAME( 1982, tutankhmb, tutankhm, tutankhm, tutankhm, tutankhm_state, empty_init, ROT90, "bootleg", "Tutankham (bootleg)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS)

103
Arcade_MiST/Konami Framebuffer/Useful Information/tutankhm.h
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@@ -1,103 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Mirko Buffoni
#ifndef MAME_KONAMI_TUTANKHM_H
#define MAME_KONAMI_TUTANKHM_H
#pragma once
#include "timeplt_a.h"
#include "emupal.h"
#include "machine/timer.h"
#include "screen.h"
static constexpr int GALAXIAN_XSCALE = 3;
static constexpr XTAL GALAXIAN_MASTER_CLOCK(18.432_MHz_XTAL);
static constexpr XTAL GALAXIAN_PIXEL_CLOCK(GALAXIAN_XSCALE*GALAXIAN_MASTER_CLOCK / 3);
static constexpr int GALAXIAN_HTOTAL = (384 * GALAXIAN_XSCALE);
static constexpr int GALAXIAN_HBEND = (0 * GALAXIAN_XSCALE);
//static constexpr int GALAXIAN_H0START = (6*GALAXIAN_XSCALE)
//static constexpr int GALAXIAN_HBSTART = (264*GALAXIAN_XSCALE)
static constexpr int GALAXIAN_H0START = (0 * GALAXIAN_XSCALE);
static constexpr int GALAXIAN_HBSTART = (256 * GALAXIAN_XSCALE);
static constexpr int GALAXIAN_VTOTAL = (264);
static constexpr int GALAXIAN_VBEND = (16);
static constexpr int GALAXIAN_VBSTART = (224 + 16);
class tutankhm_state : public driver_device
{
public:
tutankhm_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_palette(*this, "palette"),
m_screen(*this, "screen"),
m_timeplt_audio(*this, "timeplt_audio"),
m_stars_config(*this, "STARS"),
m_videoram(*this, "videoram"),
m_scroll(*this, "scroll"),
m_mainbank(*this, "mainbank")
{
}
void tutankhm(machine_config &config);
protected:
virtual void machine_start() override ATTR_COLD;
virtual void machine_reset() override ATTR_COLD;
virtual void video_start() override ATTR_COLD;
/* devices */
required_device<cpu_device> m_maincpu;
required_device<palette_device> m_palette;
required_device<screen_device> m_screen;
optional_device<timeplt_audio_device> m_timeplt_audio;
optional_ioport m_stars_config;
/* memory pointers */
required_shared_ptr<uint8_t> m_videoram;
optional_shared_ptr<uint8_t> m_scroll;
required_memory_bank m_mainbank;
/* video-related */
tilemap_t *m_bg_tilemap = nullptr;
uint8_t m_flipscreen_x = 0;
uint8_t m_flipscreen_y = 0;
/* misc */
uint8_t m_irq_toggle = 0;
uint8_t m_irq_enable = 0;
uint8_t m_star_mode = 0;
rgb_t m_star_color[64];
std::unique_ptr<uint8_t[]> m_stars;
uint8_t m_stars_enabled = 0;
uint8_t m_stars_blink_state = 0;
void irq_enable_w(int state);
void bankselect_w(uint8_t data);
void coin_counter_1_w(int state);
void coin_counter_2_w(int state);
void sound_on_w(uint8_t data);
void flip_screen_x_w(int state);
void flip_screen_y_w(int state);
uint32_t screen_update_bootleg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
uint32_t screen_update_scramble(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void vblank_irq(int state);
void galaxian_palette(palette_device &palette);
static rgb_t raw_to_rgb_func(u32 raw);
TIMER_DEVICE_CALLBACK_MEMBER(scramble_stars_blink_timer);
void stars_enable_w(uint8_t data);
void stars_init();
void stars_init_scramble();
void stars_init_bootleg();
void stars_draw_row(bitmap_rgb32 &bitmap, int maxx, int y, uint32_t star_offs);
void scramble_draw_stars(bitmap_rgb32 &bitmap, const rectangle &cliprect, int maxx);
void scramble_draw_background(bitmap_rgb32 &bitmap, const rectangle &cliprect);
void main_map(address_map &map) ATTR_COLD;
};
#endif // MAME_KONAMI_TUTANKHM_H

444
Arcade_MiST/Konami Framebuffer/Useful Information/tutankhm_v.cpp
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@@ -1,444 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Mirko Buffoni
/***************************************************************************
video.c
Functions to emulate the video hardware of the machine.
***************************************************************************/
#include "emu.h"
#include "tutankhm.h"
#include "video/resnet.h"
static constexpr uint32_t STAR_RNG_PERIOD = (1 << 17) - 1;
static constexpr unsigned RGB_MAXIMUM = 224;
/*************************************
*
* Write handlers
*
*************************************/
void tutankhm_state::flip_screen_x_w(int state)
{
m_flipscreen_x = state;
}
void tutankhm_state::flip_screen_y_w(int state)
{
m_flipscreen_y = state;
}
/*************************************
*
* Video update
*
*************************************/
uint32_t tutankhm_state::screen_update_bootleg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
bitmap.fill(rgb_t::black(), cliprect);
int const xorx = m_flipscreen_x ? 255 : 0;
int const xory = m_flipscreen_y ? 255 : 0;
for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
{
uint32_t *const dst = &bitmap.pix(y);
for (int x = cliprect.min_x / GALAXIAN_XSCALE; x <= cliprect.max_x / GALAXIAN_XSCALE; x++)
{
uint8_t const effx = x ^ xorx;
uint8_t const yscroll = (effx < 192 && m_scroll.found()) ? *m_scroll : 0;
uint8_t const effy = (y ^ xory) + yscroll;
uint8_t const vrambyte = m_videoram[effy * 128 + effx / 2];
uint8_t const shifted = vrambyte >> (4 * (effx & 1));
uint8_t const blink_state = m_stars_blink_state & 3;
bool enab = false;
switch (blink_state)
{
case 0: enab = true; break;
case 1: enab = BIT(y, 0); break;
case 2: enab = BIT(y, 1); break;
case 3: enab = BIT(~x, 3); break;
}
//enab &= (((y>>1) ^ (x >> 3)) & 1);
int const offset = y * 384 + x + 84;
uint8_t const star = m_stars[offset % STAR_RNG_PERIOD];
if (m_stars_enabled && enab && BIT(~shifted, 1) && BIT(star, 7)
&& x > 63)
{
bitmap.pix(y, GALAXIAN_XSCALE*x + 0) = m_star_color[star & 0x3f];
bitmap.pix(y, GALAXIAN_XSCALE*x + 1) = m_star_color[star & 0x3f];
bitmap.pix(y, GALAXIAN_XSCALE*x + 2) = m_star_color[star & 0x3f];
}
else
{
auto color = m_palette->pen_color(shifted & 0x0f);
u32 *const dbase = dst + x * GALAXIAN_XSCALE;
if(shifted || dbase[0] == 0xff000000) dbase[0] = color;
if(shifted || dbase[1] == 0xff000000) dbase[1] = color;
if(shifted || dbase[2] == 0xff000000) dbase[2] = color;
}
}
}
return 0;
}
uint32_t tutankhm_state::screen_update_scramble(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
scramble_draw_background(bitmap, cliprect);
int const xorx = m_flipscreen_x ? 255 : 0;
int const xory = m_flipscreen_y ? 255 : 0;
for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
{
uint32_t *const dst = &bitmap.pix(y);
for (int x = cliprect.min_x / GALAXIAN_XSCALE; x <= cliprect.max_x / GALAXIAN_XSCALE; x++)
{
uint8_t const effx = x ^ xorx;
uint8_t const yscroll = (effx < 192 && m_scroll.found()) ? *m_scroll : 0;
uint8_t const effy = (y ^ xory) + yscroll;
uint8_t const vrambyte = m_videoram[effy * 128 + effx / 2];
uint8_t const shifted = vrambyte >> (4 * (effx & 1));
auto color = m_palette->pen_color(shifted & 0x0f);
u32 *const dbase = dst + x * GALAXIAN_XSCALE;
if(shifted || dbase[0] == 0xff000000) dbase[0] = color;
if(shifted || dbase[1] == 0xff000000) dbase[1] = color;
if(shifted || dbase[2] == 0xff000000) dbase[2] = color;
}
}
return 0;
}
uint32_t tutankhm_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
u8 const mode = m_stars_config.read_safe(m_star_mode);
if (mode != m_star_mode)
{
m_star_mode = mode;
stars_init();
}
if (m_star_mode)
return screen_update_scramble(screen, bitmap, cliprect);
else
return screen_update_bootleg(screen, bitmap, cliprect);
}
/*************************************
*
* Copied from galaxian.cpp video code
*
*************************************/
rgb_t tutankhm_state::raw_to_rgb_func(u32 raw)
{
static const int rgb_resistances[3] = { 1000, 470, 220 };
/*
Sprite/tilemap colors are mapped through a color PROM as follows:
bit 7 -- 220 ohm resistor -- BLUE
-- 470 ohm resistor -- BLUE
-- 220 ohm resistor -- GREEN
-- 470 ohm resistor -- GREEN
-- 1 kohm resistor -- GREEN
-- 220 ohm resistor -- RED
-- 470 ohm resistor -- RED
bit 0 -- 1 kohm resistor -- RED
Note that not all boards have this configuration. Namco PCBs may
have 330 ohm resistors instead of 220, but the default setup has
also been used by Namco.
In parallel with these resistors are a pair of 150 ohm and 100 ohm
resistors on each R,G,B component that are connected to the star
generator.
And in parallel with the whole mess are a set of 100 ohm resistors
on each R,G,B component that are enabled when a shell/missile is
enabled.
When computing weights, we use RGB_MAXIMUM as the maximum to give
headroom for stars and shells/missiles. This is not fully accurate,
but if we included all possible sources in parallel, the brightness
of the main game would be very low to allow for all the oversaturation
of the stars and shells/missiles.
*/
double rweights[3], gweights[3], bweights[2];
compute_resistor_weights(0, RGB_MAXIMUM, -1.0,
3, &rgb_resistances[0], rweights, 470, 0,
3, &rgb_resistances[0], gweights, 470, 0,
2, &rgb_resistances[1], bweights, 470, 0);
// decode the palette first
uint8_t bit0, bit1, bit2;
// red component
bit0 = BIT(raw, 0);
bit1 = BIT(raw, 1);
bit2 = BIT(raw, 2);
int const r = combine_weights(rweights, bit0, bit1, bit2);
// green component
bit0 = BIT(raw, 3);
bit1 = BIT(raw, 4);
bit2 = BIT(raw, 5);
int const g = combine_weights(gweights, bit0, bit1, bit2);
// blue component
bit0 = BIT(raw, 6);
bit1 = BIT(raw, 7);
int const b = combine_weights(bweights, bit0, bit1);
return rgb_t(r, g, b);
}
void tutankhm_state::galaxian_palette(palette_device &palette)
{
/*
The maximum sprite/tilemap resistance is ~130 Ohms with all RGB
outputs enabled (1/(1/1000 + 1/470 + 1/220)). Since we normalized
to RGB_MAXIMUM, this maps RGB_MAXIMUM -> 130 Ohms.
The stars are at 150 Ohms for the LSB, and 100 Ohms for the MSB.
This means the 3 potential values are:
150 Ohms -> RGB_MAXIMUM * 130 / 150
100 Ohms -> RGB_MAXIMUM * 130 / 100
60 Ohms -> RGB_MAXIMUM * 130 / 60
Since we can't saturate that high, we instead approximate this
by compressing the values proportionally into the 194->255 range.
*/
int const minval = RGB_MAXIMUM * 130 / 150;
int const midval = RGB_MAXIMUM * 130 / 100;
int const maxval = RGB_MAXIMUM * 130 / 60;
// compute the values for each of 4 possible star values
uint8_t const starmap[4]{
0,
minval,
minval + (255 - minval) * (midval - minval) / (maxval - minval),
255 };
// generate the colors for the stars
for (int i = 0; i < 64; i++)
{
uint8_t bit0, bit1;
// bit 5 = red @ 150 Ohm, bit 4 = red @ 100 Ohm
bit0 = BIT(i, 5);
bit1 = BIT(i, 4);
int const r = starmap[(bit1 << 1) | bit0];
// bit 3 = green @ 150 Ohm, bit 2 = green @ 100 Ohm
bit0 = BIT(i, 3);
bit1 = BIT(i, 2);
int const g = starmap[(bit1 << 1) | bit0];
// bit 1 = blue @ 150 Ohm, bit 0 = blue @ 100 Ohm
bit0 = BIT(i, 1);
bit1 = BIT(i, 0);
int const b = starmap[(bit1 << 1) | bit0];
// set the RGB color
m_star_color[i] = rgb_t(r, g, b);
}
}
void tutankhm_state::video_start()
{
/* initialize globals */
m_flipscreen_x = 0;
m_flipscreen_y = 0;
/* initialize stars */
m_stars_enabled = 0;
m_stars_blink_state = 0;
stars_init();
galaxian_palette(*m_palette);
}
void tutankhm_state::stars_init()
{
(m_star_mode) ? stars_init_scramble() : stars_init_bootleg();
}
void tutankhm_state::stars_init_bootleg()
{
/* reset the blink and enabled states */
m_stars_enabled = false;
m_stars_blink_state = 0;
/* precalculate the RNG */
m_stars = std::make_unique<uint8_t[]>(STAR_RNG_PERIOD);
uint32_t shiftreg = 0;
for (int i = 0; i < STAR_RNG_PERIOD; i++)
{
int const newbit = ((shiftreg >> 12) ^ ~shiftreg) & 1;
/* stars are enabled if the upper 8 bits are 1 and the new bit is 0 */
int const enabled = ((shiftreg & 0x1fe00) == 0x1fe00) && (newbit == 0);
//int enabled = ((shiftreg & 0x1fe01) == 0x1fe00); // <- scramble
/* color comes from the 6 bits below the top 8 bits */
int const color = (~shiftreg & 0x1f8) >> 3;
/* store the color value in the low 6 bits and the enable in the upper bit */
m_stars[i] = color | (enabled << 7);
/* the LFSR is fed based on the XOR of bit 12 and the inverse of bit 0 */
shiftreg = (shiftreg >> 1) | (newbit << 16);
}
}
void tutankhm_state::stars_init_scramble()
{
/* precalculate the RNG */
m_stars = std::make_unique<uint8_t[]>(STAR_RNG_PERIOD);
uint32_t shiftreg = 0;
for (int i = 0; i < STAR_RNG_PERIOD; i++)
{
uint8_t const shift = 12;
/* stars are enabled if the upper 8 bits are 1 and the low bit is 0 */
int const enabled = ((shiftreg & 0x1fe01) == 0x1fe00);
/* color comes from the 6 bits below the top 8 bits */
int const color = (~shiftreg & 0x1f8) >> 3;
/* store the color value in the low 6 bits and the enable in the upper bit */
m_stars[i] = color | (enabled << 7);
/* the LFSR is fed based on the XOR of bit 12 and the inverse of bit 0 */
//shiftreg = (shiftreg >> 1) | ((((shiftreg >> 12) ^ ~shiftreg) & 1) << 16);
shiftreg = (shiftreg >> 1) | ((((shiftreg >> shift) ^ ~shiftreg) & 1) << 16);
}
}
/*************************************
*
* Star blinking
*
*************************************/
TIMER_DEVICE_CALLBACK_MEMBER(tutankhm_state::scramble_stars_blink_timer)
{
m_stars_blink_state++;
}
void tutankhm_state::stars_draw_row(bitmap_rgb32 &bitmap, int maxx, int y, uint32_t star_offs)
{
uint8_t const flipxor = (m_flipscreen_x ? 0xc0 : 0x00);
/* ensure our star offset is valid */
star_offs %= STAR_RNG_PERIOD;
/* iterate over the specified number of 6MHz pixels */
for (int x = 0; x < maxx; x++)
{
uint8_t const h8q = BIT(~x, 3); // H8 signal is inverted.
/* stars are suppressed unless V1 ^ H8 == 1 */
bool enable_star = BIT(y ^ h8q, 0);
uint8_t const blink_state = m_stars_blink_state & 3;
bool enab = false;
switch (blink_state)
{
case 0: enab = true; break;
case 1: enab = BIT(y, 0); break;
case 2: enab = BIT(y, 1); break;
case 3: enab = h8q; break; // H8 signal is inverted.
}
enable_star &= (enab && ((x & 0xc0) ^ flipxor) != 0xc0);
/*
The RNG clock is the master clock (18MHz) ANDed with the pixel clock (6MHz).
The divide-by-3 circuit that produces the pixel clock generates a square wave
with a 2/3 duty cycle, so the result of the AND generates a clock like this:
_ _ _ _ _ _ _ _
MASTER: _| |_| |_| |_| |_| |_| |_| |_| |
_______ _______ ______
PIXEL: _| |___| |___|
_ _ _ _ _ _
RNG: _| |_| |_____| |_| |_____| |_| |
Thus for each pixel, there are 3 master clocks and 2 RNG clocks, and the RNG
is clocked asymmetrically. To simulate this, we expand the horizontal screen
size by 3 and handle the first RNG clock with one pixel and the second RNG
clock with two pixels.
*/
uint8_t star;
/* first RNG clock: one pixel */
star = m_stars[star_offs++];
if (star_offs >= STAR_RNG_PERIOD)
star_offs = 0;
if (enable_star && BIT(star, 7))
bitmap.pix(y, GALAXIAN_XSCALE*x + 0) = m_star_color[star & 0x3f];
/* second RNG clock: two pixels */
star = m_stars[star_offs++];
if (star_offs >= STAR_RNG_PERIOD)
star_offs = 0;
if (enable_star && BIT(star, 7))
{
bitmap.pix(y, GALAXIAN_XSCALE*x + 1) = m_star_color[star & 0x3f];
bitmap.pix(y, GALAXIAN_XSCALE*x + 2) = m_star_color[star & 0x3f];
}
}
}
void tutankhm_state::scramble_draw_stars(bitmap_rgb32 &bitmap, const rectangle &cliprect, int maxx)
{
/* update the star origin to the current frame */
//stars_update_origin();
/* render stars if enabled */
if (m_stars_enabled)
{
/* iterate over scanlines */
for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
{
stars_draw_row(bitmap, maxx, y, y * 512);
}
}
}
void tutankhm_state::scramble_draw_background(bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
/* blue background - 390 ohm resistor */
bitmap.fill(rgb_t::black(), cliprect);
scramble_draw_stars(bitmap, cliprect, 256);
}
void tutankhm_state::stars_enable_w(uint8_t data)
{
if (BIT(m_stars_enabled ^ data, 0))
{
// m_screen->update_now();
m_screen->update_partial(m_screen->vpos());
}
m_stars_enabled = BIT(data, 0);
}

15
Arcade_MiST/Konami Framebuffer/clean.bat
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@@ -1,15 +0,0 @@
@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

514
Arcade_MiST/Konami Framebuffer/rtl/TimePilot_SND.sv
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@@ -1,514 +0,0 @@
//============================================================================
//
// Time Pilot sound PCB model
// Copyright (C) 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
module TimePilot_SND
(
input reset,
input clk_49m, //Actual frequency: 49.152MHz
input [15:0] dip_sw,
input [1:0] coin, //0 = coin 1, 1 = coin 2
input [1:0] start_buttons, //0 = Player 1, 1 = Player 2
input [3:0] p1_joystick, p2_joystick, //0 = up, 1 = down, 2 = left, 3 = right
input p1_fire,
input p2_fire,
input btn_service,
input cpubrd_A5, cpubrd_A6,
input cs_controls_dip1, cs_dip2,
input irq_trigger, cs_sounddata,
input [7:0] cpubrd_Din,
output [7:0] controls_dip,
output signed [15:0] sound,
//This input serves to select different fractional dividers to acheive 1.789772MHz for the sound Z80 and AY-3-8910s
//depending on whether Time Pilot runs with original or underclocked timings to normalize sync frequencies
input underclock,
input ep7_cs_i,
output [12:0] Sound_Rom_Addr,
input [7:0] Sound_Rom_Data,
input [24:0] ioctl_addr,
input [7:0] ioctl_data,
input ioctl_wr
//The sound board contains a video passthrough but video will instead be tapped
//straight from the CPU board implementation (this passthrough is redundant for
//an FPGA implementation)
);
//------------------------------------------------------- Signal outputs -------------------------------------------------------//
//Multiplex controls and DIP switches to be output to CPU board
assign controls_dip = cs_controls_dip1 ? controls_dip1:
cs_dip2 ? dip_sw[15:8]:
8'hFF;
//------------------------------------------------------- Clock division -------------------------------------------------------//
//Generate clock enables for sound data and IRQ logic, and DC offset removal
reg [8:0] div = 9'd0;
always_ff @(posedge clk_49m) begin
div <= div + 9'd1;
end
wire cen_3m = !div[3:0];
wire cen_dcrm = !div;
//Generate 1.789772MHz clock enable for Z80 and AY-3-8910s, clock enable for AY-3-8910 timer
//(uses Jotego's fractional clock divider from JTFRAME)
wire [9:0] sound_cen_n = underclock ? 10'd31 : 10'd30;
wire [9:0] sound_cen_m = underclock ? 10'd843 : 10'd824;
wire cen_1m79, cen_timer;
jtframe_frac_cen #(10) sound_cen
(
.clk(clk_49m),
.n(sound_cen_n),
.m(sound_cen_m),
.cen({cen_timer, 8'bZZZZZZZZ, cen_1m79})
);
//------------------------------------------------------------ CPU -------------------------------------------------------------//
//Sound CPU - Zilog Z80 (uses T80s version of the T80 soft core)
wire [15:0] sound_A;
wire [7:0] sound_Dout;
wire n_m1, n_mreq, n_iorq, n_rd, n_wr, n_rfsh;
T80s C8
(
.RESET_n(reset),
.CLK(clk_49m),
.CEN(cen_1m79),
.INT_n(n_irq),
.M1_n(n_m1),
.MREQ_n(n_mreq),
.IORQ_n(n_iorq),
.RD_n(n_rd),
.WR_n(n_wr),
.RFSH_n(n_rfsh),
.A(sound_A),
.DI(sound_Din),
.DO(sound_Dout)
);
//Address decoding for Z80
wire cs_soundrom = (~n_mreq & n_rfsh & (sound_A[15:13] == 3'b000));
wire cs_soundram = (~n_mreq & n_rfsh & (sound_A[15:12] == 4'b0011));
wire cs_ay1_1 = (~n_mreq & n_rfsh & (sound_A[15:12] == 4'b0100));
wire cs_ay1_2 = (~n_mreq & n_rfsh & (sound_A[15:12] == 4'b0101));
wire cs_ay2_1 = (~n_mreq & n_rfsh & (sound_A[15:12] == 4'b0110));
wire cs_ay2_2 = (~n_mreq & n_rfsh & (sound_A[15:12] == 4'b0111));
wire cs_lpf = ~(n_wr | ~sound_A[15]);
//Multiplex data input to Z80
wire [7:0] sound_Din =
cs_soundrom ? eprom7_D:
(cs_soundram & n_wr) ? sndram_D:
(~ay1_bdir & ay1_bc1) ? ay1_D:
(~ay2_bdir & ay2_bc1) ? ay2_D:
8'hFF;
//Sound ROM
assign Sound_Rom_Addr = sound_A[12:0];
wire [7:0] eprom7_D = Sound_Rom_Data;
//eprom_7 A6
//(
// .ADDR(sound_A[12:0]),
// .CLK(clk_49m),
// .DATA(eprom7_D),
// .ADDR_DL(ioctl_addr),
// .CLK_DL(clk_49m),
// .DATA_IN(ioctl_data),
// .CS_DL(ep7_cs_i),
// .WR(ioctl_wr)
//);
//Sound RAM (lower 4 bits)
wire [7:0] sndram_D;
spram #(4, 10) A2
(
.clk(clk_49m),
.we(cs_soundram & ~n_wr),
.addr(sound_A[9:0]),
.data(sound_Dout[3:0]),
.q(sndram_D[3:0])
);
//Sound RAM (upper 4 bits)
spram #(4, 10) A3
(
.clk(clk_49m),
.we(cs_soundram & ~n_wr),
.addr(sound_A[9:0]),
.data(sound_Dout[7:4]),
.q(sndram_D[7:4])
);
//Generate Z80 interrupts
wire irq_clr = (~reset | ~(n_iorq | n_m1));
reg n_irq = 1;
always_ff @(posedge clk_49m or posedge irq_clr) begin
if(irq_clr)
n_irq <= 1;
else if(cen_3m && irq_trigger)
n_irq <= 0;
end
//--------------------------------------------------- Controls & DIP switches --------------------------------------------------//
//Multiplex player inputs and DIP switch bank 1
wire [7:0] controls_dip1 = ({cpubrd_A6, cpubrd_A5} == 2'b00) ? {3'b111, start_buttons, btn_service, coin}:
({cpubrd_A6, cpubrd_A5} == 2'b01) ? {3'b111, p1_fire, p1_joystick[1:0], p1_joystick[3:2]}:
({cpubrd_A6, cpubrd_A5} == 2'b10) ? {3'b111, p2_fire, p2_joystick[1:0], p2_joystick[3:2]}:
({cpubrd_A6, cpubrd_A5} == 2'b11) ? dip_sw[7:0]:
8'hFF;
//--------------------------------------------------------- Sound chips --------------------------------------------------------//
//Generate BC1 and BDIR signals for both AY-3-8910s
wire ay1_bdir = ~(~cs_ay1_2 & (n_wr | ~cs_ay1_1));
wire ay1_bc1 = ~(~cs_ay1_2 & (n_rd | ~cs_ay1_1));
wire ay2_bdir = ~(~cs_ay2_2 & (n_wr | ~cs_ay2_1));
wire ay2_bc1 = ~(~cs_ay2_2 & (n_rd | ~cs_ay2_1));
//AY-3-8910 timer (code adapted from MiSTer-X's Gyruss core, which uses an identical timer)
reg [3:0] timer_sel;
wire [3:0] timer_val;
always_comb begin
case(timer_sel)
0: timer_val = 4'h0;
1: timer_val = 4'h1;
2: timer_val = 4'h2;
3: timer_val = 4'h3;
4: timer_val = 4'h4;
5: timer_val = 4'h9;
6: timer_val = 4'hA;
7: timer_val = 4'hB;
8: timer_val = 4'hA;
9: timer_val = 4'hD;
default: timer_val = 0;
endcase
end
reg [3:0] timer = 4'd0;
always_ff @(posedge clk_49m) begin
if(cen_timer) begin
timer <= timer_val;
timer_sel <= (timer_sel == 4'd9) ? 4'd0 : (timer_sel + 4'd1);
end
end
//Latch sound data coming in from CPU board
reg [7:0] sound_D = 8'd0;
always_ff @(posedge clk_49m) begin
if(!reset)
sound_D <= 8'd0;
else if(cen_3m && cs_sounddata)
sound_D <= cpubrd_Din;
end
//Sound chip 1 (AY-3-8910 - uses JT49 by Jotego)
wire [7:0] ay1_D;
wire [7:0] ay1A_raw, ay1B_raw, ay1C_raw;
jt49_bus #(.COMP(3'b100)) F7
(
.rst_n(reset),
.clk(clk_49m),
.clk_en(cen_1m79),
.bdir(ay1_bdir),
.bc1(ay1_bc1),
.din(sound_Dout),
.sel(1),
.dout(ay1_D),
.A(ay1A_raw),
.B(ay1B_raw),
.C(ay1C_raw),
.IOA_in(sound_D),
.IOB_in({timer, 4'b0000})
);
//Sound chip 2 (AY-3-8910 - uses JT49 by Jotego)
wire [7:0] ay2_D;
wire [7:0] ay2A_raw, ay2B_raw, ay2C_raw;
jt49_bus #(.COMP(3'b100)) F8
(
.rst_n(reset),
.clk(clk_49m),
.clk_en(cen_1m79),
.bdir(ay2_bdir),
.bc1(ay2_bc1),
.din(sound_Dout),
.sel(1),
.dout(ay2_D),
.A(ay2A_raw),
.B(ay2B_raw),
.C(ay2C_raw)
);
//----------------------------------------------------- Final audio output -----------------------------------------------------//
//Apply gain and remove DC offset from AY-3-8910s (uses jt49_dcrm2 from JT49 by Jotego for DC offset removal)
wire signed [15:0] ay1A_dcrm, ay1B_dcrm, ay1C_dcrm, ay2A_dcrm, ay2B_dcrm, ay2C_dcrm;
jt49_dcrm2 #(16) dcrm_ay1A
(
.clk(clk_49m),
.cen(cen_dcrm),
.rst(~reset),
.din({3'd0, ay1A_raw, 5'd0}),
.dout(ay1A_dcrm)
);
jt49_dcrm2 #(16) dcrm_ay1B
(
.clk(clk_49m),
.cen(cen_dcrm),
.rst(~reset),
.din({3'd0, ay1B_raw, 5'd0}),
.dout(ay1B_dcrm)
);
jt49_dcrm2 #(16) dcrm_ay1C
(
.clk(clk_49m),
.cen(cen_dcrm),
.rst(~reset),
.din({3'd0, ay1C_raw, 5'd0}),
.dout(ay1C_dcrm)
);
jt49_dcrm2 #(16) dcrm_ay2A
(
.clk(clk_49m),
.cen(cen_dcrm),
.rst(~reset),
.din({3'd0, ay2A_raw, 5'd0}),
.dout(ay2A_dcrm)
);
jt49_dcrm2 #(16) dcrm_ay2B
(
.clk(clk_49m),
.cen(cen_dcrm),
.rst(~reset),
.din({3'd0, ay2B_raw, 5'd0}),
.dout(ay2B_dcrm)
);
jt49_dcrm2 #(16) dcrm_ay2C
(
.clk(clk_49m),
.cen(cen_dcrm),
.rst(~reset),
.din({3'd0, ay2C_raw, 5'd0}),
.dout(ay2C_dcrm)
);
//Time Pilot's AY-3-8910s contain selectable low-pass filters with the following cutoff frequencies:
//3386.28Hz, 723.43Hz, 596.09Hz
//Model this here (the PCB handles this via 3 74HC4066 switching ICs located at A2, A3 and A4)
wire signed [15:0] ay1A_light, ay1A_med, ay1A_heavy, ay1B_light, ay1B_med, ay1B_heavy, ay1C_light, ay1C_med, ay1C_heavy;
wire signed [15:0] ay2A_light, ay2A_med, ay2A_heavy, ay2B_light, ay2B_med, ay2B_heavy, ay2C_light, ay2C_med, ay2C_heavy;
wire signed [15:0] ay1A_sound, ay1B_sound, ay1C_sound, ay2A_sound, ay2B_sound, ay2C_sound;
tp_lpf_light ay1A_lpf_light
(
.clk(clk_49m),
.reset(~reset),
.in(ay1A_dcrm),
.out(ay1A_light)
);
tp_lpf_medium ay1A_lpf_medium
(
.clk(clk_49m),
.reset(~reset),
.in(ay1A_dcrm),
.out(ay1A_med)
);
tp_lpf_heavy ay1A_lpf_heavy
(
.clk(clk_49m),
.reset(~reset),
.in(ay1A_dcrm),
.out(ay1A_heavy)
);
tp_lpf_light ay1B_lpf_light
(
.clk(clk_49m),
.reset(~reset),
.in(ay1B_dcrm),
.out(ay1B_light)
);
tp_lpf_medium ay1B_lpf_medium
(
.clk(clk_49m),
.reset(~reset),
.in(ay1B_dcrm),
.out(ay1B_med)
);
tp_lpf_heavy ay1B_lpf_heavy
(
.clk(clk_49m),
.reset(~reset),
.in(ay1B_dcrm),
.out(ay1B_heavy)
);
tp_lpf_light ay1C_lpf_light
(
.clk(clk_49m),
.reset(~reset),
.in(ay1C_dcrm),
.out(ay1C_light)
);
tp_lpf_medium ay1C_lpf_medium
(
.clk(clk_49m),
.reset(~reset),
.in(ay1C_dcrm),
.out(ay1C_med)
);
tp_lpf_heavy ay1C_lpf_heavy
(
.clk(clk_49m),
.reset(~reset),
.in(ay1C_dcrm),
.out(ay1C_heavy)
);
tp_lpf_light ay2A_lpf_light
(
.clk(clk_49m),
.reset(~reset),
.in(ay2A_dcrm),
.out(ay2A_light)
);
tp_lpf_medium ay2A_lpf_medium
(
.clk(clk_49m),
.reset(~reset),
.in(ay2A_dcrm),
.out(ay2A_med)
);
tp_lpf_heavy ay2A_lpf_heavy
(
.clk(clk_49m),
.reset(~reset),
.in(ay2A_dcrm),
.out(ay2A_heavy)
);
tp_lpf_light ay2B_lpf_light
(
.clk(clk_49m),
.reset(~reset),
.in(ay2B_dcrm),
.out(ay2B_light)
);
tp_lpf_medium ay2B_lpf_medium
(
.clk(clk_49m),
.reset(~reset),
.in(ay2B_dcrm),
.out(ay2B_med)
);
tp_lpf_heavy ay2B_lpf_heavy
(
.clk(clk_49m),
.reset(~reset),
.in(ay2B_dcrm),
.out(ay2B_heavy)
);
tp_lpf_light ay2C_lpf_light
(
.clk(clk_49m),
.reset(~reset),
.in(ay2C_dcrm),
.out(ay2C_light)
);
tp_lpf_medium ay2C_lpf_medium
(
.clk(clk_49m),
.reset(~reset),
.in(ay2C_dcrm),
.out(ay2C_med)
);
tp_lpf_heavy ay2C_lpf_heavy
(
.clk(clk_49m),
.reset(~reset),
.in(ay2C_dcrm),
.out(ay2C_heavy)
);
//Latch low-pass filter control lines
reg [1:0] ay1_filter_A = 2'd0;
reg [1:0] ay1_filter_B = 2'd0;
reg [1:0] ay1_filter_C = 2'd0;
reg [1:0] ay2_filter_A = 2'd0;
reg [1:0] ay2_filter_B = 2'd0;
reg [1:0] ay2_filter_C = 2'd0;
always_ff @(posedge clk_49m) begin
if(cen_1m79 && cs_lpf) begin
ay1_filter_A <= {sound_A[6], sound_A[7]};
ay1_filter_B <= {sound_A[8], sound_A[9]};
ay1_filter_C <= {sound_A[10], sound_A[11]};
ay2_filter_A <= {sound_A[0], sound_A[1]};
ay2_filter_B <= {sound_A[2], sound_A[3]};
ay2_filter_C <= {sound_A[4], sound_A[5]};
end
end
always_comb begin
case(ay1_filter_A)
2'b00: ay1A_sound = ay1A_dcrm;
2'b01: ay1A_sound = ay1A_light;
2'b10: ay1A_sound = ay1A_med;
2'b11: ay1A_sound = ay1A_heavy;
endcase
case(ay1_filter_B)
2'b00: ay1B_sound = ay1B_dcrm;
2'b01: ay1B_sound = ay1B_light;
2'b10: ay1B_sound = ay1B_med;
2'b11: ay1B_sound = ay1B_heavy;
endcase
case(ay1_filter_C)
2'b00: ay1C_sound = ay1C_dcrm;
2'b01: ay1C_sound = ay1C_light;
2'b10: ay1C_sound = ay1C_med;
2'b11: ay1C_sound = ay1C_heavy;
endcase
case(ay2_filter_A)
2'b00: ay2A_sound = ay2A_dcrm;
2'b01: ay2A_sound = ay2A_light;
2'b10: ay2A_sound = ay2A_med;
2'b11: ay2A_sound = ay2A_heavy;
endcase
case(ay2_filter_B)
2'b00: ay2B_sound = ay2B_dcrm;
2'b01: ay2B_sound = ay2B_light;
2'b10: ay2B_sound = ay2B_med;
2'b11: ay2B_sound = ay2B_heavy;
endcase
case(ay2_filter_C)
2'b00: ay2C_sound = ay2C_dcrm;
2'b01: ay2C_sound = ay2C_light;
2'b10: ay2C_sound = ay2C_med;
2'b11: ay2C_sound = ay2C_heavy;
endcase
end
//Mix all AY-3-8910s (this game has variable low-pass filtering based on how loud the PCB's volume dial is set and will be modeled
//externally)
//Also invert the phase as the original PCB uses an op-amp wired as an inverting amplifier prior to the power amp
assign sound = 16'hFFFF - (ay1A_sound + ay1B_sound + ay1C_sound + ay2A_sound + ay2B_sound + ay2C_sound);
endmodule

289
Arcade_MiST/Konami Framebuffer/rtl/Tutankham.sv
View File

@@ -1,289 +0,0 @@
module Tutankham(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Tutankham;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"O6,Service,Off,On;",
"OOR,CRT H adjust,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
"OSV,CRT V adjust,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
"DIP;",
"T0,Reset;",
"V,",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire [1:0] orientation = 'b10;
assign LED = ~ioctl_downl;
assign AUDIO_R = AUDIO_L;
assign SDRAM_CLK = clk_sys;
assign SDRAM_CKE = 1;
wire clk_sys;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys),//49.152
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
wire [6:0] core_mod;// for Juno First(later)
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status ),
.core_mod (core_mod )
);
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [12:0] Sound_Rom_Addr;
wire [15:0] CPU_Addr;
wire [7:0] CPU_Rom_Data, GFX_Rom_Data, Sound_Rom_Data;
data_io data_io(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
reg port1_req, port2_req;
sdram #(49) sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_sys ),
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( 16'hffff),//ioctl_downl ? 16'hffff : {2'b00, main_rom_addr[14:1]} ),
.cpu1_q ( CPU_Rom_Data ),
.cpu2_addr ( 16'hffff),//ioctl_downl ? 16'hffff : Sound_Rom_Addr[12:1] + 16'h3000 ),
.cpu2_q ( Sound_Rom_Data ),
.cpu3_addr ( 16'hffff),//),
.cpu3_q ( GFX_Rom_Data ),
// port2 for sprite graphics
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( ), // merge sprite roms to 32-bit wide words
.port2_ds ( ),
.port2_we ( ),
.port2_d ( ),
.port2_q ( ),
.sp_addr ( 16'hffff),//),
.sp_q ( )
);
// ROM download controller
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_sys) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
wire [15:0] audio;
wire hs, vs, cs, hb, vb;
wire blankn = ~(hb | vb);
wire [4:0] r,g,b;
wire [ 3:0] hoffset, voffset;
assign { voffset, hoffset } = status[31:24];
Tutankham_TOP Tutankham_TOP_inst
(
.reset(~reset),
.clk_49m(clk_sys),
.juno(0),
.coin({m_coin2, m_coin1}),
.start_buttons({m_two_players, m_one_player}),
.p1_joystick(),//todo
.p2_joystick(),
.p1_fire(m_fireA),
.p2_fire(m_fire2A),
.m_fire1_l(m_fireB),
.m_fire1_r(m_fireC),
.m_flash1(m_fireD),
.m_fire2_l(m_fire2B),
.m_fire2_r(m_fire2C),
.m_flash2(m_fire2D),
.btn_service(status[6]),
// .dip_sw(dip_sw_sig) , // input [15:0] dip_sw_sig
.video_hsync(hs),
.video_vsync(vs),
.video_csync(cs),
.video_hblank(hb),
.video_vblank(vb),
.ce_pix(),
.video_r(r),
.video_g(g),
.video_b(b),
.sound(audio),
.h_center(hoffset),
.v_center(voffset),
//Rom Data
.CPU_Addr(CPU_Addr),
.CPU_Rom_Data(CPU_Rom_Data),
.GFX_Rom_Data(GFX_Rom_Data),
.Sound_Rom_Addr(Sound_Rom_Addr),
.Sound_Rom_Data(Sound_Rom_Data),
.ioctl_addr(ioctl_addr),
.ioctl_data(ioctl_dout),
.ioctl_wr(ioctl_wr),
.ioctl_index(ioctl_index),
.pause(0),
.underclock(0),
.hs_address(),
.hs_data_in(),
.hs_data_out(),
.hs_write()
);
mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(11)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? b : 0 ),
.HSync ( ~hs ),
.VSync ( ~vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.ce_divider ( 1'b0 ),
// .rotate ( { orientation[1], rotate } ),
.scandoubler_disable( scandoublerD ),
.scanlines ( scanlines ),
.blend ( blend ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
dac #(.C_bits(16))dac(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i({~audio[15],audio[14:0]}),
.dac_o(AUDIO_L)
);
// Arcade inputs
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

625
Arcade_MiST/Konami Framebuffer/rtl/Tutankham_CPU.sv
View File

@@ -1,625 +0,0 @@
//============================================================================
//
// Tutankham main PCB model (based on Time Pilot core)
// Copyright (C) 2021 Ace, Artemio Urbina & RTLEngineering
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Module declaration, I/O ports
module Tutankham_CPU
(
input reset,
input clk_49m, //Actual frequency: 49.152MHz
input juno,
output [4:0] red, green, blue, //15-bit RGB, 5 bits per color
output video_hsync, video_vsync, video_csync, //CSync not needed for MISTer
output video_hblank, video_vblank,
output ce_pix,
input [7:0] controls_dip,
input [15:0] dip_sw,
input [2:0] p1_fire_ext, // {flash_bomb, fire_right, fire_left}
input [2:0] p2_fire_ext, // {flash_bomb, fire_right, fire_left}
input [3:0] p1_joy, // {down, up, right, left} active-HIGH
input [3:0] p2_joy, // {down, up, right, left} active-HIGH
output [7:0] cpubrd_Dout,
output reg [15:0] CPU_Addr,
input [7:0] CPU_Rom_Data,
input [7:0] GFX_Rom_Data,
output cs_sounddata, irq_trigger,
output cs_dip2, cs_controls_dip1,
//Screen centering (alters HSync, VSync and VBlank timing in the Konami 082 to reposition the video output)
input [3:0] h_center, v_center,
//ROM chip selects for main program ROMs (6x 4KB)
input rom_m1_cs_i, rom_m2_cs_i, rom_m3_cs_i,
input rom_m4_cs_i, rom_m5_cs_i, rom_m6_cs_i,
//ROM chip selects for banked graphics ROMs (9x 4KB)
input bank0_cs_i, bank1_cs_i, bank2_cs_i,
input bank3_cs_i, bank4_cs_i, bank5_cs_i,
input bank6_cs_i, bank7_cs_i, bank8_cs_i,
input [24:0] ioctl_addr,
input [7:0] ioctl_data,
input ioctl_wr,
input pause,
input [15:0] hs_address,
input [7:0] hs_data_in,
output [7:0] hs_data_out,
input hs_write
);
//------------------------------------------------------- Signal outputs -------------------------------------------------------//
//Assign active high HBlank and VBlank outputs
assign video_hblank = hblk;
assign video_vblank = vblk;
//Output pixel clock enable
assign ce_pix = cen_6m;
//Output select lines for player inputs and DIP switches to sound board
assign cs_controls_dip1 = cs_in0 | cs_in1 | cs_in2 | cs_dsw1;
assign cs_dip2 = cs_dsw2;
//Output primary MC6809E address lines A5 and A6 to sound board
// Swap A5/A6 so the sound board's {A6,A5} mux matches Tutankham's address map:
// 0x8180 (IN0): A[6:5]=00 → mux 00 = coins/start ✓
// 0x81A0 (IN1): A[6:5]=01 → need mux 01 for P1, so swap: output A5=A[6], A6=A[5]
// 0x81C0 (IN2): A[6:5]=10 → need mux 10 for P2, so swap: output A5=A[6], A6=A[5]
// 0x81E0 (DSW1): A[6:5]=11 → mux 11 = dip_sw ✓ (swap doesn't matter for 00/11)
//assign cpubrd_A5 = cpu_A[6];
//assign cpubrd_A6 = cpu_A[5];
// Latch CPU data when writing sound commands — the data bus changes
// on the next cycle but sound board needs it held for cen_3m sampling.
reg [7:0] sound_data_latch = 8'd0;
always_ff @(posedge clk_49m) begin
if(!reset)
sound_data_latch <= 8'd0;
else if(cs_soundcmd)
sound_data_latch <= cpu_Dout;
end
assign cpubrd_Dout = sound_data_latch;
// Latch sound command strobe — hold until sound board's cen_3m can sample it
// The CPU write is brief; the sound board samples on cen_3m which is every 16 clocks.
// We need to stretch the pulse so it's guaranteed to be seen.
reg cs_sounddata_latch = 0;
reg [3:0] snd_data_hold = 0;
always_ff @(posedge clk_49m) begin
if(!reset) begin
cs_sounddata_latch <= 0;
snd_data_hold <= 0;
end
else begin
if(cs_soundcmd) begin
cs_sounddata_latch <= 1;
snd_data_hold <= 4'd15; // Hold for 16 clocks (guarantees one cen_3m)
end
else if(snd_data_hold > 0)
snd_data_hold <= snd_data_hold - 4'd1;
else
cs_sounddata_latch <= 0;
end
end
assign cs_sounddata = cs_sounddata_latch;
// Sound IRQ trigger — stretch pulse so sound board's cen_3m can catch it
reg sound_irq = 0;
reg [3:0] snd_irq_hold = 0;
always_ff @(posedge clk_49m) begin
if(!reset) begin
sound_irq <= 0;
snd_irq_hold <= 0;
end
else begin
if(cs_soundon) begin
sound_irq <= 1;
snd_irq_hold <= 4'd15;
end
else if(snd_irq_hold > 0)
snd_irq_hold <= snd_irq_hold - 4'd1;
else
sound_irq <= 0;
end
end
assign irq_trigger = sound_irq;
//------------------------------------------------------- Clock division -------------------------------------------------------//
//Generate 6.144MHz and 3.072MHz clock enables
reg [3:0] div = 4'd0;
always_ff @(posedge clk_49m) begin
div <= div + 4'd1;
end
wire cen_6m = !div[2:0];
wire cen_3m = !div;
//MC6809E E and Q clock generation from existing div[3:0] counter
//div rolls over every 16 clocks: E toggles at 49.152MHz/16 = 3.072MHz, E freq = 1.536MHz
//Q leads E by 90 degrees (4 system clocks)
reg cpu_E = 0;
reg cpu_Q = 0;
always_ff @(posedge clk_49m) begin
if(~pause) begin
case(div[3:0])
4'd0: begin cpu_E <= 1; cpu_Q <= 0; end
4'd4: begin cpu_E <= 1; cpu_Q <= 1; end
4'd8: begin cpu_E <= 0; cpu_Q <= 1; end
4'd12: begin cpu_E <= 0; cpu_Q <= 0; end
default: ;
endcase
end
end
//------------------------------------------------------------ CPUs ------------------------------------------------------------//
//Primary CPU - Motorola MC6809E ( Konami1 for Juno First)
wire [15:0] cpu_A, cpu_A_J, cpu_A_T;
wire [7:0] cpu_Dout, cpu_Dout_J, cpu_Dout_T;
wire cpu_RnW, cpu_RnW_J, cpu_RnW_T;
assign CPU_Addr = juno ? cpu_A_J : cpu_A_T;//to Lazy, maybe later
assign cpu_A = juno ? cpu_A_J : cpu_A_T;
assign cpu_Dout = juno ? cpu_Dout_J : cpu_Dout_T;
assign cpu_RnW = juno ? cpu_RnW_J : cpu_RnW_T;
mc6809e E3
(
.D(cpu_Din),
.DOut(cpu_Dout_T),
.ADDR(cpu_A_T),
.RnW(cpu_RnW_T),
.E(cpu_E),
.Q(cpu_Q),
.nIRQ(n_irq),
.nFIRQ(1'b1),
.nNMI(1'b1),
.nHALT(1'b1),
.nRESET(reset)
);
KONAMI1 KONAMI1(
.CLK(clk_49m),
.fallE_en(cpu_E),
.fallQ_en(cpu_Q),
.D(cpu_Din),
.DOut(cpu_Dout_J),
.ADDR(cpu_A_J),
.RnW(cpu_RnW_J),
.nIRQ(n_irq),
.nFIRQ(1'b1),
.nNMI(1'b1),
.nHALT(1'b1),
.nRESET(reset)
);
//------------------------------------------------------ Address decoding ------------------------------------------------------//
// tutankham
// -- DIPS2 $8160
// -- IN0 $8180
// -- IN1 $81A0
// -- IN2 $81C0
// -- DIPS1 $81E0
// -- Interrupt Enable $8200
// -- RAM $8800-$8FFF
// junofrst
// -- DIPS2 $8010
// -- IN0 $8020
// -- IN1 $8024
// -- IN2 $8028
// -- DIPS1 $802C
// -- Interrupt Enable $8030
// -- blitter $8073
// -- RAM $8100-$8FFF
//Tutankham memory map
wire n_cs_videoram = ~(cpu_A[15] == 1'b0); // 0x0000-0x7FFF (32KB video RAM)
// NOTE: There is no general work RAM at 0x8000-0x87FF in Tutankham.
// That region is entirely I/O (palette, scroll, controls, mainlatch, etc.)
// The only RAM in the 0x8xxx range is at 0x8800-0x8FFF (workram2).
// Keeping this wire for hiscore compatibility but it should never be used in the data mux.
wire n_cs_workram = 1'b1; // Disabled — no work RAM at 0x8000-0x87FF
wire n_cs_workram2 = ~(cpu_A[15:11] == 5'b10001); // 0x8800-0x8FFF (2KB work RAM expansion)
wire n_cs_bankrom = ~(cpu_A[15:12] == 4'b1001); // 0x9000-0x9FFF (4KB banked ROM window)
wire n_cs_mainrom = ~(cpu_A[15:13] == 3'b101 |
cpu_A[15:13] == 3'b110 |
cpu_A[15:13] == 3'b111); // 0xA000-0xFFFF (24KB main ROM)
//Tutankham I/O decoding (memory-mapped in 0x8000-0x87FF region)
wire cs_palette = (cpu_A[15:4] == 12'h800); // 0x8000-0x800F (palette RAM)
wire cs_scroll = (cpu_A[15:4] == 12'h810); // 0x8100-0x810F (scroll register)
wire cs_watchdog = (cpu_A[15:4] == 12'h812); // 0x8120 (watchdog)
wire cs_dsw2 = (cpu_A[15:4] == 12'h816); // 0x8160 (DIP SW2)
wire cs_in0 = (cpu_A[15:4] == 12'h818); // 0x8180 (IN0: coins, start)
wire cs_in1 = (cpu_A[15:4] == 12'h81A); // 0x81A0 (IN1: P1 controls)
wire cs_in2 = (cpu_A[15:4] == 12'h81C); // 0x81C0 (IN2: P2 controls)
wire cs_dsw1 = (cpu_A[15:4] == 12'h81E); // 0x81E0 (DIP SW1)
wire cs_mainlatch = (cpu_A[15:3] == 13'h1040) & ~cpu_RnW; // 0x8200-0x8207 (main latch)
wire cs_banksel_wr = juno ? ((cpu_A[15:0] == 16'h8060) & ~cpu_RnW) : ((cpu_A[15:8] == 8'h83) & ~cpu_RnW); // 0x8300 (bank select) (8060 for Juno First)
wire cs_soundon = (cpu_A[15:8] == 8'h86) & ~cpu_RnW; // 0x8600 (sound enable)
wire cs_soundcmd = (cpu_A[15:8] == 8'h87) & ~cpu_RnW; // 0x8700 (sound command)
wire cs_blitter;
//ROM bank select register (0x8300)
reg [3:0] rom_bank = 4'd0;
always_ff @(posedge clk_49m) begin
if(!reset)
rom_bank <= 4'd0;
else if(cen_3m && cs_banksel_wr)
rom_bank <= cpu_Dout[3:0];
end
//------------------------------------------------------ CPU data input mux ---------------------------------------------------//
// Controls and DIP switch data comes from the sound board via controls_dip input.
// The sound board muxes the correct data based on cs_controls_dip1, cs_dip2,
// cpubrd_A5, and cpubrd_A6 signals.
// I/O registers must be checked first (they're in the 0x8000-0x87FF range)
// Controls/DIP data comes from the sound board via controls_dip
wire [7:0] cpu_Din = cs_palette ? palette_D :
cs_scroll ? scroll_reg :
cs_watchdog ? 8'hFF :
cs_in1 ? {1'b1, ~p1_fire_ext[2], ~p1_fire_ext[1], ~p1_fire_ext[0],
~p1_joy[3], ~p1_joy[2], ~p1_joy[1], ~p1_joy[0]} :
cs_in2 ? {1'b1, ~p2_fire_ext[2], ~p2_fire_ext[1], ~p2_fire_ext[0],
~p2_joy[3], ~p2_joy[2], ~p2_joy[1], ~p2_joy[0]} :
(cs_dsw2 | cs_in0 | cs_dsw1) ? controls_dip :
~n_cs_workram2 ? workram2_D :
~n_cs_bankrom ? bank_rom_D :
~n_cs_mainrom ? mainrom_D :
~n_cs_videoram ? videoram_D :
8'hFF;
//------------------------------------------------------- Main program ROMs ----------------------------------------------------//
//Main program ROMs (m1.1h through j6.6h, 6x 4KB = 24KB at 0xA000-0xFFFF)
//wire [7:0] rom_m1_D, rom_m2_D, rom_m3_D, rom_m4_D, rom_m5_D, rom_m6_D;
//
wire [7:0] mainrom_D = CPU_Rom_Data;
//wire [7:0] mainrom_D = (cpu_A[15:12] == 4'hA) ? rom_m1_D :
// (cpu_A[15:12] == 4'hB) ? rom_m2_D :
// (cpu_A[15:12] == 4'hC) ? rom_m3_D :
// (cpu_A[15:12] == 4'hD) ? rom_m4_D :
// (cpu_A[15:12] == 4'hE) ? rom_m5_D :
// (cpu_A[15:12] == 4'hF) ? rom_m6_D :
// 8'hFF;
//eprom_4k rom_m1 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(rom_m1_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(rom_m1_cs_i), .WR(ioctl_wr));
//eprom_4k rom_m2 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(rom_m2_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(rom_m2_cs_i), .WR(ioctl_wr));
//eprom_4k rom_m3 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(rom_m3_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(rom_m3_cs_i), .WR(ioctl_wr));
//eprom_4k rom_m4 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(rom_m4_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(rom_m4_cs_i), .WR(ioctl_wr));
//eprom_4k rom_m5 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(rom_m5_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(rom_m5_cs_i), .WR(ioctl_wr));
//eprom_4k rom_m6 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(rom_m6_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(rom_m6_cs_i), .WR(ioctl_wr));
//------------------------------------------------------ Banked graphics ROMs --------------------------------------------------//
//Banked graphics ROMs (c1.1i through c9.9i, 9x 4KB)
//Bank select register chooses which 4KB bank is visible at 0x9000-0x9FFF
wire [7:0] bank0_D, bank1_D, bank2_D, bank3_D, bank4_D;
wire [7:0] bank5_D, bank6_D, bank7_D, bank8_D;
wire [7:0] bank_rom_D = GFX_Rom_Data;//todo bank handling
//wire [7:0] bank_rom_D = (rom_bank == 4'd0) ? bank0_D :
// (rom_bank == 4'd1) ? bank1_D :
// (rom_bank == 4'd2) ? bank2_D :
// (rom_bank == 4'd3) ? bank3_D :
// (rom_bank == 4'd4) ? bank4_D :
// (rom_bank == 4'd5) ? bank5_D :
// (rom_bank == 4'd6) ? bank6_D :
// (rom_bank == 4'd7) ? bank7_D :
// (rom_bank == 4'd8) ? bank8_D :
// 8'hFF;
//eprom_4k bank0 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank0_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank0_cs_i), .WR(ioctl_wr));
//eprom_4k bank1 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank1_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank1_cs_i), .WR(ioctl_wr));
//eprom_4k bank2 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank2_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank2_cs_i), .WR(ioctl_wr));
//eprom_4k bank3 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank3_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank3_cs_i), .WR(ioctl_wr));
//eprom_4k bank4 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank4_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank4_cs_i), .WR(ioctl_wr));
//eprom_4k bank5 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank5_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank5_cs_i), .WR(ioctl_wr));
//eprom_4k bank6 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank6_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank6_cs_i), .WR(ioctl_wr));
//eprom_4k bank7 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank7_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank7_cs_i), .WR(ioctl_wr));
//eprom_4k bank8 (.ADDR(cpu_A[11:0]), .CLK(clk_49m), .DATA(bank8_D),
// .ADDR_DL(ioctl_addr), .CLK_DL(clk_49m), .DATA_IN(ioctl_data),
// .CS_DL(bank8_cs_i), .WR(ioctl_wr));
//Blitter ToDo
//blitter blitter_inst
//(
// .clk(clk_49m),
// .rst(reset),
// .clk_1M5_en(clk_1M5_en_sig) , // input clk_1M5_en_sig
// .blitter_cs(blitter_cs_sig) , // input blitter_cs_sig
// .cpu_a(cpu_a_sig) , // input [1:0] cpu_a_sig
// .cpu_d_o(cpu_d_o_sig) , // input [7:0] cpu_d_o_sig
// .cpu_rw(cpu_rw_sig) , // input cpu_rw_sig
// .cpu_ba(cpu_ba_sig) , // input cpu_ba_sig
// .cpu_bs(cpu_bs_sig) , // input cpu_bs_sig
// .vram_cs(vram_cs_sig) , // input vram_cs_sig
// .blitter_copy(blitter_copy_sig) , // input blitter_copy_sig
// .blitter_d_o(blitter_d_o_sig) , // input [7:0] blitter_d_o_sig
// .cpu_halt(cpu_halt_sig) , // output cpu_halt_sig
// .vram_a(vram_a_sig) , // output [15:0] vram_a_sig
// .vram_d_i(vram_d_i_sig) , // output [7:0] vram_d_i_sig
// .vram_wr(vram_wr_sig) // output [1:0] vram_wr_sig
//);
//------------------------------------------------------------ RAM ------------------------------------------------------------//
// Work RAM at 0x8000-0x87FF does not exist in Tutankham hardware.
// Hiscore support uses the 0x8800-0x8FFF work RAM (workram2) instead.
//Work RAM (0x8800-0x8FFF, 2KB) — the only general-purpose RAM in the I/O region
wire [7:0] workram2_D;
dpram_dc #(.widthad_a(11)) workram2
(
.clock_a(clk_49m),
.wren_a(~n_cs_workram2 & ~cpu_RnW),
.address_a(cpu_A[10:0]),
.data_a(cpu_Dout),
.q_a(workram2_D),
.clock_b(clk_49m),
.wren_b(hs_write),
.address_b(hs_address[10:0]),
.data_b(hs_data_in),
.q_b(hs_data_out)
);
// Scroll register (0x8100, 1 byte readable/writable)
reg [7:0] scroll_reg = 8'd0;
always_ff @(posedge clk_49m) begin
if(cen_6m && cs_scroll && ~cpu_RnW)
scroll_reg <= cpu_Dout;
end
// Palette register file (0x8000-0x800F, 16 entries × 8 bits)
// Uses registers instead of SPRAM so video scanout can read simultaneously with CPU
reg [7:0] palette_regs [0:15];
initial begin
integer i;
for (i = 0; i < 16; i = i + 1)
palette_regs[i] = 8'd0;
end
always_ff @(posedge clk_49m) begin
if(cs_palette && ~cpu_RnW)
palette_regs[cpu_A[3:0]] <= cpu_Dout;
end
wire [7:0] palette_D = palette_regs[cpu_A[3:0]]; // CPU read-back path
//Video RAM (0x0000-0x7FFF, 32KB) - dual port: A=CPU, B=video scanout
wire [7:0] videoram_D;
wire [7:0] videoram_vout;
// Apply flip and scroll to VRAM read coordinates (matching MAME screen_update)
wire [7:0] eff_x = pix_x ^ {8{flip_x}};
wire [7:0] scroll_y = (eff_x < 8'd192) ? scroll_reg : 8'd0;
wire [7:0] eff_y = (v_cnt[7:0] ^ {8{flip_y}}) + scroll_y;
wire [14:0] vram_rd_addr = {eff_y, eff_x[7:1]};
dpram_dc #(.widthad_a(15)) videoram
(
.clock_a(clk_49m),
.address_a(cpu_A[14:0]),
.data_a(cpu_Dout),
.wren_a(~n_cs_videoram & ~cpu_RnW),
.q_a(videoram_D),
.clock_b(clk_49m),
.address_b(vram_rd_addr),
.q_b(videoram_vout)
);
//--------------------------------------------------------- Main latch ---------------------------------------------------------//
reg irq_enable = 0;
reg flip_x = 0;
reg flip_y = 0;
reg stars_enable = 0;
reg sound_mute = 0;
always_ff @(posedge clk_49m) begin
if(!reset) begin
irq_enable <= 0;
flip_x <= 0;
flip_y <= 0;
stars_enable <= 0;
sound_mute <= 0;
end
else if(cen_3m) begin
if(cs_mainlatch)
case(cpu_A[2:0])
3'b000: irq_enable <= cpu_Dout[0]; // LS259 Q0: IRQ enable
3'b001: ; // PAY OUT - unused
3'b010: ; // Coin counter 2
3'b011: ; // Coin counter 1
3'b100: stars_enable <= cpu_Dout[0]; // Stars enable (LS259 Q4)
3'b101: sound_mute <= cpu_Dout[0]; // Sound mute (LS259 Q5)
3'b110: flip_x <= cpu_Dout[0]; // Flip screen X (LS259 Q6)
3'b111: flip_y <= cpu_Dout[0]; // Flip screen Y (LS259 Q7)
endcase
end
end
//Generate VBlank IRQ for MC6809E
// MAME: IRQ fires every other vblank frame when irq_enable is set.
// IRQ is cleared when irq_enable is written to 0.
// ALL n_irq logic is in this single always_ff to avoid multiple-driver errors.
reg n_irq = 1;
reg irq_toggle = 0;
reg vblank_irq_en_last = 0;
always_ff @(posedge clk_49m) begin
if(!reset) begin
n_irq <= 1;
irq_toggle <= 0;
vblank_irq_en_last <= 0;
end
else if(cen_6m) begin
vblank_irq_en_last <= vblank_irq_en;
// Clear IRQ when irq_enable is turned off (matches MAME irq_enable_w)
if(!irq_enable)
n_irq <= 1;
// Detect rising edge of vblank_irq_en pulse from k082
else if(vblank_irq_en && !vblank_irq_en_last) begin
irq_toggle <= ~irq_toggle;
if(!irq_toggle) // Fire on every other vblank
n_irq <= 0;
end
end
end
//-------------------------------------------------------- Video timing --------------------------------------------------------//
//Konami 082 custom chip - responsible for all video timings
wire vblk, vblank_irq_en, h256;
wire [8:0] h_cnt;
wire [7:0] v_cnt;
k082 F5
(
.reset(1),
.clk(clk_49m),
.cen(cen_6m),
.h_center(h_center),
.v_center(v_center),
.n_vsync(video_vsync),
.sync(video_csync),
.n_hsync(video_hsync),
.vblk(vblk),
.vblk_irq_en(vblank_irq_en),
.h1(h_cnt[0]),
.h2(h_cnt[1]),
.h4(h_cnt[2]),
.h8(h_cnt[3]),
.h16(h_cnt[4]),
.h32(h_cnt[5]),
.h64(h_cnt[6]),
.h128(h_cnt[7]),
.n_h256(h_cnt[8]),
.h256(h256),
.v1(v_cnt[0]),
.v2(v_cnt[1]),
.v4(v_cnt[2]),
.v8(v_cnt[3]),
.v16(v_cnt[4]),
.v32(v_cnt[5]),
.v64(v_cnt[6]),
.v128(v_cnt[7])
);
//--------------------------------------------------------- Starfield ----------------------------------------------------------//
// MC_STARS expects real clock signals, not narrow clock enables.
// div[2] = ~6.144 MHz square wave (49.152/8), div[1] = ~12.288 MHz (49.152/4)
// These have proper 50% duty cycle, matching Moon Cresta's 6/12 MHz clocks.
wire [1:0] star_r, star_g, star_b;
MC_STARS stars_gen
(
.I_CLK_12M(div[1]),
.I_CLK_6M(div[2]),
.I_H_FLIP(flip_x),
.I_V_SYNC(~video_vsync),
// .I_8HF(h_cnt[3] ^ flip_x),
// .I_256HnX(h256),
.I_8HF(pix_x[3] ^ flip_x),
.I_256HnX(1'b1),
// .I_256HnX(pix_x[7]),
.I_1VF(v_cnt[0] ^ flip_y),
.I_2V(v_cnt[1]),
.I_STARS_ON(stars_enable),
.I_STARS_OFFn(1'b1),
.I_PAUSEn(~pause),
.O_R(star_r),
.O_G(star_g),
.O_B(star_b),
.O_NOISE()
);
//----------------------------------------------------- Final video output -----------------------------------------------------//
//Generate HBlank (active high) while the horizontal counter is between 141 and 268
wire hblk = (h_cnt > 140 && h_cnt < 269);
// Generate a 0-255 pixel X counter synchronized to the visible window
// Visible pixels: h_cnt 269-511 (243 px), then 128-140 (13 px) = 256 total
// Use h_cnt offset so pixel 0 aligns with h_cnt=269
// Visible pixels: h_cnt 269-511 (243 px), then 128-140 (13 px) = 256 total
// Must produce continuous pix_x 0-255 across the wrap at h_cnt 511→128
// h_cnt 269-511: h_cnt[8]=1 (for 269-511), pix_x = h_cnt - 269
// h_cnt 128-140: h_cnt[8]=0, pix_x = h_cnt - 128 + 243 = h_cnt + 115
wire [7:0] pix_x = h_cnt[8] ? (h_cnt[7:0] - 8'd13) : (h_cnt[7:0] + 8'd115);
// Framebuffer pixel extraction: 4-bit packed pixels, 2 per byte
wire [3:0] pixel_index = eff_x[0] ? videoram_vout[7:4] : videoram_vout[3:0];
// Palette lookup — convert 4-bit pixel index to RGB via palette registers
// Palette byte format (Galaxian/Konami standard): BBGGGRRR
// bits [2:0] = Red (3 bits, through 1K/470/220 ohm resistors)
// bits [5:3] = Green (3 bits, through 1K/470/220 ohm resistors)
// bits [7:6] = Blue (2 bits, through 470/220 ohm resistors)
wire [7:0] pal_byte = palette_regs[pixel_index];
// Expand to 5-bit per channel for MiSTer output
// Blank output during HBlank and VBlank to prevent ghost pixels
wire active_video = ~hblk & ~vblk;
wire pixel_is_bg = (pixel_index == 4'd0);
wire show_stars = active_video & pixel_is_bg & stars_enable;
assign red = show_stars ? {star_r, star_r[1], 2'b00} :
active_video ? {pal_byte[2:0], pal_byte[2:1]} : 5'd0;
assign green = show_stars ? {star_g, star_g[1], 2'b00} :
active_video ? {pal_byte[5:3], pal_byte[5:4]} : 5'd0;
assign blue = show_stars ? {star_b, star_b[1], 2'b00} :
active_video ? {pal_byte[7:6], pal_byte[7:6], pal_byte[7]} : 5'd0;
endmodule

200
Arcade_MiST/Konami Framebuffer/rtl/Tutankham_TOP.sv
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@@ -1,200 +0,0 @@
//============================================================================
//
// Tutankham top-level module
// Copyright (C) 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Module declaration, I/O ports
module Tutankham_TOP
(
input reset,
input clk_49m, //Actual frequency: 49.152MHz
input juno,
input [1:0] coin, //0 = coin 1, 1 = coin 2
input [1:0] start_buttons, //0 = Player 1, 1 = Player 2
input [3:0] p1_joystick, p2_joystick, //0 = up, 1 = down, 2 = left, 3 = right
input p1_fire,
input p2_fire,
input m_fire1_l, m_fire1_r, m_flash1, // P1: fire left, fire right, flash bomb
input m_fire2_l, m_fire2_r, m_flash2, // P2: fire left, fire right, flash bomb
input btn_service,
input [15:0] dip_sw,
output video_hsync, video_vsync, video_csync,
output video_hblank, video_vblank,
output ce_pix,
output [4:0] video_r, video_g, video_b,
output signed [15:0] sound,
//Screen centering (alters HSync, VSync and VBlank timing in the Konami 082 to reposition the video output)
input [3:0] h_center, v_center,
output [15:0] CPU_Addr,
input [7:0] CPU_Rom_Data,
input [7:0] GFX_Rom_Data,
output [12:0] Sound_Rom_Addr,
input [7:0] Sound_Rom_Data,
input [24:0] ioctl_addr,
input [7:0] ioctl_data,
input ioctl_wr,
input [7:0] ioctl_index,
input pause,
//This input serves to select different fractional dividers to acheive 1.789772MHz for the sound Z80 and AY-3-8910s
//depending on whether Time Pilot runs with original or underclocked timings to normalize sync frequencies
input underclock,
input [15:0] hs_address,
input [7:0] hs_data_in,
output [7:0] hs_data_out,
input hs_write
);
//Linking signals between PCBs
wire /*A5, A6,*/ irq_trigger, cs_sounddata, cs_controls_dip1, cs_dip2;
wire [7:0] controls_dip, cpubrd_D;
//Index-filtered ROM write signals
wire ioctl_wr_cpu = ioctl_wr && (ioctl_index == 8'd0); // Main CPU board (index 0)
wire ioctl_wr_snd = ioctl_wr && (ioctl_index == 8'd1); // Sound board (index 1)
//ROM loader signals for MISTer (loads ROMs from SD card)
wire rom_m1_cs_i, rom_m2_cs_i, rom_m3_cs_i, rom_m4_cs_i, rom_m5_cs_i, rom_m6_cs_i;
wire bank0_cs_i, bank1_cs_i, bank2_cs_i, bank3_cs_i, bank4_cs_i;
wire bank5_cs_i, bank6_cs_i, bank7_cs_i, bank8_cs_i;
//Sound board ROM chip select (index 1, 8KB at 0x0000-0x1FFF)
wire ep7_cs_i = (ioctl_addr < 25'h2000);
//MiSTer data write selector
selector DLSEL
(
.ioctl_addr(ioctl_addr),
.rom_m1_cs(rom_m1_cs_i),
.rom_m2_cs(rom_m2_cs_i),
.rom_m3_cs(rom_m3_cs_i),
.rom_m4_cs(rom_m4_cs_i),
.rom_m5_cs(rom_m5_cs_i),
.rom_m6_cs(rom_m6_cs_i),
.bank0_cs(bank0_cs_i),
.bank1_cs(bank1_cs_i),
.bank2_cs(bank2_cs_i),
.bank3_cs(bank3_cs_i),
.bank4_cs(bank4_cs_i),
.bank5_cs(bank5_cs_i),
.bank6_cs(bank6_cs_i),
.bank7_cs(bank7_cs_i),
.bank8_cs(bank8_cs_i)
);
//Instantiate main PCB
Tutankham_CPU main_pcb
(
.reset(reset),
.clk_49m(clk_49m),
.juno(juno),
.red(video_r),
.green(video_g),
.blue(video_b),
.video_hsync(video_hsync),
.video_vsync(video_vsync),
.video_csync(video_csync),
.video_hblank(video_hblank),
.video_vblank(video_vblank),
.ce_pix(ce_pix),
.h_center(h_center),
.v_center(v_center),
.controls_dip(controls_dip),
.dip_sw(dip_sw),
.p1_fire_ext({m_flash1, m_fire1_r, m_fire1_l}),
.p2_fire_ext({m_flash2, m_fire2_r, m_fire2_l}),
.p1_joy({~p1_joystick[1], ~p1_joystick[0], ~p1_joystick[3], ~p1_joystick[2]}),
.p2_joy({~p2_joystick[1], ~p2_joystick[0], ~p2_joystick[3], ~p2_joystick[2]}),
.cs_sounddata(cs_sounddata),
.irq_trigger(irq_trigger),
.cs_dip2(cs_dip2),
.cs_controls_dip1(cs_controls_dip1),
.rom_m1_cs_i(rom_m1_cs_i),
.rom_m2_cs_i(rom_m2_cs_i),
.rom_m3_cs_i(rom_m3_cs_i),
.rom_m4_cs_i(rom_m4_cs_i),
.rom_m5_cs_i(rom_m5_cs_i),
.rom_m6_cs_i(rom_m6_cs_i),
.bank0_cs_i(bank0_cs_i),
.bank1_cs_i(bank1_cs_i),
.bank2_cs_i(bank2_cs_i),
.bank3_cs_i(bank3_cs_i),
.bank4_cs_i(bank4_cs_i),
.bank5_cs_i(bank5_cs_i),
.bank6_cs_i(bank6_cs_i),
.bank7_cs_i(bank7_cs_i),
.bank8_cs_i(bank8_cs_i),
//Rom Signals
.CPU_Addr(CPU_Addr),
.CPU_Rom_Data(CPU_Rom_Data),
.GFX_Rom_Data(GFX_Rom_Data),
.cpubrd_Dout(cpubrd_D),
.ioctl_addr(ioctl_addr),
.ioctl_wr(ioctl_wr_cpu),
.ioctl_data(ioctl_data),
.pause(pause),
.hs_address(hs_address),
.hs_data_out(hs_data_out),
.hs_data_in(hs_data_in),
.hs_write(hs_write)
);
//Instantiate sound PCB
TimePilot_SND sound_pcb
(
.reset(reset),
.clk_49m(clk_49m),
.irq_trigger(irq_trigger),
.cs_sounddata(cs_sounddata),
.dip_sw(dip_sw),
.coin(coin),
.start_buttons(start_buttons),
.p1_joystick(p1_joystick),
.p2_joystick(p2_joystick),
.p1_fire(~m_fire1_l),
.p2_fire(~m_fire2_l),
.btn_service(btn_service),
.cs_controls_dip1(cs_controls_dip1),
.cs_dip2(cs_dip2),
.cpubrd_A5(CPU_Addr[6]),//swapped? todo
.cpubrd_A6(CPU_Addr[5]),
.cpubrd_Din(cpubrd_D),
.controls_dip(controls_dip),
.sound(sound),
.underclock(underclock),
.Sound_Rom_Addr(Sound_Rom_Addr),
.Sound_Rom_Data(Sound_Rom_Data)
);
endmodule

150
Arcade_MiST/Konami Framebuffer/rtl/blitter.sv
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@@ -1,150 +0,0 @@
module blitter (
input wire clk,
input wire rst,
input wire clk_1M5_en,
input wire blitter_cs,
input wire [1:0] cpu_a,
input wire [7:0] cpu_d_o,
input wire cpu_rw,
input wire cpu_ba,
input wire cpu_bs,
input wire vram_cs,
input wire blitter_copy,
input wire [7:0] blitter_d_o, // VRAM data output
output reg cpu_halt,
output wire [15:0] vram_a,
output wire [7:0] vram_d_i,
output wire [1:0] vram_wr
);
// Blitter Registers
reg [15:0] blitter_src_r;
reg [15:0] blitter_dst_r;
reg blitter_go;
// Internal SM signals
reg blitting;
reg [1:0] blitter_wr;
reg [15:0] blitter_src;
reg [15:0] blitter_dst;
reg [3:0] blitter_d_i;
integer x, y;
// State Encoding
localparam S_IDLE = 3'd0,
S_HALTING = 3'd1,
S_BLIT_0 = 3'd2,
S_BLIT = 3'd3,
S_INC_0 = 3'd4,
S_INC = 3'd5;
reg [2:0] state;
// Blitter Register Process
always @(posedge clk or posedge rst) begin
if (rst) begin
blitter_src_r <= 16'h0;
blitter_dst_r <= 16'h0;
blitter_go <= 1'b0;
end else begin
blitter_go <= 1'b0; // Pulse default
if (clk_1M5_en) begin
if (blitter_cs && !cpu_rw) begin
case (cpu_a[1:0])
2'b00: blitter_dst_r[15:8] <= cpu_d_o;
2'b01: blitter_dst_r[7:0] <= cpu_d_o;
2'b10: blitter_src_r[15:8] <= cpu_d_o;
2'b11: begin
blitter_src_r[7:0] <= cpu_d_o;
blitter_go <= 1'b1;
end
endcase
end
end
end
end
// Blitter State Machine Process
always @(posedge clk or posedge rst) begin
if (rst) begin
cpu_halt <= 1'b0;
blitting <= 1'b0;
blitter_wr <= 2'b00;
state <= S_IDLE;
x <= 0; y <= 0;
end else begin
case (state)
S_IDLE: begin
blitting <= 1'b0;
if (blitter_go) begin
cpu_halt <= 1'b1;
state <= S_HALTING;
end
end
S_HALTING: begin
if (cpu_ba && cpu_bs) begin
blitting <= 1'b1;
blitter_src <= {blitter_src_r[15:2], 2'b00} + 16'd1;
blitter_dst <= blitter_dst_r;
y <= 0;
x <= 0;
state <= S_BLIT_0;
end
end
S_BLIT_0: begin
blitter_d_i <= blitter_src[0] ? blitter_d_o[7:4] : blitter_d_o[3:0];
state <= S_BLIT;
end
S_BLIT: begin
if (blitter_d_i != 4'h0) begin
if (blitter_dst[0]) blitter_wr[1] <= 1'b1;
else blitter_wr[0] <= 1'b1;
end
state <= S_INC_0;
end
S_INC_0: begin
blitter_wr <= 2'b00;
state <= S_INC;
end
S_INC: begin
blitter_src <= blitter_src + 1'b1;
blitter_wr <= 2'b00;
if (x == 15) begin
if (y == 15) begin
cpu_halt <= 1'b0;
state <= S_IDLE;
end else begin
x <= 0;
y <= y + 1;
blitter_dst <= blitter_dst + 16'd241;
state <= S_BLIT_0;
end
end else begin
x <= x + 1;
blitter_dst <= blitter_dst + 16'd1;
state <= S_BLIT_0;
end
end
default: begin
cpu_halt <= 1'b0;
state <= S_IDLE;
end
endcase
end
end
// Video RAM Data Muxing
assign vram_a = (!blitting) ? cpu_a : blitter_dst[16:1];
assign vram_d_i = (!blitting) ? cpu_d_o :
(!blitter_copy) ? 8'h00 : {blitter_d_i, blitter_d_i};
assign vram_wr = (!blitting) ? {2{(vram_cs && clk_1M5_en && !cpu_rw)}} : blitter_wr;
endmodule

35
Arcade_MiST/Konami Framebuffer/rtl/build_id.tcl
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@@ -1,35 +0,0 @@
# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

168
Arcade_MiST/Konami Framebuffer/rtl/custom/k082.sv
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@@ -1,168 +0,0 @@
//============================================================================
//
// SystemVerilog implementation of the Konami 082 custom chip, used by
// several Konami arcade PCBs to generate video timings
// Copyright (C) 2020, 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Chip pinout:
/* _____________
_| |_
reset |_|1 28|_| VCC
_| |_
h1 |_|2 27|_| GND
_| |_
h2 |_|3 26|_| v1
_| |_
h4 |_|4 25|_| v2
_| |_
h8 |_|5 24|_| v4
_| |_
h16 |_|6 23|_| v8
_| |_
h32 |_|7 22|_| v16
_| |_
h64 |_|8 21|_| v32
_| |_
h128 |_|9 20|_| v64
_| |_
n_h256 |_|10 19|_| v128
_| |_
h256 |_|11 18|_| n_vsync
_| |_
VCC |_|12 17|_| sync
_| |_
clk |_|13 16|_| vblk
_| |_
GND |_|14 15|_| n_vblk
|_____________|
Note: Pins 12 and 27 may control other features of the 082 - these, if any, have not
been modelled yet.
*/
module k082
(
input reset, //Active low
input clk,
input cen, //Set to 1 if using this code to replace a real 082
input [3:0] h_center, v_center, //These inputs are additions for screen centering and don't exist on the actual 082
output n_vsync, sync,
output n_hsync, //Not exposed on the original chip
output reg vblk = 1,
output n_vblk,
output reg vblk_irq_en = 0, //This is an extra output not present on the real 082 to signal when to
//trigger a VBlank IRQ (signal is active high)
output h1, h2, h4, h8, h16, h32, h64, h128, h256, n_h256,
output v1, v2, v4, v8, v16, v32, v64, v128
);
//The horizontal and vertical counters are 9 bits wide - delcare them here
reg [8:0] h_cnt = 9'd0;
reg [8:0] v_cnt = 9'd0;
//Define the range of values the vertical counter will count between based on the additional vertical center signal
//Shift the screen up by 1 line when horizontal centering shifts the screen left
wire [8:0] vcnt_start = 9'd248 - v_center;
wire [8:0] vcnt_end = 9'd511 - v_center;
//The horizontal and vertical counters behave as follows at every rising edge of the pixel clock:
//-Start at 0, then count to 511 (both counters increment by 1 when the horizontal counter is set to 48)
//-Horizontal counter resets to 128 for a total of 384 horizontal lines
//-Vertical counter resets to 248 for a total of 264 vertical lines (adjustable with added vertical center signal)
//-Vertical counter increments when the horizontal counter equals 176
//-VBlank is active when the horizontal counter is between 495 - 511 and 248 - 270
//Model this behavior here
always_ff @(posedge clk or negedge reset) begin
if(!reset) begin
h_cnt <= 9'd0;
v_cnt <= 9'd0;
end
else if(cen) begin
case(h_cnt)
48: begin
v_cnt <= v_cnt + 9'd1;
h_cnt <= h_cnt + 9'd1;
end
176: begin
h_cnt <= h_cnt + 9'd1;
case(v_cnt)
16: begin
vblk <= 0;
v_cnt <= v_cnt + 9'd1;
end
271: begin
vblk <= 0;
v_cnt <= v_cnt + 9'd1;
end
495: begin
vblk <= 1;
vblk_irq_en <= 1;
v_cnt <= v_cnt + 9'd1;
end
vcnt_end: v_cnt <= vcnt_start;
default: v_cnt <= v_cnt + 9'd1;
endcase
end
177: begin
vblk_irq_en <= 0;
h_cnt <= h_cnt + 9'd1;
end
511: h_cnt <= 9'd128;
default: h_cnt <= h_cnt + 9'd1;
endcase
end
end
//The Konami 082 has both an active low VBlank and an active high VBlank - generate the active low VBlank by inverting
//the active high VBlank generated in the previous sequential block
assign n_vblk = ~vblk;
//Generate active low HSync, VSync and composite sync
assign n_hsync = h_center[3] ? ~(h_cnt > (182 - h_center[2:0]) && h_cnt < (215 - h_center[2:0])):
~(h_cnt > (175 - h_center[2:0]) && h_cnt < (208 - h_center[2:0]));
assign n_vsync = h_center[3] ? ~(v_cnt >= vcnt_start + 9'd1 && v_cnt <= vcnt_start + 9'd8) : ~(v_cnt >= vcnt_start && v_cnt <= vcnt_start + 9'd7);
assign sync = n_hsync ^ n_vsync;
//Assign the individual horizontal counter bits to their respective outputs (also invert bit 8 of the horizontal counter for H256)
assign h1 = h_cnt[0];
assign h2 = h_cnt[1];
assign h4 = h_cnt[2];
assign h8 = h_cnt[3];
assign h16 = h_cnt[4];
assign h32 = h_cnt[5];
assign h64 = h_cnt[6];
assign h128 = h_cnt[7];
assign h256 = ~h_cnt[8];
assign n_h256 = h_cnt[8];
//Assign the individual vertical counter bits to their respective outputs
assign v1 = v_cnt[0];
assign v2 = v_cnt[1];
assign v4 = v_cnt[2];
assign v8 = v_cnt[3];
assign v16 = v_cnt[4];
assign v32 = v_cnt[5];
assign v64 = v_cnt[6];
assign v128 = v_cnt[7];
endmodule

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//============================================================================
//
// SystemVerilog implementation of the Konami 083 custom chip, a custom
// shift register used on many early Konami arcade PCBs for handling graphics
// ROMs
// Copyright (C) 2020, 2021 Ace & ElectronAsh
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Chip pinout:
/* _____________
_| |_
CK |_|1 28|_| VCC
_| |_
LOAD |_|2 27|_| FLIP
_| |_
DB1i(4) |_|3 26|_| DB1i(6)
_| |_
DB1i(0) |_|4 25|_| DB1i(2)
_| |_
DB0i(4) |_|5 24|_| DB0i(6)
_| |_
DB0i(6) |_|6 23|_| DB0i(2)
_| |_
DB1i(5) |_|7 22|_| DB1i(7)
_| |_
DB1i(1) |_|8 21|_| DB1i(3)
_| |_
DB0i(5) |_|9 20|_| DB0i(7)
_| |_
DB0i(1) |_|10 19|_| DB0i(3)
_| |_
NC |_|11 18|_| NC
_| |_
DSH1(1) |_|12 17|_| DSH1(0)
_| |_
DSH0(1) |_|13 16|_| DSH0(0)
_| |_
GND |_|14 15|_| NC
|_____________|
*/
module k083
(
input CK,
input CEN, //Set to 1 if using this code to replace a real 083
input FLIP,
input LOAD,
input [7:0] DB0i, DB1i,
output [1:0] DSH0, DSH1
);
//Internal registers (shift right and shift left)
reg [7:0] pixel_D0_l, pixel_D0_r;
reg [7:0] pixel_D1_l, pixel_D1_r;
//Latch and shift pixel data
always_ff @(posedge CK) begin
if(CEN) begin
if(LOAD) begin
pixel_D0_l <= DB0i;
pixel_D1_l <= DB1i;
pixel_D0_r <= DB0i;
pixel_D1_r <= DB1i;
end
else begin
pixel_D0_l[3:0] <= {pixel_D0_l[2:0], 1'b0};
pixel_D0_l[7:4] <= {pixel_D0_l[6:4], 1'b0};
pixel_D1_l[3:0] <= {pixel_D1_l[2:0], 1'b0};
pixel_D1_l[7:4] <= {pixel_D1_l[6:4], 1'b0};
pixel_D0_r[3:0] <= {1'b0, pixel_D0_r[3:1]};
pixel_D0_r[7:4] <= {1'b0, pixel_D0_r[7:5]};
pixel_D1_r[3:0] <= {1'b0, pixel_D1_r[3:1]};
pixel_D1_r[7:4] <= {1'b0, pixel_D1_r[7:5]};
end
end
end
//Output shifted pixel data (reverse the bits if FLIP is low)
assign DSH0 = FLIP ? {pixel_D0_l[3], pixel_D0_l[7]} : {pixel_D0_r[0], pixel_D0_r[4]};
assign DSH1 = FLIP ? {pixel_D1_l[3], pixel_D1_l[7]} : {pixel_D1_r[0], pixel_D1_r[4]};
endmodule

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//============================================================================
//
// SystemVerilog implementation of the Konami 501 custom chip, used by some
// Konami arcade PCBs for partial address decoding and obfuscation of data
// I/O
// Copyright (C) 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Chip pinout:
/* _____________
_| |_
D[7] |_|1 28|_| VCC
_| |_
D[6] |_|2 27|_| XD[7]
_| |_
D[5] |_|3 26|_| XD[6]
_| |_
D[4] |_|4 25|_| XD[5]
_| |_
D[3] |_|5 24|_| XD[4]
_| |_
D[2] |_|6 23|_| XD[3]
_| |_
D[1] |_|7 22|_| XD[2]
_| |_
D[0] |_|8 21|_| XD[1]
_| |_
H2 |_|9 20|_| XD[0]
_| |_
H1 |_|10 19|_| WAIT
_| |_
CLK |_|11 18|_| ENABLE
_| |_
RAM |_|12 17|_| WRITE
_| |_
RD |_|13 16|_| NC
_| |_
GND |_|14 15|_| NC
|_____________|
Note: The data bus is bidirectional - this model splits these pins into separate data I/O
*/
module k501
(
input CLK, //Clock input (add a PLL to multiply the 6.144MHz pixel clock if replacing a real 501)
input CEN, //Clock enable at 12.288MHz
input H1, H2, //Bits 0 and 1 of the horizontal counter
input RAM, //Chip select (active low)
input RD, //Z80 read input
output WAIT, //Z80 wait output
output WRITE, //Write output
output ENABLE, //Enable output
input [7:0] Di, XDi, //Inputs from data busses
output [7:0] Do, XDo //Outputs to data busses
);
//Data bus passthrough
assign XDo = Di;
assign Do = XDi;
//Latch bit 0 of the horizontal counter on each edge of the clock and preset to 1 if bit 1 of the horizontal counter
//is high
reg [1:0] h1_reg = 2'd0;
always_ff @(posedge CLK) begin
if(H2)
h1_reg[0] <= 1;
else if(CEN)
h1_reg <= {h1_reg[0], H1};
end
//AND both latched instances of H1
wire h1_lat = &h1_reg;
//Generate WAIT output
assign WAIT = ~H2 | RAM;
//Generate WRITE and ENABLE outputs
assign WRITE = ~RD | ENABLE;
assign ENABLE = h1_lat | RAM;
endmodule

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//============================================================================
//
// SystemVerilog implementation of the Konami 502 custom chip, used for
// generating sprites on a number of '80s Konami arcade PCBs
// Copyright (C) 2020, 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Chip pinout:
/* _____________
_| |_
SPLB(0) |_|1 28|_| VCC
_| |_
SPLB(1) |_|2 27|_| RESET
_| |_
SPLB(2) |_|3 26|_| SPLB(4)
_| |_
SPLB(3) |_|4 25|_| SPLB(5)
_| |_
CK1 |_|5 24|_| SPLB(6)
_| |_
CK2 |_|6 23|_| SPLB(7)
_| |_
H2 |_|7 22|_| OLD
_| |_
LDO |_|8 21|_| OCLR
_| |_
H256 |_|9 20|_| OSEL
_| |_
SPAL(3) |_|10 19|_| COL(4)
_| |_
SPAL(2) |_|11 18|_| COL(3)
_| |_
SPAL(1) |_|12 17|_| COL(2)
_| |_
SPAL(0) |_|13 16|_| COL(1)
_| |_
GND |_|14 15|_| COL(0)
|_____________|
Note: The SPLB pins are bidirectional - this model splits these pins into separate
data I/O
*/
module k502
(
input RESET,
input CK1,
input CK2,
input CEN, //Set to 1 if using this code to replace a real 502
input LDO,
input H2,
input H256,
input [3:0] SPAL,
input [7:0] SPLBi,
output OSEL,
output OLD,
output OCLR,
output [7:0] SPLBo,
output [4:0] COL
);
//Latch H256 on rising edge of LD0 and delay by one cycle (set to 0 if 502 is held in reset)
reg h256_lat = 0;
reg old_ldo;
always_ff @(posedge CK1) begin
old_ldo <= LDO;
if(!RESET)
h256_lat <= 0;
else if(!old_ldo && LDO)
h256_lat <= H256;
end
reg h256_dly = 0;
reg old_h256_lat;
always_ff @(posedge CK1) begin
old_h256_lat <= h256_lat;
if(!RESET)
h256_dly <= 0;
else if(!old_h256_lat && h256_lat)
h256_dly <= ~h256_dly;
end
//As the Konami 502 doesn't have a dedicated input for bit 2 of the horizontal counter (H4), generate
//this signal internally by dividing H2 by 2
reg h4 = 0;
reg old_h2;
always_ff @(posedge CK1) begin
old_h2 <= H2;
if(!old_h2 && H2)
h4 <= ~h4;
end
//Generate OSEL, OLD and OCLR
reg [1:0] osel_reg;
always_ff @(posedge CK1) begin
if(!RESET)
osel_reg <= 2'b00;
else if(old_h2 && !H2) begin
if(!h4)
osel_reg[1] <= h256_dly;
else
osel_reg[0] <= osel_reg[1];
end
end
assign OLD = ~osel_reg[1];
assign OSEL = osel_reg[0];
assign OCLR = ~osel_reg[0];
//Multiplex incoming line buffer RAM data
wire [3:0] lbuff_Dmux = OCLR ? SPLBi[3:0] : SPLBi[7:4];
//Latch incoming line buffer RAM data on the falling edge of CK1
reg [7:0] lbuff_lat;
always_ff @(negedge CK2) begin
if(!RESET)
lbuff_lat <= 8'd0;
else if(CEN)
lbuff_lat <= SPLBi;
end
//Latch multiplexed line buffer RAM data on the falling edge of CK2
reg [3:0] lbuff_mux_lat;
always_ff @(negedge CK2) begin
if(!RESET)
lbuff_mux_lat <= 4'd0;
else if(CEN)
lbuff_mux_lat <= lbuff_Dmux;
end
//Assign sprite data output
assign COL[4] = ~(|lbuff_mux_lat[3:0]);
assign COL[3:0] = lbuff_mux_lat[3:0];
//Select sprite or palette data based on a 4-way AND of the inverted latched line buffer data
//(upper 4 bits and lower 4 bits produce separate select signals)
wire sprite_pal_sel2 = (~lbuff_lat[7] & ~lbuff_lat[6] & ~lbuff_lat[5] & ~lbuff_lat[4]);
wire sprite_pal_sel1 = (~lbuff_lat[3] & ~lbuff_lat[2] & ~lbuff_lat[1] & ~lbuff_lat[0]);
//Multiplex sprite data from line buffer with palette data (lower 4 bits)
wire [7:0] sprite_pal_mux;
assign sprite_pal_mux[3:0] = osel_reg[0] ? (sprite_pal_sel1 ? SPAL : SPLBi[3:0]) : 4'h0;
//Multiplex sprite data from line buffer with palette data (upper 4 bits)
assign sprite_pal_mux[7:4] = ~osel_reg[0] ? (sprite_pal_sel2 ? SPAL : SPLBi[7:4]) : 4'h0;
//Output data to sprite line buffer
assign SPLBo = sprite_pal_mux;
endmodule

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@@ -1,139 +0,0 @@
//============================================================================
//
// SystemVerilog implementation of the Konami 503 custom chip, used by
// several Konami arcade PCBs for handling sprite data
// Copyright (C) 2020, 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Chip pinout:
/* _____________
_| |_
OB(7) |_|1 40|_| VCC
_| |_
OB(6) |_|2 39|_| VCNT(7)
_| |_
OB(5) |_|3 38|_| VCNT(6)
_| |_
OB(4) |_|4 37|_| VCNT(5)
_| |_
OB(3) |_|5 36|_| VCNT(4)
_| |_
OB(2) |_|6 35|_| VCNT(3)
_| |_
OB(1) |_|7 34|_| VCNT(2)
_| |_
OB(0) |_|8 33|_| VCNT(1)
_| |_
R(5) |_|9 32|_| VCNT(0)
_| |_
R(4) |_|10 31|_| NC
_| |_
R(3) |_|11 30|_| OFLP
_| |_
R(2) |_|12 29|_| OCS
_| |_
R(1) |_|13 28|_| NC
_| |_
R(0) |_|14 27|_| NC
_| |_
LD |_|15 26|_| NC
_| |_
H4 |_|16 25|_| NC
_| |_
H8 |_|17 24|_| NC
_| |_
OCOL |_|18 23|_| NC
_| |_
ODAT |_|19 22|_| NC
_| |_
GND |_|20 21|_| NC
|_____________|
*/
module k503
(
input CLK, //Extra clock input for use with MiSTer (define MISTER_K503 macro to use this)
input [7:0] OB, //Sprite data input
input [7:0] VCNT, //Vertical counter input
input H4, H8, //Horizontal counter bits 2 (H4) and 3 (H8)
input LD, //LD input (pulses low when bits 0 and 1 of the horizontal counter are both 1)
output OCS, //Sprite line buffer chip select output
output OFLP, //Sprite flip output
output ODAT, //Signal to latch upper bits of sprite address
output OCOL, //Signal to load addresses for sprite line buffer
output [5:0] R //Lower 6 bits of sprite address
);
//Sum sprite bits with vertical counter
wire [7:0] sprite_sum = OB + VCNT;
//Sprite select signal
wire sprite_sel = ~(&sprite_sum[7:4]);
//Latch sprite flip attributes and sprite information on each edge of H4, flip attributes on the positive edge,
//sprite information on the falling edge
//If the macro MISTER_K503 is defined, use alternate logic with a dedicated clock input, otherwise latch directly
//off H4
reg [6:0] sprite;
reg hflip, vflip;
`ifdef MISTER_K503
reg old_h4;
always_ff @(posedge CLK) begin
old_h4 <= H4;
if(!old_h4 && H4) begin
hflip <= OB[6];
vflip <= OB[7];
end
else if(old_h4 && !H4)
sprite <= {sprite_sel, hflip, vflip, sprite_sum[3:0]};
else begin
hflip <= hflip;
vflip <= vflip;
sprite <= sprite;
end
end
`else
always_ff @(posedge H4) begin
hflip <= OB[6];
vflip <= OB[7];
end
always_ff @(negedge H4) begin
sprite <= {sprite_sel, hflip, vflip, sprite_sum[3:0]};
end
`endif
wire sprite_vflip = sprite[4];
assign OFLP = sprite[5];
assign OCS = sprite[6];
//Assign OCOL (sprite color) and ODAT (sprite data) outputs
assign OCOL = ({H8, H4, LD} != 3'b100);
assign ODAT = ({H8, H4, LD} != 3'b010);
//XOR final output for R
assign R[5] = (sprite[3] ^ sprite_vflip);
assign R[4] = (OFLP ^ H8);
assign R[3] = (OFLP ^ ~H4);
assign R[2] = (sprite[2] ^ sprite_vflip);
assign R[1] = (sprite[1] ^ sprite_vflip);
assign R[0] = (sprite[0] ^ sprite_vflip);
endmodule

80
Arcade_MiST/Konami Framebuffer/rtl/custom/k526.sv
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@@ -1,80 +0,0 @@
//============================================================================
//
// SystemVerilog implementation of the Konami 526, an 82S153 PLA used for
// address decoding on Time Pilot
// Converted from dump available at the PLD Archive
// http://wiki.pldarchive.co.uk/index.php?title=Time_Pilot
// Copyright (C) 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Chip pinout:
/* _____________
_| |_
MREQ |_|1 20|_| VCC
_| |_
RFSH |_|2 19|_| ROM(0)
_| |_
A15 |_|3 18|_| ROM(1)
_| |_
A14 |_|4 17|_| ROM(2)
_| |_
A13 |_|5 16|_| ROM(3)
_| |_
A12 |_|6 15|_| K501
_| |_
A10 |_|7 14|_| WRAM
_| |_
ENABLE |_|8 13|_| SPRAM1
_| |_
NC |_|9 12|_| SPRAM0
_| |_
GND |_|10 11|_| NC
|_____________|
*/
module k526
(
input MREQ, //MREQ input from Z80
input RFSH, //RFSH input from Z80
input A15, A14, A13, A12, A10, //Address line inputs A[15:10] excluding A[11]
input ENABLE, //Enable input from Konami 501
output SPRAM0, //Sprite RAM 0 enable (active low)
output SPRAM1, //Sprite RAM 1 enable (active low)
output WRAM, //Work RAM/VRAM enable (active low)
output K501, //Enable for Konami 501 (active low)
output [3:0] ROM //Enable for Z80 ROMs (active low)
);
assign SPRAM0 = ~(~MREQ & RFSH & {A15, A14, A13, A12, A10} == 5'b10111 & ~ENABLE);
assign SPRAM1 = ~(~MREQ & RFSH & {A15, A14, A13, A12, A10} == 5'b10110 & ~ENABLE);
assign WRAM = ~(~MREQ & RFSH & {A15, A14, A13, A12} == 4'b1010 & ~ENABLE);
assign K501 = ~(~MREQ & RFSH & A15);
assign ROM[3] = ~(~MREQ & RFSH & {A15, A14, A13} == 3'b011);
assign ROM[2] = ~(~MREQ & RFSH & {A15, A14, A13} == 3'b010);
assign ROM[1] = ~(~MREQ & RFSH & {A15, A14, A13} == 3'b001);
assign ROM[0] = ~(~MREQ & RFSH & {A15, A14, A13} == 3'b000);
endmodule

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@@ -1,71 +0,0 @@
//============================================================================
//
// SystemVerilog implementation of the Konami 528, an 82S153 PLA used for
// controlling the vertical counter outputs on Time Pilot's Konami 082
// Converted from dump available at the PLD Archive
// http://wiki.pldarchive.co.uk/index.php?title=Time_Pilot
// Copyright (C) 2021 Ace
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
//Chip pinout:
/* _____________
_| |_
HCNT[0] |_|1 20|_| VCC
_| |_
HCNT[1] |_|2 19|_| PEN
_| |_
HCNT[2] |_|3 18|_| NVEN
_| |_
HCNT[3] |_|4 17|_| K082EN
_| |_
HCNT[4] |_|5 16|_| CLKO
_| |_
HCNT[5] |_|6 15|_| CLR
_| |_
HCNT[6] |_|7 14|_| o14
_| |_
H256 |_|8 13|_| NC
_| |_
NC |_|9 12|_| RESET1
_| |_
GND |_|10 11|_| RESET0
|_____________|
*/
module k528
(
input [6:0] HCNT, //Horizontal counter bits [6:0]
input H256, //Inverse of the most significant bit of the horizontal counter
input RESET0, RESET1, //Reset inputs (both active low)
input NVEN, PEN, //Vertical counter and pixel enable inputs (NVEN active low, PEN active high)
output CLR, //Clear output for vertical counter latch
output CLKO, //Clock output for vertical counter latch
output K082EN, //Enable output for Konami 082 vertical counter
output o14 //Unknown output, connects to pin 27 of the Konami 082
);
assign o14 = ~PEN | ~RESET0;
assign CLR = RESET1 & PEN;
assign CLKO = ~H256 & PEN;
assign K082EN = (~NVEN & PEN) | ((&HCNT) & H256 & PEN);
endmodule

7
Arcade_MiST/Konami Framebuffer/rtl/custom/tut_custom.qip
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@@ -1,7 +0,0 @@
set_global_assignment -name SYSTEMVERILOG_FILE rtl/custom/k082.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/custom/k083.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/custom/k501.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/custom/k502.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/custom/k503.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/custom/k526.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/custom/k528.sv

136
Arcade_MiST/Konami Framebuffer/rtl/dpram_dc.vhd
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@@ -1,136 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram_dc IS
GENERIC
(
init_file : string := " ";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0) := (others => '0');
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) := (others => '0');
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) := (others => '0');
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
byteena_a : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) := (others => '1');
byteena_b : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) := (others => '1');
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram_dc;
ARCHITECTURE SYN OF dpram_dc IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) ;
byteena_b : IN STD_LOGIC_VECTOR (width_a/8-1 DOWNTO 0) ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => width_a/8,
width_byteena_b => width_a/8,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1,
byteena_a => byteena_a,
byteena_b => byteena_b
);
END SYN;

58
Arcade_MiST/Konami Framebuffer/rtl/jtframe_frac_cen.v
View File

@@ -1,58 +0,0 @@
///////////////////////////////////////////////////////////////////////////
// Fractional clock enable signal
// W refers to the number of divided down cen signals available
// each one is divided by 2
module jtframe_frac_cen #(parameter W=2)(
input clk,
input [9:0] n, // numerator
input [9:0] m, // denominator
output reg [W-1:0] cen,
output reg [W-1:0] cenb // 180 shifted
);
wire [10:0] step={1'b0,n};
wire [10:0] lim ={1'b0,m};
wire [10:0] absmax = lim+step;
reg [10:0] cencnt=11'd0;
reg [10:0] next;
reg [10:0] next2;
always @(*) begin
next = cencnt+step;
next2 = next-lim;
end
reg half = 1'b0;
wire over = next>=lim;
wire halfway = next >= (lim>>1) && !half;
reg [W-1:0] edgecnt = {W{1'b0}};
wire [W-1:0] next_edgecnt = edgecnt + 1'b1;
wire [W-1:0] toggle = next_edgecnt & ~edgecnt;
always @(posedge clk) begin
cen <= {W{1'b0}};
cenb <= {W{1'b0}};
if( cencnt >= absmax ) begin
// something went wrong: restart
cencnt <= 11'd0;
end else
if( halfway ) begin
half <= 1'b1;
cenb[0] <= 1'b1;
end
if( over ) begin
cencnt <= next2;
half <= 1'b0;
edgecnt <= next_edgecnt;
cen <= { toggle[W-2:0], 1'b1 };
end else begin
cencnt <= next;
end
end
endmodule

91
Arcade_MiST/Konami Framebuffer/rtl/mc_stars.vhd
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@@ -1,91 +0,0 @@
------------------------------------------------------------------------------
-- FPGA MOONCRESTA STARS
--
-- Version : 2.00
--
-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
--
-- Important !
--
-- This program is freeware for non-commercial use.
-- The author does not guarantee this program.
-- You can use this at your own risk.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MC_STARS is
port (
I_CLK_12M : in std_logic;
I_CLK_6M : in std_logic;
I_H_FLIP : in std_logic;
I_V_SYNC : in std_logic;
I_8HF : in std_logic;
I_256HnX : in std_logic;
I_1VF : in std_logic;
I_2V : in std_logic;
I_STARS_ON : in std_logic;
I_STARS_OFFn : in std_logic;
I_PAUSEn : in std_logic;
O_R : out std_logic_vector(1 downto 0);
O_G : out std_logic_vector(1 downto 0);
O_B : out std_logic_vector(1 downto 0);
O_NOISE : out std_logic
);
end;
architecture RTL of MC_STARS is
signal CLK_1C : std_logic := '0';
signal W_2D_Qn : std_logic := '0';
signal W_3B : std_logic := '0';
signal noise : std_logic := '0';
signal W_2A : std_logic := '0';
signal W_4P : std_logic := '0';
signal CLK_1AB : std_logic := '0';
signal W_1AB_Q : std_logic_vector(15 downto 0) := (others => '0');
signal W_1C_Q : std_logic_vector( 1 downto 0) := (others => '0');
begin
O_R <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
O_G <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
O_B <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
CLK_1C <= not (I_CLK_12M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
CLK_1AB <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
W_3B <= W_2D_Qn xor W_1AB_Q(4);
W_2A <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
W_4P <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
O_NOISE <= noise ;
process(I_2V)
begin
if rising_edge(I_2V) then
noise <= W_2D_Qn;
end if;
end process;
process(CLK_1C, I_V_SYNC)
begin
if(I_V_SYNC = '1') then
W_1C_Q <= (others => '0');
elsif rising_edge(CLK_1C) then
W_1C_Q <= W_1C_Q(0) & '1';
end if;
end process;
process(CLK_1AB, I_STARS_ON)
begin
if(I_STARS_ON = '0') then
W_1AB_Q <= (others => '0');
W_2D_Qn <= '1';
elsif rising_edge(CLK_1AB) then
W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
W_2D_Qn <= not W_1AB_Q(15);
end if;
end process;
end RTL;

365
Arcade_MiST/Konami Framebuffer/rtl/pll.vhd
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@@ -1,365 +0,0 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 39,
clk0_duty_cycle => 50,
clk0_multiply_by => 71,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "39"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "49.153847"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "49.15200000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "39"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

142
Arcade_MiST/Konami Framebuffer/rtl/rom_loader.sv
View File

@@ -1,142 +0,0 @@
//============================================================================
//
// SD card ROM loader and ROM selector for MISTer.
// Copyright (C) 2019, 2020 Kitrinx (aka Rysha)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
// DEALINGS IN THE SOFTWARE.
//
//============================================================================
// ROM layout for Tutankham (index 0 - main CPU board):
// 0x0000 - 0x0FFF = rom_m1 (m1.1h)
// 0x1000 - 0x1FFF = rom_m2 (m2.2h)
// 0x2000 - 0x2FFF = rom_m3 (3j.3h)
// 0x3000 - 0x3FFF = rom_m4 (m4.4h)
// 0x4000 - 0x4FFF = rom_m5 (m5.5h)
// 0x5000 - 0x5FFF = rom_m6 (j6.6h)
// 0x6000 - 0x6FFF = bank0 (c1.1i)
// 0x7000 - 0x7FFF = bank1 (c2.2i)
// 0x8000 - 0x8FFF = bank2 (c3.3i)
// 0x9000 - 0x9FFF = bank3 (c4.4i)
// 0xA000 - 0xAFFF = bank4 (c5.5i)
// 0xB000 - 0xBFFF = bank5 (c6.6i)
// 0xC000 - 0xCFFF = bank6 (c7.7i)
// 0xD000 - 0xDFFF = bank7 (c8.8i)
// 0xE000 - 0xEFFF = bank8 (c9.9i)
// Sound board ROMs loaded separately via index 1
module selector
(
input logic [24:0] ioctl_addr,
output logic rom_m1_cs, rom_m2_cs, rom_m3_cs, rom_m4_cs, rom_m5_cs, rom_m6_cs,
output logic bank0_cs, bank1_cs, bank2_cs, bank3_cs, bank4_cs,
bank5_cs, bank6_cs, bank7_cs, bank8_cs
);
always_comb begin
{rom_m1_cs, rom_m2_cs, rom_m3_cs, rom_m4_cs, rom_m5_cs, rom_m6_cs,
bank0_cs, bank1_cs, bank2_cs, bank3_cs, bank4_cs, bank5_cs,
bank6_cs, bank7_cs, bank8_cs} = 0;
if(ioctl_addr < 'h1000)
rom_m1_cs = 1;
else if(ioctl_addr < 'h2000)
rom_m2_cs = 1;
else if(ioctl_addr < 'h3000)
rom_m3_cs = 1;
else if(ioctl_addr < 'h4000)
rom_m4_cs = 1;
else if(ioctl_addr < 'h5000)
rom_m5_cs = 1;
else if(ioctl_addr < 'h6000)
rom_m6_cs = 1;
else if(ioctl_addr < 'h7000)
bank0_cs = 1;
else if(ioctl_addr < 'h8000)
bank1_cs = 1;
else if(ioctl_addr < 'h9000)
bank2_cs = 1;
else if(ioctl_addr < 'hA000)
bank3_cs = 1;
else if(ioctl_addr < 'hB000)
bank4_cs = 1;
else if(ioctl_addr < 'hC000)
bank5_cs = 1;
else if(ioctl_addr < 'hD000)
bank6_cs = 1;
else if(ioctl_addr < 'hE000)
bank7_cs = 1;
else if(ioctl_addr < 'hF000)
bank8_cs = 1;
end
endmodule
////////////
// EPROMS //
////////////
//Generic 4KB ROM module (12-bit address)
module eprom_4k
(
input logic CLK,
input logic CLK_DL,
input logic [11:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(12)) rom
(
.clock_a(CLK),
.address_a(ADDR[11:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[11:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule
//Sound board ROM (8KB, 13-bit address) - used by sound board index 1
module eprom_7
(
input logic CLK,
input logic CLK_DL,
input logic [12:0] ADDR,
input logic [24:0] ADDR_DL,
input logic [7:0] DATA_IN,
input logic CS_DL,
input logic WR,
output logic [7:0] DATA
);
dpram_dc #(.widthad_a(13)) eprom_7
(
.clock_a(CLK),
.address_a(ADDR[12:0]),
.q_a(DATA[7:0]),
.clock_b(CLK_DL),
.address_b(ADDR_DL[12:0]),
.data_b(DATA_IN),
.wren_b(WR & CS_DL)
);
endmodule

357
Arcade_MiST/Konami Framebuffer/rtl/sdram.sv
View File

@@ -1,357 +0,0 @@
//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output reg [15:0] port1_q,
input [16:1] cpu1_addr,
output reg [15:0] cpu1_q,
input [16:1] cpu2_addr,
output reg [15:0] cpu2_q,
input [16:1] cpu3_addr,
output reg [15:0] cpu3_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output reg [31:0] port2_q,
input [16:2] sp_addr,
output reg [31:0] sp_q
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
2 words burst, CL2
cmd issued registered
0 RAS0 cas1 - data0 read burst terminated
1 ras0
2 data1 returned
3 CAS0 data1 returned
4 RAS1 cas0
5 ras1
6 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_DS1b = 3'd0;
localparam STATE_READ1b = 3'd4;
localparam STATE_LAST = 3'd6;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[3];
reg [24:1] addr_latch_next[2];
reg [16:1] addr_last[4];
reg [16:2] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1 = 3'd1;
localparam PORT_CPU2 = 3'd2;
localparam PORT_CPU3 = 3'd3;
localparam PORT_SP = 3'd1;
localparam PORT_REQ = 3'd4;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 8'd0, cpu1_addr };
end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 8'd0, cpu2_addr };
end else if (cpu3_addr != addr_last[PORT_CPU3]) begin
next_port[0] = PORT_CPU3;
addr_latch_next[0] = { 8'd0, cpu3_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT1: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (sp_addr != addr_last2[PORT_SP]) begin
next_port[1] = PORT_SP;
addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][16:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
port1_state <= port1_req;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port2_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
PORT_CPU2: begin cpu2_q <= sd_din; end
PORT_CPU3: begin cpu3_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: port2_q[15:0] <= sd_din;
PORT_SP : sp_q[15:0] <= sd_din;
default: ;
endcase;
end
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if(t == STATE_READ1b && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
PORT_SP : begin sp_q[31:16] <= sd_din; end
default: ;
endcase;
end
end
end
endmodule

46
Arcade_MiST/Konami Framebuffer/rtl/spram.vhd
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@@ -1,46 +0,0 @@
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
entity spram is
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 10
);
port
(
clk : in std_logic;
addr : in std_logic_vector((ADDR_WIDTH - 1) downto 0);
data : in std_logic_vector((DATA_WIDTH - 1) downto 0);
q : out std_logic_vector((DATA_WIDTH - 1) downto 0);
we : in std_logic := '0'
);
end spram;
architecture rtl of spram is
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
shared variable ram : memory_t;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(to_integer(unsigned(addr))) := data;
q <= data;
else
q <= ram(to_integer(unsigned(addr)));
end if;
end if;
end process;
end rtl;